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Thu, 13 Jun 2024 10:05:07 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ca2825733sm287312e87.60.2024.06.13.10.05.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jun 2024 10:05:07 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 13 Jun 2024 20:05:04 +0300 Subject: [PATCH v2 1/8] dt-bindings: display/msm/dsi: allow specifying TE source Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240613-dpu-handle-te-signal-v2-1-67a0116b5366@linaro.org> References: <20240613-dpu-handle-te-signal-v2-0-67a0116b5366@linaro.org> In-Reply-To: <20240613-dpu-handle-te-signal-v2-0-67a0116b5366@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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Usually it is connected to the first GPIO with the mdp_vsync function, which is the default. In such case the property can be skipped. Acked-by: Krzysztof Kozlowski Reviewed-by: Rob Herring (Arm) Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- .../bindings/display/msm/dsi-controller-main.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 1fa28e976559..e1cb3a1fee81 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -162,6 +162,22 @@ properties: items: enum: [ 0, 1, 2, 3 ] + qcom,te-source: + $ref: /schemas/types.yaml#/definitions/string + description: + Specifies the source of vsync signal from the panel used for + tearing elimination. + default: mdp_vsync_p + enum: + - mdp_vsync_p + - mdp_vsync_s + - mdp_vsync_e + - timer0 + - timer1 + - timer2 + - timer3 + - timer4 + required: - port@0 - port@1 @@ -452,6 +468,7 @@ examples: dsi0_out: endpoint { remote-endpoint = <&sn65dsi86_in>; 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Use this enum to pass vsync information. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 26 ++++++++++++++------------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 2 +- 5 files changed, 18 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 119f3ea50a7c..4988a1029431 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -747,7 +747,7 @@ static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, if (disp_info->is_te_using_watchdog_timer) vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0; else - vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO; + vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_GPIO_0; hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 225c1c7768ff..96f6160cf607 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -462,7 +462,7 @@ static int dpu_hw_intf_get_vsync_info(struct dpu_hw_intf *intf, } static void dpu_hw_intf_vsync_sel(struct dpu_hw_intf *intf, - u32 vsync_source) + enum dpu_vsync_source vsync_source) { struct dpu_hw_blk_reg_map *c; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index f9015c67a574..ac244f0b33fb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -107,7 +107,7 @@ struct dpu_hw_intf_ops { int (*connect_external_te)(struct dpu_hw_intf *intf, bool enable_external_te); - void (*vsync_sel)(struct dpu_hw_intf *intf, u32 vsync_source); + void (*vsync_sel)(struct dpu_hw_intf *intf, enum dpu_vsync_source vsync_source); /** * Disable autorefresh if enabled diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index 66759623fc42..a2eff36a2224 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -54,18 +54,20 @@ #define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12) #define DPU_BLEND_BG_TRANSP_EN (1 << 13) -#define DPU_VSYNC0_SOURCE_GPIO 0 -#define DPU_VSYNC1_SOURCE_GPIO 1 -#define DPU_VSYNC2_SOURCE_GPIO 2 -#define DPU_VSYNC_SOURCE_INTF_0 3 -#define DPU_VSYNC_SOURCE_INTF_1 4 -#define DPU_VSYNC_SOURCE_INTF_2 5 -#define DPU_VSYNC_SOURCE_INTF_3 6 -#define DPU_VSYNC_SOURCE_WD_TIMER_4 11 -#define DPU_VSYNC_SOURCE_WD_TIMER_3 12 -#define DPU_VSYNC_SOURCE_WD_TIMER_2 13 -#define DPU_VSYNC_SOURCE_WD_TIMER_1 14 -#define DPU_VSYNC_SOURCE_WD_TIMER_0 15 +enum dpu_vsync_source { + DPU_VSYNC_SOURCE_GPIO_0, + DPU_VSYNC_SOURCE_GPIO_1, + DPU_VSYNC_SOURCE_GPIO_2, + DPU_VSYNC_SOURCE_INTF_0 = 3, + DPU_VSYNC_SOURCE_INTF_1, + DPU_VSYNC_SOURCE_INTF_2, + DPU_VSYNC_SOURCE_INTF_3, + DPU_VSYNC_SOURCE_WD_TIMER_4 = 11, + DPU_VSYNC_SOURCE_WD_TIMER_3, + DPU_VSYNC_SOURCE_WD_TIMER_2, + DPU_VSYNC_SOURCE_WD_TIMER_1, + DPU_VSYNC_SOURCE_WD_TIMER_0, +}; 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Thu, 13 Jun 2024 10:05:09 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ca2825733sm287312e87.60.2024.06.13.10.05.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jun 2024 10:05:08 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 13 Jun 2024 20:05:06 +0300 Subject: [PATCH v2 3/8] drm/msm/dsi: drop unused GPIOs handling Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240613-dpu-handle-te-signal-v2-3-67a0116b5366@linaro.org> References: <20240613-dpu-handle-te-signal-v2-0-67a0116b5366@linaro.org> In-Reply-To: <20240613-dpu-handle-te-signal-v2-0-67a0116b5366@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2912; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=8wuA6F0zaRzQk3cvli/KQmN8/4cLG5ABY/Oy6ljx7TU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmaybBJV9O81Oecm/R1DlGgCx31s7ucMntxxY4E o3T/OvfWhyJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZmsmwQAKCRCLPIo+Aiko 1VKNB/926H76xiXl0BdvywppPDqR+MHSVLaffZghsfW+XfUFDR/1N8nC3NUgmAprkSD+vVcPeGo zWdznmpnbKtTLKr6MDtZ+gU+gQ9GcJd1D/u2CLeNm6/LsnkxKSkVSmqlHpE735LWUZbZBwHDOJh 7Chr0/nGenMcMJRa8SKA58JOg3GwDMoVljcUHTL0sXbEvMZctyH/UydHdCmjQejNcXAjQvBOHT6 HqX7xyAftWdkeAHmZMCE6b0KCP5qhMbP2B4zXLfE87pA5wKRNailS94Nt99KHnDtR/PmQBHZ0JU rOs6JOjfYjeTtIMagjmznygNV5eA3UOe6D2JRfWdURWd761O X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Neither disp-enable-gpios nor disp-te-gpios are defined in the schema. None of the board DT files use those GPIO pins. Drop them from the driver. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 37 ------------------------------------- 1 file changed, 37 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index a50f4dda5941..c4d72562c95a 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -130,9 +129,6 @@ struct msm_dsi_host { unsigned long src_clk_rate; - struct gpio_desc *disp_en_gpio; - struct gpio_desc *te_gpio; - const struct msm_dsi_cfg_handler *cfg_hnd; struct completion dma_comp; @@ -1613,28 +1609,6 @@ static irqreturn_t dsi_host_irq(int irq, void *ptr) return IRQ_HANDLED; } -static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, - struct device *panel_device) -{ - msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, - "disp-enable", - GPIOD_OUT_LOW); - if (IS_ERR(msm_host->disp_en_gpio)) { - DBG("cannot get disp-enable-gpios %ld", - PTR_ERR(msm_host->disp_en_gpio)); - return PTR_ERR(msm_host->disp_en_gpio); - } - - msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", - GPIOD_IN); - if (IS_ERR(msm_host->te_gpio)) { - DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); - return PTR_ERR(msm_host->te_gpio); - } - - return 0; -} - static int dsi_host_attach(struct mipi_dsi_host *host, struct mipi_dsi_device *dsi) { @@ -1651,11 +1625,6 @@ static int dsi_host_attach(struct mipi_dsi_host *host, if (dsi->dsc) msm_host->dsc = dsi->dsc; - /* Some gpios defined in panel DT need to be controlled by host */ - ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); - if (ret) - return ret; - ret = dsi_dev_attach(msm_host->pdev); if (ret) return ret; @@ -2422,9 +2391,6 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host, dsi_sw_reset(msm_host); dsi_ctrl_enable(msm_host, phy_shared_timings, phy); - if (msm_host->disp_en_gpio) - gpiod_set_value(msm_host->disp_en_gpio, 1); - msm_host->power_on = true; mutex_unlock(&msm_host->dev_mutex); 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Pull the is_cmd_mode condition out of the function into the calling code, so that it becomes more explicit. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 4988a1029431..bd37a56b4d03 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -736,8 +736,7 @@ static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, return; } - if (hw_mdptop->ops.setup_vsync_source && - disp_info->is_cmd_mode) { + if (hw_mdptop->ops.setup_vsync_source) { for (i = 0; i < dpu_enc->num_phys_encs; i++) vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; @@ -1226,7 +1225,8 @@ static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select( dpu_enc->cur_master->hw_mdptop); - _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); + if (dpu_enc->disp_info.is_cmd_mode) + _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); 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a=openpgp-sha256; l=2868; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=0Iv1DFyBhdoY+/Sz6mfuH/zko7qqu85Tsijz4fV/RPg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmaybB/fvZLcXlwp6Sd6UVZoGCW1bqWg7hqV1I+ WAgW9ocJneJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZmsmwQAKCRCLPIo+Aiko 1a02B/9eIc6+2K7PRVJf1MS1yHmWo3kw4wsfl3I0ZDcGMcrG914sOgEKHz04At6PIzmFVB03jHf Z2rl/6FoKCLL5F0vldvdOOhcUGme47GVp3TN16Fi9fkJd38v7J+AYOCNyQvpd1BgmVQ/e2EqJ/V VXd98uLTLkCze+c43pmvYfiIWCzwRxHdcodjcRAKAOy4dbfeT9JqGGSl/Qa70Ovs+QK3m9c+I/W sCNMYZlHKsYKtUpHZ7lZZLqpw7ON9lei9AIzNLm1sgF5se8YAYk4J8s/8veM5PRx7vTu52+J4Kg DTcTeBCMWsDpDNv1Ea321rw7wjIrvARf/1VXOtJy0NJOVJl9 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The struct msm_display_info has is_te_using_watchdog_timer field which is neither used anywhere nor is flexible enough to specify different sources. Replace it with the field specifying the vsync source using enum dpu_vsync_source. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 +---- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 5 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++ 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index bd37a56b4d03..b147f8814a18 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -743,10 +743,7 @@ static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, vsync_cfg.pp_count = dpu_enc->num_phys_encs; vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode); - if (disp_info->is_te_using_watchdog_timer) - vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0; - else - vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_GPIO_0; + vsync_cfg.vsync_source = disp_info->vsync_source; hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index 76be77e30954..cb59bd4436f4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -26,15 +26,14 @@ * @h_tile_instance: Controller instance used per tile. Number of elements is * based on num_of_h_tiles * @is_cmd_mode Boolean to indicate if the CMD mode is requested - * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is - * used instead of panel TE in cmd mode panels + * @vsync_source: Source of the TE signal for DSI CMD devices */ struct msm_display_info { enum dpu_intf_type intf_type; uint32_t num_of_h_tiles; uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; bool is_cmd_mode; - bool is_te_using_watchdog_timer; + enum dpu_vsync_source vsync_source; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 1955848b1b78..e9991f3756d4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -543,6 +543,8 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev, info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]); + info.vsync_source = DPU_VSYNC_SOURCE_GPIO_0; + encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI, &info); if (IS_ERR(encoder)) { DPU_ERROR("encoder init failed for dsi display\n"); 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Thu, 13 Jun 2024 10:05:11 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ca2825733sm287312e87.60.2024.06.13.10.05.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jun 2024 10:05:10 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 13 Jun 2024 20:05:09 +0300 Subject: [PATCH v2 6/8] drm/msm/dsi: parse vsync source from device tree Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240613-dpu-handle-te-signal-v2-6-67a0116b5366@linaro.org> References: <20240613-dpu-handle-te-signal-v2-0-67a0116b5366@linaro.org> In-Reply-To: <20240613-dpu-handle-te-signal-v2-0-67a0116b5366@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3355; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=bDZH3Se3yEXeok1v+4xcgwo8ckhAiicjF4WPwysF+hY=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmaybB2LKaRw9mB+qJ3Wcyy+ofJN/TyAW6ZOgMG +BEZKGyyn2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZmsmwQAKCRCLPIo+Aiko 1RvtB/4lo66prEsmuaIsbxhLnN5kdIup7X3NKwqkkVugXSxRS3KGlGbjuMRWGlC9PnUCnI6+AWa opaaFF+z3OoCPe9e1j/YhneHyHRoAWKpkQ88893u3CkGgvLXTfV/jhP1qjB/ZqUKrtN63lD2Ja7 ZmPU+Cpg0mAIBiC3psYh5K9u9crLtO6dLT6MYTACjXoui443ZpVZHqanmFiF7ARAihHvcjf/zRM U23qB0Nx3lQD25w2l0BPYT0ncHtyWVPa3oP/dkGxkoWuO0A1FN33z8/0tuRLQbBACJkJAskIzpW xUSW968YgQcYVAaXkgiQ/bpUQy8ZXQrac4NjraKf7QyzXHWL X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Allow board's device tree to specify the vsync source (aka TE source). If the property is omitted, the display controller driver will use the default setting. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 11 +++++++++++ drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 +++++ drivers/gpu/drm/msm/msm_drv.h | 6 ++++++ 4 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index afc290408ba4..87496db203d6 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -37,6 +37,7 @@ struct msm_dsi { struct mipi_dsi_host *host; struct msm_dsi_phy *phy; + const char *te_source; struct drm_bridge *next_bridge; diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index c4d72562c95a..c26ad0fed54d 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -1786,9 +1786,11 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) { + struct msm_dsi *msm_dsi = platform_get_drvdata(msm_host->pdev); struct device *dev = &msm_host->pdev->dev; struct device_node *np = dev->of_node; struct device_node *endpoint; + const char *te_source; int ret = 0; /* @@ -1811,6 +1813,15 @@ static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) goto err; } + ret = of_property_read_string(endpoint, "qcom,te-source", &te_source); + if (ret && ret != -EINVAL) { + DRM_DEV_ERROR(dev, "%s: invalid TE source configuration %d\n", + __func__, ret); + goto err; + } + if (!ret) + msm_dsi->te_source = devm_kstrdup(dev, te_source, GFP_KERNEL); + if (of_property_read_bool(np, "syscon-sfpb")) { msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, "syscon-sfpb"); diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 5b3f3068fd92..a210b7c9e5ca 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -603,3 +603,8 @@ bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) { return IS_MASTER_DSI_LINK(msm_dsi->id); } + +const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi) +{ + return msm_dsi->te_source; +} diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 912ebaa5df84..afd98dffea99 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -330,6 +330,7 @@ bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi); struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); +const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi); #else static inline void __init msm_dsi_register(void) { @@ -367,6 +368,11 @@ static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_ { return NULL; } + +static inline const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi) +{ + return NULL; +} #endif #ifdef CONFIG_DRM_MSM_DP From patchwork Thu Jun 13 17:05:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 804280 Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D10EB14A0B8 for ; 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Thu, 13 Jun 2024 10:05:12 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ca2825733sm287312e87.60.2024.06.13.10.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jun 2024 10:05:11 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 13 Jun 2024 20:05:10 +0300 Subject: [PATCH v2 7/8] drm/msm/dpu: support setting the TE source Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240613-dpu-handle-te-signal-v2-7-67a0116b5366@linaro.org> References: <20240613-dpu-handle-te-signal-v2-0-67a0116b5366@linaro.org> In-Reply-To: <20240613-dpu-handle-te-signal-v2-0-67a0116b5366@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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If none is specified, the driver defaults to the first GPIO (mdp_vsync0). Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 44 ++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index e9991f3756d4..6fcb3cf4a382 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -505,6 +505,44 @@ static void dpu_kms_wait_flush(struct msm_kms *kms, unsigned crtc_mask) dpu_kms_wait_for_commit_done(kms, crtc); } +static const char *dpu_vsync_sources[] = { + [DPU_VSYNC_SOURCE_GPIO_0] = "mdp_vsync_p", + [DPU_VSYNC_SOURCE_GPIO_1] = "mdp_vsync_s", + [DPU_VSYNC_SOURCE_GPIO_2] = "mdp_vsync_e", + [DPU_VSYNC_SOURCE_INTF_0] = "mdp_intf0", + [DPU_VSYNC_SOURCE_INTF_1] = "mdp_intf1", + [DPU_VSYNC_SOURCE_INTF_2] = "mdp_intf2", + [DPU_VSYNC_SOURCE_INTF_3] = "mdp_intf3", + [DPU_VSYNC_SOURCE_WD_TIMER_0] = "timer0", + [DPU_VSYNC_SOURCE_WD_TIMER_1] = "timer1", + [DPU_VSYNC_SOURCE_WD_TIMER_2] = "timer2", + [DPU_VSYNC_SOURCE_WD_TIMER_3] = "timer3", + [DPU_VSYNC_SOURCE_WD_TIMER_4] = "timer4", +}; + +static int dpu_kms_dsi_set_te_source(struct msm_display_info *info, + struct msm_dsi *dsi) +{ + const char *te_source = msm_dsi_get_te_source(dsi); + int i; + + if (!te_source) { + info->vsync_source = DPU_VSYNC_SOURCE_GPIO_0; + return 0; + } + + /* we can not use match_string since dpu_vsync_sources is a sparse array */ + for (i = 0; i < ARRAY_SIZE(dpu_vsync_sources); i++) { + if (dpu_vsync_sources[i] && + !strcmp(dpu_vsync_sources[i], te_source)) { + info->vsync_source = i; + return 0; + } + } + + return -EINVAL; +} + static int _dpu_kms_initialize_dsi(struct drm_device *dev, struct msm_drm_private *priv, struct dpu_kms *dpu_kms) @@ -543,7 +581,11 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev, info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]); - info.vsync_source = DPU_VSYNC_SOURCE_GPIO_0; + rc = dpu_kms_dsi_set_te_source(&info, priv->dsi[i]); + if (rc) { + DPU_ERROR("failed to identify TE source for dsi display\n"); + return rc; + } encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI, &info); 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Thu, 13 Jun 2024 10:05:12 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ca2825733sm287312e87.60.2024.06.13.10.05.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jun 2024 10:05:12 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 13 Jun 2024 20:05:11 +0300 Subject: [PATCH v2 8/8] drm/msm/dpu: rename dpu_hw_setup_vsync_source functions Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240613-dpu-handle-te-signal-v2-8-67a0116b5366@linaro.org> References: <20240613-dpu-handle-te-signal-v2-0-67a0116b5366@linaro.org> In-Reply-To: <20240613-dpu-handle-te-signal-v2-0-67a0116b5366@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2201; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=ueS1wf8UISai/dHWZNsJmGTXzlQKS5D7cMZLTp/g7pM=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ1q22qFk9TX8rEHKdSeV7vy9tNmzxVbbNr3lv/3a3qeZI q84j1/qZDRmYWDkYpAVU2TxKWiZGrMpOezDjqn1MINYmUCmMHBxCsBEgmU5GBoePXzIn1bMMMlk 5afCiHcR50/Z2f5WMD306KHEZLaOs282zjA4njA7OSDF8O3SQJmHb9k39v5VuCkV0WekwZ3Cp7L 8OM/GHwv9JG2VLwXuPMXUf9anmE9BMNXto0gjV9WCVWq1B0I3bM9Kdsk4u/O/QHh2OS+P2BaGxt l6YZoXprO6Htl28YWLihbD+dwl37okXVQ2t3isSJWOO9L6ZrvHl1v+q04u/qv5csP2K/Ir2W+uW v2vPau/X6k9bJJMxJ7IMAf9c33KvZt0XI10Q3t3svW3rXp+cPuNOI03e0878N14KBqZEZyy8bGW 8mahwszwnFyTnPYA8S8qzemSN62+a270fzjxXIxEgf0fAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Rename dpu_hw_setup_vsync_source functions to make the names match the implementation: on DPU 5.x the TOP only contains timer setup, while 3.x and 4.x used MDP_VSYNC_SEL register to select TE source. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index 05e48cf4ec1d..6e2ac50b94a4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -107,8 +107,8 @@ static void dpu_hw_get_danger_status(struct dpu_hw_mdp *mdp, status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x3; } -static void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp, - struct dpu_vsync_source_cfg *cfg) +static void dpu_hw_setup_wd_timer(struct dpu_hw_mdp *mdp, + struct dpu_vsync_source_cfg *cfg) { struct dpu_hw_blk_reg_map *c; u32 reg, wd_load_value, wd_ctl, wd_ctl2; @@ -163,8 +163,8 @@ static void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp, } } -static void dpu_hw_setup_vsync_source_and_vsync_sel(struct dpu_hw_mdp *mdp, - struct dpu_vsync_source_cfg *cfg) +static void dpu_hw_setup_vsync_sel(struct dpu_hw_mdp *mdp, + struct dpu_vsync_source_cfg *cfg) { struct dpu_hw_blk_reg_map *c; u32 reg, i; @@ -187,7 +187,7 @@ static void dpu_hw_setup_vsync_source_and_vsync_sel(struct dpu_hw_mdp *mdp, } DPU_REG_WRITE(c, MDP_VSYNC_SEL, reg); - dpu_hw_setup_vsync_source(mdp, cfg); + dpu_hw_setup_wd_timer(mdp, cfg); } static void dpu_hw_get_safe_status(struct dpu_hw_mdp *mdp, @@ -239,9 +239,9 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops, ops->get_danger_status = dpu_hw_get_danger_status; if (cap & BIT(DPU_MDP_VSYNC_SEL)) - ops->setup_vsync_source = dpu_hw_setup_vsync_source_and_vsync_sel; + ops->setup_vsync_source = dpu_hw_setup_vsync_sel; else - ops->setup_vsync_source = dpu_hw_setup_vsync_source; + ops->setup_vsync_source = dpu_hw_setup_wd_timer; ops->get_safe_status = dpu_hw_get_safe_status;