From patchwork Thu Oct 24 11:40:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 177410 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp2062762ill; Thu, 24 Oct 2019 04:41:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqwJirwH4rMzBU+oIrOtM8OJp3X/D/lohecI+cwLSr/apL2ykS1dUkfqWz40T0QevdzNZw1f X-Received: by 2002:a17:906:e243:: with SMTP id gq3mr19644669ejb.302.1571917263494; Thu, 24 Oct 2019 04:41:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571917263; cv=none; d=google.com; s=arc-20160816; b=rWznKmgYo95XMKRI7rBfWVyyVEVlLrk+pzVBaHYSDZmBVhi40yiQ+Mu08uIyZABuPS RF5hqM2eJ2cfegs7HY+Nw+JpBijkbmEXkfk85tWNxVAl3s1kzACH9GMUDEa5S0Cpv8n4 pzQeFTjuJ77MvyzuiKbWDaFH88CwWDtK/+sKs08Ho3lT7he52wP9xtNUrkE7zsXy0vhy IvLRwT0blGp+W5Y0LcH25QCKqcN5GVo0gZw3Wcsm0qC5As90F5nkE5Spe6J2XvSDE7O4 n8bAy672+esWrbZ0JGJR4g2w/Wvvk7wLTqvv0jQPthyYKq0CGBbj5ihQILX1Xalqir1n bTlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=WSq9OZdwKdeoLjUwzEDRH2J/CSISTFy2JDeWsxhM3og=; b=iUPIbdaKDdBH7MAVViNfFmVVea6bX2fv++S6CXrFrP7jsxAgm609g9nXxcuWm33N5n Y0dRUH2gUC4mUT8x5eMTiAqluu74lsnEUW25QU7HJi+GY78nk3y4ZaSRAjCpiMuj29Ut RIqctFK9kNLYzO/neoJsR94wxdUctq3YDmDwfLmU/bsaT9INRaP5YVrwGxK4vPNf5jfn hYBPxaYfgvsnYluPFw+uGcJ351FLA7hkDt070BA08PA6dEUneNUvgqgZp4YTVGcMMMHZ FHv6P5S/Ycn3fpFwBD1YalYnPnJfPpQ6/rK3rRb6DgRyqoDjcPR9ruY8keqzWBzeoh4A o8fQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=SXQFVePo; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g31si231887eda.325.2019.10.24.04.41.03; Thu, 24 Oct 2019 04:41:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=SXQFVePo; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2439055AbfJXLk5 (ORCPT + 8 others); Thu, 24 Oct 2019 07:40:57 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37592 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2439051AbfJXLk5 (ORCPT ); Thu, 24 Oct 2019 07:40:57 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9OBer6v012089; Thu, 24 Oct 2019 06:40:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571917253; bh=WSq9OZdwKdeoLjUwzEDRH2J/CSISTFy2JDeWsxhM3og=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SXQFVePoXYpXmI65MYjCFMB0vDB2iLUax9uohTRDTibK6lDCOtBFQQ5oUSUpngMpv 9a6hoCww1O9EazeWJpTtTN/+zUOhy0BRAfw43UgSDiuLKD5bmrPUEnKeMWSR57ufUz /6vOdQvC07QqoxBaBkjSQ+GhnxY3U2B1IcmAp5dg= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9OBerhn128811 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Oct 2019 06:40:53 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 24 Oct 2019 06:40:40 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 24 Oct 2019 06:40:40 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9OBeiTC044238; Thu, 24 Oct 2019 06:40:49 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros , Rob Herring Subject: [PATCH v3 2/3] dt-bindings: phy: ti, phy-j721e-wiz: Add Type-C dir GPIO Date: Thu, 24 Oct 2019 14:40:41 +0300 Message-ID: <20191024114042.30237-3-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191024114042.30237-1-rogerq@ti.com> References: <20191024114042.30237-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This is an optional GPIO, if specified will be used to swap lane 0 and lane 1 based on GPIO status. This is required to achieve plug flip support for USB Type-C. Type-C companions typically need some time after the cable is plugged before and before they reflect the correct status of Type-C plug orientation on the DIR line. Type-C Spec specifies CC attachment debounce time (tCCDebounce) of 100 ms (min) to 200 ms (max). Allow the DT node to specify the time (in ms) that we need to wait before sampling the DIR line. Signed-off-by: Roger Quadros Cc: Rob Herring --- .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index 8a1eccee6c1d..5dab0010bcdf 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -53,6 +53,21 @@ properties: assigned-clock-parents: maxItems: 2 + typec-dir-gpios: + maxItems: 1 + description: + GPIO to signal Type-C cable orientation for lane swap. + If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to + achieve the funtionality of an exernal type-C plug flip mux. + + typec-dir-debounce: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + Number of milliseconds to wait before sampling + typec-dir-gpio. If not specified, the GPIO will be sampled ASAP. + Type-C spec states minimum CC pin debounce of 100 ms and maximum + of 200 ms. + patternProperties: "^pll[0|1]_refclk$": type: object