From patchwork Sun Jun 16 22:07:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 804665 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 55EA761FF0; Sun, 16 Jun 2024 22:09:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718575741; cv=none; b=DxfHyXnPrBSyX4BXCHrRkTwmk+aaw16Gdoi1h7FfR4eGeX1VxBPgOHQPKULiGlg5W5lEtaY7etzQC0M0vxmRBQwIWekxvxD12jNWsEtGgNRtLlyDy5vQfVEe/ej1lf37enXhC1QtWduR9+BDvYiwvShkTb/zUMaM2S7+x1gPqis= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718575741; c=relaxed/simple; bh=i3nqmLT9aTw9DaPSVB5nW21/YLLYaayUA2fo89C4WFM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RXc+SJyHFlcEWq5HnUVqoWYlArSvnNWN+9VZPyc4gJDpAXbgF5e9pljJRe7t0V6di/WV/EZlXwAzMikCZFYlclCIrnISuZpBdHVdmbvfn1axn4124coirrG1UqSkuKYNtt7/7SuUAUIOtXrvuk7UI1+PT38Yw3C5wnKhtJZpZEQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C0AACFEC; Sun, 16 Jun 2024 15:09:18 -0700 (PDT) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5620C3F73B; Sun, 16 Jun 2024 15:08:52 -0700 (PDT) From: Andre Przywara To: Corentin Labbe , Herbert Xu , "David S . Miller" , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-crypto@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org Subject: [PATCH 1/4] dt-bindings: crypto: sun8i-ce: Add compatible for H616 Date: Sun, 16 Jun 2024 23:07:16 +0100 Message-Id: <20240616220719.26641-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.39.4 In-Reply-To: <20240616220719.26641-1-andre.przywara@arm.com> References: <20240616220719.26641-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Allwinner H616 has a crypto engine very similar to the one in the H6, although all addresses in the DMA descriptors are shifted by 2 bits, to accommodate for the larger physical address space. That makes it incompatible to the H6 variant, and thus requires a new compatible string. Clock wise it relies on the internal oscillator for the TRNG, so needs all four possible clocks specified. Add the compatible string to the list of recognised names, and add the H616 to list of devices requiring all four clocks. Signed-off-by: Andre Przywara Acked-by: Krzysztof Kozlowski Acked-by: Chen-Yu Tsai --- .../devicetree/bindings/crypto/allwinner,sun8i-ce.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml index 4287678aa79f4..da47b601c165e 100644 --- a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml +++ b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml @@ -18,6 +18,7 @@ properties: - allwinner,sun50i-a64-crypto - allwinner,sun50i-h5-crypto - allwinner,sun50i-h6-crypto + - allwinner,sun50i-h616-crypto reg: maxItems: 1 @@ -49,6 +50,7 @@ if: compatible: enum: - allwinner,sun20i-d1-crypto + - allwinner,sun50i-h616-crypto then: properties: clocks: From patchwork Sun Jun 16 22:07:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 804664 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 644487317C; Sun, 16 Jun 2024 22:09:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718575743; cv=none; b=HQVzCUSeLe379jPO9oWwA5wqvQNnY0z4WLnPL7WYu0a3cwpCl2fNa4qUdrmxAS0pqtPWyslQsZtItoQ+GWL55qL2R58OQhZNYnvIr+H1B/AWIQr/PZLw69Mc+DtnDFHM/Y9pYLSkdWK6V+xCPEH29Qqy/KFHmF/difDVlJllyXE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718575743; c=relaxed/simple; bh=vZxSHxbfbt3HjW3e0ai/LsmQdcjOkQEODGgM6YmdQQk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RshPixVdiF/GqQujTk7JnHzec+Tp+x3nfrYvCiZ1gazTk/8rrvhpCD5rz64zbBcayWib10oTodIzukhuM8zX25p7H9EYvKthBMHA+osNGVK9PMIAwJfSD9Hter1VqcjaVeDvio1AxifAk1kj6Oq3OPThrN6ZKLZO7TTwnWs/oFI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C88981476; Sun, 16 Jun 2024 15:09:20 -0700 (PDT) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5D7293F73B; Sun, 16 Jun 2024 15:08:54 -0700 (PDT) From: Andre Przywara To: Corentin Labbe , Herbert Xu , "David S . Miller" , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-crypto@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org Subject: [PATCH 2/4] crypto: sun8i-ce - wrap accesses to descriptor address fields Date: Sun, 16 Jun 2024 23:07:17 +0100 Message-Id: <20240616220719.26641-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.39.4 In-Reply-To: <20240616220719.26641-1-andre.przywara@arm.com> References: <20240616220719.26641-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Allwinner H616 (and later) SoCs support more than 32 bits worth of physical addresses. To accommodate the larger address space, the CE task descriptor fields holding addresses are now encoded as "word addresses", so take the actual address divided by four. This is true for the fields within the descriptor, but also for the descriptor base address, in the CE_TDA register. Wrap all accesses to those fields in a function, which will do the required division if needed. For now this in unused, so there should be no change in behaviour. Signed-off-by: Andre Przywara Reviewed-by: Chen-Yu Tsai --- drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c | 8 ++++---- drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 3 ++- drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c | 6 +++--- drivers/crypto/allwinner/sun8i-ce/sun8i-ce-prng.c | 6 +++--- drivers/crypto/allwinner/sun8i-ce/sun8i-ce-trng.c | 2 +- drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h | 10 ++++++++++ 6 files changed, 23 insertions(+), 12 deletions(-) diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c index de50c00ba218f..3a5674b1bd3c0 100644 --- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c +++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c @@ -190,7 +190,7 @@ static int sun8i_ce_cipher_prepare(struct crypto_engine *engine, void *async_req err = -EFAULT; goto theend; } - cet->t_key = cpu_to_le32(rctx->addr_key); + cet->t_key = sun8i_ce_desc_addr(ce, rctx->addr_key); ivsize = crypto_skcipher_ivsize(tfm); if (areq->iv && crypto_skcipher_ivsize(tfm) > 0) { @@ -208,7 +208,7 @@ static int sun8i_ce_cipher_prepare(struct crypto_engine *engine, void *async_req err = -ENOMEM; goto theend_iv; } - cet->t_iv = cpu_to_le32(rctx->addr_iv); + cet->t_iv = sun8i_ce_desc_addr(ce, rctx->addr_iv); } if (areq->src == areq->dst) { @@ -236,7 +236,7 @@ static int sun8i_ce_cipher_prepare(struct crypto_engine *engine, void *async_req len = areq->cryptlen; for_each_sg(areq->src, sg, nr_sgs, i) { - cet->t_src[i].addr = cpu_to_le32(sg_dma_address(sg)); + cet->t_src[i].addr = sun8i_ce_desc_addr(ce, sg_dma_address(sg)); todo = min(len, sg_dma_len(sg)); cet->t_src[i].len = cpu_to_le32(todo / 4); dev_dbg(ce->dev, "%s total=%u SG(%d %u off=%d) todo=%u\n", __func__, @@ -251,7 +251,7 @@ static int sun8i_ce_cipher_prepare(struct crypto_engine *engine, void *async_req len = areq->cryptlen; for_each_sg(areq->dst, sg, nr_sgd, i) { - cet->t_dst[i].addr = cpu_to_le32(sg_dma_address(sg)); + cet->t_dst[i].addr = sun8i_ce_desc_addr(ce, sg_dma_address(sg)); todo = min(len, sg_dma_len(sg)); cet->t_dst[i].len = cpu_to_le32(todo / 4); dev_dbg(ce->dev, "%s total=%u SG(%d %u off=%d) todo=%u\n", __func__, diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c index 0408b2d5d533b..89ab3e08f0697 100644 --- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c +++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c @@ -172,7 +172,8 @@ int sun8i_ce_run_task(struct sun8i_ce_dev *ce, int flow, const char *name) writel(v, ce->base + CE_ICR); reinit_completion(&ce->chanlist[flow].complete); - writel(ce->chanlist[flow].t_phy, ce->base + CE_TDQ); + writel(sun8i_ce_desc_addr(ce, ce->chanlist[flow].t_phy), + ce->base + CE_TDQ); ce->chanlist[flow].status = 0; /* Be sure all data is written before enabling the task */ diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c index ee2a28c906ede..a710ec9aa96f1 100644 --- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c +++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c @@ -403,7 +403,7 @@ int sun8i_ce_hash_run(struct crypto_engine *engine, void *breq) len = areq->nbytes; for_each_sg(areq->src, sg, nr_sgs, i) { - cet->t_src[i].addr = cpu_to_le32(sg_dma_address(sg)); + cet->t_src[i].addr = sun8i_ce_desc_addr(ce, sg_dma_address(sg)); todo = min(len, sg_dma_len(sg)); cet->t_src[i].len = cpu_to_le32(todo / 4); len -= todo; @@ -414,7 +414,7 @@ int sun8i_ce_hash_run(struct crypto_engine *engine, void *breq) goto theend; } addr_res = dma_map_single(ce->dev, result, digestsize, DMA_FROM_DEVICE); - cet->t_dst[0].addr = cpu_to_le32(addr_res); + cet->t_dst[0].addr = sun8i_ce_desc_addr(ce, addr_res); cet->t_dst[0].len = cpu_to_le32(digestsize / 4); if (dma_mapping_error(ce->dev, addr_res)) { dev_err(ce->dev, "DMA map dest\n"); @@ -445,7 +445,7 @@ int sun8i_ce_hash_run(struct crypto_engine *engine, void *breq) } addr_pad = dma_map_single(ce->dev, buf, j * 4, DMA_TO_DEVICE); - cet->t_src[i].addr = cpu_to_le32(addr_pad); + cet->t_src[i].addr = sun8i_ce_desc_addr(ce, addr_pad); cet->t_src[i].len = cpu_to_le32(j); if (dma_mapping_error(ce->dev, addr_pad)) { dev_err(ce->dev, "DMA error on padding SG\n"); diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-prng.c b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-prng.c index 80815379f6fc5..f030167f95945 100644 --- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-prng.c +++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-prng.c @@ -132,10 +132,10 @@ int sun8i_ce_prng_generate(struct crypto_rng *tfm, const u8 *src, cet->t_sym_ctl = cpu_to_le32(sym); cet->t_asym_ctl = 0; - cet->t_key = cpu_to_le32(dma_iv); - cet->t_iv = cpu_to_le32(dma_iv); + cet->t_key = sun8i_ce_desc_addr(ce, dma_iv); + cet->t_iv = sun8i_ce_desc_addr(ce, dma_iv); - cet->t_dst[0].addr = cpu_to_le32(dma_dst); + cet->t_dst[0].addr = sun8i_ce_desc_addr(ce, dma_dst); cet->t_dst[0].len = cpu_to_le32(todo / 4); ce->chanlist[flow].timeout = 2000; diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-trng.c b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-trng.c index 9c35f2a83eda8..465c1c512eb85 100644 --- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-trng.c +++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-trng.c @@ -77,7 +77,7 @@ static int sun8i_ce_trng_read(struct hwrng *rng, void *data, size_t max, bool wa cet->t_sym_ctl = 0; cet->t_asym_ctl = 0; - cet->t_dst[0].addr = cpu_to_le32(dma_dst); + cet->t_dst[0].addr = sun8i_ce_desc_addr(ce, dma_dst); cet->t_dst[0].len = cpu_to_le32(todo / 4); ce->chanlist[flow].timeout = todo; diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h index 93d4985def87a..8fa58f3bb7f86 100644 --- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h +++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h @@ -149,6 +149,7 @@ struct ce_variant { bool hash_t_dlen_in_bits; bool prng_t_dlen_in_bytes; bool trng_t_dlen_in_bytes; + bool needs_word_addresses; struct ce_clock ce_clks[CE_MAX_CLOCKS]; int esr; unsigned char prng; @@ -241,6 +242,15 @@ struct sun8i_ce_dev { #endif }; +static inline __le32 sun8i_ce_desc_addr(struct sun8i_ce_dev *dev, + dma_addr_t addr) +{ + if (dev->variant->needs_word_addresses) + return cpu_to_le32(addr / 4); + + return cpu_to_le32(addr); +} + /* * struct sun8i_cipher_req_ctx - context for a skcipher request * @op_dir: direction (encrypt vs decrypt) for this request From patchwork Sun Jun 16 22:07:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 805003 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C8A5A4E1D1; Sun, 16 Jun 2024 22:08:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718575740; cv=none; b=U5Eg1SQPyIEdNd5M3nul2xlVLei4eqXqGwmWtn0Qf+EZ9C7O1+d1TN/84qVnR5Be3L7Zfv6iUGcYZzUrdlD+Aa8nDDQg+3Ds5jhSnzOJ1iVe0J3u3zdniMt7kCpayhwaA9riQU0QbqUCp3Q0ftWSnNcKDyhs/o9ab7P/7iAdbt4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718575740; c=relaxed/simple; bh=4bOP+Cs4xqCqzCbtEQ07RbrP2ZAdBBQuE5JhBRxwiGA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=U4Kd3J54NeRScwEJsY9H4YWv4GGD1yHXAZsfh+f9HnaoW1uTLdMFHLMBDziduVLOrjLI3KY7A+Zogm6Fq2R+GmDGn+hTwEPNaj0yPUGC2V0q1c3WZdcHxdt2t+vppSeIrzeiJDpMmsj9OrnuNFuC8qZgx1eSK83880/ZSLNTo68= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D05351480; Sun, 16 Jun 2024 15:09:22 -0700 (PDT) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6623F3F73B; Sun, 16 Jun 2024 15:08:56 -0700 (PDT) From: Andre Przywara To: Corentin Labbe , Herbert Xu , "David S . Miller" , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-crypto@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org Subject: [PATCH 3/4] crypto: sun8i-ce - add Allwinner H616 support Date: Sun, 16 Jun 2024 23:07:18 +0100 Message-Id: <20240616220719.26641-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.39.4 In-Reply-To: <20240616220719.26641-1-andre.przywara@arm.com> References: <20240616220719.26641-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The crypto engine in the Allwinner H616 is very similar to the H6, but needs the base address for the task descriptor and the addresses within it to be expressed in words, not in bytes. Add a new variant struct entry for the H616, and set the new flag to mark the use of 34 bit addresses. Also the internal 32K oscillator is required for TRNG operation, so specify all four clocks. Signed-off-by: Andre Przywara Reviewed-by: Chen-Yu Tsai --- .../crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c index 89ab3e08f0697..97955595806ef 100644 --- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c +++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c @@ -92,6 +92,30 @@ static const struct ce_variant ce_h6_variant = { .trng = CE_ALG_TRNG_V2, }; +static const struct ce_variant ce_h616_variant = { + .alg_cipher = { CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES, + }, + .alg_hash = { CE_ALG_MD5, CE_ALG_SHA1, CE_ALG_SHA224, CE_ALG_SHA256, + CE_ALG_SHA384, CE_ALG_SHA512 + }, + .op_mode = { CE_OP_ECB, CE_OP_CBC + }, + .cipher_t_dlen_in_bytes = true, + .hash_t_dlen_in_bits = true, + .prng_t_dlen_in_bytes = true, + .trng_t_dlen_in_bytes = true, + .needs_word_addresses = true, + .ce_clks = { + { "bus", 0, 200000000 }, + { "mod", 300000000, 0 }, + { "ram", 0, 400000000 }, + { "trng", 0, 0 }, + }, + .esr = ESR_H6, + .prng = CE_ALG_PRNG_V2, + .trng = CE_ALG_TRNG_V2, +}; + static const struct ce_variant ce_a64_variant = { .alg_cipher = { CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES, }, @@ -1098,6 +1122,8 @@ static const struct of_device_id sun8i_ce_crypto_of_match_table[] = { .data = &ce_h5_variant }, { .compatible = "allwinner,sun50i-h6-crypto", .data = &ce_h6_variant }, + { .compatible = "allwinner,sun50i-h616-crypto", + .data = &ce_h616_variant }, {} }; MODULE_DEVICE_TABLE(of, sun8i_ce_crypto_of_match_table); From patchwork Sun Jun 16 22:07:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 805002 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BB2726BFC0; Sun, 16 Jun 2024 22:09:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718575742; cv=none; b=SFuuCrku0w3o7CnOpHULm1kUfAR9PhpR50m3/jZWh+GDI7KMG/N6Wu27JUqst6h9asBk8FZJPOZbGkl/uYBVETKvP+5PqYm5Ld/mSihrslK9u9Gr2X+yGAPjiBb4SjI0vaLZVNvAvLVaBFf9wm9O+3OnQYdnsjGbOvN+S8lA3P0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718575742; c=relaxed/simple; bh=KvmbdydXpOos6pQj7PzGDoZI5wEE4oJZr9Q2b/564JQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RkzlScHxNoXDs+swpPRPdjSv5NISVWEGmipcshQiw4Q60A1OtNzM4TrAHeFnJatJseVU4UAf06Ac2VRSDpgjb2fpzauksvhtQN4giOw08yAFTyka0hJQaDmP+ZrvyDncpdRbwGoFQPp5g269oxNkqDmI5v56XVgo6ngGVtBxgfs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D79481516; Sun, 16 Jun 2024 15:09:24 -0700 (PDT) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6DB923F73B; Sun, 16 Jun 2024 15:08:58 -0700 (PDT) From: Andre Przywara To: Corentin Labbe , Herbert Xu , "David S . Miller" , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-crypto@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org Subject: [PATCH 4/4] arm64: dts: allwinner: h616: add crypto engine node Date: Sun, 16 Jun 2024 23:07:19 +0100 Message-Id: <20240616220719.26641-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.39.4 In-Reply-To: <20240616220719.26641-1-andre.przywara@arm.com> References: <20240616220719.26641-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Allwinner H616 SoC contains a crypto engine very similar to the H6 version, but with all base addresses in the DMA descriptors shifted by two bits. This requires a new compatible string. Also the H616 CE relies on the internal osciallator for the TRNG operation, so we need to reference this clock. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index 921d5f61d8d6a..187663d45ed72 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -113,6 +113,16 @@ soc { #size-cells = <1>; ranges = <0x0 0x0 0x0 0x40000000>; + crypto: crypto@1904000 { + compatible = "allwinner,sun50i-h616-crypto"; + reg = <0x01904000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, + <&ccu CLK_MBUS_CE>, <&rtc CLK_IOSC>; + clock-names = "bus", "mod", "ram", "trng"; + resets = <&ccu RST_BUS_CE>; + }; + syscon: syscon@3000000 { compatible = "allwinner,sun50i-h616-system-control"; reg = <0x03000000 0x1000>;