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Thu, 20 Jun 2024 18:54:02 -0700 (PDT) From: Caleb Connolly To: Caleb Connolly , Jaehoon Chung , Neil Armstrong , Peng Fan , Sean Anderson , Sumit Garg , Tom Rini Cc: Peter Robinson , u-boot@lists.denx.de, u-boot-qcom@groups.io Subject: [PATCH] mmc: msm_sdhci: program core_vendor_spec Date: Fri, 21 Jun 2024 03:53:09 +0200 Message-ID: <20240621015351.1573934-1-caleb.connolly@linaro.org> X-Mailer: git-send-email 2.45.0 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean After resetting the host controller, program in the POR val for this register just like the Linux driver does. This seems to help with initialization when running U-Boot as the primary bootloader on some boards. Signed-off-by: Caleb Connolly --- drivers/mmc/msm_sdhci.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 4ce0de6c47d8..8b3188fa20d4 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -31,8 +31,10 @@ #define SDCC_MCI_STATUS2 0x6C #define SDCC_MCI_STATUS2_MCI_ACT 0x1 #define SDCC_MCI_HC_MODE 0x78 +#define CORE_VENDOR_SPEC_POR_VAL 0xa9c + struct msm_sdhc_plat { struct mmc_config cfg; struct mmc mmc; }; @@ -45,21 +47,25 @@ struct msm_sdhc { struct msm_sdhc_variant_info { bool mci_removed; + u32 core_vendor_spec; u32 core_vendor_spec_capabilities0; }; DECLARE_GLOBAL_DATA_PTR; static int msm_sdc_clk_init(struct udevice *dev) { struct msm_sdhc *prv = dev_get_priv(dev); + const struct msm_sdhc_variant_info *var_info; ofnode node = dev_ofnode(dev); ulong clk_rate; int ret, i = 0, n_clks; const char *clk_name; + var_info = (void *)dev_get_driver_data(dev); + ret = ofnode_read_u32(node, "clock-frequency", (uint *)(&clk_rate)); if (ret) clk_rate = 201500000; @@ -104,8 +110,11 @@ static int msm_sdc_clk_init(struct udevice *dev) log_warning("Couldn't set MMC core clock rate: %dE\n", clk_rate ? (int)PTR_ERR((void *)clk_rate) : 0); return -EINVAL; } + writel_relaxed(CORE_VENDOR_SPEC_POR_VAL, + prv->host.ioaddr + var_info->core_vendor_spec); + return 0; } static int msm_sdc_mci_init(struct msm_sdhc *prv) @@ -254,14 +263,16 @@ static int msm_sdc_bind(struct udevice *dev) static const struct msm_sdhc_variant_info msm_sdhc_mci_var = { .mci_removed = false, + .core_vendor_spec = 0x10c, .core_vendor_spec_capabilities0 = 0x11c, }; static const struct msm_sdhc_variant_info msm_sdhc_v5_var = { .mci_removed = true, + .core_vendor_spec = 0x20c, .core_vendor_spec_capabilities0 = 0x21c, }; static const struct udevice_id msm_mmc_ids[] = {