From patchwork Fri Jun 21 11:22:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 806931 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F697173324 for ; Fri, 21 Jun 2024 11:23:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718968999; cv=none; b=ZHp+rttOoiUn8BV0f0QGZBJV1ttPi25+sHmiNvUJi0qd+PBVsmnCV1eEURdEnjNmtQhMzgL3aED5CqqatEgLZCMRWhNacBqtiSpbgaur6k27DQ77Kgfq3h5gTl5RWt50KxoIpHlSHYRnxipoGju6+I6iH0Oee+9bUg9AI1UwI34= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718968999; c=relaxed/simple; bh=IjqB5K3yTTGpfsfSv09ofrCn4aXpotuyc6Jhgv4pWbk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Tt9IcwTKFazvl8IL8ClqeLttb7u2imgpFbO/tx9H8+3AiySzMn+KbWnmewBl8sOUd1UXVcph8ibNfV3Zx/Fmry7h0d0SCbGbPH1cC08E5Vr0TjBC3dKzkJqroTTCckePXhbBIncTHO0dfCuIpSbWtBaGq5hJ8GHkEYwDVhP0oRI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=CLXtLtX8; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="CLXtLtX8" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-a6e349c0f2bso225869966b.2 for ; Fri, 21 Jun 2024 04:23:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1718968996; x=1719573796; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cgq1OghRTQpWPIPh5SM3MxJFBQJBAY3NN025Q37Id8M=; b=CLXtLtX8c7C6khqzQ6phLdoEWz4MJBIwG4y7bqop6nTAor4wffRvgYbAvccDAp+Rqe BeleyMxht50y4kHVF3xTDOcHrRiebztnybecXC/OwFxs66xgQVCC+XoonpJfr/iMXtu2 t7Adx2jRBf22bqwunPe82BrcaZ1At+HlmBhGcMIb6UQwIEYQkQzLzFbBWDZRHW7EtPLc t0aIl2p8ts6pxPwfxnFpQzRf/YhlyWxLA9Q79F1kLJzhbKA1zpvEJUHSaGkHNP9Q1QqK XuvvTyY1imLGywFrUEQ4+SpwfJDnAxUemE63Tw3Kt/bOb+8XBy2Wl4CduazF9yAQS+0C 71nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718968996; x=1719573796; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cgq1OghRTQpWPIPh5SM3MxJFBQJBAY3NN025Q37Id8M=; b=ay61qFXgC7ZKQL0WSzGifv1VLq7w9A3IOJqyPELjU6lvMMpPWQTmo563z4UodbTtW+ sF5XuGMV5/wg1N8HVqoEbI1nrtfobOgeGo4pwTaCCZ5nM0ixYNHTOLHC1lWn5U8AyjQk eGSuzG+IrnCHwC1Tf9gUd845nF3hXthc+I9VcBE+/J5YFNYFW+umUpECUiXbMEueBRoT FwVoujgEDdXABEYC7dOKLwq3AVhGsP5sSkb5n4YYGE9z7Vdh+gHpuCBBI1VCschKaLnM cL5uvivkB+Wty5tOwoq9ynP+Tayb+0zQkd9ud4P+/6vOey9m2me+oHiEefXUThOrFUwq hUxg== X-Forwarded-Encrypted: i=1; AJvYcCU6ZeDI9INHYdSSlSAI8QXfAr360IJJucW1MvhlIOoQ1gnwBOhd/bH//hzS9KbjftNbSEUES7ZgwFQsbtqWOWYeQawEVzxhZPA9 X-Gm-Message-State: AOJu0YzGld+LFhPdc0DUOzUisSVjKQK4zYb1LnbjMnMvmsxrbINVIugB vzwQ4zdYDctk499JxvHNed1KOkNyP0pMqDznGJ3xB5Dy3MNIJEPgBeO2ZKwqYtI= X-Google-Smtp-Source: AGHT+IEs1anfd3yompMBKukVYfgrAHEqy/KpI7/nK6qHHwwIJuii2W5AgRvJ/UKk5m7gC+Xl4zJygQ== X-Received: by 2002:a17:906:da02:b0:a6f:314c:a75d with SMTP id a640c23a62f3a-a6fab7dda52mr469041566b.73.1718968995818; Fri, 21 Jun 2024 04:23:15 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6fd0838345sm64498466b.99.2024.06.21.04.23.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 04:23:15 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 01/12] clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C Date: Fri, 21 Jun 2024 14:22:52 +0300 Message-Id: <20240621112303.1607621-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> References: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add clock, reset and power domain support for the I2C channels available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a08g045-cpg.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index b068733b145f..a07eb3b359fc 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -213,6 +213,10 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1), DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1), DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9), + DEF_MOD("i2c0", R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0), + DEF_MOD("i2c1", R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1), + DEF_MOD("i2c2", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2), + DEF_MOD("i2c3", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3), DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), }; @@ -227,6 +231,10 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2), DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0), DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1), + DEF_RST(R9A08G045_I2C0_MRST, 0x880, 0), + DEF_RST(R9A08G045_I2C1_MRST, 0x880, 1), + DEF_RST(R9A08G045_I2C2_MRST, 0x880, 2), + DEF_RST(R9A08G045_I2C3_MRST, 0x880, 3), DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0), DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), @@ -272,6 +280,18 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { DEF_PD("eth1", R9A08G045_PD_ETHER1, DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)), RZG2L_PD_F_NONE), + DEF_PD("i2c0", R9A08G045_PD_I2C0, + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)), + RZG2L_PD_F_NONE), + DEF_PD("i2c1", R9A08G045_PD_I2C1, + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)), + RZG2L_PD_F_NONE), + DEF_PD("i2c2", R9A08G045_PD_I2C2, + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)), + RZG2L_PD_F_NONE), + DEF_PD("i2c3", R9A08G045_PD_I2C3, + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)), + RZG2L_PD_F_NONE), DEF_PD("scif0", R9A08G045_PD_SCIF0, DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), RZG2L_PD_F_NONE), From patchwork Fri Jun 21 11:22:53 2024 Content-Type: text/plain; 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([82.78.167.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6fd0838345sm64498466b.99.2024.06.21.04.23.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 04:23:17 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 02/12] i2c: riic: Use temporary variable for struct device Date: Fri, 21 Jun 2024 14:22:53 +0300 Message-Id: <20240621112303.1607621-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> References: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Use a temporary variable for the struct device pointers to avoid dereferencing. Signed-off-by: Claudiu Beznea --- drivers/i2c/busses/i2c-riic.c | 53 ++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 25 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index f608b1838cad..c08c988f50c7 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -131,11 +131,12 @@ static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) { struct riic_dev *riic = i2c_get_adapdata(adap); + struct device *dev = adap->dev.parent; unsigned long time_left; int i; u8 start_bit; - pm_runtime_get_sync(adap->dev.parent); + pm_runtime_get_sync(dev); if (riic_readb(riic, RIIC_ICCR2) & ICCR2_BBSY) { riic->err = -EBUSY; @@ -168,7 +169,7 @@ static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) } out: - pm_runtime_put(adap->dev.parent); + pm_runtime_put(dev); return riic->err ?: num; } @@ -303,11 +304,12 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) int ret = 0; unsigned long rate; int total_ticks, cks, brl, brh; + struct device *dev = riic->adapter.dev.parent; - pm_runtime_get_sync(riic->adapter.dev.parent); + pm_runtime_get_sync(dev); if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) { - dev_err(&riic->adapter.dev, + dev_err(dev, "unsupported bus speed (%dHz). %d max\n", t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ); ret = -EINVAL; @@ -347,7 +349,7 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) } if (brl > (0x1F + 3)) { - dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n", + dev_err(dev, "invalid speed (%lu). Too slow.\n", (unsigned long)t->bus_freq_hz); ret = -EINVAL; goto out; @@ -396,7 +398,7 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); out: - pm_runtime_put(riic->adapter.dev.parent); + pm_runtime_put(dev); return ret; } @@ -415,13 +417,14 @@ static void riic_reset_control_assert(void *data) static int riic_i2c_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct riic_dev *riic; struct i2c_adapter *adap; struct i2c_timings i2c_t; struct reset_control *rstc; int i, ret; - riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL); + riic = devm_kzalloc(dev, sizeof(*riic), GFP_KERNEL); if (!riic) return -ENOMEM; @@ -429,22 +432,22 @@ static int riic_i2c_probe(struct platform_device *pdev) if (IS_ERR(riic->base)) return PTR_ERR(riic->base); - riic->clk = devm_clk_get(&pdev->dev, NULL); + riic->clk = devm_clk_get(dev, NULL); if (IS_ERR(riic->clk)) { - dev_err(&pdev->dev, "missing controller clock"); + dev_err(dev, "missing controller clock"); return PTR_ERR(riic->clk); } - rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); + rstc = devm_reset_control_get_optional_exclusive(dev, NULL); if (IS_ERR(rstc)) - return dev_err_probe(&pdev->dev, PTR_ERR(rstc), + return dev_err_probe(dev, PTR_ERR(rstc), "Error: missing reset ctrl\n"); ret = reset_control_deassert(rstc); if (ret) return ret; - ret = devm_add_action_or_reset(&pdev->dev, riic_reset_control_assert, rstc); + ret = devm_add_action_or_reset(dev, riic_reset_control_assert, rstc); if (ret) return ret; @@ -453,29 +456,29 @@ static int riic_i2c_probe(struct platform_device *pdev) if (ret < 0) return ret; - ret = devm_request_irq(&pdev->dev, ret, riic_irqs[i].isr, + ret = devm_request_irq(dev, ret, riic_irqs[i].isr, 0, riic_irqs[i].name, riic); if (ret) { - dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name); + dev_err(dev, "failed to request irq %s\n", riic_irqs[i].name); return ret; } } - riic->info = of_device_get_match_data(&pdev->dev); + riic->info = of_device_get_match_data(dev); adap = &riic->adapter; i2c_set_adapdata(adap, riic); strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name)); adap->owner = THIS_MODULE; adap->algo = &riic_algo; - adap->dev.parent = &pdev->dev; - adap->dev.of_node = pdev->dev.of_node; + adap->dev.parent = dev; + adap->dev.of_node = dev->of_node; init_completion(&riic->msg_done); - i2c_parse_fw_timings(&pdev->dev, &i2c_t, true); + i2c_parse_fw_timings(dev, &i2c_t, true); - pm_runtime_enable(&pdev->dev); + pm_runtime_enable(dev); ret = riic_init_hw(riic, &i2c_t); if (ret) @@ -487,24 +490,24 @@ static int riic_i2c_probe(struct platform_device *pdev) platform_set_drvdata(pdev, riic); - dev_info(&pdev->dev, "registered with %dHz bus speed\n", - i2c_t.bus_freq_hz); + dev_info(dev, "registered with %dHz bus speed\n", i2c_t.bus_freq_hz); return 0; out: - pm_runtime_disable(&pdev->dev); + pm_runtime_disable(dev); return ret; } static void riic_i2c_remove(struct platform_device *pdev) { struct riic_dev *riic = platform_get_drvdata(pdev); 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([82.78.167.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6fd0838345sm64498466b.99.2024.06.21.04.23.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 04:23:19 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 03/12] i2c: riic: Call pm_runtime_get_sync() when need to access registers Date: Fri, 21 Jun 2024 14:22:54 +0300 Message-Id: <20240621112303.1607621-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> References: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea There is no need to runtime resume the device as long as the IP registers are not accessed. Calling pm_runtime_get_sync() at the register access time leads to a simpler error path. Signed-off-by: Claudiu Beznea --- drivers/i2c/busses/i2c-riic.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index c08c988f50c7..83e4d5e14ab6 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -301,19 +301,15 @@ static const struct i2c_algorithm riic_algo = { static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) { - int ret = 0; unsigned long rate; int total_ticks, cks, brl, brh; struct device *dev = riic->adapter.dev.parent; - pm_runtime_get_sync(dev); - if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) { dev_err(dev, "unsupported bus speed (%dHz). %d max\n", t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ); - ret = -EINVAL; - goto out; + return -EINVAL; } rate = clk_get_rate(riic->clk); @@ -351,8 +347,7 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) if (brl > (0x1F + 3)) { dev_err(dev, "invalid speed (%lu). Too slow.\n", (unsigned long)t->bus_freq_hz); - ret = -EINVAL; - goto out; + return -EINVAL; } brh = total_ticks - brl; @@ -384,6 +379,8 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) t->scl_fall_ns / (1000000000 / rate), t->scl_rise_ns / (1000000000 / rate), cks, brl, brh); + pm_runtime_get_sync(dev); + /* Changing the order of accessing IICRST and ICE may break things! */ riic_writeb(riic, ICCR1_IICRST | ICCR1_SOWP, RIIC_ICCR1); riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1); @@ -397,9 +394,8 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); -out: pm_runtime_put(dev); - return ret; + return 0; } static struct riic_irq_desc riic_irqs[] = { From patchwork Fri Jun 21 11:22:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 806426 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3285A176223 for ; Fri, 21 Jun 2024 11:23:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718969005; cv=none; b=aLeRVvORSY8tcbeOcOThv2HRnQKInMFucr/VZSpEK0taTab8w6pG4rxwmMJzmUM5gFxxfraix0/83l4canrTM3wK4TB2tbWEdlbyalnh12Vu4ppWPtQYtM9I4Qp8XnnzgZjtKeOqFwiiAF2matGczZUMhOSG0W567vDAsvPxJi4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718969005; c=relaxed/simple; bh=S1hm/Q+NuAcT9nxD/pVjadLD+I32CWUrwiArUqlGHZ4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=G8iYhYA0AZbK+nyso/9WI8oQVqjVwt49JOT/5//y9lrb5Fpz5Y88ldCiDMkoAyBR6uhclv1DVr7erOyN8PGzmfbKdNAyVYMsN56EQ0cB00XZKrZSlFzA57cMq7vfKXLvEX/tBsntilZneESSpJ0ZWLO5VYGQ1XaTQy1ohciC0zY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=GeZynVUt; arc=none smtp.client-ip=209.85.218.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="GeZynVUt" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-a6ef46d25efso215064266b.0 for ; Fri, 21 Jun 2024 04:23:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1718969002; x=1719573802; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2Q2S7HvfURtpVg3mGnjpDhomnr+bQTG6duN65cLSQuA=; b=GeZynVUtyNJ7ICUa+oeTYkvg05nCPYCHKrpxNRu4oAGR1PUDDW8QksNp7RoW9xMo47 EVz3gZiymrJhwTrnfKlyVGH2MZpCmoJ0RI45l0Kotpu88fhvliOoKIRMCEOv91KxcF5+ BI4pSgZ5Ajtn50Aw79Sg914/BstzazII0MW03GrTQBlX9tKzVDSK7v3MASrWpl8f4T2M rbCTY2T0gJ0zNPi+KBTWvL0stojZ+1T6SRt9yTX1rRuY8GnI/d+Wt/8d79enhuz25WM4 FbljAahvZX26/5fSR1nDXCwi+KXZmZMANLYoPlz2PEqwV7+KIXshqcXjph6CVjXIZh8z ADMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718969002; x=1719573802; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2Q2S7HvfURtpVg3mGnjpDhomnr+bQTG6duN65cLSQuA=; b=vlux1pBxGCrWlGT4TPcvYOD2Fr9gmeX/hkXGeGzTn1Sbk4SlaGb31A6s/6tmYKE3EJ cXLmYvydl/bGjhlvySdbml5Jj95VxymDr6+P817l1BTV37XYxt4P1SJqKvmwQAefzzyw RQNqvWGQ2pUVVfQZYZPVnCUk6AUV7k/XKV3gWKGJqtLx0jfoQr7BjsWCy7Wo4zdx+hM6 OweJqroL44dWpZP5i80elo7HtBFPgQHuIN9mvLxL7GYmuiUunSOoqMshLXYZQNTEryQF 6ekbZfF5XtGOwGMpMg55sinEYLRYgzTJh0YZczeVAuy7Exl/OJf3acaI3Z1hN4CDyPTR JHdw== X-Forwarded-Encrypted: i=1; AJvYcCU584MHZs//uRRJVH14OtWMTUHGiQO6zbhewLYH367mW3emEr1QLo5v9fuOR60LbpazH9vcKs7mjemcSCK9Ug4Fub6/x3D9Iqhm X-Gm-Message-State: AOJu0YzLF35wNxU4qkkY5ifWU7hXCSDUjMIbEWkvKjf2NbwyoLOEc9T8 utogk0r1f/RfN1bYWUSjAyHkGzfwige+wb+vaC98RRYK8U9lh10MR3Ot7w4lzoU= X-Google-Smtp-Source: AGHT+IFBywlMwo6ddeYYu3/kNuX5vO5gDzF03oKjx3N6oQ3I7NwLK+CukGLkpEtNcx6M4DcPC6fEDA== X-Received: by 2002:a17:906:c385:b0:a6f:5fc2:fe8b with SMTP id a640c23a62f3a-a6fab62f61dmr408251266b.32.1718969002596; Fri, 21 Jun 2024 04:23:22 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6fd0838345sm64498466b.99.2024.06.21.04.23.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 04:23:22 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 04/12] i2c: riic: Use pm_runtime_resume_and_get() Date: Fri, 21 Jun 2024 14:22:55 +0300 Message-Id: <20240621112303.1607621-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> References: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea pm_runtime_get_sync() may return with error. In case it returns with error dev->power.usage_count needs to be decremented. pm_runtime_resume_and_get() takes care of this. Thus use it. Signed-off-by: Claudiu Beznea --- drivers/i2c/busses/i2c-riic.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index 83e4d5e14ab6..6b739483ef37 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -113,6 +113,8 @@ struct riic_irq_desc { char *name; }; +static const char * const riic_rpm_err_msg = "Failed to runtime resume"; + static inline void riic_writeb(struct riic_dev *riic, u8 val, u8 offset) { writeb(val, riic->base + riic->info->regs[offset]); @@ -133,10 +135,14 @@ static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) struct riic_dev *riic = i2c_get_adapdata(adap); struct device *dev = adap->dev.parent; unsigned long time_left; - int i; + int i, ret; u8 start_bit; - pm_runtime_get_sync(dev); + ret = pm_runtime_resume_and_get(dev); + if (ret) { + dev_err(dev, riic_rpm_err_msg); + return ret; + } if (riic_readb(riic, RIIC_ICCR2) & ICCR2_BBSY) { riic->err = -EBUSY; @@ -301,6 +307,7 @@ static const struct i2c_algorithm riic_algo = { static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) { + int ret; unsigned long rate; int total_ticks, cks, brl, brh; struct device *dev = riic->adapter.dev.parent; @@ -379,7 +386,11 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) t->scl_fall_ns / (1000000000 / rate), t->scl_rise_ns / (1000000000 / rate), cks, brl, brh); - pm_runtime_get_sync(dev); + ret = pm_runtime_resume_and_get(dev); + if (ret) { + dev_err(dev, riic_rpm_err_msg); + return ret; + } /* Changing the order of accessing IICRST and ICE may break things! */ riic_writeb(riic, ICCR1_IICRST | ICCR1_SOWP, RIIC_ICCR1); @@ -498,8 +509,14 @@ static void riic_i2c_remove(struct platform_device *pdev) { struct riic_dev *riic = platform_get_drvdata(pdev); struct device *dev = &pdev->dev; + int ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret) { + dev_err(dev, riic_rpm_err_msg); + return; + } - pm_runtime_get_sync(dev); riic_writeb(riic, 0, RIIC_ICIER); pm_runtime_put(dev); i2c_del_adapter(&riic->adapter); From patchwork Fri Jun 21 11:22:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 806929 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5884176258 for ; Fri, 21 Jun 2024 11:23:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718969008; cv=none; b=lQvExXfUOzvCAIlXoyc7coKkLCiBL2Kl4bpG4I40X7m3US0LPaX8sHvCWDh3B0yUm+7tsAYlUgGbMF1vr0htWfY7zZwPtwkJAo7sY/mVt1UYbDHb9TWp8TxKSeGWvJN044AUyPffowK5i1EJkGkIDdnT3vj5WMbdbU6p8tbXF+I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718969008; c=relaxed/simple; bh=wovYL+KBiDSSeNAZuqj5Clu00lS6lYUfaKOjsQH6z1I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rqf1f+uKSovI5eGDm40gnq8w/x3Sx2n3snMsamuq3Kss+0EPnQA5+7drmimJcmd1hcz1OsmozHdybbEpqSM5N9arGh7Dj18cO7Pk7j3Lb0tZhdRon1LpMPeVbH5BOHR7s1QAxgAJqbZd6vQR1BVOAPTbz0fx3Y2cMx3MD7zVGks= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=DxdgPVxd; arc=none smtp.client-ip=209.85.218.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="DxdgPVxd" Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-a6ef793f4b8so194166466b.1 for ; Fri, 21 Jun 2024 04:23:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1718969005; x=1719573805; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dW9T/eZM5RV9t43dNQ65JhpJklu5g8GWF2aDPxi7wbI=; b=DxdgPVxdNQdH85Kp1i4VWsWAgJ3HtfIyaLY4BZz6QHWxDAP4zhdUXom5tupZJhc8Mp 8O4OMWAm1jHiiahWlnwQc0zPtKT45bsoZ6MqhII3ZbYLca0HIC4s+ba8loBEDXGMNJOP LvVzCSkghK4nPykmblRYAFgP2QlTc5i8wKjwlL90T9X5lNz1ZetDTVtV/QQ2zi6JJNJH tLmHJXRUA5yrUMTQZrne2RAgWRBCWgAAa+9UXydzcc/GM2+miV6T/djEELurH8g8J1uD wSm0RKNnf9kzCH78uDSxhXGURYLR9HoZS7pMCfxX31uZ7bCr9I3ARmZY1PSAliZn5/3F j6zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718969005; x=1719573805; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dW9T/eZM5RV9t43dNQ65JhpJklu5g8GWF2aDPxi7wbI=; b=nI8/BKotF/jbRuifXV3Eo5WjUuzBGvUY2Qx1ekzyIhNpDzzXpCVhc8Ohz0RNd9o58c OKHBlEKfGCOubXQKecr/bp0INSFH4cNP66KO2Vpk7QbRFHiUOzVcFqcxtfRgoyJ9k978 UQR0qpe547AAFk/gm/0lXb0IZLsc2PdHlHOn7d6DD0sGJI5S7IYG+qI471ZRYtG+QuDt gPpb0hlEuzGtq3jtZb7C0r8ylHLge7bFhseNnkVxXFgdhlbPOXpO78OKidQOqNOeG9sF 85rCwUHey8tBvoDxIpkldHY3RmjTe44BceU9P5dA4w8+t0bs/s4Ki15h0bzwCcqoSiB/ XhSg== X-Forwarded-Encrypted: i=1; AJvYcCVWEjhVIvyzVIx0g/KxDYmcmenkRImZNtdePV7m7uJcq4bADFohcbeTRNLtykP5DmVDJPzefxdg0OeTDuLy9P06FOYXeNr10p74 X-Gm-Message-State: AOJu0Yz77jTGgBPuSSei1qpMTSSH7SQLTxzUrI6Reg7xUC474PXYTV9I XzLqR029J7b13TZc0sQ1CeqAK4uKyvEwV6zDzAdKAGWtan8f0lwoU37kcfnppZc= X-Google-Smtp-Source: AGHT+IFy1kAEcnlAOSo5nHvfvKjAEwLrS0YbBwtI4Y6CfpkEaCc5opX+RA9D00tsKvOBrO+igWIdbg== X-Received: by 2002:a17:907:c80a:b0:a6f:bdb3:9748 with SMTP id a640c23a62f3a-a6fbdb397e2mr314408366b.33.1718969005480; Fri, 21 Jun 2024 04:23:25 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6fd0838345sm64498466b.99.2024.06.21.04.23.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 04:23:24 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 05/12] i2c: riic: Enable runtime PM autosuspend support Date: Fri, 21 Jun 2024 14:22:56 +0300 Message-Id: <20240621112303.1607621-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> References: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable runtime PM autosuspend support for the RIIC driver. With this, in case there are consecutive xfer requests the device wouldn't be runtime enabled/disabled after each consecutive xfer but after the the delay configured by user. With this, we can avoid touching hardware registers involved in runtime PM suspend/resume saving in this way some cycles. The default chosen autosuspend delay is zero to keep the previous driver behavior. Signed-off-by: Claudiu Beznea --- drivers/i2c/busses/i2c-riic.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index 6b739483ef37..00fb09786e48 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -175,7 +175,8 @@ static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) } out: - pm_runtime_put(dev); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); return riic->err ?: num; } @@ -405,7 +406,8 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); - pm_runtime_put(dev); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); return 0; } @@ -485,6 +487,8 @@ static int riic_i2c_probe(struct platform_device *pdev) i2c_parse_fw_timings(dev, &i2c_t, true); + pm_runtime_set_autosuspend_delay(dev, 0); + pm_runtime_use_autosuspend(dev); pm_runtime_enable(dev); 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([82.78.167.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6fd0838345sm64498466b.99.2024.06.21.04.23.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 04:23:27 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 06/12] i2c: riic: Add suspend/resume support Date: Fri, 21 Jun 2024 14:22:57 +0300 Message-Id: <20240621112303.1607621-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> References: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add suspend/resume support for the RIIC driver. This is necessary for the Renesas RZ/G3S SoC which support suspend to deep sleep state where power to most of the SoC components is turned off. As a result the I2C controller needs to be reconfigured after suspend/resume. For this, the reset line was stored in the driver private data structure as well as i2c timings. The reset line and I2C timings are necessary to re-initialize the controller after resume. Signed-off-by: Claudiu Beznea --- drivers/i2c/busses/i2c-riic.c | 66 +++++++++++++++++++++++++++++------ 1 file changed, 55 insertions(+), 11 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index 00fb09786e48..f9b9e92570d8 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -105,6 +105,8 @@ struct riic_dev { struct completion msg_done; struct i2c_adapter adapter; struct clk *clk; + struct reset_control *rstc; + struct i2c_timings i2c_t; }; struct riic_irq_desc { @@ -306,11 +308,12 @@ static const struct i2c_algorithm riic_algo = { .functionality = riic_func, }; -static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) +static int riic_init_hw(struct riic_dev *riic) { int ret; unsigned long rate; int total_ticks, cks, brl, brh; + struct i2c_timings *t = &riic->i2c_t; struct device *dev = riic->adapter.dev.parent; if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) { @@ -429,8 +432,6 @@ static int riic_i2c_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct riic_dev *riic; struct i2c_adapter *adap; - struct i2c_timings i2c_t; - struct reset_control *rstc; int i, ret; riic = devm_kzalloc(dev, sizeof(*riic), GFP_KERNEL); @@ -447,16 +448,16 @@ static int riic_i2c_probe(struct platform_device *pdev) return PTR_ERR(riic->clk); } - rstc = devm_reset_control_get_optional_exclusive(dev, NULL); - if (IS_ERR(rstc)) - return dev_err_probe(dev, PTR_ERR(rstc), + riic->rstc = devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(riic->rstc)) + return dev_err_probe(dev, PTR_ERR(riic->rstc), "Error: missing reset ctrl\n"); - ret = reset_control_deassert(rstc); + ret = reset_control_deassert(riic->rstc); if (ret) return ret; - ret = devm_add_action_or_reset(dev, riic_reset_control_assert, rstc); + ret = devm_add_action_or_reset(dev, riic_reset_control_assert, riic->rstc); if (ret) return ret; @@ -485,13 +486,13 @@ static int riic_i2c_probe(struct platform_device *pdev) init_completion(&riic->msg_done); - i2c_parse_fw_timings(dev, &i2c_t, true); + i2c_parse_fw_timings(dev, &riic->i2c_t, true); pm_runtime_set_autosuspend_delay(dev, 0); pm_runtime_use_autosuspend(dev); pm_runtime_enable(dev); - ret = riic_init_hw(riic, &i2c_t); + ret = riic_init_hw(riic); if (ret) goto out; @@ -501,7 +502,7 @@ static int riic_i2c_probe(struct platform_device *pdev) platform_set_drvdata(pdev, riic); - dev_info(dev, "registered with %dHz bus speed\n", i2c_t.bus_freq_hz); + dev_info(dev, "registered with %dHz bus speed\n", riic->i2c_t.bus_freq_hz); return 0; out: @@ -561,6 +562,48 @@ static const struct riic_of_data riic_rz_v2h_info = { }, }; +static int riic_i2c_suspend(struct device *dev) +{ + struct riic_dev *riic = dev_get_drvdata(dev); + int ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + i2c_mark_adapter_suspended(&riic->adapter); + + /* Disable output on SDA, SCL pins. */ + riic_clear_set_bit(riic, ICCR1_ICE, 0, RIIC_ICCR1); + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_sync(dev); + + return reset_control_assert(riic->rstc); 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([82.78.167.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6fd0838345sm64498466b.99.2024.06.21.04.23.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 04:23:29 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 07/12] i2c: riic: Define individual arrays to describe the register offsets Date: Fri, 21 Jun 2024 14:22:58 +0300 Message-Id: <20240621112303.1607621-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> References: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Define individual arrays to describe the register offsets. In this way we can describe different IP variants that share the same register offsets but have differences in other characteristics. Commit prepares for the addition of fast mode plus. Signed-off-by: Claudiu Beznea --- drivers/i2c/busses/i2c-riic.c | 58 +++++++++++++++++++---------------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index f9b9e92570d8..46070f323810 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -91,7 +91,7 @@ enum riic_reg_list { }; struct riic_of_data { - u8 regs[RIIC_REG_END]; + const u8 *regs; }; struct riic_dev { @@ -530,36 +530,40 @@ static void riic_i2c_remove(struct platform_device *pdev) pm_runtime_dont_use_autosuspend(dev); } +static const u8 riic_rz_a_regs[RIIC_REG_END] = { + [RIIC_ICCR1] = 0x00, + [RIIC_ICCR2] = 0x04, + [RIIC_ICMR1] = 0x08, + [RIIC_ICMR3] = 0x10, + [RIIC_ICSER] = 0x18, + [RIIC_ICIER] = 0x1c, + [RIIC_ICSR2] = 0x24, + [RIIC_ICBRL] = 0x34, + [RIIC_ICBRH] = 0x38, + [RIIC_ICDRT] = 0x3c, + [RIIC_ICDRR] = 0x40, +}; + static const struct riic_of_data riic_rz_a_info = { - .regs = { - [RIIC_ICCR1] = 0x00, - [RIIC_ICCR2] = 0x04, - [RIIC_ICMR1] = 0x08, - [RIIC_ICMR3] = 0x10, - [RIIC_ICSER] = 0x18, - [RIIC_ICIER] = 0x1c, - [RIIC_ICSR2] = 0x24, - [RIIC_ICBRL] = 0x34, - [RIIC_ICBRH] = 0x38, - [RIIC_ICDRT] = 0x3c, - [RIIC_ICDRR] = 0x40, - }, + .regs = riic_rz_a_regs, +}; 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([82.78.167.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6fd0838345sm64498466b.99.2024.06.21.04.23.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 04:23:31 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 08/12] dt-bindings: i2c: renesas, riic: Document the R9A08G045 support Date: Fri, 21 Jun 2024 14:22:59 +0300 Message-Id: <20240621112303.1607621-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> References: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is compatible with the version available on Renesas RZ/V2H (R9A09G075). Most of the IP variants that the RIIC driver is working with supports fast mode plus. However, it happens that on the same SoC to have IP instatiations that support fast mode plus as well as IP instantiation that doesn't support it. For this, introduced the renesas,riic-no-fast-mode-plus property. Signed-off-by: Claudiu Beznea --- Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml index 91ecf17b7a81..c0964edbca69 100644 --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml @@ -25,6 +25,10 @@ properties: - renesas,riic-r9a07g054 # RZ/V2L - const: renesas,riic-rz # RZ/A or RZ/G2L + - items: + - const: renesas,riic-r9a08g045 # RZ/G3S + - const: renesas,riic-r9a09g057 + - const: renesas,riic-r9a09g057 # RZ/V2H(P) reg: @@ -66,6 +70,10 @@ properties: resets: maxItems: 1 + renesas,riic-no-fast-mode-plus: + description: specifies if fast mode plus is not supported + type: boolean + required: - compatible - reg From patchwork Fri Jun 21 11:23:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 806927 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D9A01791EF for ; Fri, 21 Jun 2024 11:23:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718969018; cv=none; b=Lm/8EWKbBkAUeiinMUqGVFgmZAmE/7kvzpgPikZsqucs0WtYuY+E1yGcUa7npBq1jS1I4vI7nyeMM/NyA7XbunTsrLEXf7MVqBz1Lxv17zpX5W3G7aM/kNC7aUGmvV3Q0jhBzEFaU+6AZrxymciisWhTFalPaY3zyGrwNF+nSFg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718969018; c=relaxed/simple; bh=ij3uV6J3X/K1ZAOcphoXyGB9f+JD3XmCdAzZi2OaBxA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=teXI6JGppNq+RVt7QT2WBcvtaxqNhQDc2YRtldk2ts3TqbKKzDSzTDakC/EjrE7aEYT71hYFGAhMSXwFDpogf2bf2/2aHrNfk5LJkE1TCFvWYCsLTRwbA82SJ9M6P0DAgKesjfkb0B62ZE3f2hwotQGg/z8S4mLacuWS2UDxaJU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=JslEfuNu; arc=none smtp.client-ip=209.85.218.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="JslEfuNu" Received: by mail-ej1-f52.google.com with SMTP id a640c23a62f3a-a6e43dad8ecso322699866b.1 for ; Fri, 21 Jun 2024 04:23:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1718969015; x=1719573815; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mzooG8q3y54I5nVFOpy/sRgqo30+e1A/eDOSMBNJffw=; b=JslEfuNua7tF8zrwb/sqVIAntRhFQXlEvBShMqzz5q/DJ2E5w8H+OZ+y26Q5Gra7s1 fV9PriJ4sI88xVH3eG917b28ZYDDctSqQZqcASvuJ9DWe5MRmOgHB2MuOqowqJf0/0zV 8XNhi/qvIyOj52nhQACcHFtNYKz59YC9NJ4a8W6lO+IeW1jjZtuXVlVauCP7f40hGvAp yT+SOg1z0RovIpjn76fA5yITGL+s293r5AEWXqzhYx3oy9lGkZPQtxSVZDWzWHBtgNHg cC1B2OJKclDRXzJHU0Z6JKhUtLsXNepG/Vyq+Y+XTIruTz0LmHd5yPZhOFlEf10a4Rsc mvlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718969015; x=1719573815; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mzooG8q3y54I5nVFOpy/sRgqo30+e1A/eDOSMBNJffw=; b=drTy/N1+B9uZAD6BgkP9UPchGtOCkLZ4kp6INrBN8+BZAmAEUCprFj9n3pu70aBdZI dXhDZxt9hgQ55lNpIyAdsARj6V9yrq7f570Pl49wzi4RujiXuCvqojr2KnR/m+yzpUia +OERGJHAMXV1avwOWpwTD4K52ETck2Mc8K9DkHZUl7nR32RBRbIBrrxryhY2xqxS+K5p Fx/gFZNCyZAM9eBExtwe1jzXlOuaz4iASVYNBVW/5FBl+RCv2UCeLmu6+FkgWKJFoZsF ogrNAQmE8d7qcTnNPn8JSMzdlaWaCXHt6Xs/1MQlNZOi/7b+FDwVsdZ5uM2huVsU2kam rIug== X-Forwarded-Encrypted: i=1; AJvYcCUL4n2uCOE9lHvx3WTK/mc2W0jm0rsIuVu8q8/RjifcPRNrpqvxDA7BfnsZ/Zijut7riD/xWwiFQIYPOgT/1rUivF6zQ80dZnP4 X-Gm-Message-State: AOJu0Ywbr/vZCWhCOYymyyakXYMsTOTqH5Duuahu6aX8hgVvussPTNad aR211g2PhPfaTf+p6y8jcXHIweJ32R/fFKl8WvYeVJLMaknT/SW9CMb6t1m2thQ= X-Google-Smtp-Source: AGHT+IGlGxv7FMPWXU1mq1C+qo0WZXeJY4oV0Qo4ZYYvf0BrFDYx+1/DPENJzXqHjmukDxE4Y0PLYg== X-Received: by 2002:a17:907:c205:b0:a6e:f53c:8da0 with SMTP id a640c23a62f3a-a6fa40d43c0mr648572866b.8.1718969014938; Fri, 21 Jun 2024 04:23:34 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6fd0838345sm64498466b.99.2024.06.21.04.23.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 04:23:34 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 09/12] i2c: riic: Add support for fast mode plus Date: Fri, 21 Jun 2024 14:23:00 +0300 Message-Id: <20240621112303.1607621-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> References: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Fast mode plus is available on most of the IP variants that RIIC driver is working with. The exception is (according to HW manuals of the SoCs where this IP is available) the Renesas RZ/A1H. Along with it, according to the RZ/G3S HW manual, chapter 47.5.15 I2C Bus Interface Access Timing, note 7, Tfmin cannot meet the specification in fast-mode plus for the RIIC ch2 and ch3. Due to these limitations: - the struct riic_of_data::fast_mode_plus was introduced to address the Renesas RZ/A1H use case - the renesas,riic-no-fast-mode-plus was introduced to address the Renesas RZ/G3S limitation. Fast mode plus was tested on RZ/G3S, RZ/G2{L,UL,LC}, RZ/Five by instantiating the RIIC frequency to 1MHz and issuing i2c reads on the fast mode plus capable devices (and the i2c clock frequency was checked on RZ/G3S). Signed-off-by: Claudiu Beznea --- drivers/i2c/busses/i2c-riic.c | 36 +++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index 46070f323810..d246143a1037 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -63,6 +63,8 @@ #define ICMR3_ACKWP 0x10 #define ICMR3_ACKBT 0x08 +#define ICFER_FMPE 0x80 + #define ICIER_TIE 0x80 #define ICIER_TEIE 0x40 #define ICIER_RIE 0x20 @@ -80,6 +82,7 @@ enum riic_reg_list { RIIC_ICCR2, RIIC_ICMR1, RIIC_ICMR3, + RIIC_ICFER, RIIC_ICSER, RIIC_ICIER, RIIC_ICSR2, @@ -92,6 +95,7 @@ enum riic_reg_list { struct riic_of_data { const u8 *regs; + bool fast_mode_plus; }; struct riic_dev { @@ -107,6 +111,7 @@ struct riic_dev { struct clk *clk; struct reset_control *rstc; struct i2c_timings i2c_t; + bool fast_mode_plus; }; struct riic_irq_desc { @@ -316,10 +321,11 @@ static int riic_init_hw(struct riic_dev *riic) struct i2c_timings *t = &riic->i2c_t; struct device *dev = riic->adapter.dev.parent; - if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) { - dev_err(dev, - "unsupported bus speed (%dHz). %d max\n", - t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ); + if ((!riic->fast_mode_plus && t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) || + (riic->fast_mode_plus && t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)) { + dev_err(dev, "unsupported bus speed (%dHz). %d max\n", t->bus_freq_hz, + riic->fast_mode_plus ? I2C_MAX_FAST_MODE_PLUS_FREQ : + I2C_MAX_FAST_MODE_FREQ); return -EINVAL; } @@ -407,6 +413,9 @@ static int riic_init_hw(struct riic_dev *riic) riic_writeb(riic, 0, RIIC_ICSER); riic_writeb(riic, ICMR3_ACKWP | ICMR3_RDRFS, RIIC_ICMR3); + if (riic->fast_mode_plus && t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ) + riic_clear_set_bit(riic, 0, ICFER_FMPE, RIIC_ICFER); + riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); pm_runtime_mark_last_busy(dev); @@ -487,6 +496,14 @@ static int riic_i2c_probe(struct platform_device *pdev) init_completion(&riic->msg_done); i2c_parse_fw_timings(dev, &riic->i2c_t, true); + if (riic->info->fast_mode_plus) { + /* + * On the same SoC it may happen to have IP variants that support + * fast mode plus as well as IP variants that doesn't support it. + */ + riic->fast_mode_plus = !of_property_read_bool(dev->of_node, + "renesas,riic-no-fast-mode-plus"); + } pm_runtime_set_autosuspend_delay(dev, 0); pm_runtime_use_autosuspend(dev); @@ -535,6 +552,7 @@ static const u8 riic_rz_a_regs[RIIC_REG_END] = { [RIIC_ICCR2] = 0x04, [RIIC_ICMR1] = 0x08, [RIIC_ICMR3] = 0x10, + [RIIC_ICFER] = 0x14, [RIIC_ICSER] = 0x18, [RIIC_ICIER] = 0x1c, [RIIC_ICSR2] = 0x24, @@ -548,11 +566,17 @@ static const struct riic_of_data riic_rz_a_info = { .regs = riic_rz_a_regs, }; +static const struct riic_of_data riic_rz_g2_info = { + .regs = riic_rz_a_regs, + .fast_mode_plus = true, +}; + static const u8 riic_rz_v2h_regs[RIIC_REG_END] = { [RIIC_ICCR1] = 0x00, [RIIC_ICCR2] = 0x01, [RIIC_ICMR1] = 0x02, [RIIC_ICMR3] = 0x04, + [RIIC_ICFER] = 0x05, [RIIC_ICSER] = 0x06, [RIIC_ICIER] = 0x07, [RIIC_ICSR2] = 0x09, @@ -564,6 +588,7 @@ static const u8 riic_rz_v2h_regs[RIIC_REG_END] = { static const struct riic_of_data riic_rz_v2h_info = { .regs = riic_rz_v2h_regs, + .fast_mode_plus = true, }; static int riic_i2c_suspend(struct device *dev) @@ -610,6 +635,9 @@ static const struct dev_pm_ops riic_i2c_pm_ops = { static const struct of_device_id riic_i2c_dt_ids[] = { { .compatible = "renesas,riic-rz", .data = &riic_rz_a_info }, + { .compatible = "renesas,riic-r9a07g043", .data = &riic_rz_g2_info, }, + { .compatible = "renesas,riic-r9a07g044", .data = &riic_rz_g2_info, }, + { .compatible = "renesas,riic-r9a07g054", .data = &riic_rz_g2_info, }, { .compatible = "renesas,riic-r9a09g057", .data = &riic_rz_v2h_info }, { /* Sentinel */ }, }; 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([82.78.167.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6fd0838345sm64498466b.99.2024.06.21.04.23.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 04:23:36 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 10/12] arm64: dts: renesas: r9a08g045: Add I2C nodes Date: Fri, 21 Jun 2024 14:23:01 +0300 Message-Id: <20240621112303.1607621-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> References: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The Renesas RZ/G3S has 4 I2C channels. Add DT nodes for it. Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 90 ++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 2162c247d6de..cc5beed37ae8 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,96 @@ scif0: serial@1004b800 { status = "disabled"; }; + i2c0: i2c@10090000 { + compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; + reg = <0 0x10090000 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A08G045_I2C0_MRST>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@10090400 { + compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; + reg = <0 0x10090400 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A08G045_I2C1_MRST>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@10090800 { + compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; + reg = <0 0x10090800 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A08G045_I2C2_MRST>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + renesas,riic-no-fast-mode-plus; + status = "disabled"; + }; + + i2c3: i2c@10090c00 { + compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; + reg = <0 0x10090c00 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; 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([82.78.167.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6fd0838345sm64498466b.99.2024.06.21.04.23.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 04:23:39 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 11/12] arm64: dts: renesas: rzg3s-smarc: Enable i2c0 node Date: Fri, 21 Jun 2024 14:23:02 +0300 Message-Id: <20240621112303.1607621-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> References: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable i2c0 node. Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index deb2ad37bb2e..7945d44e6ee1 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -11,6 +11,7 @@ / { aliases { + i2c0 = &i2c0; serial0 = &scif0; mmc1 = &sdhi1; }; @@ -66,6 +67,12 @@ vccq_sdhi1: regulator-vccq-sdhi1 { }; }; +&i2c0 { + status = "okay"; + + clock-frequency = <1000000>; +}; + &pinctrl { key-1-gpio-hog { gpio-hog; From patchwork Fri Jun 21 11:23:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 806422 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4196B17B43D for ; Fri, 21 Jun 2024 11:23:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718969024; cv=none; b=T1NRJGGaMqmb9hx4jxTZrEnH+hla/yd6iMztUKNCpOYgPEi9ZeYZd1XFoMhbMTpGOhKTDuuFQFN/Ar0bnpWKYdJ3T2MTj2OWe7WpQYLCWAr7Twz235kGaMP2Becsa7u0/QN59GNyS72OlnkexA3zeWYAxRCVikgkt6gh+oqJdWw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718969024; c=relaxed/simple; bh=n02VnI1z3Lo/vCVvdYX3gNJ/na1w3LKQu6cqOd+GMII=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cxMqy4NeIH81GQZUu5Vz6YgiaibWDztA5S4tUgkuoZD4BDdaGvL9cOg4P9nwKYspe+3UtEqkE4ikpwdqUUurke31V4cNbHXJ+Cyp745VV8mRrmOO4JLKWgRQh0M+PWbg/cuOORjB87f658YA0uUJ4q6orzzBbP0My02nRHWGUE0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=e8GGMkk+; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="e8GGMkk+" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-a6f1da33826so239062166b.0 for ; Fri, 21 Jun 2024 04:23:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1718969021; x=1719573821; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=veIrjSKIW0msyP1BPKwCOv7rRYyO3ebgm2ScapHwacw=; b=e8GGMkk+MEXMMx8ecWdrmUcnfitLVwhwuDlqjvGYpUyGhaWvRXyN5hdsYkLxR7tuV1 IuxOuTN7n8C/W6q8+nERUdyT7V/jcGADm4gRzAneS+IkzEAxyJSSciw2rwOxAi3LmpzY ajVubbLI+apSF3iG7ocIzwYsbcVXO9EB1er0xxTY/3JmfhNZQYeGC5yEUZGQJffmVGI4 3Ymvez3WGcJ1juZQ0TVoJI/ywBLAmc508wv2kQE0naQuF1ni/bTnnCRYx+NcpnGHaHj6 AlqSrHwEmsKSxrXxk+caxlBNtZAO8qJPJgJL5mKPq9kypOiiK7xqbY2H5MVCSy43L9NN cOaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718969021; x=1719573821; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=veIrjSKIW0msyP1BPKwCOv7rRYyO3ebgm2ScapHwacw=; b=Fwrli7b/UtaOHHpnFvqCUpnoQfM9qEtIvFuVrrJvApmvcatlmNqZoDmKMvy7hb7BrM 8G4Pfhlj370niLuwl75l+YQc7rN2kcHaDsiVlfZIp8SrqSiu8kHbCLh9cVuZoskbKp1f iRjIAoVpTHizstus6kt22RK8VZKS6vdxglcP7E6ZLhR5Kaca2kAl+6Nb/quCyL3ppy0f 0d0oOdgSiJQHqAR6SMffUx8ZoGDAbl6sVnZadKuyPNBrYs50YHYG5VOnsgQ6yRFgR9s7 wHWoEO/NbFEEI3619lOMevUVI/Bq1g9p4nRWHWF6CT6WHuXFpEY4K9MxUjmEdeq8uqTP Sl7Q== X-Forwarded-Encrypted: i=1; AJvYcCVATWq4Zowraea/XDoqTJLMHDDYTkBJkyjwCrZKOgnQc5EBY0dHLKqHmwMuUWPoeGjx4Aqoc7oqtD9bZ4tpqGPUb4U2mupzxkUZ X-Gm-Message-State: AOJu0YzQgECQTp1rMWj31Bx4/Ou9ua74p0RgyTaktUo+QTXz1wJd7C5L d9TRns4XPprT4iwwOIbZabN2Nk68aYMYtv8opK98ZR6afpL0cIOecef+efhmLqa7XnO2SNCifzG Y X-Google-Smtp-Source: AGHT+IEEH1uXQ9SWBQpZ3LT5PHwfn4wvDC947Dj2o3fom2F9AP5MXqF9KQPaa6c5ngH5rqOd6vpGow== X-Received: by 2002:a17:907:ca1b:b0:a63:49d3:e1c5 with SMTP id a640c23a62f3a-a6fab7d6a8emr476914666b.64.1718969021696; Fri, 21 Jun 2024 04:23:41 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6fd0838345sm64498466b.99.2024.06.21.04.23.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 04:23:41 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 12/12] arm64: dts: renesas: rzg3s-smarc-som: Enable i2c1 node Date: Fri, 21 Jun 2024 14:23:03 +0300 Message-Id: <20240621112303.1607621-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> References: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable i2c1 node. Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 8a3d302f1535..21bfa4e03972 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -32,6 +32,7 @@ / { compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; aliases { + i2c1 = &i2c1; mmc0 = &sdhi0; #if SW_CONFIG3 == SW_OFF mmc2 = &sdhi2; @@ -150,6 +151,10 @@ &extal_clk { clock-frequency = <24000000>; }; +&i2c1 { + status = "okay"; +}; + #if SW_CONFIG2 == SW_ON /* SD0 slot */ &sdhi0 {