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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Varadarajan Narayanan --- v2: Add Reviewed-by --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom-rpmpd.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 929b7ef9c1bc..e20ba25fa094 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - enum: + - qcom,ipq9574-rpmpd - qcom,mdm9607-rpmpd - qcom,msm8226-rpmpd - qcom,msm8909-rpmpd diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 608087fb9a3d..0538370bfbb4 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -402,6 +402,9 @@ #define QCM2290_VDD_LPI_CX 6 #define QCM2290_VDD_LPI_MX 7 +/* IPQ9574 Power Domains */ +#define IPQ9574_VDDAPC 0 + /* RPM SMD Power Domain performance levels */ #define RPM_SMD_LEVEL_RETENTION 16 #define RPM_SMD_LEVEL_RETENTION_PLUS 32 From patchwork Mon Jun 24 05:02:50 2024 Content-Type: text/plain; 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Signed-off-by: Praveenkumar I Signed-off-by: Varadarajan Narayanan --- v2: Fix Signed-off-by order --- drivers/pmdomain/qcom/rpmpd.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pmdomain/qcom/rpmpd.c b/drivers/pmdomain/qcom/rpmpd.c index 5e6280b4cf70..947d6a9c3897 100644 --- a/drivers/pmdomain/qcom/rpmpd.c +++ b/drivers/pmdomain/qcom/rpmpd.c @@ -38,6 +38,7 @@ static struct qcom_smd_rpm *rpmpd_smd_rpm; #define KEY_FLOOR_CORNER 0x636676 /* vfc */ #define KEY_FLOOR_LEVEL 0x6c6676 /* vfl */ #define KEY_LEVEL 0x6c766c76 /* vlvl */ +#define RPM_KEY_UV 0x00007675 /* "uv" */ #define MAX_CORNER_RPMPD_STATE 6 @@ -644,6 +645,23 @@ static const struct rpmpd_desc mdm9607_desc = { .max_state = RPM_SMD_LEVEL_TURBO, }; +static struct rpmpd apc_s1_lvl = { + .pd = { .name = "apc", }, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = RPM_KEY_UV, +}; + +static struct rpmpd *ipq9574_rpmpds[] = { + [IPQ9574_VDDAPC] = &apc_s1_lvl, +}; + +static const struct rpmpd_desc ipq9574_desc = { + .rpmpds = ipq9574_rpmpds, + .num_pds = ARRAY_SIZE(ipq9574_rpmpds), + .max_state = RPM_SMD_LEVEL_TURBO_HIGH, +}; + static struct rpmpd *msm8226_rpmpds[] = { [MSM8226_VDDCX] = &cx_s1a_corner, [MSM8226_VDDCX_AO] = &cx_s1a_corner_ao, @@ -931,6 +949,7 @@ static const struct rpmpd_desc qcm2290_desc = { }; static const struct of_device_id rpmpd_match_table[] = { + { .compatible = "qcom,ipq9574-rpmpd", .data = &ipq9574_desc }, { .compatible = "qcom,mdm9607-rpmpd", .data = &mdm9607_desc }, { .compatible = "qcom,msm8226-rpmpd", .data = &msm8226_desc }, { .compatible = "qcom,msm8909-rpmpd", .data = &msm8916_desc }, From patchwork Mon Jun 24 05:02:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 807176 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4682D28DCB; Mon, 24 Jun 2024 05:04:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 24 Jun 2024 05:03:57 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45O53uOW019979 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Jun 2024 05:03:56 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 23 Jun 2024 22:03:50 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 5/7] clk: qcom: gcc-ipq9574: Add CPR clock definition Date: Mon, 24 Jun 2024 10:32:52 +0530 Message-ID: <20240624050254.2942959-6-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624050254.2942959-1-quic_varada@quicinc.com> References: <20240624050254.2942959-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: AmgOaITc3MKwIquDDCOGyLaxltRo3GeM X-Proofpoint-GUID: AmgOaITc3MKwIquDDCOGyLaxltRo3GeM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-24_04,2024-06-21_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 spamscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406240038 Add the CPR clock definition needed for enabling access to CPR register space. Signed-off-by: Varadarajan Narayanan --- v2: Add rbcpr_clk_src to gcc_ipq9574_hws for registration. --- drivers/clk/qcom/gcc-ipq9574.c | 39 ++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index e1dc74d04ed1..eac557937fd3 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -3994,6 +3994,43 @@ static struct clk_branch gcc_xo_div4_clk = { }, }; +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { + F(24000000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 rbcpr_clk_src = { + .cmd_rcgr = 0x48044, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_xo_map, + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "rbcpr_clk_src", + .parent_data = gcc_xo_gpll0_gpll4, + .num_parents = ARRAY_SIZE(gcc_xo_map), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_rbcpr_clk = { + .halt_reg = 0x48008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x48008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rbcpr_clk", + .parent_hws = (const struct clk_hw *[]) { + &rbcpr_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_hw *gcc_ipq9574_hws[] = { &gpll0_out_main_div2.hw, &gcc_xo_div4_clk_src.hw, @@ -4219,6 +4256,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, + [GCC_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, + [GCC_RBCPR_CLK] = &gcc_rbcpr_clk.clkr, }; static const struct qcom_reset_map gcc_ipq9574_resets[] = { From patchwork Mon Jun 24 05:02:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 807175 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3053539AD6; Mon, 24 Jun 2024 05:04:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 24 Jun 2024 05:04:10 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45O549mm029531 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Jun 2024 05:04:09 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 23 Jun 2024 22:04:03 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 7/7] dts: arm64: qcom: ipq9574: Enable CPR Date: Mon, 24 Jun 2024 10:32:54 +0530 Message-ID: <20240624050254.2942959-8-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624050254.2942959-1-quic_varada@quicinc.com> References: <20240624050254.2942959-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 4Eyw4X2P9aInD9xovC7DrcwmZgTIB7DI X-Proofpoint-ORIG-GUID: 4Eyw4X2P9aInD9xovC7DrcwmZgTIB7DI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-24_04,2024-06-21_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 spamscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406240038 * Add CPR, RPMPD, OPP table nodes as applicable to IPQ9574 to enable CPR functionality on IPQ9574. * Bootloader set frequency 792MHz is added to the OPP table to the avoid unknown frequency warning message at boot time. * Remove 1.2GHz as it is not supported in any of the IPQ9574 SKUs. Signed-off-by: Varadarajan Narayanan --- v2: Update commit log. No code change. --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 269 ++++++++++++++++++++++++-- 1 file changed, 252 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 04ba09a9156c..439ee5accc47 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -42,8 +43,9 @@ CPU0: cpu@0 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq9574_s1>; #cooling-cells = <2>; + power-domains = <&apc_cprh 0>; + power-domain-names = "perf"; }; CPU1: cpu@1 { @@ -55,8 +57,9 @@ CPU1: cpu@1 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq9574_s1>; #cooling-cells = <2>; + power-domains = <&apc_cprh 0>; + power-domain-names = "perf"; }; CPU2: cpu@2 { @@ -68,8 +71,9 @@ CPU2: cpu@2 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq9574_s1>; #cooling-cells = <2>; + power-domains = <&apc_cprh 0>; + power-domain-names = "perf"; }; CPU3: cpu@3 { @@ -81,8 +85,9 @@ CPU3: cpu@3 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq9574_s1>; #cooling-cells = <2>; + power-domains = <&apc_cprh 0>; + power-domain-names = "perf"; }; L2_0: l2-cache { @@ -105,58 +110,111 @@ memory@40000000 { reg = <0x0 0x40000000 0x0 0x0>; }; + cprh_opp_table: opp-table-cprh { + compatible = "operating-points-v2-qcom-level"; + + cprh_opp0: opp-0 { + opp-level = <1>; + qcom,opp-fuse-level = <1>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp1: opp-1 { + opp-level = <2>; + qcom,opp-fuse-level = <1>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp2: opp-2 { + opp-level = <3>; + qcom,opp-fuse-level = <1>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp3: opp-3 { + opp-level = <4>; + qcom,opp-fuse-level = <2>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp4: opp-4 { + opp-level = <5>; + qcom,opp-fuse-level = <2>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp5: opp-5 { + opp-level = <6>; + qcom,opp-fuse-level = <3>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp6: opp-6 { + opp-level = <7>; + qcom,opp-fuse-level = <4>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + }; + cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2-kryo-cpu"; opp-shared; nvmem-cells = <&cpu_speed_bin>; + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0>; + clock-latency-ns = <200000>; + required-opps = <&cprh_opp0>; + }; + opp-936000000 { opp-hz = /bits/ 64 <936000000>; - opp-microvolt = <725000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + required-opps = <&cprh_opp1>; }; opp-1104000000 { opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <787500>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <862500>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + required-opps = <&cprh_opp2>; }; opp-1416000000 { opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <862500>; opp-supported-hw = <0x7>; clock-latency-ns = <200000>; + required-opps = <&cprh_opp3>; }; opp-1488000000 { opp-hz = /bits/ 64 <1488000000>; - opp-microvolt = <925000>; opp-supported-hw = <0x7>; clock-latency-ns = <200000>; + required-opps = <&cprh_opp4>; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <987500>; opp-supported-hw = <0x5>; clock-latency-ns = <200000>; + required-opps = <&cprh_opp5>; }; opp-2208000000 { opp-hz = /bits/ 64 <2208000000>; - opp-microvolt = <1062500>; opp-supported-hw = <0x1>; clock-latency-ns = <200000>; + required-opps = <&cprh_opp6>; }; }; @@ -182,6 +240,40 @@ glink-edge { rpm_requests: rpm-requests { compatible = "qcom,rpm-ipq9574"; qcom,glink-channels = "rpm_requests"; + + rpmpd: power-controller { + compatible = "qcom,ipq9574-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_svs: opp1 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp2 { + opp-level = ; + }; + + rpmpd_opp_nom: opp3 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp4 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp5 { + opp-level = ; + }; + + rpmpd_opp_turbo_high: opp6 { + opp-level = ; + }; + }; + }; }; }; }; @@ -252,6 +344,95 @@ cpu_speed_bin: cpu-speed-bin@15 { reg = <0x15 0x2>; bits = <7 2>; }; + + cpr_efuse_speedbin: speedbin@5 { + reg = <0x5 0x8>; + bits = <0 3>; + }; + + cpr_fuse_revision: cpr-fusing-rev@7 { + reg = <0x7 0x8>; + bits = <1 5>; + }; + + /* CPR Ring Oscillator: Power Cluster */ + cpr_ro_sel0_pwrcl: rosel0-pwrcl@358 { /* ROSEL_SVS */ + reg = <0x358 0x1>; + bits = <4 4>; + }; + + cpr_ro_sel1_pwrcl: rosel1-pwrcl@358 { /* ROSEL_NOM */ + reg = <0x358 0x1>; + bits = <0 4>; + }; + + cpr_ro_sel2_pwrcl: rosel2-pwrcl@350 { /* ROSEL_TUR */ + reg = <0x350 0x1>; + bits = <4 4>; + }; + + cpr_ro_sel3_pwrcl: rosel3-pwrcl@350 { /* ROSEL_STUR */ + reg = <0x350 0x1>; + bits = <0 4>; + }; + + /* CPR Init Voltage: Power Cluster */ + cpr_init_voltage0_pwrcl: ivolt0-pwrcl@343 { /* VOLT_SVS */ + reg = <0x343 0x1>; + bits = <0 6>; + }; + + cpr_init_voltage1_pwrcl: ivolt1-pwrcl@342 { /* VOLT_NOM */ + reg = <0x342 0x1>; + bits = <2 6>; + }; + + cpr_init_voltage2_pwrcl: ivolt2-pwrcl@341 { /* VOLT_TUR */ + reg = <0x341 0x2>; + bits = <4 6>; + }; + + cpr_init_voltage3_pwrcl: ivolt3-pwrcl@340 { /* VOLT_STUR */ + reg = <0x340 0x2>; + bits = <6 6>; + }; + + /* CPR Target Quotients: Power Cluster */ + cpr_quot0_pwrcl: quot0-pwrcl@354 { /* QUOT_VMIN_SVS */ + reg = <0x354 0x2>; + bits = <0 12>; + }; + + cpr_quot1_pwrcl: quot1-pwrcl@352 { /* QUOT_VMIN_NOM */ + reg = <0x352 0x2>; + bits = <4 12>; + }; + + cpr_quot2_pwrcl: quot2-pwrcl@351 { /* QUOT_VMIN_TUR */ + reg = <0x351 0x2>; + bits = <0 12>; + }; + + cpr_quot3_pwrcl: quot3-pwrcl@355 { /* QUOT_VMIN_STUR */ + reg = <0x355 0x2>; + bits = <4 12>; + }; + + /* CPR Quotient Offsets: Power Cluster */ + cpr_quot_offset1_pwrcl: qoff1-pwrcl@34e { /* QUOT_OFFSET_NOM_SVS */ + reg = <0x34e 0x1>; + bits = <0 8>; + }; + + cpr_quot_offset2_pwrcl: qoff2-pwrcl@34d { /* QUOT_OFFSET_TUR_NOM */ + reg = <0x34d 0x1>; + bits = <0 8>; + }; + + cpr_quot_offset3_pwrcl: qoff0-pwrcl@34c { /* QUOT_OFFSET_STUR_TUR */ + reg = <0x34c 0x1>; + bits = <0 8>; + }; }; cryptobam: dma-controller@704000 { @@ -639,6 +820,60 @@ usb_0_dwc3: usb@8a00000 { }; }; + apc_cprh: power-controller@b018000 { + compatible = "qcom,ipq9574-cprh", "qcom,cprh"; + reg = <0x0b018000 0x4000>, + <0x00048000 0x4000>; + + clocks = <&gcc GCC_RBCPR_CLK>; + + interrupts = ; + vdd-supply = <&ipq9574_s1>; + + /* Set the CPR clock here, it needs to match XO */ + assigned-clocks = <&gcc GCC_RBCPR_CLK>; + assigned-clock-rates = <24000000>; + + operating-points-v2 = <&cprh_opp_table>; + power-domains = <&rpmpd IPQ9574_VDDAPC>; + #power-domain-cells = <1>; + + nvmem-cells = <&cpr_efuse_speedbin>, + <&cpr_fuse_revision>, + <&cpr_quot0_pwrcl>, + <&cpr_quot1_pwrcl>, + <&cpr_quot2_pwrcl>, + <&cpr_quot3_pwrcl>, + <&cpr_quot_offset1_pwrcl>, + <&cpr_quot_offset2_pwrcl>, + <&cpr_quot_offset3_pwrcl>, + <&cpr_init_voltage0_pwrcl>, + <&cpr_init_voltage1_pwrcl>, + <&cpr_init_voltage2_pwrcl>, + <&cpr_init_voltage3_pwrcl>, + <&cpr_ro_sel0_pwrcl>, + <&cpr_ro_sel1_pwrcl>, + <&cpr_ro_sel2_pwrcl>, + <&cpr_ro_sel3_pwrcl>; + nvmem-cell-names = "cpr_speed_bin", + "cpr_fuse_revision", + "cpr0_quotient1", + "cpr0_quotient2", + "cpr0_quotient3", + "cpr0_quotient4", + "cpr0_quotient_offset2", + "cpr0_quotient_offset3", + "cpr0_quotient_offset4", + "cpr0_init_voltage1", + "cpr0_init_voltage2", + "cpr0_init_voltage3", + "cpr0_init_voltage4", + "cpr0_ring_osc1", + "cpr0_ring_osc2", + "cpr0_ring_osc3", + "cpr0_ring_osc4"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */