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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d3042fd72sm6323136a12.48.2024.06.25.11.28.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 11:28:15 -0700 (PDT) From: Konrad Dybcio Date: Tue, 25 Jun 2024 20:28:06 +0200 Subject: [PATCH v4 1/5] drm/msm/adreno: Implement SMEM-based speed bin Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240625-topic-smem_speedbin-v4-1-f6f8493ab814@linaro.org> References: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> In-Reply-To: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719340091; l=5838; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ZXaBkJpkEi6I9lto/tGjByodIdA+A4HUW8SYjctW8+0=; b=7EbrsfA01bwk4JX0dOd021Lq44oCnoz/hsE+x15jRkJm2+pP6b+4RD6RGaveF7IiCeVYhv9SI SWjs8yQ7sFHB8vwYlQX3GdafSYlma2n1DeBvzX4tRAgsx9JkhGEoXpu X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is abstracted through SMEM, instead of being directly available in a fuse. Add support for SMEM-based speed binning, which includes getting "feature code" and "product code" from said source and parsing them to form something that lets us match OPPs against. Due to the product code being ignored in the context of Adreno on production parts (as of SM8650), hardcode it to SOCINFO_PC_UNKNOWN. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 +++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 41 +++++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++++- 4 files changed, 50 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c98cdb1e9326..8ace096bb68c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2124,13 +2124,15 @@ static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) return UINT_MAX; } -static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info) +static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu, + struct device *dev, + const struct adreno_info *info) { u32 supp_hw; u32 speedbin; int ret; - ret = adreno_read_speedbin(dev, &speedbin); + ret = adreno_read_speedbin(adreno_gpu, dev, &speedbin); /* * -ENOENT means that the platform doesn't support speedbin which is * fine @@ -2290,7 +2292,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); - ret = a6xx_set_supported_hw(&pdev->dev, config->info); + ret = a6xx_set_supported_hw(adreno_gpu, &pdev->dev, config->info); if (ret) { a6xx_llc_slices_destroy(a6xx_gpu); kfree(a6xx_gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 1e789ff6945e..e514346088f9 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -6,6 +6,8 @@ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. */ +#include + #include "adreno_gpu.h" bool hang_debug = false; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 1c6626747b98..6ffd02f38499 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -21,6 +21,9 @@ #include "msm_gem.h" #include "msm_mmu.h" +#include +#include + static u64 address_space_size = 0; MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space"); module_param(address_space_size, ullong, 0600); @@ -1061,9 +1064,39 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) adreno_ocmem->hdl); } -int adreno_read_speedbin(struct device *dev, u32 *speedbin) +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *fuse) { - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); + u32 fcode; + int ret; + + /* + * Try reading the speedbin via a nvmem cell first + * -ENOENT means "no nvmem-cells" and essentially means "old DT" or + * "nvmem fuse is irrelevant", simply assume it's fine. + */ + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", fuse); + if (!ret) + return 0; + else if (ret != -ENOENT) + return dev_err_probe(dev, ret, "Couldn't read the speed bin fuse value\n"); + +#ifdef CONFIG_QCOM_SMEM + /* + * Only check the feature code - the product code only matters for + * proto SoCs unavailable outside Qualcomm labs, as far as GPU bin + * matching is concerned. + * + * Ignore EOPNOTSUPP, as not all SoCs expose this info through SMEM. + */ + ret = qcom_smem_get_feature_code(&fcode); + if (!ret) + *fuse = ADRENO_SKU_ID(fcode); + else if (ret != -EOPNOTSUPP) + return dev_err_probe(dev, ret, "Couldn't get feature code from SMEM\n"); +#endif + + return 0; } int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, @@ -1102,9 +1135,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) + if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin) speedbin = 0xffff; - adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); + adreno_gpu->speedbin = speedbin; gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index cff8ce541d2c..563c08b44624 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -79,6 +79,10 @@ struct adreno_reglist { struct adreno_speedbin { uint16_t fuse; +/* As of SM8650, PCODE on production SoCs is meaningless wrt the GPU bin */ +#define ADRENO_SKU_ID_FCODE GENMASK(15, 0) +#define ADRENO_SKU_ID(fcode) (fcode) + uint16_t speedbin; }; @@ -545,7 +549,8 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, struct adreno_smmu_fault_info *info, const char *block, u32 scratch[4]); -int adreno_read_speedbin(struct device *dev, u32 *speedbin); +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *speedbin); /* * For a5xx and a6xx targets load the zap shader that is used to pull the GPU From patchwork Tue Jun 25 18:28:08 2024 Content-Type: text/plain; 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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d3042fd72sm6323136a12.48.2024.06.25.11.28.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 11:28:20 -0700 (PDT) From: Konrad Dybcio Date: Tue, 25 Jun 2024 20:28:08 +0200 Subject: [PATCH v4 3/5] drm/msm/adreno: Define A530 speed bins explicitly Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240625-topic-smem_speedbin-v4-3-f6f8493ab814@linaro.org> References: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> In-Reply-To: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719340091; l=874; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hlAsvCKJeJlsvCjk6T4iu/SvTfq4qoydQ2dHeLtqkkA=; b=IRMR1HRLN2YRjxVqz6xKwmuxF680eWYXDX4vQzB+gFNVfylWuVcDos2bQwzKA7wmZ4U3gJ32x gg7nzrlgLmLBSFRvmSiO2FyHkPwIZb+ULPTqUvjdw9Y1u9Ob9HaCm+V X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= In preparation for commonizing the speedbin handling code. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c index 455a953dee67..c98ad4ea558c 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c @@ -116,6 +116,12 @@ static const struct adreno_info a5xx_gpus[] = { ADRENO_QUIRK_FAULT_DETECT_MASK, .init = a5xx_gpu_init, .zapfw = "a530_zap.mdt", + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 1, 1 }, + { 2, 2 }, + { 3, 3 }, + ), }, { .chip_ids = ADRENO_CHIP_IDS(0x05040001), .family = ADRENO_5XX, From patchwork Tue Jun 25 18:28:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 807311 Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D4C717D344 for ; Tue, 25 Jun 2024 18:28:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719340107; cv=none; b=jtWAu9Wpn5+5QaLrvzqrGJCPZBy7JYuSRLDtdjDHoliwogZl04DL6Xdylu8eCU9c2IdTOVUDkGBhEmw8SlW8kTrIwhgvtcfxkTC1atqG9TqkP9os+iJ04/hDLl1nD+2jhtAaLrqVeIvxTK/5bgk8En+UZFak7vChCe7vv/OfHzE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719340107; c=relaxed/simple; bh=Il2UvibnuII6pAMEt7ZcsOO48MoDeeFboVabC36fJtY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=o13WXL1I6kXXqGWyR6FN1V9RACOngjtKH0aEyBALWDwbjLr9EsstfIg01+jo1ptCq1PWvXLXTXNV64+HnuURr9ZFM6nrl8riRUcltlpSF/BNgMCHItU4ZzRyVYfO6VMXt7byN8lv3S4/WXcoM8Mi4LI/oiNh765AvX+7NS4rVh8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=xTuwTLq+; arc=none smtp.client-ip=209.85.208.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="xTuwTLq+" Received: by mail-lj1-f178.google.com with SMTP id 38308e7fff4ca-2ec50d4e47bso44987871fa.2 for ; Tue, 25 Jun 2024 11:28:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719340104; x=1719944904; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OZxsbIBefCYoeKy9Cb25bQD5JKjjQqCGKHe9J4bV87I=; b=xTuwTLq+TOnetH/du6R/O8MB1QSlvCyUoTZ/EuiotZTJA+bWR77QrQB88qcOMh6TsR UQsCeH1YJHW2hcyh3qjs4mwaj+dlmzXrXg+tEamJwldidDssg+sZzPasMNC/S9td/32V QQAGKy38QC3knBist1bVMj/eI9gi0domtU5ezJ3Qjb+9oPJ5fE+JU4Iub5WwSSQDZGw7 U7jogrXg4vhRZTG/abNJpBjmax5oPFf8wRYgxgG3aFTwmLL/9FW18pdTv7p60tqaFl8Z 7SpMeRyDpwyBGx15J8KblSiSNbUKGKc84A2b+xN0iXvtGL/2OxEIvycZPKGU8ENHWx/6 wH1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719340104; x=1719944904; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OZxsbIBefCYoeKy9Cb25bQD5JKjjQqCGKHe9J4bV87I=; b=dJlmaYuLOXxGte2PdPQv0fTEEkFu3WRU0SQou4cjsdUdxcifMmarv1q+zmNcVQBR0G 2Y4D+7wtPQzD+EC74tOx8+RJYX7majYwJri83IcgDg+gFLLj9XRZXTdMGzHWPi2NjgIm Wp/fufV52XIUxClsRufTNLaK5VXRysu315VAdbKhs4imWjAtCJLs2HVQCdARYU4u8JlV stawprdSaZbWxcw/UYaC9rGvWkASfKRRAXh4AOzBE5f8Yge5oSGnQlghL2doxd50MBmR 1fXqKsDWGKxdLC+Bx6ibYeuroPv5AqkTpKfj/1rUd5FCypKwgxLzQiMtRIpu3Qk3cTo8 ++kQ== X-Forwarded-Encrypted: i=1; AJvYcCX/vvpr7tzTHxbsgO1gebuFR1QntOO+9DMztIL5WdXjeAwdKKeNvSBy5cGvVX7wdhqP3FHbwrJpOABq0Ic+m7KDpZRawx7tp2cg5Ouo3Q== X-Gm-Message-State: AOJu0YzYjxzbx0kiCWOVG6Cujf9bRpE7K+F7Wz+peE9I4k2Em+zc0gLz WJ5FHefjBEj6dLMQ/e+CScjb2FhuGVWT1V0GFvNiceRGy7TMP8pQGieSoSF3L/g= X-Google-Smtp-Source: AGHT+IERTLnLNNHy3T1W68s0MqqOr6aCsT3CWd3e/h0KiEMukzd8w8NKEEGKBwI+4WE9ry1o8Lt2xg== X-Received: by 2002:a2e:730b:0:b0:2ec:95:d6fe with SMTP id 38308e7fff4ca-2ec5b28ae9cmr48217441fa.24.1719340103431; Tue, 25 Jun 2024 11:28:23 -0700 (PDT) Received: from [192.168.215.29] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d3042fd72sm6323136a12.48.2024.06.25.11.28.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 11:28:23 -0700 (PDT) From: Konrad Dybcio Date: Tue, 25 Jun 2024 20:28:10 +0200 Subject: [PATCH v4 5/5] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240625-topic-smem_speedbin-v4-5-f6f8493ab814@linaro.org> References: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> In-Reply-To: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719340091; l=2474; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Il2UvibnuII6pAMEt7ZcsOO48MoDeeFboVabC36fJtY=; b=BlXBbM1o+PokhijSw+a2fl1gngXBbq3ayq9OQmI+TCgtGvPpsbaOQBkdjIvAjvDF7aXjlDpJH esr8rfv+fDKDgRA+7vpMkcyhgkuyqJI/f62VXU0kMJnbmcR074FZ4FI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add the speedbin masks to ensure only the desired OPPs are available on chips of a given bin. Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 4c9820adcf52..c1e3cec1540a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2119,48 +2119,67 @@ zap-shader { memory-region = <&gpu_micro_code_mem>; }; - /* Speedbin needs more work on A740+, keep only lower freqs */ gpu_opp_table: opp-table { compatible = "operating-points-v2"; + opp-719000000 { + opp-hz = /bits/ 64 <719000000>; + opp-level = ; + opp-supported-hw = <0x1>; + }; + opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-615000000 { opp-hz = /bits/ 64 <615000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-475000000 { opp-hz = /bits/ 64 <475000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-401000000 { opp-hz = /bits/ 64 <401000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-348000000 { opp-hz = /bits/ 64 <348000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-295000000 { opp-hz = /bits/ 64 <295000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-220000000 { opp-hz = /bits/ 64 <220000000>; opp-level = ; + opp-supported-hw = <0x3>; + }; + + opp-124800000 { + opp-hz = /bits/ 64 <124800000>; + opp-level = ; + opp-supported-hw = <0x3>; }; }; };