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Wed, 10 Jul 2024 11:16:33 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 10 Jul 2024 04:16:27 -0700 From: Krishna chaitanya chundru Date: Wed, 10 Jul 2024 16:46:10 +0530 Subject: [PATCH v6 3/5] PCI: qcom-ep: Add wake up host op to dw_pcie_ep_ops Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240710-wakeup_host-v6-3-ef00f31ea38d@quicinc.com> References: <20240710-wakeup_host-v6-0-ef00f31ea38d@quicinc.com> In-Reply-To: <20240710-wakeup_host-v6-0-ef00f31ea38d@quicinc.com> To: Manivannan Sadhasivam , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas , Jonathan Corbet , Jingoo Han , Lorenzo Pieralisi , Rob Herring CC: , , , , , , , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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If the wakeup type is PME, then trigger inband PME by writing to the PARF PARF_PM_CTRL register, otherwise toggle #WAKE. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 627a33a1c5ca..d17e8542d07a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -97,6 +97,7 @@ /* PARF_PM_CTRL register fields */ #define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1) #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2) +#define PARF_PM_CTRL_XMT_PME BIT(4) #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5) /* PARF_MHI_CLOCK_RESET_CTRL fields */ @@ -817,10 +818,34 @@ static void qcom_pcie_ep_init(struct dw_pcie_ep *ep) dw_pcie_ep_reset_bar(pci, bar); } +static bool qcom_pcie_ep_wakeup_host(struct dw_pcie_ep *ep, u8 func_no, bool send_pme) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); + struct device *dev = pci->dev; + u32 val; + + if (send_pme) { + dev_dbg(dev, "Waking up the host using PME\n"); + val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); + writel_relaxed(val | PARF_PM_CTRL_XMT_PME, pcie_ep->parf + PARF_PM_CTRL); + writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); + + } else { + dev_dbg(dev, "Waking up the host by toggling WAKE#\n"); + gpiod_set_value_cansleep(pcie_ep->wake, 1); + usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500); + gpiod_set_value_cansleep(pcie_ep->wake, 0); + } + + return true; +} + static const struct dw_pcie_ep_ops pci_ep_ops = { .init = qcom_pcie_ep_init, .raise_irq = qcom_pcie_ep_raise_irq, .get_features = qcom_pcie_epc_get_features, + .wakeup_host = qcom_pcie_ep_wakeup_host, }; static int qcom_pcie_ep_probe(struct platform_device *pdev) From patchwork Wed Jul 10 11:16:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 811814 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1ACF190686; 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If the D-state is in D3cold toggle wake signal, otherwise send PME. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 11 +++++++++++ include/linux/mhi_ep.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c index 6de9014e6e53..82fc52490324 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -708,6 +708,16 @@ static int pci_epf_mhi_dma_init(struct pci_epf_mhi *epf_mhi) return ret; } +static int pci_epf_mhi_wakeup_host(struct mhi_ep_cntrl *mhi_cntrl) +{ + struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); + struct pci_epf *epf = epf_mhi->epf; + struct pci_epc *epc = epf->epc; + + return pci_epc_wakeup_host(epc, epf->func_no, epf->vfunc_no, + (mhi_cntrl->dstate == PCI_D3cold) ? false : true); +} + static void pci_epf_mhi_dma_deinit(struct pci_epf_mhi *epf_mhi) { destroy_workqueue(epf_mhi->dma_wq); @@ -803,6 +813,7 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf) mhi_cntrl->unmap_free = pci_epf_mhi_unmap_free; mhi_cntrl->read_sync = mhi_cntrl->read_async = pci_epf_mhi_iatu_read; mhi_cntrl->write_sync = mhi_cntrl->write_async = pci_epf_mhi_iatu_write; + mhi_cntrl->wakeup_host = pci_epf_mhi_wakeup_host; if (info->flags & MHI_EPF_USE_DMA) { mhi_cntrl->read_sync = pci_epf_mhi_edma_read; mhi_cntrl->write_sync = pci_epf_mhi_edma_write; diff --git a/include/linux/mhi_ep.h b/include/linux/mhi_ep.h index 7c9e5895ea2c..04646cf7782b 100644 --- a/include/linux/mhi_ep.h +++ b/include/linux/mhi_ep.h @@ -165,6 +165,7 @@ struct mhi_ep_cntrl { int (*write_sync)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info *buf_info); int (*read_async)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info *buf_info); int (*write_async)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info *buf_info); + int (*wakeup_host)(struct mhi_ep_cntrl *mhi_cntrl); enum mhi_state mhi_state; From patchwork Wed Jul 10 11:16:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 811813 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89B271922C6; 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Wed, 10 Jul 2024 11:16:44 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46ABGiD0005026 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jul 2024 11:16:44 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 10 Jul 2024 04:16:38 -0700 From: Krishna chaitanya chundru Date: Wed, 10 Jul 2024 16:46:12 +0530 Subject: [PATCH v6 5/5] bus: mhi: ep: wake up host if the MHI state is in M3 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240710-wakeup_host-v6-5-ef00f31ea38d@quicinc.com> References: <20240710-wakeup_host-v6-0-ef00f31ea38d@quicinc.com> In-Reply-To: <20240710-wakeup_host-v6-0-ef00f31ea38d@quicinc.com> To: Manivannan Sadhasivam , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas , Jonathan Corbet , Jingoo Han , Lorenzo Pieralisi , Rob Herring CC: , , , , , , , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720610170; l=1937; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=V3qNvuQS2LeXL1m3qYfqkOp0sRscvt8GfvIxIVH7D/I=; b=D2TIwHwusj16VY5el2ak7Xh6HN7eS3JtKcD06F42WquNPbBc29Qm0MvcwQM+kHRIH9TGzJdpT GfSazy0HcSlDm3v/WK+IZsTw78GC3QH7PFmXA+UAqDbH5Iee0jZWnIf X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: TdcnI4A4KDzACUjGHrbvEvrKaxWjJVmC X-Proofpoint-ORIG-GUID: TdcnI4A4KDzACUjGHrbvEvrKaxWjJVmC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-10_06,2024-07-10_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 spamscore=0 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 malwarescore=0 mlxscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407100077 If the MHI state is in M3 then most probably the host kept the device in D3 hot or D3 cold, due to that endpoint transactions will not reach the host, endpoint needs to wakes up the host to bring the host to D0 which eventually bring back the MHI state to M0. while queueing packets if the MHI state is in M3 wakeup host to bring back link to M0. Signed-off-by: Krishna chaitanya chundru --- drivers/bus/mhi/ep/main.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/bus/mhi/ep/main.c b/drivers/bus/mhi/ep/main.c index b3eafcf2a2c5..b8713e5c1e1a 100644 --- a/drivers/bus/mhi/ep/main.c +++ b/drivers/bus/mhi/ep/main.c @@ -25,6 +25,26 @@ static DEFINE_IDA(mhi_ep_cntrl_ida); static int mhi_ep_create_device(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id); static int mhi_ep_destroy_device(struct device *dev, void *data); +static int mhi_ep_wake_host(struct mhi_ep_cntrl *mhi_cntrl) +{ + enum mhi_state state; + bool mhi_reset; + u32 count = 0; + + mhi_cntrl->wakeup_host(mhi_cntrl); + + /* Wait for Host to set the M0 state */ + while (count++ < M0_WAIT_COUNT) { + msleep(M0_WAIT_DELAY_MS); + + mhi_ep_mmio_get_mhi_state(mhi_cntrl, &state, &mhi_reset); + if (state == MHI_STATE_M0) + return 0; + } + + return -ENODEV; +} + static int mhi_ep_send_event(struct mhi_ep_cntrl *mhi_cntrl, u32 ring_idx, struct mhi_ring_element *el, bool bei) { @@ -564,6 +584,14 @@ int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, struct sk_buff *skb) mutex_lock(&mhi_chan->lock); + if (mhi_cntrl->mhi_state == MHI_STATE_M3) { + ret = mhi_ep_wake_host(mhi_cntrl); + if (ret) { + dev_err(dev, "Failed to wakeup host\n"); + goto err_exit; + } + } + do { /* Don't process the transfer ring if the channel is not in RUNNING state */ if (mhi_chan->state != MHI_CH_STATE_RUNNING) {