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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id j11sm7876250pgk.3.2019.11.01.17.16.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2019 17:16:34 -0700 (PDT) From: Bjorn Andersson To: Kishon Vijay Abraham I Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/5] phy: qcom-qmp: Increase PHY ready timeout Date: Fri, 1 Nov 2019 17:16:25 -0700 Message-Id: <20191102001628.4090861-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191102001628.4090861-1-bjorn.andersson@linaro.org> References: <20191102001628.4090861-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org It's typical for the QHP PHY to take slightly above 1ms to initialize, so increase the timeout of the PHY ready check to 10ms - as already done in the downstream PCIe driver. Signed-off-by: Bjorn Andersson --- Changes since v1: - New patch drivers/phy/qualcomm/phy-qcom-qmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.23.0 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 091e20303a14..66f91726b8b2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -66,7 +66,7 @@ /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ -#define PHY_INIT_COMPLETE_TIMEOUT 1000 +#define PHY_INIT_COMPLETE_TIMEOUT 10000 #define POWER_DOWN_DELAY_US_MIN 10 #define POWER_DOWN_DELAY_US_MAX 11 From patchwork Sat Nov 2 00:16:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 178347 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp1214759ill; Fri, 1 Nov 2019 17:16:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqwbXlCKk8ZPJW8tcCuGO7O4rEDjf83xUK6lJwVe9h+QeQnxp3dTM3eGXD3KQaznBGwnKoFJ X-Received: by 2002:a17:907:41ae:: with SMTP id of22mr12659768ejb.30.1572653803927; Fri, 01 Nov 2019 17:16:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1572653803; cv=none; d=google.com; s=arc-20160816; b=wRqMi2pVLIW2KFq3r6kAS7rrQv+l8ns51YtoqlKys5oliXHtjbooF828fGvvLgF8oj gBg3mBFw3S42HswGod3FBfjzmuqiCjzaOLya+GErRRD2nRnseAM78cMawH/t4+KVZHsP NS4E90+jj9BWFYnP6myXLvEfnckv5/rzo6M9Jv6kj59zz2kTiTt3TiQPXMxqi/saP/oc imeeygOuqkAboBAUjF1jjy/6mDVt35LrUSL5Y5N3thVpwY0DPBoBma317z3+rgvYurhd VzBOdPJZX/lKeIpxorB9q6lzlJLY17Uy/ND8zQ0aveR+vYQiXtYdC4MRi/tHhvH8k0ed 4ivg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vwfNasNmk/zaE6boGrbx1PqkuEi6mq3j6Mt8dGLE6Ps=; b=dS14+lFNYgS57kQ3NT0G+qRKLX8qZr6VgtH+D2qole0StPr2PtWeX22FhU2hwQ5Fah +jLGazVFao2EaAvuOpKdV1fBoIdbo/rUthqy/NA78Ks2eOdYgqjDmNWWvgClkHuqgx9U Hu2wjWyHgBl0ooNg4P0uV+H60H71cqQkkW8Ca3jvN7jHwpapPdoqgO4NuB8ZjuLPn1YX fFt3vmaLRBeNNmq0PmgaJVoGBQUFu9jhMV/l9yiXlmiwbO3YESD0ycfIvXn0YcsQiNtT GEoF8Tfnm3iaqpSNLUshFuqZsii9Aa8rf/ILqXmW9dqqK/druWpPoTVGoJSQwHUva2H2 xUQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EPcVFzqS; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id j11sm7876250pgk.3.2019.11.01.17.16.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2019 17:16:35 -0700 (PDT) From: Bjorn Andersson To: Kishon Vijay Abraham I Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/5] phy: qcom: qmp: Use power_on/off ops for PCIe Date: Fri, 1 Nov 2019 17:16:26 -0700 Message-Id: <20191102001628.4090861-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191102001628.4090861-1-bjorn.andersson@linaro.org> References: <20191102001628.4090861-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The PCIe PHY initialization requires the attached device to be present, which is primarily achieved by the PCI controller driver. So move the logic from init/exit to power_on/power_off. Signed-off-by: Bjorn Andersson --- Changes since v1: - New patch drivers/phy/qualcomm/phy-qcom-qmp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.23.0 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 66f91726b8b2..b9f849d86795 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -1968,7 +1968,7 @@ static const struct phy_ops qcom_qmp_phy_gen_ops = { .owner = THIS_MODULE, }; -static const struct phy_ops qcom_qmp_ufs_ops = { +static const struct phy_ops qcom_qmp_pcie_ufs_ops = { .power_on = qcom_qmp_phy_enable, .power_off = qcom_qmp_phy_disable, .set_mode = qcom_qmp_phy_set_mode, @@ -2068,8 +2068,8 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) } } - if (qmp->cfg->type == PHY_TYPE_UFS) - ops = &qcom_qmp_ufs_ops; + if (qmp->cfg->type == PHY_TYPE_UFS || qmp->cfg->type == PHY_TYPE_PCIE) + ops = &qcom_qmp_pcie_ufs_ops; generic_phy = devm_phy_create(dev, np, ops); if (IS_ERR(generic_phy)) {