From patchwork Fri Nov 8 15:25:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 178913 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2860695ilf; Fri, 8 Nov 2019 07:26:52 -0800 (PST) X-Google-Smtp-Source: APXvYqxv9Gj8fxWAC3NW30hz8sUAKwUd15D7nNpM2PrIVmRSx7A/zz04WVJ3//pg1G75yZ6RNPNt X-Received: by 2002:a17:906:4019:: with SMTP id v25mr9479349ejj.11.1573226812322; Fri, 08 Nov 2019 07:26:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573226812; cv=none; d=google.com; s=arc-20160816; b=OoFoSVnQP86Tu21+wNpiyGskLqMkLR/tX5N46iYFXgu4Lc469+9Xqqmvtpmgm3g2Cs NedtRGbz63Kb6KDvw10FkUcEUvYgAjwQYyzefO3osnvxjuDM0MxqG8tdQSGsbkwiEjk3 PrEgQQX73afRHDquDtb3e6WHLhdiNZTixF5Y8Kyc0fiDotLy3l0vRji/6vwPsq2WyUT9 dbunpDWTVGMGLbNlGy5WPYnHQLlWqJ8IjOONxdor7ulYB/c//QR++As2+W0O5mNOTq2s hGy5PZY2+oyL4uqLQte0qIq5KDGwc+u7PFAmVz4F2mrhoGhiv2jZO3NzaypHDvLy77xO VUWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xkWcxJ6Iuy+TFzutOZwKsDdjGV2W0A5RS2sI5DD8vzM=; b=bbGwhjGNF5DaY9EnKzOZv4Ni4GeVPMwX4lRXxnftmh8BVOEZ06b848nHvzl4fFW+J9 4VabEcuUujlJTJXKVKHyXiHcYPjY0RnfiRP3o984SFA4XwDyTKyxjSiFYSm/0yP77w2J SUAVWgfB3p3UIxVm6xCwnJZIgp5ahKyw1uLUPSn4xfk7cHWc7blu8sNOwALqhIMBVKFX z5Yv6lr+pf1L6HkimZNd+0bJaDR+rPvGY7NAQ1p/yJd4bY0cQBbgs1F18fupU63tNfaK Vfn7B4JCNFZpmjv4lXpmeRg1C/angivS9V51uzvJhDqURDYHBNM3rTUVhHwMma0XpEBL woTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rr+E9RT1; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y31si4384892edb.47.2019.11.08.07.26.52; Fri, 08 Nov 2019 07:26:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rr+E9RT1; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725941AbfKHP0u (ORCPT + 7 others); Fri, 8 Nov 2019 10:26:50 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:37713 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726457AbfKHP0u (ORCPT ); Fri, 8 Nov 2019 10:26:50 -0500 Received: by mail-wm1-f66.google.com with SMTP id q130so6641026wme.2 for ; Fri, 08 Nov 2019 07:26:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xkWcxJ6Iuy+TFzutOZwKsDdjGV2W0A5RS2sI5DD8vzM=; b=rr+E9RT1m3Uo7HDUww3oQBuqgMwd4smQJlm1F51cGsAn5yxcXpfWYxrw5HNGAbAN0T vCuV/pFnYtG6J/pA8tYatmkzzIt46o+Dibijb10+j8gXZtsXmaPI2hVExy0xaTPM1pUw jWyJ4iAp0CaA+2OriDDPyVEAYwIpVTS1sbFx5qbFpaZE0rXPjKfyiWXPnoRAZqG++wEI quuvaGA4UYD7FneNYZe2huxUVlofu3I9+CDwSJXYrb2yPBxitzAAjDVaYj/cfBnZTpZK Q/VnQBsoVhbXhLUrHkrWvVm1kgTuEYPkBFnVWoN8dc8lROj6lv/76Wr+Dt4SpoqAyU3N Cv2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xkWcxJ6Iuy+TFzutOZwKsDdjGV2W0A5RS2sI5DD8vzM=; b=HzMdravIx/gsJy1//xeSK2jPZAxnPAuJMuvxRYLftwk+Q2ZsehS2Y0/bzzzyWeny96 Tff32uRyQB/LXCpBSuK/Byb8K8/sH0k3GMDaF+tZxRmhcRV7X5oNfSBGWJxXLAXCGTzX 4mtBJ2S9bfxAjP1eFTLSIq8t96zQMFISLAnm++3zSPCQ2bF5RUNu+FHgKwJ8vo+jx25m nxMfqYaCJmF0TC+2LEsAfBzbuPoJQah9byUTq0KYDtVh5OD8RlCQRwCOOGP49+80/SOg kJpiPBtHf13vS1gxgisaTZ5QvhEK6dVsLYZzDyZnGTHtF3Fx1SBBcyVq17G/m+L5AWMH ixjw== X-Gm-Message-State: APjAAAURecL0lR5n9ffOm2ObWL1SqZcmfxUh8nd+ZEErr2lASSBi8OuA 6DD/MeFnvEKYlQcFPQKfJCS8+Q== X-Received: by 2002:a05:600c:210b:: with SMTP id u11mr9006014wml.170.1573226808499; Fri, 08 Nov 2019 07:26:48 -0800 (PST) Received: from localhost.localdomain ([85.195.192.192]) by smtp.gmail.com with ESMTPSA id w18sm6579232wrp.31.2019.11.08.07.26.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 07:26:47 -0800 (PST) From: Jean-Philippe Brucker To: iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, guohanjun@huawei.com, sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org, will@kernel.org, robin.murphy@arm.com, zhangfei.gao@linaro.org, eric.auger@redhat.com, jonathan.cameron@huawei.com Subject: [PATCH v2 1/8] dt-bindings: document PASID property for IOMMU masters Date: Fri, 8 Nov 2019 16:25:01 +0100 Message-Id: <20191108152508.4039168-2-jean-philippe@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191108152508.4039168-1-jean-philippe@linaro.org> References: <20191108152508.4039168-1-jean-philippe@linaro.org> MIME-Version: 1.0 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On Arm systems, some platform devices behind an SMMU may support the PASID feature, which offers multiple address space. Let the firmware tell us when a device supports PASID. Reviewed-by: Rob Herring Reviewed-by: Eric Auger Signed-off-by: Jean-Philippe Brucker --- Documentation/devicetree/bindings/iommu/iommu.txt | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.23.0 diff --git a/Documentation/devicetree/bindings/iommu/iommu.txt b/Documentation/devicetree/bindings/iommu/iommu.txt index 5a8b4624defc..3c36334e4f94 100644 --- a/Documentation/devicetree/bindings/iommu/iommu.txt +++ b/Documentation/devicetree/bindings/iommu/iommu.txt @@ -86,6 +86,12 @@ have a means to turn off translation. But it is invalid in such cases to disable the IOMMU's device tree node in the first place because it would prevent any driver from properly setting up the translations. +Optional properties: +-------------------- +- pasid-num-bits: Some masters support multiple address spaces for DMA, by + tagging DMA transactions with an address space identifier. By default, + this is 0, which means that the device only has one address space. + Notes: ====== From patchwork Fri Nov 8 15:25:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 178915 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2860739ilf; Fri, 8 Nov 2019 07:26:54 -0800 (PST) X-Google-Smtp-Source: APXvYqyXP2TH2Yk5O3Zd/JEJiy5oRQhI9SqTRRzR34oJXacpQTxebaUm+rLbRwNIPeD2BuxldeAP X-Received: by 2002:a17:906:ecf5:: with SMTP id qt21mr9075288ejb.295.1573226814116; Fri, 08 Nov 2019 07:26:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573226814; cv=none; d=google.com; s=arc-20160816; b=W32g0qJDFNgUgogzN2vzS3d4wO09A5BrvSVnHcnTWWagzYEDsAM4YFCzlVXiDxScri bnxQf23VTfiELeh/j61fu+/TLzrw2205S61mtLo0GzgcLIjG/emZ94HK9XYdsHoF71QK a7Vz/R73kcgEhWTtFEI3fqEMiQ/7rLxI4w9aSIeWZZqFI1sgduSkoAvhgXeAVecPc0Ej ipGIF+OJnV2at0Lt6SA3yeBBs/qAYxYEKPsUSax7kvDzSuqVyaukRenywW7vLiu7wp1h bx0J6YzDElyerMSZkGEAweU7e2NlMRvrwWBCnPg4VaNpvQzdOz12ImveUQ5GZvAeplvY GhMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+aAa3kHo6X36UARQ/hBD+CYIStSC9Mwak+bAj3lpxxM=; b=h6cMy3CWBBDsqhUBBc7pH+lLGRKMMZWrPsbnAK6WOYiUgf5E8iobafDiEiieKRBpAu DZoAP1gU0agFZ7sCnm46YAYptpSnFon8oqCUP3VIR0gifd8QhNR/meVpAKNa48h1RdNs jUYYwCgroqXNPNzi3sPyr/1pLNQe13AKJLEvotYNLIW99bEe3SzTGlvid8TQxjGgbLJX 9j/Ybfx6vrPtRiU0ePooYTnygU8Nim57Zh1YZyeIIi1pzIBlXCMQnmsYUC8uSrjfofvr bu5ztQbSHSLI0fZq8OC16XnmvnPEk+0/bcVQ4WVmBPq96C3STtIrao+KtJRdWZWirPKe pJGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rk9za0j+; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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PASID) supported by the device. Propagate this value to the fwspec structure in order to enable PASID for platform devices. Signed-off-by: Jean-Philippe Brucker --- drivers/acpi/arm64/iort.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) -- 2.23.0 Acked-by: Hanjun Guo diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 5a7551d060f2..9aebb180744f 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -11,6 +11,7 @@ #define pr_fmt(fmt) "ACPI: IORT: " fmt #include +#include #include #include #include @@ -924,6 +925,20 @@ static int iort_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data) return iort_iommu_xlate(info->dev, parent, streamid); } +static void iort_named_component_init(struct device *dev, + struct acpi_iort_node *node) +{ + struct acpi_iort_named_component *nc; + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + + if (!fwspec) + return; + + nc = (struct acpi_iort_named_component *)node->node_data; + fwspec->num_pasid_bits = FIELD_GET(ACPI_IORT_NC_PASID_BITS, + nc->node_flags); +} + /** * iort_iommu_configure - Set-up IOMMU configuration for a device. * @@ -978,6 +993,9 @@ const struct iommu_ops *iort_iommu_configure(struct device *dev) if (parent) err = iort_iommu_xlate(dev, parent, streamid); } while (parent && !err); + + if (!err) + iort_named_component_init(dev, node); } /* From patchwork Fri Nov 8 15:25:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 178916 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2860766ilf; Fri, 8 Nov 2019 07:26:55 -0800 (PST) X-Google-Smtp-Source: APXvYqz2q8qvMVOHmJDOJ9EkkS7QBWgW6ZOGgXO3l9+tGdjyHvIvFdc3cxiV7UJ/yXKRwvNo0ovX X-Received: by 2002:a50:cc07:: with SMTP id m7mr11104157edi.146.1573226815379; Fri, 08 Nov 2019 07:26:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573226815; cv=none; d=google.com; s=arc-20160816; b=Z/AHdwQ7Jq8ywEYdZ7/qMV2t9C2n6agndFo5HaAILgApXxISPLXb4/Xe4uHNQ/9fuC ukCU3dy6FZUPQ12LO0QR/00w+2osZKUBiAItAAQDbf6b4+miGbby589l5mGXXmquKqCW JxXLhwWvSUWjtRx6JVw6q14J5zFnwuaR4jPhv8F60uEGM8vkUavEZ6On1/9JxecKngCE rQBBM9/ku28s1qMYFIv/2eDdC2IC0S+PD9ARlU4uJgKe6Yzi5R1xJeKTcHW88lH0RP5N Tb0t195cU9O+bXN8x4ZtwuJZTKQ0dfRCH65gwPpNHVJVUqCMNsZef8y2P9Z+BP/5j5jI CMfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xxbc6VKpREb2fLxcCnG9+DNNv+AFHLlTfvdpuIaWoGY=; b=I3zkrmK2o7T7I9JKpnNDMHjYnpSrzkungMKUAPjdafQNMpm9xoTvDMVMbRXFqPYOFV tJ8FUMrSHcWPsFGL2eAlyFoGXchQsnto9ahrIWXFFots1VfhghKcoGMvpvKa9MRwsDsz SfHz5YxJRfbcH/2JFhJROQfvmF4ludmv5kU+3WaxPLtpV/QsLY7Cg3o32MwKPKlYcGrO bfUfSzM36BmS41rF59ZCfv5Xa3U8RIY6++q+9cLMWxjEYtAJD780HWrOiry2xge5PPRU pfyAjCUP+evVezoqzqpzdK99A65W7vfTlvIzcYxCf3s6nttROBtBJLtxrI3jDyEzSXfK py+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mDQVkLG4; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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For the moment S1CDMax is still 0 in the STE, so the additional context descriptors are ignored. Context descriptor tables are allocated once for the first master attached to a domain. Therefore attaching multiple devices with different SSID sizes is tricky, and we currently don't support it. As a future improvement it would be nice to at least support attaching a SSID-capable device to a domain that isn't using SSID, by reallocating the SSID table. This would allow supporting a SSID-capable device that is in the same IOMMU group as a bridge, for example. Varying SSID size is less of a concern, since the PCIe specification "highly recommends" that devices supporting PASID implement all 20 bits of it. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 117 ++++++++++++++++++++++++++---------- 1 file changed, 85 insertions(+), 32 deletions(-) -- 2.23.0 diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 33488da8f742..122bed0168a3 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -553,16 +553,22 @@ struct arm_smmu_strtab_l1_desc { dma_addr_t l2ptr_dma; }; +struct arm_smmu_ctx_desc { + u16 asid; + u64 ttbr; + u64 tcr; + u64 mair; +}; + +struct arm_smmu_cd_table { + __le64 *ptr; + dma_addr_t ptr_dma; +}; + struct arm_smmu_s1_cfg { - __le64 *cdptr; - dma_addr_t cdptr_dma; - - struct arm_smmu_ctx_desc { - u16 asid; - u64 ttbr; - u64 tcr; - u64 mair; - } cd; + u8 s1cdmax; + struct arm_smmu_cd_table table; + struct arm_smmu_ctx_desc cd; }; struct arm_smmu_s2_cfg { @@ -1450,6 +1456,31 @@ static int arm_smmu_cmdq_issue_sync(struct arm_smmu_device *smmu) } /* Context descriptor manipulation functions */ +static int arm_smmu_alloc_cd_leaf_table(struct arm_smmu_device *smmu, + struct arm_smmu_cd_table *table, + size_t num_entries) +{ + size_t size = num_entries * (CTXDESC_CD_DWORDS << 3); + + table->ptr = dmam_alloc_coherent(smmu->dev, size, &table->ptr_dma, + GFP_KERNEL | __GFP_ZERO); + if (!table->ptr) { + dev_warn(smmu->dev, + "failed to allocate context descriptor table\n"); + return -ENOMEM; + } + return 0; +} + +static void arm_smmu_free_cd_leaf_table(struct arm_smmu_device *smmu, + struct arm_smmu_cd_table *table, + size_t num_entries) +{ + size_t size = num_entries * (CTXDESC_CD_DWORDS << 3); + + dmam_free_coherent(smmu->dev, size, table->ptr, table->ptr_dma); +} + static u64 arm_smmu_cpu_tcr_to_cd(u64 tcr) { u64 val = 0; @@ -1471,6 +1502,7 @@ static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu, struct arm_smmu_s1_cfg *cfg) { u64 val; + __le64 *cdptr = cfg->table.ptr; /* * We don't need to issue any invalidation here, as we'll invalidate @@ -1488,12 +1520,29 @@ static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu, if (smmu->features & ARM_SMMU_FEAT_STALL_FORCE) val |= CTXDESC_CD_0_S; - cfg->cdptr[0] = cpu_to_le64(val); + cdptr[0] = cpu_to_le64(val); val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK; - cfg->cdptr[1] = cpu_to_le64(val); + cdptr[1] = cpu_to_le64(val); - cfg->cdptr[3] = cpu_to_le64(cfg->cd.mair); + cdptr[3] = cpu_to_le64(cfg->cd.mair); +} + +static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain) +{ + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; + + return arm_smmu_alloc_cd_leaf_table(smmu, &cfg->table, + 1 << cfg->s1cdmax); +} + +static void arm_smmu_free_cd_tables(struct arm_smmu_domain *smmu_domain) +{ + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; + + arm_smmu_free_cd_leaf_table(smmu, &cfg->table, 1 << cfg->s1cdmax); } /* Stream table manipulation functions */ @@ -1624,7 +1673,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, !(smmu->features & ARM_SMMU_FEAT_STALL_FORCE)) dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD); - val |= (s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) | + val |= (s1_cfg->table.ptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) | FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS); } @@ -2138,12 +2187,8 @@ static void arm_smmu_domain_free(struct iommu_domain *domain) if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; - if (cfg->cdptr) { - dmam_free_coherent(smmu_domain->smmu->dev, - CTXDESC_CD_DWORDS << 3, - cfg->cdptr, - cfg->cdptr_dma); - + if (cfg->table.ptr) { + arm_smmu_free_cd_tables(smmu_domain); arm_smmu_bitmap_free(smmu->asid_map, cfg->cd.asid); } } else { @@ -2156,6 +2201,7 @@ static void arm_smmu_domain_free(struct iommu_domain *domain) } static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_master *master, struct io_pgtable_cfg *pgtbl_cfg) { int ret; @@ -2167,19 +2213,19 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, if (asid < 0) return asid; - cfg->cdptr = dmam_alloc_coherent(smmu->dev, CTXDESC_CD_DWORDS << 3, - &cfg->cdptr_dma, - GFP_KERNEL | __GFP_ZERO); - if (!cfg->cdptr) { - dev_warn(smmu->dev, "failed to allocate context descriptor\n"); - ret = -ENOMEM; + cfg->s1cdmax = master->ssid_bits; + + ret = arm_smmu_alloc_cd_tables(smmu_domain); + if (ret) goto out_free_asid; - } cfg->cd.asid = (u16)asid; cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr; cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; + + arm_smmu_write_ctx_desc(smmu, cfg); + return 0; out_free_asid: @@ -2188,6 +2234,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, } static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_master *master, struct io_pgtable_cfg *pgtbl_cfg) { int vmid; @@ -2204,7 +2251,8 @@ static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, return 0; } -static int arm_smmu_domain_finalise(struct iommu_domain *domain) +static int arm_smmu_domain_finalise(struct iommu_domain *domain, + struct arm_smmu_master *master) { int ret; unsigned long ias, oas; @@ -2212,6 +2260,7 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain) struct io_pgtable_cfg pgtbl_cfg; struct io_pgtable_ops *pgtbl_ops; int (*finalise_stage_fn)(struct arm_smmu_domain *, + struct arm_smmu_master *, struct io_pgtable_cfg *); struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_device *smmu = smmu_domain->smmu; @@ -2266,7 +2315,7 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain) domain->geometry.aperture_end = (1UL << pgtbl_cfg.ias) - 1; domain->geometry.force_aperture = true; - ret = finalise_stage_fn(smmu_domain, &pgtbl_cfg); + ret = finalise_stage_fn(smmu_domain, master, &pgtbl_cfg); if (ret < 0) { free_io_pgtable_ops(pgtbl_ops); return ret; @@ -2419,7 +2468,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) if (!smmu_domain->smmu) { smmu_domain->smmu = smmu; - ret = arm_smmu_domain_finalise(domain); + ret = arm_smmu_domain_finalise(domain, master); if (ret) { smmu_domain->smmu = NULL; goto out_unlock; @@ -2431,6 +2480,13 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) dev_name(smmu->dev)); ret = -ENXIO; goto out_unlock; + } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && + master->ssid_bits != smmu_domain->s1_cfg.s1cdmax) { + dev_err(dev, + "cannot attach to incompatible domain (%u SSID bits != %u)\n", + smmu_domain->s1_cfg.s1cdmax, master->ssid_bits); + ret = -EINVAL; + goto out_unlock; } master->domain = smmu_domain; @@ -2438,9 +2494,6 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) if (smmu_domain->stage != ARM_SMMU_DOMAIN_BYPASS) master->ats_enabled = arm_smmu_ats_supported(master); - if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) - arm_smmu_write_ctx_desc(smmu, &smmu_domain->s1_cfg); - arm_smmu_install_ste_for_dev(master); spin_lock_irqsave(&smmu_domain->devices_lock, flags); From patchwork Fri Nov 8 15:25:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 178918 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2860846ilf; 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[209.132.180.67]) by mx.google.com with ESMTP id y31si4384892edb.47.2019.11.08.07.26.59; Fri, 08 Nov 2019 07:26:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pjkXYKXP; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726910AbfKHP06 (ORCPT + 7 others); Fri, 8 Nov 2019 10:26:58 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:54243 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726879AbfKHP06 (ORCPT ); Fri, 8 Nov 2019 10:26:58 -0500 Received: by mail-wm1-f68.google.com with SMTP id x4so6586684wmi.3 for ; Fri, 08 Nov 2019 07:26:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dGJYFkJIv52PSafGiVwNPcKfln8k/8BPJx1rxkdK2ds=; b=pjkXYKXPb3SLkO7ZaYHacMMb2aAKLwC2PIg9nJYoHIgB8AK7R/rSwGBI4n3lNDsEC6 LOvAr+IYjgfbfY/yuH9YLHIckOoAzwk1HAzlzFO+a5BKhwxNkwaBYk31MSISiU2nTNEc YGWD54Iz6n126lR4eHiap7OVINZTztNhKXEIO+ShKRsCV3AIOsIisi2h3nqevJ8a8DK1 esua2PGerZRywwDMBSIEtuhLI4IWu4UVTQvE9PtCYy7VKbT0+ewy4WO4cl2rLahrQQmy j0zIAr/fp0TvFwOQMAWUL9nl6Z/2EuV2APCYJiH+54BXuuhfLl4ocNGnbUz2W4lo46L9 5geg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dGJYFkJIv52PSafGiVwNPcKfln8k/8BPJx1rxkdK2ds=; b=Xp6SWZzFGm2Wi8OQwX1smfufkDlXC+0+PboWX8BdgT4v7to7n2X/O0HmvFviLum/r1 eFjy/nDrLnrAc9xupUVQIHDrBjfd0ASHCLPgn1aW6BzQ5KBZhzEVyYuPN1KiPd4jm7ho uwcOhkpYu5hVU4igYNFMVL9M/agjjtT7Fzf8QTLti+La/lceERdB41ZJrfmqz0UehgqL D45cMWfdfVKQ7a3Uo5AqxS6X0nqRixxZcSjAIvcAfEVuOOXY3T4OYfm2oKOgkvmLdolL rrEzYek2piPfpPy6aW+BrhprlDN46gnPJ80jbwTeX+cDT8Y8gsQ4MqZwRXfacSH0MOPh WxXQ== X-Gm-Message-State: APjAAAX7c7Sow5P/qSzTu43MQKtuW/w+4t0ojuazfk8XUWPpgnFlMuQV LWjbchc+ILoPWlhje1v7v/gKxg== X-Received: by 2002:a1c:1fcc:: with SMTP id f195mr3521190wmf.137.1573226814586; Fri, 08 Nov 2019 07:26:54 -0800 (PST) Received: from localhost.localdomain ([85.195.192.192]) by smtp.gmail.com with ESMTPSA id w18sm6579232wrp.31.2019.11.08.07.26.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 07:26:54 -0800 (PST) From: Jean-Philippe Brucker To: iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, guohanjun@huawei.com, sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org, will@kernel.org, robin.murphy@arm.com, zhangfei.gao@linaro.org, eric.auger@redhat.com, jonathan.cameron@huawei.com Subject: [PATCH v2 6/8] iommu/arm-smmu-v3: Add second level of context descriptor table Date: Fri, 8 Nov 2019 16:25:06 +0100 Message-Id: <20191108152508.4039168-7-jean-philippe@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191108152508.4039168-1-jean-philippe@linaro.org> References: <20191108152508.4039168-1-jean-philippe@linaro.org> MIME-Version: 1.0 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The SMMU can support up to 20 bits of SSID. Add a second level of page tables to accommodate this. Devices that support more than 1024 SSIDs now have a table of 1024 L1 entries (8kB), pointing to tables of 1024 context descriptors (64kB), allocated on demand. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 137 +++++++++++++++++++++++++++++++++--- 1 file changed, 126 insertions(+), 11 deletions(-) -- 2.23.0 diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index df7d45503c65..82eac89ee187 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -224,6 +224,7 @@ #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4) #define STRTAB_STE_0_S1FMT_LINEAR 0 +#define STRTAB_STE_0_S1FMT_64K_L2 2 #define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6) #define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59) @@ -263,7 +264,20 @@ #define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4) -/* Context descriptor (stage-1 only) */ +/* + * Context descriptors. + * + * Linear: when less than 1024 SSIDs are supported + * 2lvl: at most 1024 L1 entries, + * 1024 lazy entries per table. + */ +#define CTXDESC_SPLIT 10 +#define CTXDESC_L2_ENTRIES (1 << CTXDESC_SPLIT) + +#define CTXDESC_L1_DESC_DWORDS 1 +#define CTXDESC_L1_DESC_VALID 1 +#define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12) + #define CTXDESC_CD_DWORDS 8 #define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0) #define ARM64_TCR_T0SZ GENMASK_ULL(5, 0) @@ -577,7 +591,10 @@ struct arm_smmu_cd_table { struct arm_smmu_s1_cfg { u8 s1fmt; u8 s1cdmax; - struct arm_smmu_cd_table table; + struct arm_smmu_cd_table *tables; + size_t num_tables; + __le64 *l1ptr; + dma_addr_t l1ptr_dma; struct arm_smmu_ctx_desc cd; }; @@ -1521,12 +1538,51 @@ static void arm_smmu_free_cd_leaf_table(struct arm_smmu_device *smmu, { size_t size = num_entries * (CTXDESC_CD_DWORDS << 3); + if (!table->ptr) + return; dmam_free_coherent(smmu->dev, size, table->ptr, table->ptr_dma); } -static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_s1_cfg *cfg, u32 ssid) +static void arm_smmu_write_cd_l1_desc(__le64 *dst, + struct arm_smmu_cd_table *table) { - return cfg->table.ptr + ssid * CTXDESC_CD_DWORDS; + u64 val = (table->ptr_dma & CTXDESC_L1_DESC_L2PTR_MASK) | + CTXDESC_L1_DESC_VALID; + + WRITE_ONCE(*dst, cpu_to_le64(val)); +} + +static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_domain *smmu_domain, + u32 ssid) +{ + __le64 *l1ptr; + unsigned int idx; + struct arm_smmu_cd_table *table; + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; + + if (cfg->s1fmt == STRTAB_STE_0_S1FMT_LINEAR) { + table = &cfg->tables[0]; + idx = ssid; + } else { + idx = ssid >> CTXDESC_SPLIT; + if (idx >= cfg->num_tables) + return NULL; + + table = &cfg->tables[idx]; + if (!table->ptr) { + if (arm_smmu_alloc_cd_leaf_table(smmu, table, + CTXDESC_L2_ENTRIES)) + return NULL; + + l1ptr = cfg->l1ptr + idx * CTXDESC_L1_DESC_DWORDS; + arm_smmu_write_cd_l1_desc(l1ptr, table); + /* An invalid L1CD can be cached */ + arm_smmu_sync_cd(smmu_domain, ssid, false); + } + idx = ssid & (CTXDESC_L2_ENTRIES - 1); + } + return table->ptr + idx * CTXDESC_CD_DWORDS; } static u64 arm_smmu_cpu_tcr_to_cd(u64 tcr) @@ -1552,7 +1608,7 @@ static int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, u64 val; bool cd_live; struct arm_smmu_device *smmu = smmu_domain->smmu; - __le64 *cdptr = arm_smmu_get_cd_ptr(&smmu_domain->s1_cfg, ssid); + __le64 *cdptr = arm_smmu_get_cd_ptr(smmu_domain, ssid); /* * This function handles the following cases: @@ -1612,20 +1668,76 @@ static int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain) { + int ret; + size_t size = 0; + size_t max_contexts; struct arm_smmu_device *smmu = smmu_domain->smmu; struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; - cfg->s1fmt = STRTAB_STE_0_S1FMT_LINEAR; - return arm_smmu_alloc_cd_leaf_table(smmu, &cfg->table, - 1 << cfg->s1cdmax); + max_contexts = 1 << cfg->s1cdmax; + + if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || + max_contexts <= CTXDESC_L2_ENTRIES) { + cfg->s1fmt = STRTAB_STE_0_S1FMT_LINEAR; + cfg->num_tables = 1; + } else { + cfg->s1fmt = STRTAB_STE_0_S1FMT_64K_L2; + cfg->num_tables = DIV_ROUND_UP(max_contexts, + CTXDESC_L2_ENTRIES); + + size = cfg->num_tables * (CTXDESC_L1_DESC_DWORDS << 3); + cfg->l1ptr = dmam_alloc_coherent(smmu->dev, size, + &cfg->l1ptr_dma, + GFP_KERNEL | __GFP_ZERO); + if (!cfg->l1ptr) { + dev_warn(smmu->dev, "failed to allocate L1 context table\n"); + return -ENOMEM; + } + } + + cfg->tables = devm_kzalloc(smmu->dev, sizeof(struct arm_smmu_cd_table) * + cfg->num_tables, GFP_KERNEL); + if (!cfg->tables) { + ret = -ENOMEM; + goto err_free_l1; + } + + /* With two levels, leaf tables are allocated lazily */ + if (!cfg->l1ptr) { + ret = arm_smmu_alloc_cd_leaf_table(smmu, &cfg->tables[0], + max_contexts); + if (ret) + goto err_free_tables; + } + + return 0; + +err_free_tables: + devm_kfree(smmu->dev, cfg->tables); +err_free_l1: + if (cfg->l1ptr) + dmam_free_coherent(smmu->dev, size, cfg->l1ptr, cfg->l1ptr_dma); + return ret; } static void arm_smmu_free_cd_tables(struct arm_smmu_domain *smmu_domain) { + int i; struct arm_smmu_device *smmu = smmu_domain->smmu; struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; + size_t num_leaf_entries = 1 << cfg->s1cdmax; + struct arm_smmu_cd_table *table = cfg->tables; - arm_smmu_free_cd_leaf_table(smmu, &cfg->table, 1 << cfg->s1cdmax); + if (cfg->l1ptr) { + size_t size = cfg->num_tables * (CTXDESC_L1_DESC_DWORDS << 3); + + dmam_free_coherent(smmu->dev, size, cfg->l1ptr, cfg->l1ptr_dma); + num_leaf_entries = CTXDESC_L2_ENTRIES; + } + + for (i = 0; i < cfg->num_tables; i++, table++) + arm_smmu_free_cd_leaf_table(smmu, table, num_leaf_entries); + devm_kfree(smmu->dev, cfg->tables); } /* Stream table manipulation functions */ @@ -1745,6 +1857,9 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, } if (s1_cfg) { + dma_addr_t ptr_dma = s1_cfg->l1ptr ? s1_cfg->l1ptr_dma : + s1_cfg->tables[0].ptr_dma; + BUG_ON(ste_live); dst[1] = cpu_to_le64( FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) | @@ -1757,7 +1872,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, !(smmu->features & ARM_SMMU_FEAT_STALL_FORCE)) dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD); - val |= (s1_cfg->table.ptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) | + val |= (ptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) | FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | FIELD_PREP(STRTAB_STE_0_S1CDMAX, s1_cfg->s1cdmax) | FIELD_PREP(STRTAB_STE_0_S1FMT, s1_cfg->s1fmt); @@ -2273,7 +2388,7 @@ static void arm_smmu_domain_free(struct iommu_domain *domain) if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; - if (cfg->table.ptr) { + if (cfg->tables) { arm_smmu_free_cd_tables(smmu_domain); arm_smmu_bitmap_free(smmu->asid_map, cfg->cd.asid); } From patchwork Fri Nov 8 15:25:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 178917 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2860814ilf; Fri, 8 Nov 2019 07:26:58 -0800 (PST) X-Google-Smtp-Source: APXvYqzS2Ipj2kg5xB5WINyhqzYFi6LuVgDF8ciGdrfCVx9NByBXIppsHsIHVFLwihY0bMgJhzZF X-Received: by 2002:a17:906:27cc:: with SMTP id k12mr9252937ejc.181.1573226818106; Fri, 08 Nov 2019 07:26:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573226818; cv=none; d=google.com; s=arc-20160816; b=ROrIJ85QnMdQ7HySqG7EDm+FjAvci6Ihcwzo3nLCtW2dqzBGzTZiAOumPKAetO7Fz0 HYlwX2O/mQxhnSr4tXhYcULJDNhewdU9KUOPyOKkOyzFxXYjgBubDYZRvBDmX8RPhRHy q/6n7RbAoDGEt9D10im3cowpDfuKUjocY5jzC9I7Y5JFWCQntY6EDUxIFo2Kzd0AHERp u01HRGPOMfwgK9aF8gsWqXCe0u9quofVtCRvRY6stAs/HG7mR7LnMB7kkK3qEFDcBEGk WHcPXvk2el47N228qkhpKAwg2DBOYf66p3oxpb0ONV22keWf+b4QI5fjtE0k8COkZ/iw l/kQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id y31si4384892edb.47.2019.11.08.07.26.57; Fri, 08 Nov 2019 07:26:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BDQ7ZeC9; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726101AbfKHP05 (ORCPT + 7 others); Fri, 8 Nov 2019 10:26:57 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:37728 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726845AbfKHP05 (ORCPT ); Fri, 8 Nov 2019 10:26:57 -0500 Received: by mail-wm1-f66.google.com with SMTP id q130so6641378wme.2 for ; Fri, 08 Nov 2019 07:26:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XcF4FI/xEJT2ddBZxLwsH4kwVBtXhLcA/n4y2uy3gfU=; b=BDQ7ZeC9LB/2Lh6DQj16J8t0f6umU/jbny0nZwuikklVbgDi7dCWTbWMm0aRjLi005 V9skokHIp4EKef66gOqo4I/nTxWGvc+9S6EKjBlJxyLdKbQSqZqWvqeY+Z77HTqkfX16 4JkmEuH7gjM/RdLJO9BN/Vyp34vnY9Hjxh0xTuSOc2pbbXcqJvbeKLT8KPs3B6zuGeSk oQeEJyv8qFljGOOQ55RrjTk0fCjjESA+CfjKaY7SQ8SZ3HRmaDrfbgz8Gb5nIqgT00q+ AA1hFm+CnyswDokicO8N1z95D2kGm5pzZtaKebbBgrFl7rKhfqfepJE34J7LhtfZSbFY G1Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XcF4FI/xEJT2ddBZxLwsH4kwVBtXhLcA/n4y2uy3gfU=; b=DUvGcVhRbM508nKdqzBAy/1aDTFInhNiwrrNQNi0c4bCBwRz3WQSttJlxoz7TR7yOr YA1Hbizv1NIQ5Iyg9KE2BE+Wk4TcOGv/yo6iYrnGErd9P3zDq0QR7/MwbeoRXDVykU47 d2iT2q5HmXbCU1wO4nphNs8JzkvU/efyt04CtDZgsWU4Xukd6P/1NnOWDfmRW0tkk0Cz ZnzkE2w7a1QrE0xWvZnfDYy4xJlxX5I6bXOygYXNW6AewhHAiR+3BTeJkvx3ISTDPtOH YZRQ8kkLCrjCFsIk61RAsKTEPYPEEAE72Fhcwjb+C9++jAjbudodGl171mZWeyqN0Alg Xvgw== X-Gm-Message-State: APjAAAV1Ot7Wi42uiUpu1MB32prOfhBUQ25iBo0PIRHwpP6+OjX8ExvI q4/2jtJiWXeODWmhgX+eS9FYNQ== X-Received: by 2002:a1c:9917:: with SMTP id b23mr8603435wme.42.1573226815904; Fri, 08 Nov 2019 07:26:55 -0800 (PST) Received: from localhost.localdomain ([85.195.192.192]) by smtp.gmail.com with ESMTPSA id w18sm6579232wrp.31.2019.11.08.07.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 07:26:55 -0800 (PST) From: Jean-Philippe Brucker To: iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, guohanjun@huawei.com, sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org, will@kernel.org, robin.murphy@arm.com, zhangfei.gao@linaro.org, eric.auger@redhat.com, jonathan.cameron@huawei.com Subject: [PATCH v2 7/8] iommu/arm-smmu-v3: Improve add_device() error handling Date: Fri, 8 Nov 2019 16:25:07 +0100 Message-Id: <20191108152508.4039168-8-jean-philippe@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191108152508.4039168-1-jean-philippe@linaro.org> References: <20191108152508.4039168-1-jean-philippe@linaro.org> MIME-Version: 1.0 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org Let add_device() clean up after itself. The iommu_bus_init() function does call remove_device() on error, but other sites (e.g. of_iommu) do not. Don't free level-2 stream tables because we'd have to track if we allocated each of them or if they are used by other endpoints. It's not worth the hassle since they are managed resources. Reviewed-by: Eric Auger Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) -- 2.23.0 diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 82eac89ee187..88ec0bf33492 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -2826,14 +2826,16 @@ static int arm_smmu_add_device(struct device *dev) for (i = 0; i < master->num_sids; i++) { u32 sid = master->sids[i]; - if (!arm_smmu_sid_in_range(smmu, sid)) - return -ERANGE; + if (!arm_smmu_sid_in_range(smmu, sid)) { + ret = -ERANGE; + goto err_free_master; + } /* Ensure l2 strtab is initialised */ if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { ret = arm_smmu_init_l2_strtab(smmu, sid); if (ret) - return ret; + goto err_free_master; } } @@ -2843,13 +2845,25 @@ static int arm_smmu_add_device(struct device *dev) master->ssid_bits = min_t(u8, master->ssid_bits, CTXDESC_LINEAR_CDMAX); + ret = iommu_device_link(&smmu->iommu, dev); + if (ret) + goto err_free_master; + group = iommu_group_get_for_dev(dev); - if (!IS_ERR(group)) { - iommu_group_put(group); - iommu_device_link(&smmu->iommu, dev); + if (IS_ERR(group)) { + ret = PTR_ERR(group); + goto err_unlink; } - return PTR_ERR_OR_ZERO(group); + iommu_group_put(group); + return 0; + +err_unlink: + iommu_device_unlink(&smmu->iommu, dev); +err_free_master: + kfree(master); + fwspec->iommu_priv = NULL; + return ret; } static void arm_smmu_remove_device(struct device *dev)