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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Conor Dooley , Alim Akhtar , Sam Protsenko , Anand Moon , Marek Szyprowski Subject: [PATCH v4 1/7] drivers/thermal/exynos: use DEFINE_SIMPLE_DEV_PM_OPS Date: Wed, 11 Sep 2024 14:11:24 +0200 Message-ID: <20240911121136.1120026-2-m.majewski2@samsung.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240911121136.1120026-1-m.majewski2@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrMKsWRmVeSWpSXmKPExsWy7djPc7ocnQ/TDBbdsLR4MG8bm8X3LdeZ LNbsPcdkMe+zrMX8I+dYLc6f38BusenxNVaLy7vmsFl87j3CaDHj/D4mi3Ubb7FbLGxqYbeY eGwys8XaI3fZLeZ+mcps8X/PDnaLJw/72Cye9+1jchDyWDNvDaPHzll32T0W73nJ5LFpVSeb x51re9g8Ni+p9+jbsorR4/MmuQCOKC6blNSczLLUIn27BK6Mn/NmMhe8ZatoW7WUpYHxB2sX IyeHhICJxIm+CUxdjFwcQgIrGCXmP5vJDpIQEvjCKNH4jRci8ZlR4urvdnaYjksH30IVLWeU +PUhD6KolUniye+vzCAJNgEDiQdvlrGDJEQEFgNN+vGOFcRhFpjIIrH+TTcjSJWwgI/EmuaD YKNYBFQlHm/ZAhbnFbCTWPtjPdSB8hIX1zxnA7E5Bewlvr9eDlUjKHFy5hMWEJsZqKZ562xm kAUSArM5JfZN/scC0ewicXP5PCYIW1ji1fEtUD/ISPzfOR8qni8xY/N7oHoOILtC4u5BLwjT WuLjGWYQk1lAU2L9Ln2IYkeJla82QxXzSdx4KwhxAJ/EpG3TmSHCvBIdbUIQ1aoSx/dMYoaw pSWetNyGWukhcfjQZcYJjIqzkLwyC8krsxD2LmBkXsUonlpanJueWmyYl1quV5yYW1yal66X nJ+7iRGY7k7/O/5pB+PcVx/1DjEycTAeYpTgYFYS4e23u5cmxJuSWFmVWpQfX1Sak1p8iFGa g0VJnFc1RT5VSCA9sSQ1OzW1ILUIJsvEwSnVwMSrMpFH//ltvk+5ni8F1zyotQ2w3R1+Qunj 4kXPf+hflctu2rza3fOx+6aUsqdqD+ev38bQ7rVP5/HU5Aw35kmXXzmtKDG6+6VqSvSMQ0XV XhcTFDiu1t2w2/qb98QrBvuSaYF9h2dvU/j6lkvqSNCf3U+N5xlOjXG+9/q7p0FU5juthN19 PC9335ysyCa5/fGH09lZL5bnfzc3XLhx1qepN0+/X/kv96v+i12P7DNqPi5TyNO7vK3OeI/t tEOSgV8Xvc1qkTh9NuCAvsLLzvkhcRKFU2ut9jvFREqV7ZjhtPaX5A3V9gyV9nJzva1T8/kX nPoQs7n/91cNFwZ5uY6pyzZ3LV1SPX3q7bhPXj8YlFiKMxINtZiLihMBO69uLeYDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKIsWRmVeSWpSXmKPExsVy+t/xu7ocnQ/TDHZNk7J4MG8bm8X3LdeZ LNbsPcdkMe+zrMX8I+dYLc6f38BusenxNVaLy7vmsFl87j3CaDHj/D4mi3Ubb7FbLGxqYbeY eGwys8XaI3fZLeZ+mcps8X/PDnaLJw/72Cye9+1jchDyWDNvDaPHzll32T0W73nJ5LFpVSeb x51re9g8Ni+p9+jbsorR4/MmuQCOKD2bovzSklSFjPziElulaEMLIz1DSws9IxNLPUNj81gr I1MlfTublNSczLLUIn27BL2Mn/NmMhe8ZatoW7WUpYHxB2sXIyeHhICJxKWDb9m7GLk4hASW Mkqc/3UXKiEtcfjLFHYIW1jiz7UuNoiiZiaJu+t3MIEk2AQMJB68WQZWJCKwnFFic7sHSBGz wFwWic7Xq8ESwgI+EmuaD4LZLAKqEo+3bGEEsXkF7CTW/lgPtU1e4uKa52wgNqeAvcT318vB aoSAaj5uPMkKUS8ocXLmExYQmxmovnnrbOYJjAKzkKRmIUktYGRaxSiSWlqcm55bbKRXnJhb XJqXrpecn7uJERif24793LKDceWrj3qHGJk4GA8xSnAwK4nw9tvdSxPiTUmsrEotyo8vKs1J LT7EaAp090RmKdHkfGCCyCuJNzQzMDU0MbM0MLU0M1YS52W7cj5NSCA9sSQ1OzW1ILUIpo+J g1OqgYn/85k3zc/YG0qEC01aTKtNNh1ceTHX5czURO7VfP13vcIvd3SvdbzXIPQuytf1s57l b6sFalOsRcujr3xxdI/7uTksRk5CUn6dGhvnbdU7saFdfiE37vZu9pKKePUw8OzHfcpzrwsW LxJzsbWTdI/iOj2hU6uWJ0c1fnqcpVtKZ9jkmwqxUlO5wu7r7nnldf+DrnvAmx7HI7fmcVaf qw7h627OzN398mrt6YunTn6OrIjfccZuxfV5jLoLNjvGXSt7s1Nx45brv1fE/FHq/7vz6IQA aTEDO4k+Rv7eWeL5E4x3Pu10qlsf/XLdKXM77SpNnjlRM52+hLz5+n2P5TWnfbnfqv+EPSg0 Zn2ZosRSnJFoqMVcVJwIACaeMpxYAwAA X-CMS-MailID: 20240911121152eucas1p113445ce1ce6b6bd9c8f96322604bf517 X-Msg-Generator: CA X-RootMTR: 20240911121152eucas1p113445ce1ce6b6bd9c8f96322604bf517 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20240911121152eucas1p113445ce1ce6b6bd9c8f96322604bf517 References: <20240911121136.1120026-1-m.majewski2@samsung.com> SIMPLE_DEV_PM_OPS is deprecated, as noted next to its definition. Signed-off-by: Mateusz Majewski Reviewed-by: Sam Protsenko --- drivers/thermal/samsung/exynos_tmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index 96cffb2c44ba..9b7ca93a72f1 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -1150,8 +1150,8 @@ static int exynos_tmu_resume(struct device *dev) return 0; } -static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, - exynos_tmu_suspend, exynos_tmu_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(exynos_tmu_pm, + exynos_tmu_suspend, exynos_tmu_resume); #define EXYNOS_TMU_PM (&exynos_tmu_pm) #else #define EXYNOS_TMU_PM NULL From patchwork Wed Sep 11 12:11:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mateusz Majewski X-Patchwork-Id: 827610 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB8F8192B9F for ; Wed, 11 Sep 2024 12:11:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726056720; cv=none; b=PH3kyYFGDCiPvZAeH+RZpDM/1H1wMVMUZVj64jwCZublMmPklP5fGmd3er0NZD3++8bXvmR3QsZKabyhz+mcoD3rtf0WkUrbnVKAGyzQF35rsxVWG6upQs+j+WOiHDYmZNlPpAuDhbBShg9aw1JV6tI/Rdy5mO1l4UVjlO1Ytto= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726056720; c=relaxed/simple; bh=gY3sYk1R8x/s7rHhF9wyEi7cHSsdKFKDg0teFGH3L/o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=UZl14Tjb+CWk+WsSmxdkvrtg+WJGpZwniKvQdaq2L1jUnvVWXAcsdOGXsnSLybbRPyzh3sF+pg2EJ9bag1r93c0hZKNp42fDeB/CKTYjrdjo1GLEk+MYvZDR9hJps201jFN0ewKx7chPacRN5TJo8VCgqI8FsIfWydNDsjF96Vk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=sVUvEWl8; arc=none smtp.client-ip=210.118.77.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="sVUvEWl8" Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20240911121155euoutp02cedb68748ed6c23f9e393865f8f09497~0L3ApCqTF3264732647euoutp02g for ; Wed, 11 Sep 2024 12:11:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20240911121155euoutp02cedb68748ed6c23f9e393865f8f09497~0L3ApCqTF3264732647euoutp02g DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1726056716; bh=NJdZThH/4rVsf6XBL7/98lsA2ZRMGdmDLTG8epuqeXs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sVUvEWl8dUly/UZEf4otCf/jikq/x12KFsLJ2LUnQb21zQXb2wtclrIdxnu8b2gy0 Wkii4g9hDuOCPLv47Dn3Ppm7gx4qQzgu0WrMCL5ioA1L+qB31X+Ae0jY0QYlhRJ27C dNSlJ8CDO4vTNpkILyYSa3PzqtPDAlgtsI0QXte4= Received: from eusmges2new.samsung.com (unknown [203.254.199.244]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20240911121155eucas1p1f1fda5e90a3c7cf15e520430d0564982~0L3ADN0pR1328313283eucas1p1s; Wed, 11 Sep 2024 12:11:55 +0000 (GMT) Received: from eucas1p2.samsung.com ( [182.198.249.207]) by eusmges2new.samsung.com (EUCPMTA) with SMTP id D2.61.09875.B0981E66; Wed, 11 Sep 2024 13:11:55 +0100 (BST) Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by eucas1p1.samsung.com (KnoxPortal) with ESMTPA id 20240911121154eucas1p1a429a565c446cdd968f565df1ffae42c~0L2-fJYMn2450124501eucas1p1N; Wed, 11 Sep 2024 12:11:54 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20240911121154eusmtrp28d359762649260d33f3c7f8a315fd71e~0L2-eCf6X2688526885eusmtrp2c; Wed, 11 Sep 2024 12:11:54 +0000 (GMT) X-AuditID: cbfec7f4-131ff70000002693-93-66e1890b802d Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id DC.4D.19096.A0981E66; Wed, 11 Sep 2024 13:11:54 +0100 (BST) Received: from AMDC4515.eu.corp.samsungelectronics.net (unknown [106.120.51.28]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20240911121153eusmtip1f4eff36b994b8846f7538e82aadde599~0L2_jbr-E0774607746eusmtip14; Wed, 11 Sep 2024 12:11:53 +0000 (GMT) From: Mateusz Majewski To: linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mateusz Majewski , Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Conor Dooley , Alim Akhtar , Sam Protsenko , Anand Moon , Marek Szyprowski Subject: [PATCH v4 3/7] drivers/thermal/exynos: improve sanitize_temp_error Date: Wed, 11 Sep 2024 14:11:26 +0200 Message-ID: <20240911121136.1120026-4-m.majewski2@samsung.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240911121136.1120026-1-m.majewski2@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrEKsWRmVeSWpSXmKPExsWy7djP87rcnQ/TDH7eZrd4MG8bm8X3LdeZ LNbsPcdkMe+zrMX8I+dYLc6f38BusenxNVaLy7vmsFl87j3CaDHj/D4mi3Ubb7FbLGxqYbeY eGwys8XaI3fZLeZ+mcps8X/PDnaLJw/72Cye9+1jchDyWDNvDaPHzll32T0W73nJ5LFpVSeb x51re9g8Ni+p9+jbsorR4/MmuQCOKC6blNSczLLUIn27BK6Mo4fWMBZc0quY+Og5UwPjCbUu Rk4OCQETidefnzJ2MXJxCAmsYJR41H6OHSQhJPCFUaLzjw9E4jOjxKnv7SwwHS9vvGCDSCxn lDjy/AGU08oksevMM0aQKjYBA4kHb5axgyREBBYzSjT+eMcK4jALTGSRWP+mG6xKWMBb4ujz SawgNouAqsT9y71gO3gF7CR+/vzEBLFPXuLimudsIDangL3E99fLGSFqBCVOznwCVs8MVNO8 dTYzyAIJgfmcEu+2zgYaygHkuEisOJELMUdY4tXxLewQtozE/53zoebnS8zY/J4ForxC4u5B LwjTWuLjGWYQk1lAU2L9Ln2IYkeJyxumsUFU8EnceCsIsZ9PYtK26cwQYV6JjjYhiGpVieN7 JjFD2NIST1puM0GUeEi8+Mw9gVFxFpJHZiF5ZBbC2gWMzKsYxVNLi3PTU4uN8lLL9YoTc4tL 89L1kvNzNzECk93pf8e/7GBc/uqj3iFGJg7GQ4wSHMxKIrz9dvfShHhTEiurUovy44tKc1KL DzFKc7AoifOqpsinCgmkJ5akZqemFqQWwWSZODilGphWxv9Typ+k2R36p1NUJOhkitTVBRX/ vJe9EGOZM2l1/HFmoVfLDu/SctPJrtFh3tO8idlOdW96WKztee8tW5uk3uf287RNrr6dV9PN 4v0sJ7dkXl4rY+yN63lNrtGh6tbv+ydUJCyW/vP5ad+l8tVev5fMkJJdb5OSsTn/8+m0Pr54 3+ROxQyRe8Gycx9sj95TVPOMf39n06UTAp3aVp2F727NeyPyRM0nqKw3UEPNibulfdt67lly tx/wCXZ84lzz38/QLT314qpX37T47t36sdUibo7VtS9VoU1yZaFHdm0Wu2Eh95D7xDz7R8sT t4e+2OFx/7zXJCHz82JVb3iCspYzahosU/5kNCH1ghJLcUaioRZzUXEiAKWnpeTlAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrCIsWRmVeSWpSXmKPExsVy+t/xu7pcnQ/TDD5dVbN4MG8bm8X3LdeZ LNbsPcdkMe+zrMX8I+dYLc6f38BusenxNVaLy7vmsFl87j3CaDHj/D4mi3Ubb7FbLGxqYbeY eGwys8XaI3fZLeZ+mcps8X/PDnaLJw/72Cye9+1jchDyWDNvDaPHzll32T0W73nJ5LFpVSeb x51re9g8Ni+p9+jbsorR4/MmuQCOKD2bovzSklSFjPziElulaEMLIz1DSws9IxNLPUNj81gr I1MlfTublNSczLLUIn27BL2Mo4fWMBZc0quY+Og5UwPjCbUuRk4OCQETiZc3XrB1MXJxCAks ZZSYsusmK0RCWuLwlynsELawxJ9rXWwgtpBAM5PEs/PVIDabgIHEgzfLwGpEBJYzSmxu9wAZ xCwwl0Wi8/VqsISwgLfE0eeTwIayCKhK3L/cywJi8wrYSfz8+YkJYoG8xMU1z8EWcArYS3x/ vZwRYpmdxMeNJ1kh6gUlTs58AtbLDFTfvHU28wRGgVlIUrOQpBYwMq1iFEktLc5Nzy020itO zC0uzUvXS87P3cQIjM5tx35u2cG48tVHvUOMTByMhxglOJiVRHj77e6lCfGmJFZWpRblxxeV 5qQWH2I0Bbp7IrOUaHI+MD3klcQbmhmYGpqYWRqYWpoZK4nzsl05nyYkkJ5YkpqdmlqQWgTT x8TBKdXApD7zem0qA4OU9M/K7vj/su/iYi70xZzobTNN9b5p/1QpbUXoH6c/P+bJya3ODLZ2 tlUP0i/aaSEl/1KeZ4rJ/rzNz5Tq/xj+392+Ys1r60NVX09uu5WUMdF30+KvX153/LecwbzY ryXywpWevt8evSfmHTp+8l/WxnnJ1yrX26WxiZaeSgj85BciKBhwdPe0G5NDiyZUc0p0Totw uMLWwFT79aLaoj8ld7Rn7YgOXFTcVC7tEVpl9fnwthrpdX8enfKas33xe9kzF5ZEF7ew/0r9 p3FjbcF19ZaYR6/iPjH8Ddm96IFw4R3Ob2Ia1vICGx9q7uxKSotLbZrNdjT94O3zyg1SH+PM lir4WS3gUWIpzkg01GIuKk4EADuSQhZXAwAA X-CMS-MailID: 20240911121154eucas1p1a429a565c446cdd968f565df1ffae42c X-Msg-Generator: CA X-RootMTR: 20240911121154eucas1p1a429a565c446cdd968f565df1ffae42c X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20240911121154eucas1p1a429a565c446cdd968f565df1ffae42c References: <20240911121136.1120026-1-m.majewski2@samsung.com> There are two minor issues regarding this function. One is that it attempts to calculate the second calibration value even if 1-point trimming is being used; in this case, the calculated value is probably not useful and is never used anyway. Changing this also requires a minor reordering in Exynos5433 initialization function, so that we know which type of trimming is used before we call sanitize_temp_error. The second issue is that the function is not very consistent when it comes to the use of Exynos7-specific parameters. This seems to not be an issue in practice, in part because some of these issues are related to the mentioned calculation of the second calibration value. However, fixing this makes the code a bit less confusing, and will be required for Exynos850 which has 9-bit temperature values and uses 2-point trimming. Signed-off-by: Mateusz Majewski --- v3 -> v4: further reworked to avoid SoC-specific code, instead using SoC-specific parameters inside of exynos_tmu_data (probably different enough to drop R-b). v1 -> v2: reworked to change shift instead of only mask and to also fix the 2-point trimming issue. drivers/thermal/samsung/exynos_tmu.c | 40 ++++++++++++++++++---------- 1 file changed, 26 insertions(+), 14 deletions(-) diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index b68e9755c933..8b1014915c31 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -111,6 +111,7 @@ #define EXYNOS7_TMU_REG_EMUL_CON 0x160 #define EXYNOS7_TMU_TEMP_MASK 0x1ff +#define EXYNOS7_TMU_TEMP_SHIFT 9 #define EXYNOS7_PD_DET_EN_SHIFT 23 #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0 #define EXYNOS7_EMUL_DATA_SHIFT 7 @@ -152,6 +153,8 @@ enum soc_type { * @max_efuse_value: maximum valid trimming data * @temp_error1: fused value of the first point trim. * @temp_error2: fused value of the second point trim. + * @temp_mask: SoC specific temperature mask + * @temp_85_shift: SoC specific address shift * @gain: gain of amplifier in the positive-TC generator block * 0 < gain <= 15 * @reference_voltage: reference voltage of amplifier @@ -182,6 +185,8 @@ struct exynos_tmu_data { u32 min_efuse_value; u32 max_efuse_value; u16 temp_error1, temp_error2; + u16 temp_mask; + int temp_85_shift; u8 gain; u8 reference_voltage; struct thermal_zone_device *tzd; @@ -229,25 +234,26 @@ static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code) EXYNOS_FIRST_POINT_TRIM; } +/* + * Sanitize sensor calibration values, according to minimum and maximum + * values defined for each SoC. + */ static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info) { - u16 tmu_temp_mask = - (data->soc == SOC_ARCH_EXYNOS7) ? EXYNOS7_TMU_TEMP_MASK - : EXYNOS_TMU_TEMP_MASK; - - data->temp_error1 = trim_info & tmu_temp_mask; - data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) & - EXYNOS_TMU_TEMP_MASK); - + data->temp_error1 = trim_info & data->temp_mask; if (!data->temp_error1 || (data->min_efuse_value > data->temp_error1) || (data->temp_error1 > data->max_efuse_value)) - data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK; + data->temp_error1 = data->efuse_value & data->temp_mask; - if (!data->temp_error2) - data->temp_error2 = - (data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) & - EXYNOS_TMU_TEMP_MASK; + if (data->cal_type == TYPE_TWO_POINT_TRIMMING) { + data->temp_error2 = (trim_info >> data->temp_85_shift) & + data->temp_mask; + if (!data->temp_error2) + data->temp_error2 = + (data->efuse_value >> data->temp_85_shift) & + data->temp_mask; + } } static int exynos_tmu_initialize(struct platform_device *pdev) @@ -510,7 +516,6 @@ static void exynos5433_tmu_initialize(struct platform_device *pdev) int sensor_id, cal_type; trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); - sanitize_temp_error(data, trim_info); /* Read the temperature sensor id */ sensor_id = (trim_info & EXYNOS5433_TRIMINFO_SENSOR_ID_MASK) @@ -532,6 +537,8 @@ static void exynos5433_tmu_initialize(struct platform_device *pdev) break; } + sanitize_temp_error(data, trim_info); + dev_info(&pdev->dev, "Calibration type is %d-point calibration\n", cal_type ? 2 : 1); } @@ -876,6 +883,7 @@ static int exynos_map_dt_data(struct platform_device *pdev) data->tmu_control = exynos4210_tmu_control; data->tmu_read = exynos4210_tmu_read; data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; + data->temp_mask = EXYNOS_TMU_TEMP_MASK; data->gain = 15; data->reference_voltage = 7; data->efuse_value = 55; @@ -898,6 +906,7 @@ static int exynos_map_dt_data(struct platform_device *pdev) data->tmu_read = exynos4412_tmu_read; data->tmu_set_emulation = exynos4412_tmu_set_emulation; data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; + data->temp_mask = EXYNOS_TMU_TEMP_MASK; data->gain = 8; data->reference_voltage = 16; data->efuse_value = 55; @@ -919,6 +928,8 @@ static int exynos_map_dt_data(struct platform_device *pdev) data->tmu_read = exynos4412_tmu_read; data->tmu_set_emulation = exynos4412_tmu_set_emulation; data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; + data->temp_mask = EXYNOS_TMU_TEMP_MASK; + data->temp_85_shift = EXYNOS_TRIMINFO_85_SHIFT; data->gain = 8; if (res.start == EXYNOS5433_G3D_BASE) data->reference_voltage = 23; @@ -939,6 +950,7 @@ static int exynos_map_dt_data(struct platform_device *pdev) data->tmu_read = exynos7_tmu_read; data->tmu_set_emulation = exynos4412_tmu_set_emulation; data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; + data->temp_mask = EXYNOS7_TMU_TEMP_MASK; data->gain = 9; data->reference_voltage = 17; data->efuse_value = 75; From patchwork Wed Sep 11 12:11:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mateusz Majewski X-Patchwork-Id: 827609 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C643192B9F for ; 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Wed, 11 Sep 2024 12:11:57 +0000 (GMT) From: Mateusz Majewski To: linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mateusz Majewski , Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Conor Dooley , Alim Akhtar , Sam Protsenko , Anand Moon , Marek Szyprowski Subject: [PATCH v4 6/7] drivers/thermal/exynos: add initial Exynos850 support Date: Wed, 11 Sep 2024 14:11:29 +0200 Message-ID: <20240911121136.1120026-7-m.majewski2@samsung.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240911121136.1120026-1-m.majewski2@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCKsWRmVeSWpSXmKPExsWy7djPc7p8nQ/TDLruGFs8mLeNzeL7lutM Fmv2nmOymPdZ1mL+kXOsFufPb2C32PT4GqvF5V1z2Cw+9x5htJhxfh+TxbqNt9gtFja1sFtM PDaZ2WLtkbvsFnO/TGW2+L9nB7vFk4d9bBbP+/YxOQh5rJm3htFj56y77B6L97xk8ti0qpPN 4861PWwem5fUe/RtWcXo8XmTXABHFJdNSmpOZllqkb5dAldG86Q3bAWfoitOzFrL2MB40beL kZNDQsBE4kz7RNYuRi4OIYEVjBLN/2ezQThfGCWubD3NDOF8ZpT427ILyOEAa3k/xxwivpxR ov3tfCYIp5VJomvnBxaQuWwCBhIP3ixjB0mICCxmlGj88Q5sCbPARBaJ9W+6GUGqhAX8JW5N bQKzWQRUJdZvuwbWzStgJ9HZ+ZQN4kJ5iYtrnoPZnAL2Et9fL2eEqBGUODnzCVg9M1BN89bZ YLdKCMznlGhs7oBqdpHYCgxRCFtY4tXxLVC2jMT/nSB3g9j5EjM2v2eB+K1C4u5BLwjTWuLj GbCPmQU0Jdbv0ocodpRoXHgZqphP4sZbQYgD+CQmbZsODR9eiY42IYhqVYnjeyYxQ9jSEk9a bkOt9JB4vXEW0wRGxVlIXpmF5JVZCHsXMDKvYhRPLS3OTU8tNsxLLdcrTswtLs1L10vOz93E CEx4p/8d/7SDce6rj3qHGJk4GA8xSnAwK4nw9tvdSxPiTUmsrEotyo8vKs1JLT7EKM3BoiTO q5oinyokkJ5YkpqdmlqQWgSTZeLglGpgknox45bHF9XKpGuyc79IlHR7y+aLCKpHbivf5eVf 90J3nfzkq9FXOF7LWWUZvCvw4TlazL345dnLHzLz/69czyqRujZCTXTFy7MyWg9d//mmvxT5 MVWlfFoj0xvPAO7mIwc3M6z0qDcWWXDlhHTuwv+nD1d4eT5ee1PJyb0qylpMfs6DB01r38Yc LJUJ+PZogTWDtzfPxWrt7bHSv/Yl+W6dHfLqmCiXTOgB5tlX/hdFyk2zUY2cIvDa45+j6vLp zz1SgpRuft1dOPWPTJTkmwm/L0ociGp/+37JfsV5P26e23G2iO3bxCar2wqsx54tqEi8smux bfPWI0ztzydqHin/+l03cKmk2olE4Sc/kpRYijMSDbWYi4oTAZ+Y7RfnAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMIsWRmVeSWpSXmKPExsVy+t/xu7p8nQ/TDJoeMVo8mLeNzeL7lutM Fmv2nmOymPdZ1mL+kXOsFufPb2C32PT4GqvF5V1z2Cw+9x5htJhxfh+TxbqNt9gtFja1sFtM PDaZ2WLtkbvsFnO/TGW2+L9nB7vFk4d9bBbP+/YxOQh5rJm3htFj56y77B6L97xk8ti0qpPN 4861PWwem5fUe/RtWcXo8XmTXABHlJ5NUX5pSapCRn5xia1StKGFkZ6hpYWekYmlnqGxeayV kamSvp1NSmpOZllqkb5dgl5G86Q3bAWfoitOzFrL2MB40beLkYNDQsBE4v0c8y5GTg4hgaWM Ej+Xs4DYEgLSEoe/TGGHsIUl/lzrYuti5AKqaWaSaNjfDZZgEzCQePBmGZgtIrCcUWJzuwdI EbPAXBaJzterwRLCAr4Sa6acArNZBFQl1m+7BraBV8BOorPzKRvEBnmJi2ueg9mcAvYS318v Z4S4yE7i48aTrBD1ghInZz4B62UGqm/eOpt5AqPALCSpWUhSCxiZVjGKpJYW56bnFhvpFSfm Fpfmpesl5+duYgTG5rZjP7fsYFz56qPeIUYmDsZDjBIczEoivP1299KEeFMSK6tSi/Lji0pz UosPMZoC3T2RWUo0OR+YHPJK4g3NDEwNTcwsDUwtzYyVxHnZrpxPExJITyxJzU5NLUgtgulj 4uCUamCavWuhk9zBPtfpOncnmBrW754S/lltQ5FJwL/1H3r9vkeXXUh3mKm4w06wboKgh49M WMNrbeZjTDV9mqnxeySqCj+K9HgYXPh+RXjGoY+JKekKobYdG9y//DD82TjxfqLWQy5fRjcD zj9vzweyBZ2PuM28yXnz563ruuffrD8r2+ct9e9hpL3vk88zD7XmPF9vyyN9OCFh+xGVQo+/ k0LEWdbfXp+X+Dmw6JWpBIdC/hm2kwVtsgu/tjfXev68/kN70rev5747JZ0MWWwRsvRvS0aH +bkX+55XFdXkv/NP4LZtn9fku2xat8qUeWHztA8ttmHV+bbGV5sz61BkC/OKpaXfCvfMb0vY t/33Y1YlluKMREMt5qLiRACJPi8EVgMAAA== X-CMS-MailID: 20240911121158eucas1p2ab3ec5b5b59351af22c5740e02236b16 X-Msg-Generator: CA X-RootMTR: 20240911121158eucas1p2ab3ec5b5b59351af22c5740e02236b16 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20240911121158eucas1p2ab3ec5b5b59351af22c5740e02236b16 References: <20240911121136.1120026-1-m.majewski2@samsung.com> This is loosely adapted from an implementation available at https://gitlab.com/Linaro/96boards/e850-96/kernel/-/blob/android-exynos-4.14-linaro/drivers/thermal/samsung/exynos_tmu.c Some differences from that implementation: - unlike that implementation, we do not use the ACPM mechanism, instead we just access the registers, like we do for other SoCs, - the SoC is supposed to support multiple sensors inside one unit. The vendor implementation uses one kernel device per sensor, we would probably prefer to have one device for all sensors, have #thermal-sensor-cells = <1> and so on. We implemented this, but we could not get the extra sensors to work on our hardware so far. This might be due to a misconfiguration and we will probably come back to this, however our implementation only supports a single sensor for now, - the vendor implementation supports disabling CPU cores as a cooling device. We did not attempt to port this, and this would not really fit this driver anyway. Additionally, some differences from the other SoCs supported by this driver: - we do not really constrain the e-fuse information like the other SoCs do (data->{min,max}_efuse_value). In our tests, those values (as well as the raw sensor values) were much higher than in the other SoCs, to the degree that reusing the data->{min,max}_efuse_value from the other SoCs would cause instant critical temperature reset on boot, - this SoC provides more information in the e-fuse data than other SoCs, so we read some values inside exynos850_tmu_initialize instead of hardcoding them in exynos_map_dt_data. Reviewed-by: Sam Protsenko Signed-off-by: Mateusz Majewski --- v3 -> v4: adapted to sanitize_temp_error change. v1 -> v2: rename and reorder some registers, use the correct register offset for EXYNOS850_TMU_REG_AVG_CON, make the clock required, additionally do some minor style changes. drivers/thermal/samsung/exynos_tmu.c | 179 ++++++++++++++++++++++++++- 1 file changed, 176 insertions(+), 3 deletions(-) diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index 9bddf9fd5049..c5769f9b6471 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -117,6 +117,41 @@ #define EXYNOS7_EMUL_DATA_SHIFT 7 #define EXYNOS7_EMUL_DATA_MASK 0x1ff +/* Exynos850 specific registers */ +#define EXYNOS850_TMU_REG_CURRENT_TEMP0_1 0x40 +#define EXYNOS850_TMU_REG_THD_TEMP0_RISE 0x50 +#define EXYNOS850_TMU_REG_THD_TEMP0_FALL 0x60 + +#define EXYNOS850_TMU_TRIMINFO_SHIFT 4 +#define EXYNOS850_TMU_TRIMINFO_OFFSET(n) \ + (EXYNOS_TMU_REG_TRIMINFO + (n) * EXYNOS850_TMU_TRIMINFO_SHIFT) +#define EXYNOS850_TMU_T_TRIM0_SHIFT 18 + +#define EXYNOS850_TMU_REG_CONTROL1 0x24 +#define EXYNOS850_TMU_LPI_MODE_MASK 1 +#define EXYNOS850_TMU_LPI_MODE_SHIFT 10 + +#define EXYNOS850_TMU_REG_COUNTER_VALUE0 0x30 +#define EXYNOS850_TMU_EN_TEMP_SEN_OFF_MASK 0xffff +#define EXYNOS850_TMU_EN_TEMP_SEN_OFF_SHIFT 0 + +#define EXYNOS850_TMU_REG_COUNTER_VALUE1 0x34 +#define EXYNOS850_TMU_CLK_SENSE_ON_MASK 0xffff +#define EXYNOS850_TMU_CLK_SENSE_ON_SHIFT 16 + +#define EXYNOS850_TMU_REG_AVG_CON 0x38 +#define EXYNOS850_TMU_AVG_MODE_MASK 0x7 +#define EXYNOS850_TMU_DEM_ENABLE BIT(4) + +#define EXYNOS850_TMU_REG_TRIM0 0x3c +#define EXYNOS850_TMU_TRIM0_MASK 0xf +#define EXYNOS850_TMU_VBEI_TRIM_SHIFT 8 +#define EXYNOS850_TMU_VREF_TRIM_SHIFT 12 +#define EXYNOS850_TMU_BGRI_TRIM_SHIFT 20 + +#define EXYNOS850_TMU_TEM1051X_SENSE_VALUE 0x028a +#define EXYNOS850_TMU_TEM1456X_SENSE_VALUE 0x0a28 + #define EXYNOS_FIRST_POINT_TRIM 25 #define EXYNOS_SECOND_POINT_TRIM 85 @@ -134,6 +169,7 @@ enum soc_type { SOC_ARCH_EXYNOS5420_TRIMINFO, SOC_ARCH_EXYNOS5433, SOC_ARCH_EXYNOS7, + SOC_ARCH_EXYNOS850, }; /** @@ -584,6 +620,114 @@ static void exynos7_tmu_initialize(struct platform_device *pdev) sanitize_temp_error(data, trim_info); } +static void exynos850_tmu_set_low_temp(struct exynos_tmu_data *data, u8 temp) +{ + exynos_tmu_update_temp(data, EXYNOS850_TMU_REG_THD_TEMP0_FALL + 12, 0, + temp); + exynos_tmu_update_bit(data, EXYNOS7_TMU_REG_INTEN, + EXYNOS_TMU_INTEN_FALL0_SHIFT + 0, true); +} + +static void exynos850_tmu_set_high_temp(struct exynos_tmu_data *data, u8 temp) +{ + exynos_tmu_update_temp(data, EXYNOS850_TMU_REG_THD_TEMP0_RISE + 12, 16, + temp); + exynos_tmu_update_bit(data, EXYNOS7_TMU_REG_INTEN, + EXYNOS7_TMU_INTEN_RISE0_SHIFT + 1, true); +} + +static void exynos850_tmu_disable_low(struct exynos_tmu_data *data) +{ + exynos_tmu_update_bit(data, EXYNOS7_TMU_REG_INTEN, + EXYNOS_TMU_INTEN_FALL0_SHIFT + 0, false); +} + +static void exynos850_tmu_disable_high(struct exynos_tmu_data *data) +{ + exynos_tmu_update_bit(data, EXYNOS7_TMU_REG_INTEN, + EXYNOS7_TMU_INTEN_RISE0_SHIFT + 1, false); +} + +static void exynos850_tmu_set_crit_temp(struct exynos_tmu_data *data, u8 temp) +{ + exynos_tmu_update_temp(data, EXYNOS850_TMU_REG_THD_TEMP0_RISE + 0, 16, + temp); + exynos_tmu_update_bit(data, EXYNOS_TMU_REG_CONTROL, + EXYNOS_TMU_THERM_TRIP_EN_SHIFT, true); + exynos_tmu_update_bit(data, EXYNOS7_TMU_REG_INTEN, + EXYNOS7_TMU_INTEN_RISE0_SHIFT + 7, true); +} + +static void exynos850_tmu_initialize(struct platform_device *pdev) +{ + struct exynos_tmu_data *data = platform_get_drvdata(pdev); + u32 cal_type, avg_mode, reg, bgri, vref, vbei; + + reg = readl(data->base + EXYNOS850_TMU_TRIMINFO_OFFSET(0)); + cal_type = (reg & EXYNOS5433_TRIMINFO_CALIB_SEL_MASK) >> + EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT; + data->reference_voltage = (reg >> EXYNOS850_TMU_T_TRIM0_SHIFT) & + EXYNOS_TMU_REF_VOLTAGE_MASK; + reg = readl(data->base + EXYNOS850_TMU_TRIMINFO_OFFSET(1)); + data->gain = (reg >> EXYNOS850_TMU_T_TRIM0_SHIFT) & + EXYNOS_TMU_BUF_SLOPE_SEL_MASK; + reg = readl(data->base + EXYNOS850_TMU_TRIMINFO_OFFSET(2)); + avg_mode = (reg >> EXYNOS850_TMU_T_TRIM0_SHIFT) & + EXYNOS850_TMU_AVG_MODE_MASK; + reg = readl(data->base + EXYNOS850_TMU_TRIMINFO_OFFSET(3)); + bgri = (reg >> EXYNOS850_TMU_T_TRIM0_SHIFT) & EXYNOS850_TMU_TRIM0_MASK; + reg = readl(data->base + EXYNOS850_TMU_TRIMINFO_OFFSET(4)); + vref = (reg >> EXYNOS850_TMU_T_TRIM0_SHIFT) & EXYNOS850_TMU_TRIM0_MASK; + reg = readl(data->base + EXYNOS850_TMU_TRIMINFO_OFFSET(5)); + vbei = (reg >> EXYNOS850_TMU_T_TRIM0_SHIFT) & EXYNOS850_TMU_TRIM0_MASK; + + data->cal_type = cal_type == EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING ? + TYPE_TWO_POINT_TRIMMING : + TYPE_ONE_POINT_TRIMMING; + + reg = readl(data->base + EXYNOS850_TMU_TRIMINFO_OFFSET(0)); + sanitize_temp_error(data, reg); + + dev_info(&pdev->dev, "Calibration type is %d-point calibration\n", + cal_type ? 2 : 1); + + reg = readl(data->base + EXYNOS850_TMU_REG_AVG_CON); + reg &= ~EXYNOS850_TMU_AVG_MODE_MASK; + reg &= ~EXYNOS850_TMU_DEM_ENABLE; + if (avg_mode) { + reg |= avg_mode; + reg |= EXYNOS850_TMU_DEM_ENABLE; + } + writel(reg, data->base + EXYNOS850_TMU_REG_AVG_CON); + + reg = readl(data->base + EXYNOS850_TMU_REG_COUNTER_VALUE0); + reg &= ~(EXYNOS850_TMU_EN_TEMP_SEN_OFF_MASK + << EXYNOS850_TMU_EN_TEMP_SEN_OFF_SHIFT); + reg |= EXYNOS850_TMU_TEM1051X_SENSE_VALUE + << EXYNOS850_TMU_EN_TEMP_SEN_OFF_SHIFT; + writel(reg, data->base + EXYNOS850_TMU_REG_COUNTER_VALUE0); + + reg = readl(data->base + EXYNOS850_TMU_REG_COUNTER_VALUE1); + reg &= ~(EXYNOS850_TMU_CLK_SENSE_ON_MASK + << EXYNOS850_TMU_CLK_SENSE_ON_SHIFT); + reg |= EXYNOS850_TMU_TEM1051X_SENSE_VALUE + << EXYNOS850_TMU_CLK_SENSE_ON_SHIFT; + writel(reg, data->base + EXYNOS850_TMU_REG_COUNTER_VALUE1); + + reg = readl(data->base + EXYNOS850_TMU_REG_TRIM0); + reg &= ~(EXYNOS850_TMU_TRIM0_MASK << EXYNOS850_TMU_BGRI_TRIM_SHIFT); + reg &= ~(EXYNOS850_TMU_TRIM0_MASK << EXYNOS850_TMU_VREF_TRIM_SHIFT); + reg &= ~(EXYNOS850_TMU_TRIM0_MASK << EXYNOS850_TMU_VBEI_TRIM_SHIFT); + reg |= bgri << EXYNOS850_TMU_BGRI_TRIM_SHIFT; + reg |= vref << EXYNOS850_TMU_VREF_TRIM_SHIFT; + reg |= vbei << EXYNOS850_TMU_VBEI_TRIM_SHIFT; + writel(reg, data->base + EXYNOS850_TMU_REG_TRIM0); + + reg = readl(data->base + EXYNOS850_TMU_REG_CONTROL1); + reg &= ~(EXYNOS850_TMU_LPI_MODE_MASK << EXYNOS850_TMU_LPI_MODE_SHIFT); + writel(reg, data->base + EXYNOS850_TMU_REG_CONTROL1); +} + static void exynos4210_tmu_control(struct platform_device *pdev, bool on) { struct exynos_tmu_data *data = platform_get_drvdata(pdev); @@ -673,7 +817,8 @@ static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val, val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT); val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT); - if (data->soc == SOC_ARCH_EXYNOS7) { + if (data->soc == SOC_ARCH_EXYNOS7 || + data->soc == SOC_ARCH_EXYNOS850) { val &= ~(EXYNOS7_EMUL_DATA_MASK << EXYNOS7_EMUL_DATA_SHIFT); val |= (temp_to_code(data, temp) << @@ -703,7 +848,8 @@ static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data, emul_con = EXYNOS5260_EMUL_CON; else if (data->soc == SOC_ARCH_EXYNOS5433) emul_con = EXYNOS5433_TMU_EMUL_CON; - else if (data->soc == SOC_ARCH_EXYNOS7) + else if (data->soc == SOC_ARCH_EXYNOS7 || + data->soc == SOC_ARCH_EXYNOS850) emul_con = EXYNOS7_TMU_REG_EMUL_CON; else emul_con = EXYNOS_EMUL_CON; @@ -758,6 +904,12 @@ static int exynos7_tmu_read(struct exynos_tmu_data *data) EXYNOS7_TMU_TEMP_MASK; } +static int exynos850_tmu_read(struct exynos_tmu_data *data) +{ + return readw(data->base + EXYNOS850_TMU_REG_CURRENT_TEMP0_1) & + EXYNOS7_TMU_TEMP_MASK; +} + static irqreturn_t exynos_tmu_threaded_irq(int irq, void *id) { struct exynos_tmu_data *data = id; @@ -784,7 +936,8 @@ static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) if (data->soc == SOC_ARCH_EXYNOS5260) { tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT; tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR; - } else if (data->soc == SOC_ARCH_EXYNOS7) { + } else if (data->soc == SOC_ARCH_EXYNOS7 || + data->soc == SOC_ARCH_EXYNOS850) { tmu_intstat = EXYNOS7_TMU_REG_INTPEND; tmu_intclear = EXYNOS7_TMU_REG_INTPEND; } else if (data->soc == SOC_ARCH_EXYNOS5433) { @@ -835,6 +988,9 @@ static const struct of_device_id exynos_tmu_match[] = { }, { .compatible = "samsung,exynos7-tmu", .data = (const void *)SOC_ARCH_EXYNOS7, + }, { + .compatible = "samsung,exynos850-tmu", + .data = (const void *)SOC_ARCH_EXYNOS850, }, { }, }; @@ -952,6 +1108,23 @@ static int exynos_map_dt_data(struct platform_device *pdev) data->min_efuse_value = 15; data->max_efuse_value = 100; break; + case SOC_ARCH_EXYNOS850: + data->tmu_set_low_temp = exynos850_tmu_set_low_temp; + data->tmu_set_high_temp = exynos850_tmu_set_high_temp; + data->tmu_disable_low = exynos850_tmu_disable_low; + data->tmu_disable_high = exynos850_tmu_disable_high; + data->tmu_set_crit_temp = exynos850_tmu_set_crit_temp; + data->tmu_initialize = exynos850_tmu_initialize; + data->tmu_control = exynos4210_tmu_control; + data->tmu_read = exynos850_tmu_read; + data->tmu_set_emulation = exynos4412_tmu_set_emulation; + data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; + data->temp_mask = EXYNOS7_TMU_TEMP_MASK; + data->temp_85_shift = EXYNOS7_TMU_TEMP_SHIFT; + data->efuse_value = 55; + data->min_efuse_value = 0; + data->max_efuse_value = 511; + break; default: dev_err(&pdev->dev, "Platform not supported\n"); return -EINVAL;