From patchwork Thu Sep 19 09:12:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 829773 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 514DF12E48; Thu, 19 Sep 2024 09:18:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726737520; cv=none; b=XXHr0g9QYh2P1P3GkOQXOkegRpMQBjFL7giwWhHxv/+X+0wdvAtJOZKSyt92fy3OLf2enFbYljb/Cha0fmd/egql0pyWnmlzGtMhRqR0FXVxuYOM60wI++Ywju5TkhVBnQ/fPMssu08RCxbJX/fER5zYyGq2mhdFzKtHO+L4lgg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726737520; c=relaxed/simple; bh=Zxm1uLqr1zUwk6C1A4ApcASI47Ep0+VpPk2kApygxO0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AbiQ8YwnIVQuuXkIasZ8rD4/oPCd6xr+mXih/OarE/sgXlckGPM/eayPBAUyy/xymR6dRfn1m8902Vuy2TaG9lpTkUjDgV7kvP35HlzIdsMca8fcLtzjvAfEGl5OSwFiDF94TXJMeC7M91OUcZVxixl+HWCxBzcm2Yd1LVm1rIY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=p8IxNupL; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="p8IxNupL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1726737516; bh=Zxm1uLqr1zUwk6C1A4ApcASI47Ep0+VpPk2kApygxO0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p8IxNupLEi1CO37HBlbjusvnuFIXtFUWOIq1ZrBo8FjbwNC7puM9FfInIJkgLKdc6 zFt/0ho4FEjSfoa4Ja6R6syk1kgexB3Z/KzPh8jNChqKcLrNw2wBxOAP1Pw1c1y4I2 7YRI4G66Q1bfNahuxFF91JdiKGBJ7lQ4wA3NpAgebeszWU1pX6MF6ocUB+fAnLYVAj V1Vsd7EL9OiOaP2s83dtJBfN3rt1itloAj1FBKBkhAjAyAAdij1Vq52KCAH0DshQ77 jqRyRSQwfmbAge5AfR80K9MA07t5cLDEDLd1xgJFa+bkInNg4runv4f2PBjci2Oqhf AqKUuVqYYUaow== Received: from jupiter.universe (dyndsl-091-248-208-160.ewe-ip-backbone.de [91.248.208.160]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id 808BF17E1082; Thu, 19 Sep 2024 11:18:36 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 5C1B5480085; Thu, 19 Sep 2024 11:18:36 +0200 (CEST) From: Sebastian Reichel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Ulf Hansson Cc: Elaine Zhang , =?utf-8?q?Adri=C3=A1n_Mart?= =?utf-8?q?=C3=ADnez_Larumbe?= , Boris Brezillon , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v2 3/6] pmdomain: rockchip: reduce indentation in rockchip_pd_power Date: Thu, 19 Sep 2024 11:12:44 +0200 Message-ID: <20240919091834.83572-4-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240919091834.83572-1-sebastian.reichel@collabora.com> References: <20240919091834.83572-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Rework the logic, so that the function exits early when the power domain state is already correct to reduce code indentation. No functional change intended. Reviewed-by: Heiko Stuebner Tested-by: Adrian Larumbe # On Rock 5B Signed-off-by: Sebastian Reichel --- drivers/pmdomain/rockchip/pm-domains.c | 45 +++++++++++++------------- 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c index 5e5291dedd28..663d390faaeb 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -537,36 +537,37 @@ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on) guard(mutex)(&pmu->mutex); - if (rockchip_pmu_domain_is_on(pd) != power_on) { - ret = clk_bulk_enable(pd->num_clks, pd->clks); - if (ret < 0) { - dev_err(pmu->dev, "failed to enable clocks\n"); - return ret; - } + if (rockchip_pmu_domain_is_on(pd) == power_on) + return 0; - if (!power_on) { - rockchip_pmu_save_qos(pd); + ret = clk_bulk_enable(pd->num_clks, pd->clks); + if (ret < 0) { + dev_err(pmu->dev, "failed to enable clocks\n"); + return ret; + } - /* if powering down, idle request to NIU first */ - rockchip_pmu_set_idle_request(pd, true); - } + if (!power_on) { + rockchip_pmu_save_qos(pd); - ret = rockchip_do_pmu_set_power_domain(pd, power_on); - if (ret < 0) { - clk_bulk_disable(pd->num_clks, pd->clks); - return ret; - } + /* if powering down, idle request to NIU first */ + rockchip_pmu_set_idle_request(pd, true); + } - if (power_on) { - /* if powering up, leave idle mode */ - rockchip_pmu_set_idle_request(pd, false); + ret = rockchip_do_pmu_set_power_domain(pd, power_on); + if (ret < 0) { + clk_bulk_disable(pd->num_clks, pd->clks); + return ret; + } - rockchip_pmu_restore_qos(pd); - } + if (power_on) { + /* if powering up, leave idle mode */ + rockchip_pmu_set_idle_request(pd, false); - clk_bulk_disable(pd->num_clks, pd->clks); + rockchip_pmu_restore_qos(pd); } + clk_bulk_disable(pd->num_clks, pd->clks); + return 0; } From patchwork Thu Sep 19 09:12:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 829771 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8167819A2A3; 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Thu, 19 Sep 2024 11:18:36 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 6153048008A; Thu, 19 Sep 2024 11:18:36 +0200 (CEST) From: Sebastian Reichel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Ulf Hansson Cc: Elaine Zhang , =?utf-8?q?Adri=C3=A1n_Mart?= =?utf-8?q?=C3=ADnez_Larumbe?= , Boris Brezillon , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v2 6/6] arm64: dts: rockchip: Add GPU power domain regulator dependency for RK3588 Date: Thu, 19 Sep 2024 11:12:47 +0200 Message-ID: <20240919091834.83572-7-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240919091834.83572-1-sebastian.reichel@collabora.com> References: <20240919091834.83572-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enabling the GPU power domain requires that the GPU regulator is enabled. The regulator is enabled at boot time, but automatically gets disabled when there are no users. If the GPU driver is not probed at boot time or rebound while the system is running the system will try to enable the power domain before the regulator is enabled resulting in a failure hanging the whole system. Avoid this by adding an explicit dependency. Reported-by: Adrián Martínez Larumbe Tested-by: Adrian Larumbe # On Rock 5B Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 4 ++++ 12 files changed, 45 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts index c667704ba985..00a1cd96781d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -286,6 +286,10 @@ &pcie3x4 { status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 905f37876c23..d82ac5a481b4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -861,7 +861,7 @@ power-domain@RK3588_PD_NPU2 { }; }; /* These power domains are grouped by VD_GPU */ - power-domain@RK3588_PD_GPU { + pd_gpu: power-domain@RK3588_PD_GPU { reg = ; clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi index fde8b228f2c7..cf9d75159ba6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi @@ -277,6 +277,10 @@ &pcie2x1l2 { status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi index e3a9598b99fc..1af0a30866f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi @@ -256,6 +256,10 @@ &pcie2x1l2 { status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { gpio-leds { led_sys_pin: led-sys-pin { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index 31d2f8994f85..3cefaf830229 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -403,6 +403,10 @@ &pcie3x4 { status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts index c2a08bdf09e8..a9c1fed929fd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts @@ -312,6 +312,10 @@ &pcie3x4 { status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { pcie2 { pcie2_0_rst: pcie2-0-rst { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts index d0b922b8d67e..0eadf4fb4ba4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -530,6 +530,10 @@ &pcie3x4 { status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { rtc_int: rtc-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 8f7a59918db7..717504383d46 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -465,6 +465,10 @@ &pcie3x4 { status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hdmirx { hdmirx_hpd: hdmirx-5v-detection { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index 615094bb8ba3..1b5c4a7fd5c6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -317,6 +317,10 @@ &pcie3x4 { reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts index 074c316a9a69..d938db0e2239 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts @@ -329,6 +329,10 @@ &pcie2x1l2 { status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index dbddfc3bb464..d29d404417ee 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -233,6 +233,10 @@ hym8563: rtc@51 { }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { vdd_sd { vdd_sd_en: vdd-sd-en { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts index feea6b20a6bf..ef3a721d1fc7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts @@ -297,6 +297,10 @@ &pcie2x1l2 { status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { gpio-func { leds_gpio: leds-gpio {