From patchwork Fri Oct 11 14:09:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikram Sharma X-Patchwork-Id: 834819 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3871A219CB7; Fri, 11 Oct 2024 14:10:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728655821; cv=none; b=pPTyRokSj7RTCBq2uqTacYRpSVbC61xSGnjP0yC8+VcjsQ5nAcUYbqJ30BWdcelt8BW2LT8WOydC+wSnPaZROPFyVi5Y1GB6Sp6pbe3yU5OGr7yT/J7GlVNciNIE3J/dxXDkmXXjBOwC+TBIkpx+sDliaFRzalZUi+UVe+zSHn4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728655821; c=relaxed/simple; bh=V4+aj5BFZILaxLqhLV2OEKBT7M+/SK0eHM6RQD60qbg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XYecsvotPoyR+DPYDRXbz1zQi/hL1XVyxqHo2aHdLUXFNwW7YcRYtyjdo9TkVV/C4Y738D74nMmVt9lcHwKxX1SizE9VBe449/ldxml4I9yLU7D6d+2YA0CtJdLSA7pG4SgcsdeAyTH2x4UirbYERsnCakrkEM2oIWPySKuGFUw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=NXNP08sf; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="NXNP08sf" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49BAnUAf005437; Fri, 11 Oct 2024 14:10:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= oCok2KEHfbpxPZ4SGuFSV2vqPH3+dUQoaWJsB9kcZjM=; b=NXNP08sfAnPi8Dr4 lkvwQMaAmeQRngCGjg4QRkj6pmYnwzUdxvrqf8fFKLYliDIKVfwjTO+9qDnOGYZR bBLvuwTZPhcCtleLvoq7NBDIuVFuueyQOsgHI4EORdQXtGkCkBgrENuWSVBHX/cE 2ZbLuXq9EsQolIFmEsByA+/jL3uP1Nn5nl98WproGaRdlLrHH5NqhNUViZuT1hlP nVMAwK20Fc5w7keIe6aMHntlOjCwTkpESbF0V8TrKUTdz1ga2VUjzVgDiVtjhXT+ k+XauzFuWHOcKNZRtS+DqPCjniHAmwZxBeHBQ3/fF6okDueWQf26X4SvDqa94T86 iQKn+w== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 426t7ssyhr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Oct 2024 14:10:09 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49BEA9ff010452 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Oct 2024 14:10:09 GMT Received: from hu-vikramsa-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 11 Oct 2024 07:10:00 -0700 From: Vikram Sharma To: , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v3 2/8] media: dt-bindings: Add qcs6490-rb3gen2-vision-mezzanine Date: Fri, 11 Oct 2024 19:39:26 +0530 Message-ID: <20241011140932.1744124-3-quic_vikramsa@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241011140932.1744124-1-quic_vikramsa@quicinc.com> References: <20241011140932.1744124-1-quic_vikramsa@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: VDfP-o051O8Sier4kt4LaUrWPnbApQ6c X-Proofpoint-ORIG-GUID: VDfP-o051O8Sier4kt4LaUrWPnbApQ6c X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 phishscore=0 mlxscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 clxscore=1015 adultscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410110097 The qcs6490-rb3gen2-vision-mezzanine is a mezz on top of the qcs6490-rb3gen2 core kit. The vision mezzanine includes the IMX577 camera sensor. Signed-off-by: Vikram Sharma --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 5de6290cd063..f00851f30d3e 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -390,6 +390,7 @@ properties: - fairphone,fp5 - qcom,qcm6490-idp - qcom,qcs6490-rb3gen2 + - qcom,qcs6490-rb3gen2-vision-mezzanine - shift,otter - const: qcom,qcm6490 From patchwork Fri Oct 11 14:09:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikram Sharma X-Patchwork-Id: 834818 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD04C2194BE; Fri, 11 Oct 2024 14:10:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728655840; cv=none; b=kf6QLUr3RKLPA1krnwLuhqvXeLZvukJyoxkqMfWF/+8Enfi7AxRq1TS7HgzdagSGgCp4A5NjJ5RwQ4VCrmSoldb6ZyeFSqdfSml7A+uOk7unNuBQoULhRe1fwi85KqicnUjA5gGpYhnsVleKZmNeX3oVAxL6rfbMrcQUrlESZUg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728655840; c=relaxed/simple; bh=dlHSkf99QZo0zqpBla5ZxIUadtSXzTu72noMrQ/LqQY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=g1Ni36n+GQYhlny8A4WlN0LRlbo3POMkQcgrzjdWguvWOMNArloYwgmMVnlLBrCE8UwCg8R7aaOfnChm96PUQsnOd3jP3HMje+lR4SktD5DehERit2KFysS0L+7Wx9GzsnW4TjM/9TFSQD6twoYCVJFw1sgqBz6OdI5PK51X5+k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=EuWc+2OD; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="EuWc+2OD" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49BCbsd9004925; Fri, 11 Oct 2024 14:10:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= FzloPuAEpyRbzzUhiQi4u4rCIYfeQfUlSCqWhN0P4rQ=; b=EuWc+2ODKO3qVmYS qIy5O7XJePl+Jd40GeoGM6TziN3DOUenY4PMyvZLm6dPKjSRSFKRTzzLD5fvwmTK TbjDbfAJoQeaaj3Z0FLNvi9mjNSrckkqwr2Kc00f5NWBuW/nsAE01M9KCbagX6Sw HaiCx7YxbzLLmwdu7PdsvsH1AaMslwNQy8YWfoePvswsq7RaVM3I1BBdOnTjTSAo 7MyqvXetqfkhqJHv86T2y85zrJ3tayXI4R+7Jz9ruYPJEMp4V3RWMh235aUIUjbv hdPgYXQPcIAaFLEs6LlxA2WDK6rTmK6SwVdm2AMNwV0rimnA1941EAi19Pej5IPF 2G5kgg== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 426g6nbehe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Oct 2024 14:10:22 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49BEALad008655 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Oct 2024 14:10:21 GMT Received: from hu-vikramsa-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 11 Oct 2024 07:10:13 -0700 From: Vikram Sharma To: , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v3 4/8] media: qcom: camss: Sort CAMSS version enums and compatible strings Date: Fri, 11 Oct 2024 19:39:28 +0530 Message-ID: <20241011140932.1744124-5-quic_vikramsa@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241011140932.1744124-1-quic_vikramsa@quicinc.com> References: <20241011140932.1744124-1-quic_vikramsa@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: bSaerBeIsU5kYioWOtLKCCguZYRUbmkT X-Proofpoint-ORIG-GUID: bSaerBeIsU5kYioWOtLKCCguZYRUbmkT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 impostorscore=0 phishscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410110098 Sort CAMSS version enums and compatible strings alphanumerically. Signed-off-by: Suresh Vankadara Signed-off-by: Trishansh Bhardwaj Signed-off-by: Vikram Sharma --- .../media/platform/qcom/camss/camss-csiphy-3ph-1-0.c | 10 +++++----- drivers/media/platform/qcom/camss/camss-vfe.c | 6 +++--- drivers/media/platform/qcom/camss/camss.c | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index df7e93a5a4f6..7d2490c9de01 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -505,10 +505,6 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, u32 val; switch (csiphy->camss->res->version) { - case CAMSS_845: - r = &lane_regs_sdm845[0][0]; - array_size = ARRAY_SIZE(lane_regs_sdm845[0]); - break; case CAMSS_8250: r = &lane_regs_sm8250[0][0]; array_size = ARRAY_SIZE(lane_regs_sm8250[0]); @@ -517,6 +513,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, r = &lane_regs_sc8280xp[0][0]; array_size = ARRAY_SIZE(lane_regs_sc8280xp[0]); break; + case CAMSS_845: + r = &lane_regs_sdm845[0][0]; + array_size = ARRAY_SIZE(lane_regs_sdm845[0]); + break; default: WARN(1, "unknown cspi version\n"); return; @@ -557,9 +557,9 @@ static bool csiphy_is_gen2(u32 version) bool ret = false; switch (version) { - case CAMSS_845: case CAMSS_8250: case CAMSS_8280XP: + case CAMSS_845: ret = true; break; } diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index 83c5a36d071f..ffcb1e2ec417 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -333,11 +333,11 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, return sink_code; } break; - case CAMSS_8x96: case CAMSS_660: - case CAMSS_845: + case CAMSS_8x96: case CAMSS_8250: case CAMSS_8280XP: + case CAMSS_845: switch (sink_code) { case MEDIA_BUS_FMT_YUYV8_1X16: { @@ -1692,9 +1692,9 @@ static int vfe_bpl_align(struct vfe_device *vfe) int ret = 8; switch (vfe->camss->res->version) { - case CAMSS_845: case CAMSS_8250: case CAMSS_8280XP: + case CAMSS_845: ret = 16; break; default: diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index b6658df37709..dfa0213ecfbf 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -2446,10 +2446,10 @@ static const struct camss_resources sc8280xp_resources = { static const struct of_device_id camss_dt_match[] = { { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources }, + { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources }, { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources }, { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources }, { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources }, - { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources }, { } }; From patchwork Fri Oct 11 14:09:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikram Sharma X-Patchwork-Id: 834817 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3019021BB08; Fri, 11 Oct 2024 14:10:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728655847; cv=none; b=QRP5AkNm1SuokOmqvaqmpJiDJxEFNVfXBYbkqaxYEsHO5hLT3uNzPwYhB5VXrPu60WMwsZis+5NgU3656scl0JvjmxtvSJaa8I1jnt8yyr8/KjRPtigqxTGYG7gPEvp2Z/nUyYeAQS7E6cM1Yz6MwCJhbRkigYtUePEfKO2RWNU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728655847; c=relaxed/simple; bh=baS8TN5DhkPG3ZlO1P+wvAvGcCWnOgVuhQXQoOI//NE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Z3CmFC9EYuseDLRNQzUFA1RdXmqnWG2hcFkuO+npgbsCrF+trvq4hCqAUudwehYMe+rOGz29HtmHFPiCzSi+2OUL3dVfkpGQWKDtqI7NqG9mGoj0AriQPfdFRzxzg2I/FXZcy6gwVjqb7/+/XFGz++ON46AyzFT1g9N1s6HiANA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=P0KOSkrV; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="P0KOSkrV" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49B6oThA023942; Fri, 11 Oct 2024 14:10:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= BKFTDHW7naAxdCx8QOlxs+kHojjjDypCigunDcjVTbU=; b=P0KOSkrVzQIGT4HJ C2UZspputA6SPSx63CLfMxoRuqCw1lN9JiGzXVBWeCFQmVfMBwHpMpfJj7biAQKo 3TJ6zWHlMNeLxNs136i/uk+MLEdsL4NXweIlQyMgGTmcFqBPPUNq7jbwwFxJxXAY XyMpQzOSWasdl6iyGaRO5sy2/aYfKTDT+K2b/mnghYsUkebakp4PTSvIWUM9wPsl BgO9VDME0wQ+C55kFdqO/STjZu9EMCi5loybuclAfxzdmuN0WMwSTWpnjht28YZ2 EfCvwWfzwIEhYH7oEXTErS11tGg/XU5Fh0cycZdE2GiFcqtw/EAbk/HxhDrkXi/A uPpKFw== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 426y3vsa67-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Oct 2024 14:10:35 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49BEAYqo012610 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Oct 2024 14:10:34 GMT Received: from hu-vikramsa-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 11 Oct 2024 07:10:25 -0700 From: Vikram Sharma To: , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v3 6/8] media: qcom: camss: Restructure camss_link_entities Date: Fri, 11 Oct 2024 19:39:30 +0530 Message-ID: <20241011140932.1744124-7-quic_vikramsa@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241011140932.1744124-1-quic_vikramsa@quicinc.com> References: <20241011140932.1744124-1-quic_vikramsa@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: jMRHR0gesReZSDbvWzBeMMwATIXVDJWr X-Proofpoint-GUID: jMRHR0gesReZSDbvWzBeMMwATIXVDJWr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 clxscore=1015 mlxscore=0 phishscore=0 impostorscore=0 adultscore=0 mlxlogscore=958 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410110098 Refactor the camss_link_entities function by breaking it down into three distinct functions. Each function will handle the linking of a specific entity separately, enhancing readability. Signed-off-by: Suresh Vankadara Signed-off-by: Trishansh Bhardwaj Signed-off-by: Vikram Sharma --- drivers/media/platform/qcom/camss/camss.c | 159 ++++++++++++++-------- 1 file changed, 105 insertions(+), 54 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 7ae4a1312e9f..db2710ad0d5c 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -2152,14 +2152,66 @@ static int camss_init_subdevices(struct camss *camss) } /* - * camss_link_entities - Register subdev nodes and create links + * camss_link_entities_csid - Register subdev nodes and create links * @camss: CAMSS device * * Return 0 on success or a negative error code on failure */ -static int camss_link_entities(struct camss *camss) +static int camss_link_entities_csid(struct camss *camss) { - int i, j, k; + int i, j; + int ret, line_num; + u16 src_pad; + u16 sink_pad; + struct media_entity *src_entity; + struct media_entity *sink_entity; + + for (i = 0; i < camss->res->csid_num; i++) { + if (camss->ispif) + line_num = camss->ispif->line_num; + else + line_num = camss->vfe[i].res->line_num; + + src_entity = &camss->csid[i].subdev.entity; + for (j = 0; j < line_num; j++) { + if (camss->ispif) { + sink_entity = &camss->ispif->line[j].subdev.entity; + src_pad = MSM_CSID_PAD_SRC; + sink_pad = MSM_ISPIF_PAD_SINK; + } else { + sink_entity = &camss->vfe[i].line[j].subdev.entity; + src_pad = MSM_CSID_PAD_FIRST_SRC + j; + sink_pad = MSM_VFE_PAD_SINK; + } + + ret = media_create_pad_link(src_entity, + src_pad, + sink_entity, + sink_pad, + 0); + if (ret < 0) { + dev_err(camss->dev, + "Failed to link %s->%s entities: %d\n", + src_entity->name, + sink_entity->name, + ret); + return ret; + } + } + } + + return 0; +} + +/* + * camss_link_entities_csiphy - Register subdev nodes and create links + * @camss: CAMSS device + * + * Return 0 on success or a negative error code on failure + */ +static int camss_link_entities_csiphy(struct camss *camss) +{ + int i, j; int ret; for (i = 0; i < camss->res->csiphy_num; i++) { @@ -2180,71 +2232,70 @@ static int camss_link_entities(struct camss *camss) } } - if (camss->ispif) { - for (i = 0; i < camss->res->csid_num; i++) { - for (j = 0; j < camss->ispif->line_num; j++) { - ret = media_create_pad_link(&camss->csid[i].subdev.entity, - MSM_CSID_PAD_SRC, - &camss->ispif->line[j].subdev.entity, - MSM_ISPIF_PAD_SINK, + return 0; +} + +/* + * camss_link_entities_ispif - Register subdev nodes and create links + * @camss: CAMSS device + * + * Return 0 on success or a negative error code on failure + */ +static int camss_link_entities_ispif(struct camss *camss) +{ + int i, j, k; + int ret; + + for (i = 0; i < camss->ispif->line_num; i++) { + for (k = 0; k < camss->res->vfe_num; k++) { + for (j = 0; j < camss->vfe[k].res->line_num; j++) { + struct v4l2_subdev *ispif = &camss->ispif->line[i].subdev; + struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev; + + ret = media_create_pad_link(&ispif->entity, + MSM_ISPIF_PAD_SRC, + &vfe->entity, + MSM_VFE_PAD_SINK, 0); if (ret < 0) { dev_err(camss->dev, "Failed to link %s->%s entities: %d\n", - camss->csid[i].subdev.entity.name, - camss->ispif->line[j].subdev.entity.name, + ispif->entity.name, + vfe->entity.name, ret); return ret; } } } - - for (i = 0; i < camss->ispif->line_num; i++) - for (k = 0; k < camss->res->vfe_num; k++) - for (j = 0; j < camss->vfe[k].res->line_num; j++) { - struct v4l2_subdev *ispif = &camss->ispif->line[i].subdev; - struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev; - - ret = media_create_pad_link(&ispif->entity, - MSM_ISPIF_PAD_SRC, - &vfe->entity, - MSM_VFE_PAD_SINK, - 0); - if (ret < 0) { - dev_err(camss->dev, - "Failed to link %s->%s entities: %d\n", - ispif->entity.name, - vfe->entity.name, - ret); - return ret; - } - } - } else { - for (i = 0; i < camss->res->csid_num; i++) - for (k = 0; k < camss->res->vfe_num; k++) - for (j = 0; j < camss->vfe[k].res->line_num; j++) { - struct v4l2_subdev *csid = &camss->csid[i].subdev; - struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev; - - ret = media_create_pad_link(&csid->entity, - MSM_CSID_PAD_FIRST_SRC + j, - &vfe->entity, - MSM_VFE_PAD_SINK, - 0); - if (ret < 0) { - dev_err(camss->dev, - "Failed to link %s->%s entities: %d\n", - csid->entity.name, - vfe->entity.name, - ret); - return ret; - } - } } return 0; } +/* + * camss_link_entities - Register subdev nodes and create links + * @camss: CAMSS device + * + * Return 0 on success or a negative error code on failure + */ +static int camss_link_entities(struct camss *camss) +{ + int ret; + + ret = camss_link_entities_csiphy(camss); + if (ret < 0) + return ret; + + ret = camss_link_entities_csid(camss); + if (ret < 0) + return ret; + + if (camss->ispif) + ret = camss_link_entities_ispif(camss); + + return ret; +} + /* * camss_register_entities - Register subdev nodes and create links * @camss: CAMSS device From patchwork Fri Oct 11 14:09:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikram Sharma X-Patchwork-Id: 834816 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED94221A6FE; Fri, 11 Oct 2024 14:11:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728655864; cv=none; b=gHkGaNWZPQD34GTa3h8PqdmVwToxh38LuElRK/CkknsBK3DumBmeZ6e+f6+mAMMJz6Bnce2EziiUaBnOfQSXVRwlcvQ8m9leg5Lu5RQHZzJXSzfHVrLN4mosNOGc9oGCuylOR0nx4rFFKeqc5gvQ8k2W6becgVhxn/HrP7FamaQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728655864; c=relaxed/simple; bh=qhRRa+1gCVFxS2URaNDFg5S6iBEmjXRytWLg5woUsrs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Phfz3Rta+pBqcEQgt2Yc2XUtcRJ62P8m+9kXt6dilOa9m+Vra3+QPyyP4xwxfvZ1gxfYCUlVE7Ec5lrHxpyTk5UB7WIJclGnkWcVaVVv/WaFQW3lu3AbVZ9nqVEGBZUvj4jIHn+AunUz4gVn/+M9/fMoP4DrimTBzTPAkIU/w1E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=T8IKJxF0; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="T8IKJxF0" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49BCCuXu032566; Fri, 11 Oct 2024 14:10:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ztomLQVgs+j0jsrvBYpYTGoNgMdBJzql6rt62p4C3rQ=; b=T8IKJxF0G1kUOn8i KoR/taRehQU2jKuTRSxlvQsjiuygd9X1s1EBOWrpGGVljLgzHK3w1KcATsnLu847 sMVAGIEMAvxCnJ7vkRAjV4djI8YXkkoXLE7/DJYDsGc1nuzphFCTR4R1kaP2zt20 HDxBbBaguGbcuQmxHMgdZwXMIKlc/i82sOL0St+TZUS1hop9VSz5ETml2awEGgdC zwOBJ1qM4xAswzYB5ByCS7jpwNNy1UQ6I/KanptYIDVeKYQKM+jlGJuWRMQskRwv SPZ10ELZ+JzRVQGktrGmp88/N/WueurZZwIkagfjV9b2ELr63nq6LuVQ4r0tSzoI nSc85Q== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 424cy7pp75-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Oct 2024 14:10:49 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49BEAmdP023564 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Oct 2024 14:10:48 GMT Received: from hu-vikramsa-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 11 Oct 2024 07:10:38 -0700 From: Vikram Sharma To: , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v3 8/8] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine Date: Fri, 11 Oct 2024 19:39:32 +0530 Message-ID: <20241011140932.1744124-9-quic_vikramsa@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241011140932.1744124-1-quic_vikramsa@quicinc.com> References: <20241011140932.1744124-1-quic_vikramsa@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: wlYPjgfPZvThRb51eocBvDgmxaUQAl9k X-Proofpoint-GUID: wlYPjgfPZvThRb51eocBvDgmxaUQAl9k X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 adultscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 malwarescore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410110097 The Vision Mezzanine for the RB3 ships with an imx577 camera sensor. Enable the IMX577 on the vision mezzanine. An example media-ctl pipeline for the imx577 is: media-ctl --reset media-ctl -v -V '"imx577 '19-001a'":0[fmt:SRGGB10/4056x3040 field:none]' media-ctl -V '"msm_csiphy3":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]' media-ctl -l '"msm_csiphy3":1->"msm_csid0":0[1]' media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video0 Signed-off-by: Hariram Purushothaman Signed-off-by: Vikram Sharma Signed-off-by: Trishansh Bhardwaj --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../qcom/qcs6490-rb3gen2-vision-mezzanine.dts | 61 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 33 ++++++++++ 3 files changed, 95 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index aea1d69db541..7208da1d3697 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -111,6 +111,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dts new file mode 100644 index 000000000000..04b5fe80d38d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "qcs6490-rb3gen2.dts" + +&camcc { + status = "okay"; +}; + +&camss { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + status = "okay"; + + ports { + /* The port index denotes CSIPHY id i.e. csiphy3 */ + port@3 { + reg = <3>; + csiphy3_ep: endpoint { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx577_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@1a { + compatible = "sony,imx577"; + reg = <0x1a>; + + reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "suspend"; + pinctrl-0 = <&cam2_default>; + pinctrl-1 = <&cam2_suspend>; + + clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clock-rates = <24000000>; + + dovdd-supply = <&vreg_l18b_1p8>; + + port { + imx577_ep: endpoint { + clock-lanes = <7>; + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 9bab2d8dc1b4..74f65129e653 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -5115,6 +5115,39 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 175>; wakeup-parent = <&pdc>; + cam2_default: cam2-default-state { + rst-pins { + pins = "gpio78"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + mclk-pins { + pins = "gpio67"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam2_suspend: cam2-suspend-state { + rst-pins { + pins = "gpio78"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + + mclk-pins { + pins = "gpio67"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + cci0_default: cci0-default-state { pins = "gpio69", "gpio70"; function = "cci_i2c";