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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Paolo Bonzini Subject: [PULL 01/27] tcg: remove singlestep_enabled from DisasContextBase Date: Sun, 13 Oct 2024 15:12:09 -0700 Message-ID: <20241013221235.1585193-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Paolo Bonzini It is used in a couple of places only, both within the same target. Those can use the cflags just as well, so remove the separate field. Signed-off-by: Paolo Bonzini Message-ID: <20241010083641.1785069-1-pbonzini@redhat.com> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/exec/translator.h | 2 -- accel/tcg/translator.c | 1 - target/mips/tcg/translate.c | 5 +++-- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index 25004dfb76..d8dcb77b5f 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -71,7 +71,6 @@ typedef enum DisasJumpType { * @is_jmp: What instruction to disassemble next. * @num_insns: Number of translated instructions (including current). * @max_insns: Maximum number of instructions to be translated in this TB. - * @singlestep_enabled: "Hardware" single stepping enabled. * @plugin_enabled: TCG plugin enabled in this TB. * @fake_insn: True if translator_fake_ldb used. * @insn_start: The last op emitted by the insn_start hook, @@ -86,7 +85,6 @@ struct DisasContextBase { DisasJumpType is_jmp; int num_insns; int max_insns; - bool singlestep_enabled; bool plugin_enabled; bool fake_insn; struct TCGOp *insn_start; diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 113edcffe3..cbad00a517 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -129,7 +129,6 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns, db->is_jmp = DISAS_NEXT; db->num_insns = 0; db->max_insns = *max_insns; - db->singlestep_enabled = cflags & CF_SINGLE_STEP; db->insn_start = NULL; db->fake_insn = false; db->host_addr[0] = host_pc; diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 333469b268..50d8537a3b 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15362,7 +15362,8 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) * hardware does (e.g. if a delay slot instruction faults, the * reported PC is the PC of the branch). */ - if (ctx->base.singlestep_enabled && (ctx->hflags & MIPS_HFLAG_BMASK)) { + if ((tb_cflags(ctx->base.tb) & CF_SINGLE_STEP) && + (ctx->hflags & MIPS_HFLAG_BMASK)) { ctx->base.max_insns = 2; } @@ -15445,7 +15446,7 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) * together with its delay slot. */ if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE - && !ctx->base.singlestep_enabled) { + && !(tb_cflags(ctx->base.tb) & CF_SINGLE_STEP)) { ctx->base.is_jmp = DISAS_TOO_MANY; } } From patchwork Sun Oct 13 22:12:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835096 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1735176wrd; Sun, 13 Oct 2024 15:15:05 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWR3ZksyMF4g3NifgeGJy/5ExUbSX9VC3wFrb0wlhURXxMzWqcUkPjth/aQxYx3gx0yZvZDVg==@linaro.org X-Google-Smtp-Source: AGHT+IFGY8tZ3c5ZkyZegPoBb2YLcvbftIdR+UDPkOOcSLeiZo0mZ/gFHvI3HQ9aeL6UQaDvv+X8 X-Received: by 2002:a05:620a:170e:b0:7b1:184f:caba with SMTP id af79cd13be357-7b121006418mr1202956085a.40.1728857705334; Sun, 13 Oct 2024 15:15:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728857705; cv=none; d=google.com; s=arc-20240605; b=fVTpWmK2rX2EYJ+lfFILbjZfKXVWxNIu5c0HPkFkR3JCjH/RgvtGyE28jFsj/MzJwR XS+U9qkT5M0jgj6mo8t0N1e9IBsi/W2gTP91mn6Dy9mhh/HLo4K3PEL496AvvYQG6DDM 0jHyN6OxHPG378p8+rFttF9+Xf+Mup8C5ExnX1DaZYtYFBBUNvCzcyfIIPkOCBdrwrbZ Lp76g9XqCYBwRx+CfmKS13zcg1+OoQjGzJvm964GPwSPMnv4b7MH/kC7/ZEx5a/xOaWk ZoppBxMWrHWeu7DJ6VnGDobhRhWYT8ZIhK8TS6+CDVsr3evkxD39e7q8eleXjARPASk4 U3lA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nYSXn25U/DdvMWs7SvnxnC83hyNQjHsWrN+gaiP3cZI=; fh=o2XzhdKG+B45MJCghEfnYoypmHvLX2hd4SL6yXeiyXI=; b=B8hseT5sy1bKk11Uvzd/+QxLzzWaqzA6WCOj/s/kvpHQRK1Rz7iaNSifxLGMt6MOzO HbPUi6fNvFvLchcH/bu/28F+sfCSb7V40iU+hWnGdtYHuLqsfR1bgLADNv+dEyUq+Awe KysbY9FYGJvPvockHRueKKkyQ96QZF917RrIBL6GWc4sqr4Ex5jrNmPxsEO6LghSn5o7 YuD3l1z9mC3zEWeF8x1QnuPAbbKSmbErg6UYIcHGiuWAqf8EqFLwL4tXne0Uz2bO46bL yuctDn45D6i/IqQTPGCF8Ty6e8TaLrwyxMGXlcQyIrtEmSajOnqoUfp+EIprTPfxv0u4 lhbw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UV4A9fMg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich Subject: [PULL 02/27] include/exec: Introduce env_cpu_const() Date: Sun, 13 Oct 2024 15:12:10 -0700 Message-ID: <20241013221235.1585193-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich It's the same as env_cpu(), but for const objects. Reviewed-by: Richard Henderson Signed-off-by: Ilya Leoshkevich Message-ID: <20240912093012.402366-2-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- include/exec/cpu-common.h | 13 ++++++++++++- linux-user/elfload.c | 2 +- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 2e1b499cb7..638dc806a5 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -238,6 +238,17 @@ static inline ArchCPU *env_archcpu(CPUArchState *env) return (void *)env - sizeof(CPUState); } +/** + * env_cpu_const(env) + * @env: The architecture environment + * + * Return the CPUState associated with the environment. + */ +static inline const CPUState *env_cpu_const(const CPUArchState *env) +{ + return (void *)env - sizeof(CPUState); +} + /** * env_cpu(env) * @env: The architecture environment @@ -246,7 +257,7 @@ static inline ArchCPU *env_archcpu(CPUArchState *env) */ static inline CPUState *env_cpu(CPUArchState *env) { - return (void *)env - sizeof(CPUState); + return (CPUState *)env_cpu_const(env); } #ifndef CONFIG_USER_ONLY diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 52c88a68a9..352960b771 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -4314,7 +4314,7 @@ static int wmr_write_region(void *opaque, target_ulong start, */ static int elf_core_dump(int signr, const CPUArchState *env) { - const CPUState *cpu = env_cpu((CPUArchState *)env); + const CPUState *cpu = env_cpu_const(env); const TaskState *ts = (const TaskState *)get_task_state((CPUState *)cpu); struct rlimit dumpsize; CountAndSizeRegions css; From patchwork Sun Oct 13 22:12:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835086 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1734809wrd; Sun, 13 Oct 2024 15:13:32 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX6IsCg8EQyHJSWgfgKfgC2Wr+INFdZ/LtRuXB1YD6eDFrh70uIs3AC18Ejlxk2y3Za9s8SMw==@linaro.org X-Google-Smtp-Source: AGHT+IGvhCBPrXbbf80CBNqC+wzbw3ITk/icxVPCNlh0U7chJtez08gr6VmKkrGvr/KPY1cKMS6x X-Received: by 2002:a05:6214:4290:b0:6cb:f7d0:f627 with SMTP id 6a1803df08f44-6cbf9ea35b9mr126578986d6.46.1728857612513; Sun, 13 Oct 2024 15:13:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728857612; cv=none; d=google.com; s=arc-20240605; b=QhDGccHRMEZdD7YWWByCNyofw0R+jJBpR+49pz0MEWaU4DOB1YL2/zHrb+SNnXjzqG cfF2XDUd1EhvapZvvB6P+uE4oLhDQvoivpNvmn+yFjXsiTnWh7WBeZ/zl7t13FRVQsYF +y6cj1pcDqYX7x8uTOjVldz+JYPXlrLwV0vSZQtpS21CVlDsimEUVMs9a7/wMXd3TBE7 F1jnzo2AQ34VfqMf2SzVejOc5mERHuuVW5tid2O9W/qYxMPJGKnMcrWs2Mib1KZmffPx algmjgtFoT3Bqczd65cinZef73J3s82IKuyeArVStrILC+bW7IYxK3w0k60vFR1lu4Qt UDSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=P8UtO3iFeY9lIilr4u+dWsz4U2zyzDHMfO1R07G1hdY=; fh=o2XzhdKG+B45MJCghEfnYoypmHvLX2hd4SL6yXeiyXI=; b=A4+/7MY4rNCXfT+ZFN+AqbiZpb0XJjzU0EbXOhpyQMoJG109w4DH3ckxTDtR7hK4+N wwnTA/HajAqArS7FhNgR1gDE5V0+BqqMIuZWe1f+dPN5AniJPUQbwhE4IgkIwsroKLg2 fHI0J8olGjpu2Ivx8tVeav4h2R5H7lg9H0d6cckKhga8KuqALQc9tJAilxiC0Qcuh0Jm dbBeY5PhmbthDm8rUsdppUdTc3LyXClBaUJCGh4ZZH8zWJZ3uIMzVh+WZvMqtb4jlOwO DoXi1ABHUjqNdKc+q98KeeC0QNYwbO1cQotUOIAiz/cPXKIvYw8NiqZTFoorjfzx4nKr Pamw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jRs7SHdq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich Subject: [PULL 03/27] linux-user/i386: Emulate orig_ax Date: Sun, 13 Oct 2024 15:12:11 -0700 Message-ID: <20241013221235.1585193-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich The kernel uses orig_rax/orig_eax to store the syscall number before a syscall. One can see this value in core dumps and ptrace. Reviewed-by: Richard Henderson Signed-off-by: Ilya Leoshkevich Message-ID: <20240912093012.402366-3-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- linux-user/qemu.h | 4 ++++ linux-user/elfload.c | 4 ++-- linux-user/i386/cpu_loop.c | 3 +++ 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 98ad848ab2..895bdd722a 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -113,6 +113,10 @@ struct TaskState { struct target_vm86plus_struct vm86plus; uint32_t v86flags; uint32_t v86mask; +#endif +#if defined(TARGET_I386) + /* Last syscall number. */ + target_ulong orig_ax; #endif abi_ulong child_tidptr; #ifdef TARGET_M68K diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 352960b771..6cef8db3b5 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -203,7 +203,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUX86State *en (*regs)[12] = tswapreg(env->regs[R_EDX]); (*regs)[13] = tswapreg(env->regs[R_ESI]); (*regs)[14] = tswapreg(env->regs[R_EDI]); - (*regs)[15] = tswapreg(env->regs[R_EAX]); /* XXX */ + (*regs)[15] = tswapreg(get_task_state(env_cpu_const(env))->orig_ax); (*regs)[16] = tswapreg(env->eip); (*regs)[17] = tswapreg(env->segs[R_CS].selector & 0xffff); (*regs)[18] = tswapreg(env->eflags); @@ -306,7 +306,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUX86State *en (*regs)[8] = tswapreg(env->segs[R_ES].selector & 0xffff); (*regs)[9] = tswapreg(env->segs[R_FS].selector & 0xffff); (*regs)[10] = tswapreg(env->segs[R_GS].selector & 0xffff); - (*regs)[11] = tswapreg(env->regs[R_EAX]); /* XXX */ + (*regs)[11] = tswapreg(get_task_state(env_cpu_const(env))->orig_ax); (*regs)[12] = tswapreg(env->eip); (*regs)[13] = tswapreg(env->segs[R_CS].selector & 0xffff); (*regs)[14] = tswapreg(env->eflags); diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index 92beb6830c..7a35215278 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -172,6 +172,7 @@ static void emulate_vsyscall(CPUX86State *env) /* * Perform the syscall. None of the vsyscalls should need restarting. */ + get_task_state(env_cpu(env))->orig_ax = syscall; ret = do_syscall(env, syscall, env->regs[R_EDI], env->regs[R_ESI], env->regs[R_EDX], env->regs[10], env->regs[8], env->regs[9], 0, 0); @@ -221,6 +222,7 @@ void cpu_loop(CPUX86State *env) case EXCP_SYSCALL: #endif /* linux syscall from int $0x80 */ + get_task_state(cs)->orig_ax = env->regs[R_EAX]; ret = do_syscall(env, env->regs[R_EAX], env->regs[R_EBX], @@ -239,6 +241,7 @@ void cpu_loop(CPUX86State *env) #ifdef TARGET_X86_64 case EXCP_SYSCALL: /* linux syscall from syscall instruction. */ + get_task_state(cs)->orig_ax = env->regs[R_EAX]; ret = do_syscall(env, env->regs[R_EAX], env->regs[R_EDI], From patchwork Sun Oct 13 22:12:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835101 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1735483wrd; Sun, 13 Oct 2024 15:16:17 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW9tvf8UQL/DuDQRh+WJxRTP1FK7jZGmL5mXD4PbDvNW57cr86ZTX3lU1UXdExanZmLbao1dw==@linaro.org X-Google-Smtp-Source: AGHT+IH9Trf934cbkKM7FTcSE1yOzkCefWluxD4Y1F2pGpEgBaTEWGe44M9t6yFnZiJv6WQ5gFRF X-Received: by 2002:ac8:7d0a:0:b0:45d:79af:430c with SMTP id d75a77b69052e-4604bbcf76fmr128820691cf.28.1728857777273; Sun, 13 Oct 2024 15:16:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728857777; cv=none; d=google.com; s=arc-20240605; b=gl47DvS22IeOLscBTR2DVhr9sRZ7efj6ppMQdyh6QbwlTagrgHmYL1m3W/WjHKC4/+ GQz/jxaesN7lMCzzE6xtMIYSHY42779CU1LbxJSEGjjXiCH/7RfmV6wUgI/lVHvrIXYL KQMuQeQyls4fTllz95Ug0Tv7a8U3AP/B7yNYF8zXbxd01SnIqn/TX7spBiuQTX84xGVu al8Na7sreW1j8+BVgEcsoWQCpdPlsMgl391HyluS1bJFVTvq61JfrWk8+3Iq63vofOUv HlUX9qxAYH/k8UgF1y0HldQcQlcQqRw29mnxHvwdCOJbQCpXetaD9PbJS53u4zMDVll7 7xyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HvIjzJygM9GXaQbwvZ4DDVniWBW4y8rSWWHM++5r4d8=; fh=o2XzhdKG+B45MJCghEfnYoypmHvLX2hd4SL6yXeiyXI=; b=PopB7t7a2eLQSyZc8A2kFkne1Hp+CQ0UoAnh41QOl4zqz1eLjAFw15IxvYwAucVZVS Xno/9e1RzmwF6/C9WDfcXmXI4uGiQe7mTCA7yxImJEaHaZjSFWSR+jldZxPfN+jm9kJ6 eh/yDWOGa0IHM8XLLbaRcMDx9QQlr9v9H6KIGKn+IHo1ouZz5ms3aFy89OWxPpDVmsYr c7gP1KeiyeGPlT8MZ1scdGPtBULNdYnHzZRZZaBWTJZkawiTDXyPijCsTbxh7qiMoIta aXIsxFCr+8RdpshKTKf+FAcSBdQYadqENox0lCVbXnVaXbMqZ0F9wBIaCAGM6BgCXx+i 8eQA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MCSbN0vG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich Subject: [PULL 04/27] target/i386/gdbstub: Factor out gdb_get_reg() and gdb_write_reg() Date: Sun, 13 Oct 2024 15:12:12 -0700 Message-ID: <20241013221235.1585193-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich i386 gdbstub handles both i386 and x86_64. Factor out two functions for reading and writing registers without knowing their bitness. While at it, simplify the TARGET_LONG_BITS == 32 case. Reviewed-by: Richard Henderson Signed-off-by: Ilya Leoshkevich Message-ID: <20240912093012.402366-4-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- target/i386/gdbstub.c | 51 +++++++++++++++++++++++++------------------ 1 file changed, 30 insertions(+), 21 deletions(-) diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index 4acf485879..cc5eceeb7e 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -96,6 +96,19 @@ static int gdb_write_reg_cs64(uint32_t hflags, uint8_t *buf, target_ulong *val) return 4; } +static int gdb_get_reg(CPUX86State *env, GByteArray *mem_buf, target_ulong val) +{ + if (TARGET_LONG_BITS == 64) { + if (env->hflags & HF_CS64_MASK) { + return gdb_get_reg64(mem_buf, val); + } else { + return gdb_get_reg64(mem_buf, val & 0xffffffffUL); + } + } else { + return gdb_get_reg32(mem_buf, val); + } +} + int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { X86CPU *cpu = X86_CPU(cs); @@ -137,15 +150,7 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) } else { switch (n) { case IDX_IP_REG: - if (TARGET_LONG_BITS == 64) { - if (env->hflags & HF_CS64_MASK) { - return gdb_get_reg64(mem_buf, env->eip); - } else { - return gdb_get_reg64(mem_buf, env->eip & 0xffffffffUL); - } - } else { - return gdb_get_reg32(mem_buf, env->eip); - } + return gdb_get_reg(env, mem_buf, env->eip); case IDX_FLAGS_REG: return gdb_get_reg32(mem_buf, env->eflags); @@ -248,6 +253,21 @@ static int x86_cpu_gdb_load_seg(X86CPU *cpu, X86Seg sreg, uint8_t *mem_buf) return 4; } +static int gdb_write_reg(CPUX86State *env, uint8_t *mem_buf, target_ulong *val) +{ + if (TARGET_LONG_BITS == 64) { + if (env->hflags & HF_CS64_MASK) { + *val = ldq_p(mem_buf); + } else { + *val = ldq_p(mem_buf) & 0xffffffffUL; + } + return 8; + } else { + *val = (uint32_t)ldl_p(mem_buf); + return 4; + } +} + int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { X86CPU *cpu = X86_CPU(cs); @@ -288,18 +308,7 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } else { switch (n) { case IDX_IP_REG: - if (TARGET_LONG_BITS == 64) { - if (env->hflags & HF_CS64_MASK) { - env->eip = ldq_p(mem_buf); - } else { - env->eip = ldq_p(mem_buf) & 0xffffffffUL; - } - return 8; - } else { - env->eip &= ~0xffffffffUL; - env->eip |= (uint32_t)ldl_p(mem_buf); - return 4; - } + return gdb_write_reg(env, mem_buf, &env->eip); case IDX_FLAGS_REG: env->eflags = ldl_p(mem_buf); return 4; From patchwork Sun Oct 13 22:12:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835108 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1736414wrd; Sun, 13 Oct 2024 15:20:10 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUN8vRbVQX68J4tom5jC7ur4TcfOvAeJFwnZQYp1nhB7jKD2+yUrWQueSbAidz43yivsFPjLw==@linaro.org X-Google-Smtp-Source: AGHT+IGuza198Amw2zkkmqrxIb3d4grsjSwuTNsP0xQIvOA6J7F0OtjNCbAYLOuNSrnxK0gUlm6m X-Received: by 2002:a05:622a:64f:b0:45b:5cdf:54f3 with SMTP id d75a77b69052e-4604bb93cabmr171080961cf.10.1728858010715; Sun, 13 Oct 2024 15:20:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728858010; cv=none; d=google.com; s=arc-20240605; b=esd3MYF+pSvCL7bBeTiH+w1i5FyS/oKPuv9ifCyMNPin5Nyy0DdhYq5wK6ZABMRr4y buV7sqp/vCSuko29UdAgXLUP7mETSeoWbHNluahvTSO1aRJ2HRtShoU1pQRFvVnv+WMf 42qybRDAj819/vF4e9EmTB5D7OaV/Vz3pNhTSgd68XbhprI0ph7DqKHsehxEvC+SRo96 MaDsgtGr2L1tPU/l72lfpRuKcFt2ORue3h3En21Qj5Azu9SHJSKV2j4K324UbI1vXln9 LeBAoAYGL3aV8c0u3HDHJpEbHf3nCJZfowfYApK/trDRKf3epTbIH+wayYp326cvclbI 5ftQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=t8ym6NLxoNvu+SOj1YsRaeOvfI7iJrafTEN4muCnoIE=; fh=o2XzhdKG+B45MJCghEfnYoypmHvLX2hd4SL6yXeiyXI=; b=J+F5MGB4aC5yDW2azMqIuFEMVKynSTY1X3VDkOseKssvDjrFKuSPxWcz+yCL8mpxIO SyoCBstb9NK3MSCZXvpfUqMCie9EcekS+/B5rsEFGvFPDdpPOkg8ncYSmWchKC/knAlK ouY6gQkCZ38DGY6uGysrqg/3hmL4fQD9PQpY3QD1Iq3OSH9xK8YghyT5vUezyMLjaPej bxCZhx3VlSSHuYt4yzHkjsiJp5DOWjPpNa15ybqLXAoTo12iNAL1e+s0s0X0BU7ov8GJ 1Yrwva/eMeADlyJuJrTc8XrBp0b59qn9DzBpHKdykcdI8Gl9CmqhnBKK6TlmHYp+iiTn iOLQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PqXzSt9n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich Subject: [PULL 05/27] target/i386/gdbstub: Expose orig_ax Date: Sun, 13 Oct 2024 15:12:13 -0700 Message-ID: <20241013221235.1585193-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich Copy XML files describing orig_ax from GDB and glue them with CPUX86State.orig_ax. Reviewed-by: Richard Henderson Signed-off-by: Ilya Leoshkevich Message-ID: <20240912093012.402366-5-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- target/i386/cpu.h | 1 + target/i386/cpu.c | 1 + target/i386/gdbstub.c | 51 +++++++++++++++++++++++++++ configs/targets/i386-linux-user.mak | 2 +- configs/targets/x86_64-linux-user.mak | 2 +- gdb-xml/i386-32bit-linux.xml | 11 ++++++ gdb-xml/i386-64bit-linux.xml | 11 ++++++ 7 files changed, 77 insertions(+), 2 deletions(-) create mode 100644 gdb-xml/i386-32bit-linux.xml create mode 100644 gdb-xml/i386-64bit-linux.xml diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9c39384ac0..4c63e7b045 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2226,6 +2226,7 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +void x86_cpu_gdb_init(CPUState *cs); void x86_cpu_list(void); int cpu_x86_support_mca_broadcast(CPUX86State *env); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ff227a8c5c..0d30191482 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7831,6 +7831,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) mce_init(cpu); + x86_cpu_gdb_init(cs); qemu_init_vcpu(cs); /* diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index cc5eceeb7e..04c49e802d 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -18,8 +18,13 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" +#include "accel/tcg/vcpu-state.h" #include "cpu.h" +#include "exec/gdbstub.h" #include "gdbstub/helpers.h" +#ifdef CONFIG_LINUX_USER +#include "linux-user/qemu.h" +#endif #ifdef TARGET_X86_64 static const int gpr_map[16] = { @@ -406,3 +411,49 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) /* Unrecognised register. */ return 0; } + +#ifdef CONFIG_LINUX_USER + +#define IDX_ORIG_AX 0 + +static int x86_cpu_gdb_read_linux_register(CPUState *cs, GByteArray *mem_buf, + int n) +{ + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + + switch (n) { + case IDX_ORIG_AX: + return gdb_get_reg(env, mem_buf, get_task_state(cs)->orig_ax); + } + return 0; +} + +static int x86_cpu_gdb_write_linux_register(CPUState *cs, uint8_t *mem_buf, + int n) +{ + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + + switch (n) { + case IDX_ORIG_AX: + return gdb_write_reg(env, mem_buf, &get_task_state(cs)->orig_ax); + } + return 0; +} + +#endif + +void x86_cpu_gdb_init(CPUState *cs) +{ +#ifdef CONFIG_LINUX_USER + gdb_register_coprocessor(cs, x86_cpu_gdb_read_linux_register, + x86_cpu_gdb_write_linux_register, +#ifdef TARGET_X86_64 + gdb_find_static_feature("i386-64bit-linux.xml"), +#else + gdb_find_static_feature("i386-32bit-linux.xml"), +#endif + 0); +#endif +} diff --git a/configs/targets/i386-linux-user.mak b/configs/targets/i386-linux-user.mak index 5b2546a430..b72a156473 100644 --- a/configs/targets/i386-linux-user.mak +++ b/configs/targets/i386-linux-user.mak @@ -1,4 +1,4 @@ TARGET_ARCH=i386 TARGET_SYSTBL_ABI=i386 TARGET_SYSTBL=syscall_32.tbl -TARGET_XML_FILES= gdb-xml/i386-32bit.xml +TARGET_XML_FILES= gdb-xml/i386-32bit.xml gdb-xml/i386-32bit-linux.xml diff --git a/configs/targets/x86_64-linux-user.mak b/configs/targets/x86_64-linux-user.mak index 9ceefbb615..86042814d3 100644 --- a/configs/targets/x86_64-linux-user.mak +++ b/configs/targets/x86_64-linux-user.mak @@ -2,4 +2,4 @@ TARGET_ARCH=x86_64 TARGET_BASE_ARCH=i386 TARGET_SYSTBL_ABI=common,64 TARGET_SYSTBL=syscall_64.tbl -TARGET_XML_FILES= gdb-xml/i386-64bit.xml +TARGET_XML_FILES= gdb-xml/i386-64bit.xml gdb-xml/i386-64bit-linux.xml diff --git a/gdb-xml/i386-32bit-linux.xml b/gdb-xml/i386-32bit-linux.xml new file mode 100644 index 0000000000..5ffe5616e6 --- /dev/null +++ b/gdb-xml/i386-32bit-linux.xml @@ -0,0 +1,11 @@ + + + + + + + diff --git a/gdb-xml/i386-64bit-linux.xml b/gdb-xml/i386-64bit-linux.xml new file mode 100644 index 0000000000..0f26990d2f --- /dev/null +++ b/gdb-xml/i386-64bit-linux.xml @@ -0,0 +1,11 @@ + + + + + + + From patchwork Sun Oct 13 22:12:14 2024 Content-Type: text/plain; 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PULL 06/27] tests/tcg: Run test-proc-mappings.py on i386 Date: Sun, 13 Oct 2024 15:12:14 -0700 Message-ID: <20241013221235.1585193-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich Now that orig_ax is exposed and GDB is happy, don't skip test-proc-mappings.py on i386. In fact, it's broken only on m68k now, so skip only this architecture. Acked-by: Alex Bennée Signed-off-by: Ilya Leoshkevich Message-ID: <20240912093012.402366-6-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- .../tcg/multiarch/gdbstub/test-proc-mappings.py | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/tests/tcg/multiarch/gdbstub/test-proc-mappings.py b/tests/tcg/multiarch/gdbstub/test-proc-mappings.py index 564613fabf..0f687f3284 100644 --- a/tests/tcg/multiarch/gdbstub/test-proc-mappings.py +++ b/tests/tcg/multiarch/gdbstub/test-proc-mappings.py @@ -8,17 +8,12 @@ def run_test(): """Run through the tests one by one""" - try: - mappings = gdb.execute("info proc mappings", False, True) - except gdb.error as exc: - exc_str = str(exc) - if "Not supported on this target." in exc_str: - # Detect failures due to an outstanding issue with how GDB handles - # the x86_64 QEMU's target.xml, which does not contain the - # definition of orig_rax. Skip the test in this case. - print("SKIP: {}".format(exc_str)) - return - raise + if gdb.selected_inferior().architecture().name() == "m68k": + # m68k GDB supports only GDB_OSABI_SVR4, but GDB_OSABI_LINUX is + # required for the info proc support (see set_gdbarch_info_proc()). + print("SKIP: m68k GDB does not support GDB_OSABI_LINUX") + exit(0) + mappings = gdb.execute("info proc mappings", False, True) report(isinstance(mappings, str), "Fetched the mappings from the inferior") # Broken with host page size > guest page size # report("/sha1" in mappings, "Found the test binary name in the mappings") From patchwork Sun Oct 13 22:12:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835102 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1735515wrd; Sun, 13 Oct 2024 15:16:24 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVYM2aLr4a44t4CxoEeJO3FuoVL5cmQqwt5sYqZ8URoRoQYclL/WZkG2BZtEiJh3KMYuSSryw==@linaro.org X-Google-Smtp-Source: AGHT+IH2SrR4g7uGs4aevheI5obhYUrE0f0Ihw1UYxHvZvM1Z12GZlRIShRFmNVxvQn/QTPnhKhf X-Received: by 2002:a05:6214:4b08:b0:6cb:ee32:12ee with SMTP id 6a1803df08f44-6cbf9e954b4mr116887866d6.49.1728857784411; Sun, 13 Oct 2024 15:16:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728857784; cv=none; d=google.com; s=arc-20240605; b=TGEREXHslqEQ71E2o3qZEtGRjymyBqsCweddw1fD5A+Fht/+TBudplXYWiwqRw5IQN FtsU/Sw1r9MINWxcPlimYDgH17JPfFXKAWF93mBueX+T/DZ+6a4CYc+XQ30m8Wbam5MP +7BTkY7kgdF8ubR0ljJSP7S4kQlyFoQEJEHtnXE+g9BcPh9E+4tW3pod5wx0htbz5GWC JAwRxVym8DrALMq+DBAcuFqfch4jhI0XDbUnDc9T1j6Ih2RaJijE0T1GGtjrG1VD4/oE 0eWowahDGW/5vUKaQd4B1h9Rxb6v+DmCKhNNYQV+BxkavasDuRXI+PwGFMbxFdiWvJNC TxxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=VpiQ0uRviqHvIpHCmWWiDcmFLJXAKpr3mqpGqdFoplg=; fh=SzLD/0rjI/l9YS3Gj7fNOJTCpTQugFdyYkIg3L+Q84A=; b=ASkVdbF64J27SHMQt8cJquGHpzfimlKKQQLsBfQSN7TDNQnb8DrtJqmWuTMAEmGYJ6 PN6NPLQBP6tAhpjuJpLA152d3I+EuZVcy2VMTrdkVrpi9NyH7nuWGOg+nuZ3RRjd/I2p meGDYsmJVI3JWOBQbWL0eCwCAqCcaB3FEjFml3xQw/1K9VrXo92ebR3iHZlWz0UQi5k5 Hr7EAndOqGExmX4uap9YwWSpvQMxe4wodtxK3xbudJVnicFouIxmt65QuFDDxFil3Nxy mQC0TCbHD/6VWQlJd6rp1spLRB3hwFUbOtrf68WSR4A7nQWLcIj0qP1VZZyH36SPfRlg eMjw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G86hBLNp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Thomas Huth , "Dr . David Alan Gilbert" Subject: [PULL 07/27] linux-user/vm86: Fix compilation with Clang Date: Sun, 13 Oct 2024 15:12:15 -0700 Message-ID: <20241013221235.1585193-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Thomas Huth Since commit 95b9c27c81 ("linux-user: Remove unused handle_vm86_fault") a bunch of other "static inline" function are now unused, too. Clang warns about such unused "static inline" functions in .c files, so the build currently breaks when compiling with "--enable-werror". Remove the unused functions to get it going again. Fixes: 95b9c27c81 ("linux-user: Remove unused handle_vm86_fault") Signed-off-by: Thomas Huth Reviewed-by: Richard Henderson Reviewed-by: Dr. David Alan Gilbert Message-ID: <20241011161845.417342-1-thuth@redhat.com> Signed-off-by: Richard Henderson --- linux-user/vm86.c | 65 ----------------------------------------------- 1 file changed, 65 deletions(-) diff --git a/linux-user/vm86.c b/linux-user/vm86.c index 31a2d707cf..5091d53fb8 100644 --- a/linux-user/vm86.c +++ b/linux-user/vm86.c @@ -47,30 +47,6 @@ static inline void vm_putw(CPUX86State *env, uint32_t segptr, cpu_stw_data(env, segptr + (reg16 & 0xffff), val); } -static inline void vm_putl(CPUX86State *env, uint32_t segptr, - unsigned int reg16, unsigned int val) -{ - cpu_stl_data(env, segptr + (reg16 & 0xffff), val); -} - -static inline unsigned int vm_getb(CPUX86State *env, - uint32_t segptr, unsigned int reg16) -{ - return cpu_ldub_data(env, segptr + (reg16 & 0xffff)); -} - -static inline unsigned int vm_getw(CPUX86State *env, - uint32_t segptr, unsigned int reg16) -{ - return cpu_lduw_data(env, segptr + (reg16 & 0xffff)); -} - -static inline unsigned int vm_getl(CPUX86State *env, - uint32_t segptr, unsigned int reg16) -{ - return cpu_ldl_data(env, segptr + (reg16 & 0xffff)); -} - void save_v86_state(CPUX86State *env) { CPUState *cs = env_cpu(env); @@ -131,19 +107,6 @@ static inline void return_to_32bit(CPUX86State *env, int retval) env->regs[R_EAX] = retval; } -static inline int set_IF(CPUX86State *env) -{ - CPUState *cs = env_cpu(env); - TaskState *ts = get_task_state(cs); - - ts->v86flags |= VIF_MASK; - if (ts->v86flags & VIP_MASK) { - return_to_32bit(env, TARGET_VM86_STI); - return 1; - } - return 0; -} - static inline void clear_IF(CPUX86State *env) { CPUState *cs = env_cpu(env); @@ -162,34 +125,6 @@ static inline void clear_AC(CPUX86State *env) env->eflags &= ~AC_MASK; } -static inline int set_vflags_long(unsigned long eflags, CPUX86State *env) -{ - CPUState *cs = env_cpu(env); - TaskState *ts = get_task_state(cs); - - set_flags(ts->v86flags, eflags, ts->v86mask); - set_flags(env->eflags, eflags, SAFE_MASK); - if (eflags & IF_MASK) - return set_IF(env); - else - clear_IF(env); - return 0; -} - -static inline int set_vflags_short(unsigned short flags, CPUX86State *env) -{ - CPUState *cs = env_cpu(env); - TaskState *ts = get_task_state(cs); - - set_flags(ts->v86flags, flags, ts->v86mask & 0xffff); - set_flags(env->eflags, flags, SAFE_MASK); - if (flags & IF_MASK) - return set_IF(env); - else - clear_IF(env); - return 0; -} - static inline unsigned int get_vflags(CPUX86State *env) { CPUState *cs = env_cpu(env); From patchwork Sun Oct 13 22:12:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835100 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1735452wrd; Sun, 13 Oct 2024 15:16:12 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUDn7Cgyn0aNBtUye/XVwipQcVaPGoyAy/agqa4M4eRaR6piP/1cQv9Mazg+oEJFPSd9crO4g==@linaro.org X-Google-Smtp-Source: AGHT+IGYJhGV3FrG7vVxIKED06NScUQD3n9F7uUkzItHC4XbSMmLjDidn3IoSICTo1DBuxdfW6Oe X-Received: by 2002:a05:6214:4a92:b0:6cb:c85c:5654 with SMTP id 6a1803df08f44-6cbeff81414mr142571716d6.4.1728857771897; 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , Peter Maydell Subject: [PULL 08/27] accel/tcg: Assert noreturn from write-only page for atomics Date: Sun, 13 Oct 2024 15:12:16 -0700 Message-ID: <20241013221235.1585193-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org There should be no "just in case"; the page is already in the tlb, and known to be not readable. Reviewed-by: Helge Deller Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 117b516739..fd6459b695 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1852,10 +1852,9 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, /* * Since we don't support reads and writes to different * addresses, and we do have the proper page loaded for - * write, this shouldn't ever return. But just in case, - * handle via stop-the-world. + * write, this shouldn't ever return. */ - goto stop_the_world; + g_assert_not_reached(); } /* Collect tlb flags for read. */ tlb_addr |= tlbe->addr_read; From patchwork Sun Oct 13 22:12:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835106 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1735877wrd; Sun, 13 Oct 2024 15:17:44 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVsADOoXzEOmkL+TEEt9p0ohjxGJzbgPypqg0XCplXHTdIOkrhgS+fXOckdZtyIdVCOvXOQ+g==@linaro.org X-Google-Smtp-Source: AGHT+IH6tLqKHINEeLRTWulj3IGLKMwesOb0ciXg/FlDoiyoiH1biXMeq47TqE7/TwfpyFoEpCbj X-Received: by 2002:a05:620a:4406:b0:7a9:aaef:305e with SMTP id af79cd13be357-7b11a37980cmr1811718585a.12.1728857864585; Sun, 13 Oct 2024 15:17:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728857864; cv=none; d=google.com; s=arc-20240605; b=SydLEDVH+FbxAKhXPKuFV5+dH9dsYh17xB2aFIe1mbcG+kgh8tL50QwN8n6RPZU7J6 kf3TmcCe2b2cbxWOFId8wlNK6z9Cg58SBW+aDsS9YlUTvW9jhz8ttsPUfahtrA35vQAY S8rhlfLOGd1reigOe0UQnA2K5Wxj645QhEuR5PFXzkP9WnvG3yZ2zj7IdDeClxAfBabS jdQcYMM7McdjsViB0UaV4Xk4/gi4Lt6qJa/RbpOOw4Z98d7Uk+8GnEtNvw9hiIAGuYop f+EWIgmqvhHj9rXU0TdlCuJBTcS0j0XzjYT9nwtlEfKDHyibfgmfVBsBzbNj9wf/tagB VW2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=O9DVukvxY0Nz2lbOkkF1UGxIJ0HiyrlwFe+DiEN47Z4=; fh=jPrxLhM/2+ATb52kRFb3bxuZkptRVHP7DuqEwlo+BX0=; b=V6YwKgdxMNbOmXMF8j9tZcc9aJ/GtyUhl1hCVS+RtEj7QIrrxUOMnvDCJdqJY01yov m+uk/rguziU4dHedaYN1lEMluDCGPnbuWGrc2CMYHdemOFfU0nOJNR8BFITbtNu9g31z OpwPUQQS20k/Ta0+x8raTEfBSaPTPpehVx3FBww/jn5oDTSAtbiSsx8r0/gFheRD68D1 UxFIaRMNerKFSbJq6Lnao1EKmwwk5OkN8yfj9AXPxpQcp6KUx6KeTU1AOHBdi3IVVBl1 fR7pF0wj0q4e0S3PaJrTxPthIl5FgLcPhOjwNHeg7Qc+UJc3KCOCm/altO23qBiar0IT QZow==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iH5rXdJd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PULL 09/27] include/exec/memop: Move get_alignment_bits from tcg.h Date: Sun, 13 Oct 2024 15:12:17 -0700 Message-ID: <20241013221235.1585193-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This function is specific to MemOp, not TCG in general. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/memop.h | 23 +++++++++++++++++++++++ include/tcg/tcg.h | 23 ----------------------- 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index f881fe7af4..97720a8ee7 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -170,4 +170,27 @@ static inline bool memop_big_endian(MemOp op) return (op & MO_BSWAP) == MO_BE; } +/** + * get_alignment_bits + * @memop: MemOp value + * + * Extract the alignment size from the memop. + */ +static inline unsigned get_alignment_bits(MemOp memop) +{ + unsigned a = memop & MO_AMASK; + + if (a == MO_UNALN) { + /* No alignment required. */ + a = 0; + } else if (a == MO_ALIGN) { + /* A natural alignment requirement. */ + a = memop & MO_SIZE; + } else { + /* A specific alignment requirement. */ + a = a >> MO_ASHIFT; + } + return a; +} + #endif diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 21d5884741..824fb3560d 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -281,29 +281,6 @@ static inline int tcg_type_size(TCGType t) return 4 << i; } -/** - * get_alignment_bits - * @memop: MemOp value - * - * Extract the alignment size from the memop. - */ -static inline unsigned get_alignment_bits(MemOp memop) -{ - unsigned a = memop & MO_AMASK; - - if (a == MO_UNALN) { - /* No alignment required. */ - a = 0; - } else if (a == MO_ALIGN) { - /* A natural alignment requirement. */ - a = memop & MO_SIZE; - } else { - /* A specific alignment requirement. */ - a = a >> MO_ASHIFT; - } - return a; -} - typedef tcg_target_ulong TCGArg; /* Define type and accessor macros for TCG variables. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PULL 10/27] include/exec/memop: Rename get_alignment_bits Date: Sun, 13 Oct 2024 15:12:18 -0700 Message-ID: <20241013221235.1585193-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rename to use "memop_" prefix, like other functions that operate on MemOp. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/memop.h | 4 ++-- accel/tcg/cputlb.c | 4 ++-- accel/tcg/user-exec.c | 4 ++-- target/arm/tcg/translate-a64.c | 4 ++-- target/xtensa/translate.c | 2 +- tcg/tcg-op-ldst.c | 6 +++--- tcg/tcg.c | 2 +- tcg/arm/tcg-target.c.inc | 4 ++-- tcg/sparc64/tcg-target.c.inc | 2 +- 9 files changed, 16 insertions(+), 16 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index 97720a8ee7..f53bf618c6 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -171,12 +171,12 @@ static inline bool memop_big_endian(MemOp op) } /** - * get_alignment_bits + * memop_alignment_bits: * @memop: MemOp value * * Extract the alignment size from the memop. */ -static inline unsigned get_alignment_bits(MemOp memop) +static inline unsigned memop_alignment_bits(MemOp memop) { unsigned a = memop & MO_AMASK; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index fd6459b695..a975fe5f89 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1709,7 +1709,7 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, tcg_debug_assert(l->mmu_idx < NB_MMU_MODES); /* Handle CPU specific unaligned behaviour */ - a_bits = get_alignment_bits(l->memop); + a_bits = memop_alignment_bits(l->memop); if (addr & ((1 << a_bits) - 1)) { cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); } @@ -1797,7 +1797,7 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, { uintptr_t mmu_idx = get_mmuidx(oi); MemOp mop = get_memop(oi); - int a_bits = get_alignment_bits(mop); + int a_bits = memop_alignment_bits(mop); uintptr_t index; CPUTLBEntry *tlbe; vaddr tlb_addr; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 11b6d45e90..51b2c16dbe 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -954,7 +954,7 @@ void page_reset_target_data(target_ulong start, target_ulong last) { } static void *cpu_mmu_lookup(CPUState *cpu, vaddr addr, MemOp mop, uintptr_t ra, MMUAccessType type) { - int a_bits = get_alignment_bits(mop); + int a_bits = memop_alignment_bits(mop); void *ret; /* Enforce guest required alignment. */ @@ -1236,7 +1236,7 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, int size, uintptr_t retaddr) { MemOp mop = get_memop(oi); - int a_bits = get_alignment_bits(mop); + int a_bits = memop_alignment_bits(mop); void *ret; /* Enforce guest required alignment. */ diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 071b6349fc..ec0b1ee252 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -294,7 +294,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr, desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc = FIELD_DP32(desc, MTEDESC, ALIGN, get_alignment_bits(memop)); + desc = FIELD_DP32(desc, MTEDESC, ALIGN, memop_alignment_bits(memop)); desc = FIELD_DP32(desc, MTEDESC, SIZEM1, memop_size(memop) - 1); ret = tcg_temp_new_i64(); @@ -326,7 +326,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc = FIELD_DP32(desc, MTEDESC, ALIGN, get_alignment_bits(single_mop)); + desc = FIELD_DP32(desc, MTEDESC, ALIGN, memop_alignment_bits(single_mop)); desc = FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1); ret = tcg_temp_new_i64(); diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 75b7bfda4c..f4da4a40f9 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -521,7 +521,7 @@ static MemOp gen_load_store_alignment(DisasContext *dc, MemOp mop, mop |= MO_ALIGN; } if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) { - tcg_gen_andi_i32(addr, addr, ~0 << get_alignment_bits(mop)); + tcg_gen_andi_i32(addr, addr, ~0 << memop_alignment_bits(mop)); } return mop; } diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 23dc807f11..a318011229 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -45,7 +45,7 @@ static void check_max_alignment(unsigned a_bits) static MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) { - unsigned a_bits = get_alignment_bits(op); + unsigned a_bits = memop_alignment_bits(op); check_max_alignment(a_bits); @@ -559,7 +559,7 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr, TCGv_i64 ext_addr = NULL; TCGOpcode opc; - check_max_alignment(get_alignment_bits(memop)); + check_max_alignment(memop_alignment_bits(memop)); tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); /* In serial mode, reduce atomicity. */ @@ -676,7 +676,7 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp *addr, TCGv_i64 ext_addr = NULL; TCGOpcode opc; - check_max_alignment(get_alignment_bits(memop)); + check_max_alignment(memop_alignment_bits(memop)); tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); /* In serial mode, reduce atomicity. */ diff --git a/tcg/tcg.c b/tcg/tcg.c index 34e3056380..5decd83cf4 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -5506,7 +5506,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) static TCGAtomAlign atom_and_align_for_opc(TCGContext *s, MemOp opc, MemOp host_atom, bool allow_two_ops) { - MemOp align = get_alignment_bits(opc); + MemOp align = memop_alignment_bits(opc); MemOp size = opc & MO_SIZE; MemOp half = size ? size - 1 : 0; MemOp atom = opc & MO_ATOM_MASK; diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 3de5f50b62..56072d89a2 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1587,7 +1587,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, tcg_debug_assert((datalo & 1) == 0); tcg_debug_assert(datahi == datalo + 1); /* LDRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >= MO_64) { + if (memop_alignment_bits(opc) >= MO_64) { if (h.index < 0) { tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); break; @@ -1691,7 +1691,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, tcg_debug_assert((datalo & 1) == 0); tcg_debug_assert(datahi == datalo + 1); /* STRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >= MO_64) { + if (memop_alignment_bits(opc) >= MO_64) { if (h.index < 0) { tcg_out_strd_8(s, h.cond, datalo, h.base, 0); } else { diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 176c98740b..32f9ec24b5 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1133,7 +1133,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, * Otherwise, test for at least natural alignment and defer * everything else to the helper functions. */ - if (s_bits != get_alignment_bits(opc)) { + if (s_bits != memop_alignment_bits(opc)) { tcg_debug_assert(check_fit_tl(a_mask, 13)); tcg_out_arithi(s, TCG_REG_G0, addr_reg, a_mask, ARITH_ANDCC); From patchwork Sun Oct 13 22:12:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835090 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1734903wrd; Sun, 13 Oct 2024 15:13:58 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVcr1R2vzYN/zPgbYWDDig06Xq82v12CpHcYxVAoEB1vJkMkB+OgufjgkVIFLbeCUNlpbjvjw==@linaro.org X-Google-Smtp-Source: AGHT+IFvKgr9w7t8e7AineaFQa+dvX2jxRYPY++y1yqqfeTJtp72XVJq/6eMEPaqtd3vo+ep4DVo X-Received: by 2002:a05:620a:2989:b0:7b1:1947:ca99 with SMTP id af79cd13be357-7b120fba6b8mr1031008685a.22.1728857638646; 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 11/27] include/exec/memop: Introduce memop_atomicity_bits Date: Sun, 13 Oct 2024 15:12:19 -0700 Message-ID: <20241013221235.1585193-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Split out of mmu_lookup. Reviewed-by: Helge Deller Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/memop.h | 24 ++++++++++++++++++++++++ accel/tcg/cputlb.c | 16 ++-------------- 2 files changed, 26 insertions(+), 14 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index f53bf618c6..b699bf7688 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -193,4 +193,28 @@ static inline unsigned memop_alignment_bits(MemOp memop) return a; } +/* + * memop_atomicity_bits: + * @memop: MemOp value + * + * Extract the atomicity size from the memop. + */ +static inline unsigned memop_atomicity_bits(MemOp memop) +{ + unsigned size = memop & MO_SIZE; + + switch (memop & MO_ATOM_MASK) { + case MO_ATOM_NONE: + size = MO_8; + break; + case MO_ATOM_IFALIGN_PAIR: + case MO_ATOM_WITHIN16_PAIR: + size = size ? size - 1 : 0; + break; + default: + break; + } + return size; +} + #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a975fe5f89..35cda1e2b0 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1767,20 +1767,8 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, * Device memory type require alignment. */ if (unlikely(flags & TLB_CHECK_ALIGNED)) { - MemOp size = l->memop & MO_SIZE; - - switch (l->memop & MO_ATOM_MASK) { - case MO_ATOM_NONE: - size = MO_8; - break; - case MO_ATOM_IFALIGN_PAIR: - case MO_ATOM_WITHIN16_PAIR: - size = size ? size - 1 : 0; - break; - default: - break; - } - if (addr & ((1 << size) - 1)) { + a_bits = memop_atomicity_bits(l->memop); + if (addr & ((1 << a_bits) - 1)) { cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); } } From patchwork Sun Oct 13 22:12:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835109 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1736541wrd; Sun, 13 Oct 2024 15:20:43 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVW0/Wlb4YO7w0iJgP9ti+/Rt0+ft9x5K7jE6xVMZ2ROYfzXX0DOwLrAHb9XI60TQEa/2/eYA==@linaro.org X-Google-Smtp-Source: AGHT+IFlLz+5zLBBz9CKnHHun2+rA5EqBKaxffU1hXiaoRzmJhjdEYOfd4QoVSLqYvQ07e3a26Sh X-Received: by 2002:a05:622a:4e04:b0:460:62c0:6077 with SMTP id d75a77b69052e-46062c0610amr49072331cf.4.1728858043079; Sun, 13 Oct 2024 15:20:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728858043; cv=none; d=google.com; s=arc-20240605; b=kNPbmBpyTEGgDBzzcktsXS5jJmYmVRqAVP+oDXqZriN++ZlfOmyv3zlLSZwkT7zk1l +vIPe8GEPGBDoymsI5gjwkzXCVTZHSgfFSIEE0qTjuXpdpL5+xaT4LA/OIcp3rO5yOeJ +cfTMU/Zf4xhErp3jvxUE73bxMST2ljiQ6hIvZM9yvUqCX2WtjFCbo7bm8SinNZ7uzVR 75uECg6dDvwR80DD/a9EWdyvJpROz1FBsh6mLI4l5yIGT9Nyii3QS6hL64u/7zJaDzvp W83lfCMP2YodWwxdTgvNQQLFdb5OWRtp/2S8RWf/IbnV2hYsKb9pAvS68Bka9/XB909r CFxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RgjF9MWTX9WVkUUJb/RiYkmVHDzeAEtDtYq3Lai+k+w=; fh=GQHtCn/E3suSoDw0oyVI1IVtbfZwNmpadSzuYPhysFY=; b=kWnNkVoL47ihjijRWEm9k3vIPGSZyCEkya7Zfsq2SmgNRwLxpAk0mTT+QLZMrG/Fpp pe7A/jF51B7j/vKsuNcwBYbCyNQIjnqe9Q7J5SOGz1ROm0iCjYQrYuX0z9EqPmWV57Pe zDqLomVS3YwIMKC63fZXMSNFLvE/JPQMmLNHTXaGv/04O4wuL5/E+xQoM8Zvq0gyuRSv nBw+wMUulqu91koeGocsIUh5L4UUrmsUAqKix5z6pyh5tUd1rhM5aDyEZfFlGtJN+oky 4ifQYUId9mMxFjPLyrJPY092hrdj/C7GHy3wGdMuldor+cSii5CzoQ2B75ps75V0x050 pDJA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vnJuaoA2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , Peter Maydell Subject: [PULL 12/27] accel/tcg: Add TCGCPUOps.tlb_fill_align Date: Sun, 13 Oct 2024 15:12:20 -0700 Message-ID: <20241013221235.1585193-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a new callback to handle softmmu paging. Return the page details directly, instead of passing them indirectly to tlb_set_page. Handle alignment simultaneously with paging so that faults are handled with target-specific priority. Route all calls of the two hooks through a tlb_fill_align function local to cputlb.c. As yet no targets implement the new hook. As yet cputlb.c does not use the new alignment check. Reviewed-by: Helge Deller Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 4 +-- include/hw/core/tcg-cpu-ops.h | 26 +++++++++++++++ include/qemu/typedefs.h | 1 + accel/tcg/cputlb.c | 61 ++++++++++++++++++++++------------- 4 files changed, 67 insertions(+), 25 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 04e9ad4996..d21a24c82f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -205,7 +205,7 @@ struct CPUClass { * so the layout is not as critical as that of CPUTLBEntry. This is * also why we don't want to combine the two structs. */ -typedef struct CPUTLBEntryFull { +struct CPUTLBEntryFull { /* * @xlat_section contains: * - in the lower TARGET_PAGE_BITS, a physical section number @@ -261,7 +261,7 @@ typedef struct CPUTLBEntryFull { bool guarded; } arm; } extra; -} CPUTLBEntryFull; +}; /* * Data elements that are per MMU mode, minus the bits accessed by diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 34318cf0e6..663efb9133 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -13,6 +13,7 @@ #include "exec/breakpoint.h" #include "exec/hwaddr.h" #include "exec/memattrs.h" +#include "exec/memop.h" #include "exec/mmu-access-type.h" #include "exec/vaddr.h" @@ -131,6 +132,31 @@ struct TCGCPUOps { * same function signature. */ bool (*cpu_exec_halt)(CPUState *cpu); + /** + * @tlb_fill_align: Handle a softmmu tlb miss + * @cpu: cpu context + * @out: output page properties + * @addr: virtual address + * @access_type: read, write or execute + * @mmu_idx: mmu context + * @memop: memory operation for the access + * @size: memory access size, or 0 for whole page + * @probe: test only, no fault + * @ra: host return address for exception unwind + * + * If the access is valid, fill in @out and return true. + * Otherwise if probe is true, return false. + * Otherwise raise an exception and do not return. + * + * The alignment check for the access is deferred to this hook, + * so that the target can determine the priority of any alignment + * fault with respect to other potential faults from paging. + * Zero may be passed for @memop to skip any alignment check + * for non-memory-access operations such as probing. + */ + bool (*tlb_fill_align)(CPUState *cpu, CPUTLBEntryFull *out, vaddr addr, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t ra); /** * @tlb_fill: Handle a softmmu tlb miss * diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 9d222dc376..3d84efcac4 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -40,6 +40,7 @@ typedef struct ConfidentialGuestSupport ConfidentialGuestSupport; typedef struct CPUArchState CPUArchState; typedef struct CPUPluginState CPUPluginState; typedef struct CPUState CPUState; +typedef struct CPUTLBEntryFull CPUTLBEntryFull; typedef struct DeviceState DeviceState; typedef struct DirtyBitmapSnapshot DirtyBitmapSnapshot; typedef struct DisasContextBase DisasContextBase; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 35cda1e2b0..d72f454e9e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1221,22 +1221,35 @@ void tlb_set_page(CPUState *cpu, vaddr addr, } /* - * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the - * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must - * be discarded and looked up again (e.g. via tlb_entry()). + * Note: tlb_fill_align() can trigger a resize of the TLB. + * This means that all of the caller's prior references to the TLB table + * (e.g. CPUTLBEntry pointers) must be discarded and looked up again + * (e.g. via tlb_entry()). */ -static void tlb_fill(CPUState *cpu, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +static bool tlb_fill_align(CPUState *cpu, vaddr addr, MMUAccessType type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t ra) { - bool ok; + const TCGCPUOps *ops = cpu->cc->tcg_ops; + CPUTLBEntryFull full; - /* - * This is not a probe, so only valid return is success; failure - * should result in exception + longjmp to the cpu loop. - */ - ok = cpu->cc->tcg_ops->tlb_fill(cpu, addr, size, - access_type, mmu_idx, false, retaddr); - assert(ok); + if (ops->tlb_fill_align) { + if (ops->tlb_fill_align(cpu, &full, addr, type, mmu_idx, + memop, size, probe, ra)) { + tlb_set_page_full(cpu, mmu_idx, addr, &full); + return true; + } + } else { + /* Legacy behaviour is alignment before paging. */ + if (addr & ((1u << memop_alignment_bits(memop)) - 1)) { + ops->do_unaligned_access(cpu, addr, type, mmu_idx, ra); + } + if (ops->tlb_fill(cpu, addr, size, type, mmu_idx, probe, ra)) { + return true; + } + } + assert(probe); + return false; } static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, @@ -1351,22 +1364,22 @@ static int probe_access_internal(CPUState *cpu, vaddr addr, if (!tlb_hit_page(tlb_addr, page_addr)) { if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, page_addr)) { - if (!cpu->cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type, - mmu_idx, nonfault, retaddr)) { + if (!tlb_fill_align(cpu, addr, access_type, mmu_idx, + 0, fault_size, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost = NULL; *pfull = NULL; return TLB_INVALID_MASK; } - /* TLB resize via tlb_fill may have moved the entry. */ + /* TLB resize via tlb_fill_align may have moved the entry. */ index = tlb_index(cpu, mmu_idx, addr); entry = tlb_entry(cpu, mmu_idx, addr); /* * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately, - * to force the next access through tlb_fill. We've just - * called tlb_fill, so we know that this entry *is* valid. + * to force the next access through tlb_fill_align. We've just + * called tlb_fill_align, so we know that this entry *is* valid. */ flags &= ~TLB_INVALID_MASK; } @@ -1613,7 +1626,7 @@ typedef struct MMULookupLocals { * * Resolve the translation for the one page at @data.addr, filling in * the rest of @data with the results. If the translation fails, - * tlb_fill will longjmp out. Return true if the softmmu tlb for + * tlb_fill_align will longjmp out. Return true if the softmmu tlb for * @mmu_idx may have resized. */ static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, @@ -1631,7 +1644,8 @@ static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, if (!tlb_hit(tlb_addr, addr)) { if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, addr & TARGET_PAGE_MASK)) { - tlb_fill(cpu, addr, data->size, access_type, mmu_idx, ra); + tlb_fill_align(cpu, addr, access_type, mmu_idx, + 0, data->size, false, ra); maybe_resized = true; index = tlb_index(cpu, mmu_idx, addr); entry = tlb_entry(cpu, mmu_idx, addr); @@ -1821,8 +1835,8 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, if (!tlb_hit(tlb_addr, addr)) { if (!victim_tlb_hit(cpu, mmu_idx, index, MMU_DATA_STORE, addr & TARGET_PAGE_MASK)) { - tlb_fill(cpu, addr, size, - MMU_DATA_STORE, mmu_idx, retaddr); + tlb_fill_align(cpu, addr, MMU_DATA_STORE, mmu_idx, + 0, size, false, retaddr); index = tlb_index(cpu, mmu_idx, addr); tlbe = tlb_entry(cpu, mmu_idx, addr); } @@ -1836,7 +1850,8 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, * but addr_read will only be -1 if PAGE_READ was unset. */ if (unlikely(tlbe->addr_read == -1)) { - tlb_fill(cpu, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); + tlb_fill_align(cpu, addr, MMU_DATA_LOAD, mmu_idx, + 0, size, false, retaddr); /* * Since we don't support reads and writes to different * addresses, and we do have the proper page loaded for From patchwork Sun Oct 13 22:12:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835091 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1734908wrd; Sun, 13 Oct 2024 15:13:59 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU0v6rkowPJxt+D1563F3MYt5+qAO+HxmDn3BUbFOv2u8bPExdfR92vjrb6BoRd0sCWM+58QA==@linaro.org X-Google-Smtp-Source: AGHT+IGh2YNgalS7Mw88B1baoPwNR1elpJbFeOWX3OBJjCpXqP7nHP7YZycIQma1qWwDdYc6nmP2 X-Received: by 2002:a05:622a:1a1b:b0:460:394e:27a with SMTP id d75a77b69052e-460584b00acmr114832671cf.42.1728857639599; Sun, 13 Oct 2024 15:13:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728857639; cv=none; d=google.com; s=arc-20240605; b=dwluquR0+Rd2+FuKDwpJFBPYWUS7cdpkqah2hLqlcC2pSNISsYqi4bTJQm5gyhE/IA NB9CDaN4m/RSuZ9ydzV5RzbsYEsx6pezPjsFlyL1NmxZ+rHfZQrh4qiftZknAz0qT/uq 41gDgKwJCNg6VxV0LyhZa7TqzsXNs78aQ1yw8Rvzye5zr8LM2sMEDqe4MZGH9s3+acvP vozSa1QQX1GARB4eVmLadGbhkqU3yNsenoeKx+tGYdUstqefQ5strngA9m/ws78sgkCu 7yeV8ipDQURPkkktcLglMNDVIIzUG7tNxFTOUk0KoCFmk2xjEbCFYdc+3OpPTEouBhnw Wohg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5umYHNvw5oCQCN5hr78TRmNHjTlt1NzNl+yfC2iTChU=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=WgyUbonbHkwO0cny5q+Vp8gLsQuv8CZM0DKIWNQlKqn2mehHsByblQksGxcqiMqo83 Hho3wL16k8x2G/xcrLtm1On76khMJHEmiIytS9RMp6bx18h3IUz771iYx2bHUygN1GjO W4uA/3T9oupUbJE6Qn6IMtTcCQiQxUc55ADsgCIQ5uDBqsm8VZ7DhgnQMm0XsSiG5x6V LvVxE9WoGlOijkHUCsxuZYeWz3dTxorchcWcp8EBo9KhSKd68Jnkw9SnAe2lccp1IX3v +ufUo/GrrprDaTsziCD7in6wuLbOMCxf0TPqarOHO1b7KoBETCWqnwYjygLENGisPVZc 846w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="efk/BcX8"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 13/27] accel/tcg: Use the alignment test in tlb_fill_align Date: Sun, 13 Oct 2024 15:12:21 -0700 Message-ID: <20241013221235.1585193-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When we have a tlb miss, defer the alignment check to the new tlb_fill_align hook. Move the existing alignment check so that we only perform it with a tlb hit. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 88 ++++++++++++++++++++++++---------------------- 1 file changed, 45 insertions(+), 43 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d72f454e9e..b76a4eac4e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1620,6 +1620,7 @@ typedef struct MMULookupLocals { * mmu_lookup1: translate one page * @cpu: generic cpu state * @data: lookup parameters + * @memop: memory operation for the access, or 0 * @mmu_idx: virtual address context * @access_type: load/store/code * @ra: return address into tcg generated code, or 0 @@ -1629,7 +1630,7 @@ typedef struct MMULookupLocals { * tlb_fill_align will longjmp out. Return true if the softmmu tlb for * @mmu_idx may have resized. */ -static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, +static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, MemOp memop, int mmu_idx, MMUAccessType access_type, uintptr_t ra) { vaddr addr = data->addr; @@ -1645,7 +1646,7 @@ static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, addr & TARGET_PAGE_MASK)) { tlb_fill_align(cpu, addr, access_type, mmu_idx, - 0, data->size, false, ra); + memop, data->size, false, ra); maybe_resized = true; index = tlb_index(cpu, mmu_idx, addr); entry = tlb_entry(cpu, mmu_idx, addr); @@ -1657,6 +1658,25 @@ static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, flags = tlb_addr & (TLB_FLAGS_MASK & ~TLB_FORCE_SLOW); flags |= full->slow_flags[access_type]; + if (likely(!maybe_resized)) { + /* Alignment has not been checked by tlb_fill_align. */ + int a_bits = memop_alignment_bits(memop); + + /* + * This alignment check differs from the one above, in that this is + * based on the atomicity of the operation. The intended use case is + * the ARM memory type field of each PTE, where access to pages with + * Device memory type require alignment. + */ + if (unlikely(flags & TLB_CHECK_ALIGNED)) { + int at_bits = memop_atomicity_bits(memop); + a_bits = MAX(a_bits, at_bits); + } + if (unlikely(addr & ((1 << a_bits) - 1))) { + cpu_unaligned_access(cpu, addr, access_type, mmu_idx, ra); + } + } + data->full = full; data->flags = flags; /* Compute haddr speculatively; depending on flags it might be invalid. */ @@ -1713,7 +1733,6 @@ static void mmu_watch_or_dirty(CPUState *cpu, MMULookupPageData *data, static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type, MMULookupLocals *l) { - unsigned a_bits; bool crosspage; int flags; @@ -1722,12 +1741,6 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, tcg_debug_assert(l->mmu_idx < NB_MMU_MODES); - /* Handle CPU specific unaligned behaviour */ - a_bits = memop_alignment_bits(l->memop); - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); - } - l->page[0].addr = addr; l->page[0].size = memop_size(l->memop); l->page[1].addr = (addr + l->page[0].size - 1) & TARGET_PAGE_MASK; @@ -1735,7 +1748,7 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, crosspage = (addr ^ l->page[1].addr) & TARGET_PAGE_MASK; if (likely(!crosspage)) { - mmu_lookup1(cpu, &l->page[0], l->mmu_idx, type, ra); + mmu_lookup1(cpu, &l->page[0], l->memop, l->mmu_idx, type, ra); flags = l->page[0].flags; if (unlikely(flags & (TLB_WATCHPOINT | TLB_NOTDIRTY))) { @@ -1754,8 +1767,8 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, * Lookup both pages, recognizing exceptions from either. If the * second lookup potentially resized, refresh first CPUTLBEntryFull. */ - mmu_lookup1(cpu, &l->page[0], l->mmu_idx, type, ra); - if (mmu_lookup1(cpu, &l->page[1], l->mmu_idx, type, ra)) { + mmu_lookup1(cpu, &l->page[0], l->memop, l->mmu_idx, type, ra); + if (mmu_lookup1(cpu, &l->page[1], 0, l->mmu_idx, type, ra)) { uintptr_t index = tlb_index(cpu, l->mmu_idx, addr); l->page[0].full = &cpu->neg.tlb.d[l->mmu_idx].fulltlb[index]; } @@ -1774,19 +1787,6 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, tcg_debug_assert((flags & TLB_BSWAP) == 0); } - /* - * This alignment check differs from the one above, in that this is - * based on the atomicity of the operation. The intended use case is - * the ARM memory type field of each PTE, where access to pages with - * Device memory type require alignment. - */ - if (unlikely(flags & TLB_CHECK_ALIGNED)) { - a_bits = memop_atomicity_bits(l->memop); - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); - } - } - return crosspage; } @@ -1799,34 +1799,18 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, { uintptr_t mmu_idx = get_mmuidx(oi); MemOp mop = get_memop(oi); - int a_bits = memop_alignment_bits(mop); uintptr_t index; CPUTLBEntry *tlbe; vaddr tlb_addr; void *hostaddr; CPUTLBEntryFull *full; + bool did_tlb_fill = false; tcg_debug_assert(mmu_idx < NB_MMU_MODES); /* Adjust the given return address. */ retaddr -= GETPC_ADJ; - /* Enforce guest required alignment. */ - if (unlikely(a_bits > 0 && (addr & ((1 << a_bits) - 1)))) { - /* ??? Maybe indicate atomic op to cpu_unaligned_access */ - cpu_unaligned_access(cpu, addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* Enforce qemu required alignment. */ - if (unlikely(addr & (size - 1))) { - /* We get here if guest alignment was not requested, - or was not enforced by cpu_unaligned_access above. - We might widen the access and emulate, but for now - mark an exception and exit the cpu loop. */ - goto stop_the_world; - } - index = tlb_index(cpu, mmu_idx, addr); tlbe = tlb_entry(cpu, mmu_idx, addr); @@ -1836,7 +1820,8 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, if (!victim_tlb_hit(cpu, mmu_idx, index, MMU_DATA_STORE, addr & TARGET_PAGE_MASK)) { tlb_fill_align(cpu, addr, MMU_DATA_STORE, mmu_idx, - 0, size, false, retaddr); + mop, size, false, retaddr); + did_tlb_fill = true; index = tlb_index(cpu, mmu_idx, addr); tlbe = tlb_entry(cpu, mmu_idx, addr); } @@ -1859,6 +1844,23 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, */ g_assert_not_reached(); } + + /* Enforce guest required alignment, if not handled by tlb_fill_align. */ + if (!did_tlb_fill && (addr & ((1 << memop_alignment_bits(mop)) - 1))) { + cpu_unaligned_access(cpu, addr, MMU_DATA_STORE, mmu_idx, retaddr); + } + + /* Enforce qemu required alignment. */ + if (unlikely(addr & (size - 1))) { + /* + * We get here if guest alignment was not requested, or was not + * enforced by cpu_unaligned_access or tlb_fill_align above. + * We might widen the access and emulate, but for now + * mark an exception and exit the cpu loop. + */ + goto stop_the_world; + } + /* Collect tlb flags for read. */ tlb_addr |= tlbe->addr_read; From patchwork Sun Oct 13 22:12:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835092 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1735038wrd; Sun, 13 Oct 2024 15:14:33 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU2ltLRdT3na4epteoxUeh5TPDfMiKCmrPFE1uXuyDTVl+oQe7cJF9pc6gpOPM0SNSnntoX9g==@linaro.org X-Google-Smtp-Source: AGHT+IE5DbnqAZ0TrrsGLZvhcGM9yJjZ4omSEEzJkl/cJYKUvC5kSM+srHv0+2OVkykx/WBbYb1J X-Received: by 2002:a05:620a:4105:b0:7a9:c04a:f5a with SMTP id af79cd13be357-7b11a36d503mr1523919885a.31.1728857672840; Sun, 13 Oct 2024 15:14:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728857672; cv=none; d=google.com; s=arc-20240605; b=J562tH1aQis/HNnJFBdhvgJ5ZCh6dGa3o1Dv0F9fxfeKxJE+xUsxZXuj54SkEZCTfT eHP/GHpbH6bJrd11xxR91vjs6ebmSNJPRaBJcakt12qk2sLoQQ3BAHWB2XqwbzJjo3CI UHDADkR5jKJrDZ8ffaXr5Uy2u2jbCKvC9UdgH3OA5xs7FmSMYAcw1JAwauF7vcaM8/J3 z9Lj0Jm971Xke4eqUX5U1Tzy5VQVrWtmBNFisBMZPsoebdGh9rpIr2tN0hTvyYEKyiPX lIJNtXZ4FD7Go/a1yQrpXohKNr+PWYf+gCOBzOZgLrt5g9sjhFwpkO/mI6uF2BT3AFv0 KUlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZMaSkZRoz5YPXdGi4Fagk1yb2WqLYDqE0+TVeXDEoMY=; fh=3//KcqJEsa04kIBt5Nb/DJuP+2GuH1NwDRxnSl44zdw=; b=NjEgIZPadbaCxtTc3kK/vskIYpBae1EAWhuTn7NRqVQmKtZfdtP18opYWNMX+Nevw+ wpD7BNAdR+4yeb950B5n71MpTFmQu1FsyW4n4YyrBNCyT6gwmQOoFkfmV7qtiAVewzId psMfYejWCsE6Aj1ixM8V/jTCNX4+62zWB6mTPG5IZI/nZo969zq8bXrM/e8+oEqd/iVK NaIuzl0SySglhZY7/Ir015yXkaR1NCvzCO4JjpwGNuEd4HJDeJuM3N+faL5Xqg6XqdQK R5Ol7SP4QXPHnt0Ri95hC5FWZ79s4kPpPfXI+NL3mfmHAvui1p1tfSocr0FAo1+iXSPv 7NJA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kgGX6F6s; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 14/27] target/hppa: Add MemOp argument to hppa_get_physical_address Date: Sun, 13 Oct 2024 15:12:22 -0700 Message-ID: <20241013221235.1585193-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Just add the argument, unused at this point. Zero is the safe do-nothing value for all callers. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 +- target/hppa/int_helper.c | 2 +- target/hppa/mem_helper.c | 9 +++++---- target/hppa/op_helper.c | 2 +- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index f4e051f176..526855f982 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -369,7 +369,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, - int type, hwaddr *pphys, int *pprot); + int type, MemOp mop, hwaddr *pphys, int *pprot); void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 391f32f27d..58695def82 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -167,7 +167,7 @@ void hppa_cpu_do_interrupt(CPUState *cs) vaddr = hppa_form_gva_psw(old_psw, env->iasq_f, vaddr); t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX, - 0, &paddr, &prot); + 0, 0, &paddr, &prot); if (t >= 0) { /* We can't re-load the instruction. */ env->cr[CR_IIR] = 0; diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index b984f730aa..a386c80fa4 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -197,7 +197,7 @@ static int match_prot_id64(CPUHPPAState *env, uint32_t access_id) } int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, - int type, hwaddr *pphys, int *pprot) + int type, MemOp mop, hwaddr *pphys, int *pprot) { hwaddr phys; int prot, r_prot, w_prot, x_prot, priv; @@ -340,7 +340,7 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) mmu_idx = (cpu->env.psw & PSW_D ? MMU_KERNEL_IDX : cpu->env.psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX); - excp = hppa_get_physical_address(&cpu->env, addr, mmu_idx, 0, + excp = hppa_get_physical_address(&cpu->env, addr, mmu_idx, 0, 0, &phys, &prot); /* Since we're translating for debugging, the only error that is a @@ -438,7 +438,8 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, break; } - excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, &phys, &prot); + excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, 0, + &phys, &prot); if (unlikely(excp >= 0)) { if (probe) { return false; @@ -678,7 +679,7 @@ target_ulong HELPER(lpa)(CPUHPPAState *env, target_ulong addr) hwaddr phys; int prot, excp; - excp = hppa_get_physical_address(env, addr, MMU_KERNEL_IDX, 0, + excp = hppa_get_physical_address(env, addr, MMU_KERNEL_IDX, 0, 0, &phys, &prot); if (excp >= 0) { if (excp == EXCP_DTLB_MISS) { diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 7f79196fff..744325969f 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -334,7 +334,7 @@ target_ulong HELPER(probe)(CPUHPPAState *env, target_ulong addr, } mmu_idx = PRIV_P_TO_MMU_IDX(level, env->psw & PSW_P); - excp = hppa_get_physical_address(env, addr, mmu_idx, 0, &phys, &prot); + excp = hppa_get_physical_address(env, addr, mmu_idx, 0, 0, &phys, &prot); if (excp >= 0) { cpu_restore_state(env_cpu(env), GETPC()); hppa_set_ior_and_isr(env, addr, MMU_IDX_MMU_DISABLED(mmu_idx)); From patchwork Sun Oct 13 22:12:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835103 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1735558wrd; Sun, 13 Oct 2024 15:16:33 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXwl4GmiraVy/d+mjbkQc6tKrDg5x+YJVEpcZg8F6mnNJY5EHa0r3jeP54XmM8rF9e0z6rpOQ==@linaro.org X-Google-Smtp-Source: AGHT+IFdRMzdOk/FM0rEqWYuHdi+iS7Ofnr9/rT2OSPUoILwRrJk8N86ATCy59I01yDizZTn6907 X-Received: by 2002:a05:620a:4592:b0:7a9:a1b3:2240 with SMTP id af79cd13be357-7b11a3dfe82mr1520528785a.61.1728857793568; Sun, 13 Oct 2024 15:16:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728857793; cv=none; d=google.com; s=arc-20240605; b=WWNay48HAvdlVhWIki2f14GXVm/MQcGIdcS1AQwA9uchdZ3kQJW9+Z6N7UBMqQLWEM kX/d7qKoOaJ0EFckOXww7UTiq73J55R5AcyXFjjK5MKMLj1jFQ2gqigZiA1qYfW9O8QN 3hdR5GUkcJyzUHmSp7b2gdKx6JkxHXTjvJcupXZTTRoIR4HIJPvV9/P/RxZK3Go5xQz9 EMFCONi/bpMelfinuKpoFTD32yGZiLu8Kw5GcUnr9lkoFrJxVJ+0kqarb9plWeygPkXL TxeIK2z8B2/MkJprEzF3xI/iRtXictIe1qaeIcfGjIvj2pUQBg1Q9mCQ6eFybWhtut3u 9QEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jvwlrMz3Fk2P5q43/JWG8Wh7xLnVWB9wP6XAmMUyGN8=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=gz1NKaL/EtIC3rDIy/nkxPFLWkUXioMq8qIVW4sAUpMTi+WkJDwUZgc5iCp3riD3XV Iq/qdfVvJRLL6FuXxBnA7Cf1rsxv3P1onE96RnEszya19IUrFI3gq4WYBRzmD8mv44Mg +RF+ggBDbjSRPeHyyV7IQx6BB4N7AiHjnucbY+UMWK0y9IhfjSlufKiB09Kb9AYul3j9 uOFZruE3btPFi3bA6LVqlmU7aPYt/MKJ2yEi8/eL9avGb6JJz2a3nYUZ6PSYa+0UlA/w XC6JJQQyqfy78wWqtAbZNgY4QdL4lRGGIL06lLfx4GuaffvKvjlPnIlg0nGa8dH+AWKN Zr9A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JSCedkKG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 15/27] target/hppa: Perform access rights before protection id check Date: Sun, 13 Oct 2024 15:12:23 -0700 Message-ID: <20241013221235.1585193-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In Chapter 5, Interruptions, the group 3 exceptions lists "Data memory access rights trap" in priority order ahead of "Data memory protection ID trap". Swap these checks in hppa_get_physical_address. Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index a386c80fa4..f027c494e2 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -267,6 +267,12 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, goto egress; } + if (unlikely(!(prot & type))) { + /* Not allowed -- Inst/Data Memory Access Rights Fault. */ + ret = (type & PAGE_EXEC) ? EXCP_IMP : EXCP_DMAR; + goto egress; + } + /* access_id == 0 means public page and no check is performed */ if (ent->access_id && MMU_IDX_TO_P(mmu_idx)) { int access_prot = (hppa_is_pa20(env) @@ -281,12 +287,6 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, prot &= access_prot; } - if (unlikely(!(prot & type))) { - /* Not allowed -- Inst/Data Memory Access Rights Fault. */ - ret = (type & PAGE_EXEC) ? EXCP_IMP : EXCP_DMAR; - goto egress; - } - /* * In priority order, check for conditions which raise faults. * Remove PROT bits that cover the condition we want to check, From patchwork Sun Oct 13 22:12:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835105 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1735768wrd; Sun, 13 Oct 2024 15:17:18 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVNVi+TyI+bRrXF1f6R6RsvF9y/Mxk8vRSXU7pILS7MXaO2T4INNnOIq66S1ndytCVDjvt+VA==@linaro.org X-Google-Smtp-Source: AGHT+IH2ZN8nGlcbEb2czmnX8aoEU5vzir+gZZtNLws6aznf4TC0c9owjU//0JNaBJ+gbuIyplHp X-Received: by 2002:a05:6214:4607:b0:6cb:ee73:6932 with SMTP id 6a1803df08f44-6cbf0036301mr148383406d6.28.1728857838243; Sun, 13 Oct 2024 15:17:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728857838; cv=none; d=google.com; s=arc-20240605; b=XbZFsgGERrs+uKDfKerhMtr16rEaHzi4YSGB1ElfRFnYtb5u/NTtNLGANVBzLob1V3 seobrpxjC7RMcGFNcTnK1ilp80hljbvk0B4fAUPSQuTswEZ5Kotwt3xbchjAJ1NhwdAA OjZeC4Co/N/kgSaSmrx80cn3Pm3DqD60kIts4EP+F4JZ5pY+HnhTsrEm8+XBHvjKnF4o bC+xBBz0hA1c/NXjmLgoEKEr1A2uSiFGVzL7ZeWp8rSmxXJk34a54MuJx3Lk2YGGoEqC SzZuQleIK+lXHv2wCHH3j52qAuhz54iDGUCdAzyruagg/iJWzsgU4wv5/EJlCs1kA4a5 VsUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8E2Z9ZSy95UZsg9Y2N2fIiaRxpU5aj12TR1V9ijHxjM=; fh=3//KcqJEsa04kIBt5Nb/DJuP+2GuH1NwDRxnSl44zdw=; b=QeIZGBJNXBnlhdSflOEklvIdhMxswk/OO9hCfKsJCtuPPKvYYE1ZC2tVwh5KxI+ZoE 1Bg4qGPmNkPtmuGYmSAsRybdTXaShHHICHuBa5piNBXdZ6YB2mZAWrMO+t1LKP903EoT BZsxP0O/x6RQFYNV2lkSPx3lOZSW/xCk4REVq/Cj7dS3PAkWMhn+SITNuEsHPJXIpGyN Z4vR45Aq0pxcuXcp5pOx7XeO8PxdkPstCsfMshPdNiGjXkN871mc57YkneASSVU8ENxA X5tewkKn/8L64hzGTJIOYYPy7X28GabL0tEahJ3o9cWwNe3pLCMlyT2ebMjKw/wpSm5T eoUA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="E5L/rcVo"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 16/27] target/hppa: Fix priority of T, D, and B page faults Date: Sun, 13 Oct 2024 15:12:24 -0700 Message-ID: <20241013221235.1585193-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Drop the 'else' so that ret is overridden with the highest priority fault. Fixes: d8bc1381250 ("target/hppa: Implement PSW_X") Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index f027c494e2..f71cedd7a9 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -288,7 +288,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, } /* - * In priority order, check for conditions which raise faults. + * In reverse priority order, check for conditions which raise faults. * Remove PROT bits that cover the condition we want to check, * so that the resulting PROT will force a re-check of the * architectural TLB entry for the next access. @@ -299,13 +299,15 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, /* The T bit is set -- Page Reference Fault. */ ret = EXCP_PAGE_REF; } - } else if (!ent->d) { + } + if (unlikely(!ent->d)) { prot &= PAGE_READ | PAGE_EXEC; if (type & PAGE_WRITE) { /* The D bit is not set -- TLB Dirty Bit Fault. */ ret = EXCP_TLB_DIRTY; } - } else if (unlikely(ent->b)) { + } + if (unlikely(ent->b)) { prot &= PAGE_READ | PAGE_EXEC; if (type & PAGE_WRITE) { /* From patchwork Sun Oct 13 22:12:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835093 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1735087wrd; Sun, 13 Oct 2024 15:14:44 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVhLyixwpK6YEnG8cfKs1KSMOi13IXWKfnpubRAXFjZYGXTX7d1qec5FKGW7L52IB4o3i5fNA==@linaro.org X-Google-Smtp-Source: AGHT+IHyjaUTdjYMqcENBlWBSqJGePgqPYBStY8baNNt00Noq8WGeJV4k26cAP3MlOz3i8YNhVKL X-Received: by 2002:a05:6214:468d:b0:6cb:f9cd:b400 with SMTP id 6a1803df08f44-6cbf9cdb498mr103378756d6.9.1728857683866; Sun, 13 Oct 2024 15:14:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728857683; cv=none; d=google.com; s=arc-20240605; b=bznLduxLYT3h31GfQrSk+73GYgE5lPxc1KU4LPWVClT1JfgEeGH3KDDwziMIJsq/oD KW1PBwQmL06m4Hp6JAlCLvuvD2zIk/JdfjaXvtp+Pxksxcy0C8pPgB5YEqoWQFJV904h soE/mNROYm1vVDh2LueD/xuCeoXp5XfjQ1yG6fBYeR2MzHcKpeF9PvJmltJ8cTaLej5F eK2gjwBrJvmShzHK3xJLTTO0SJj5BkNjiW281PU7gK4attuuP9Bub3ZiNDi60zD/kUuI JVOKo6x1hUzcEwp6smYuUeiyedqCRY0EAEYhrv5e3Y0t8BSkcDbFuobo1v5VSn9wBy4s 3q4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xQhK8NjjgW/kNvx5X1m22TpA6VVxTZtyOqTVcWaZJho=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=QjUubS1iy4lnvHX7aUyu5RkolXh5zVZ3z8D0vnjRPNIYbdanuAXYdocAHCGmuhhKue xXz38jvAHPrmMTVLVemOaBqjTqSqul0BdB9LaMWLmzNSYI5pLAb+C547ua6uU4YvbD04 upftByIMSD7jTLZdHWIPhtiluy88zQLFla5HbE6j8sgRAIYTwge1vwVzZ4APPtSbhKBD wJNM8/UiQ5RCGhhkor23MA7axixF0oa9IVZqeJHoYio2AHhynVwlSS4JgftrjRN/hCvp uc30kPBZsQbE1eZz9XHwrH2psBU4XEzQ83q9YCfs9fmTzMKSlSpE6mcjgyegsxgX4lCZ eTsA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OTdi2pZT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index f71cedd7a9..d38054da8a 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -221,7 +221,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, g_assert_not_reached(); } prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - goto egress; + goto egress_align; } /* Find a valid tlb entry that matches the virtual address. */ @@ -323,6 +323,11 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, } } + egress_align: + if (addr & ((1u << memop_alignment_bits(mop)) - 1)) { + ret = EXCP_UNALIGN; + } + egress: *pphys = phys; *pprot = prot; From patchwork Sun Oct 13 22:12:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835112 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1736556wrd; Sun, 13 Oct 2024 15:20:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVDkz2zqYZJ5Y+S/G/j0STxGwun9aR8wViFh+TfSD8jCCzRzBZV2zlJaYv5LThV+errVaxqIQ==@linaro.org X-Google-Smtp-Source: AGHT+IF34LMUlXTB0TS2v77xckb5pjsxmYRskp1Zc4gez7egGDU1KtqjLBYdmZPubs5yGjYVORKT X-Received: by 2002:a05:620a:1a8b:b0:7a9:beaf:ce4e with SMTP id af79cd13be357-7b11a3532f4mr1636223685a.18.1728858045120; Sun, 13 Oct 2024 15:20:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728858045; cv=none; d=google.com; s=arc-20240605; b=GoGaCLNpBfREkBHXLwl7494iYuUEbQqNgZnNorRk6iMI8Sm930NJDPuwW4FMcvqZVO HkrSmMzBK9L68xJBUDtAgwDUg+RavrfZpO3gbPn5aE+hoIx2uZhKdk1PAJMQN1uDAdNY 4xpGj7rdUNwR4vdxQaXUuFBRg1yA8ghn3ZFXqxYdmujV+5egtXTFRZqBHHKeqtynf4rI GN34rq1BxIFzYzU0+DbtRUdqhjVidrtND4kRUSwRliCVzY1Pc+dm5IFL0Q+xfIpNEXnX Gncnc7GeEX0CCfZWbl8LAr2jyys4kFOO8TCEM4JqngX9CDUQ1m74nGWGqFd0f3m8grUb Y8mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qyIQGMW9LXzuIdZhtsfgRRXnueKIctdP5fxMu5c0xxA=; fh=wDljmxUHXfz9MGj2//jPHYRc53BMWF157v8rVKELrf4=; b=OTTrt4g9+ksk+FKwmKzVUTUt+YG9fQM4Cr8EU3YgawGZJYtEqexFP8+NOztI/Tiv/Z V2PUV34cF0kwKQb9ss45GzyM/hjlG8I3/VQLld79C4Gq4pyrafDZ5OKoZh8fWe2k4bVt vkLevvWtPKC14aRuy+UQPJrQ4t+5JNpc1Cx4Ftw1EZjdICdPnXsLihWnInYFRicn2RyV AUvywTe5CBmb3u67SFagdsco27KS9+JLj11pcUXPfecDl0uxB5ZFqmMCDkUHnYR6VvFY VG9DHqdp67I1rPU2Mpw7Dzk+FlxCHycdggKqZxBH1j9T1yjbeM26FKESTVaOJ5wh2hSD 7yBQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ha8hBcWJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller Subject: [PULL 18/27] target/hppa: Implement TCGCPUOps.tlb_fill_align Date: Sun, 13 Oct 2024 15:12:26 -0700 Message-ID: <20241013221235.1585193-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert hppa_cpu_tlb_fill to hppa_cpu_tlb_fill_align so that we can recognize alignment exceptions in the correct priority order. Resolves: https://bugzilla.kernel.org/show_bug.cgi?id=219339 Tested-by: Helge Deller Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 6 +++--- target/hppa/cpu.c | 2 +- target/hppa/mem_helper.c | 21 ++++++++++++--------- 3 files changed, 16 insertions(+), 13 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 526855f982..e45ba50a59 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -363,9 +363,9 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); void hppa_ptlbe(CPUHPPAState *env); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled); -bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t ra); void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 7cf2e2f266..c38439c180 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -226,7 +226,7 @@ static const TCGCPUOps hppa_tcg_ops = { .restore_state_to_opc = hppa_restore_state_to_opc, #ifndef CONFIG_USER_ONLY - .tlb_fill = hppa_cpu_tlb_fill, + .tlb_fill_align = hppa_cpu_tlb_fill_align, .cpu_exec_interrupt = hppa_cpu_exec_interrupt, .cpu_exec_halt = hppa_cpu_has_work, .do_interrupt = hppa_cpu_do_interrupt, diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index d38054da8a..b8c3e55170 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -424,12 +424,11 @@ void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, } } -bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, - MMUAccessType type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, + MMUAccessType type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t ra) { - HPPACPU *cpu = HPPA_CPU(cs); - CPUHPPAState *env = &cpu->env; + CPUHPPAState *env = cpu_env(cs); int prot, excp, a_prot; hwaddr phys; @@ -445,7 +444,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, break; } - excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, 0, + excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, memop, &phys, &prot); if (unlikely(excp >= 0)) { if (probe) { @@ -454,7 +453,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, trace_hppa_tlb_fill_excp(env, addr, size, type, mmu_idx); /* Failure. Raise the indicated exception. */ - raise_exception_with_ior(env, excp, retaddr, addr, + raise_exception_with_ior(env, excp, ra, addr, MMU_IDX_MMU_DISABLED(mmu_idx)); } @@ -468,8 +467,12 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, * the large page protection mask. We do not require this, * because we record the large page here in the hppa tlb. */ - tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, - prot, mmu_idx, TARGET_PAGE_SIZE); + memset(out, 0, sizeof(*out)); + out->phys_addr = phys; + out->prot = prot; + out->attrs = MEMTXATTRS_UNSPECIFIED; + out->lg_page_size = TARGET_PAGE_BITS; + return true; } From patchwork Sun Oct 13 22:12:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835104 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1735615wrd; Sun, 13 Oct 2024 15:16:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWi9Z3Dkqq5eSu7jUnviDIs9w+8TdUoO89F66rX50pxtdoBbYgPT1jlguwJTMHttF1Wj6LJ2A==@linaro.org X-Google-Smtp-Source: AGHT+IF8U+dEO+VBMwuDwvAAhygHdBKaWu/mPKvpe2r1xQEmJ2/bf1Gkab7I5L7PzcF7oOF/+Al0 X-Received: by 2002:a05:620a:4144:b0:7b1:161c:ef58 with SMTP id af79cd13be357-7b11a3734b3mr1012459885a.28.1728857805260; Sun, 13 Oct 2024 15:16:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728857805; cv=none; d=google.com; s=arc-20240605; b=RHeDWQip/PGB/VCD3mDLzbjrnKa29kBWdQ7Sq7xMCog/A4+EysZJ6lZPTaWL5dPSKl rWkF0mbMt3ziNT8AqUeW/rKJFpXO1yu+5AgwUWvCpTIj9AW3dMNOZssrmbetncrEvWc3 rkGXTcTPMgmS0OwI0W1rH9rL43fLKH57SplsDeBOanNg4X1ZDuOPraHyq9BtUBMF0ZxL CnYWMnpp/vcjNc8BUE5uSzXyDmRz+NMbSDOv+QBvSn8BdY+NbQkm0DzyFKxI0YizuSmG kGa3Ce2j1a3Sa0DXIeS49p9enm0VuEvAh+JDVVFRq9rBa8GxIMspee5SLDUY2eMe3xD3 qOmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RUID/VOY3Ga2ZN/DeZx4JrZs9/xknXUyzF7dZ/9YQNo=; fh=3//KcqJEsa04kIBt5Nb/DJuP+2GuH1NwDRxnSl44zdw=; b=SAa0r/hfbdB1zCsM+x63hM8i53Q67HVkgTUvKQbI9GKvPe7pnnonMiU5SmhOsZRNzy Lz44w6/nlOnWdsq3miKKg98IaQXCFhWTrvqIyDgkA88op8vz3I8IzmqRZgBx7h+SkIoJ mBx0ez2eIfcMEOS0uCyrVt6xWl7RV6xk3mZpl8HJ3O0oQ3Wr2wKF9iE/FxchdRRvV74N kM6z28OFAT13PJI2wQW8JsYQx1X0Pht6GTc5ngHJsV0pv//NG6VWiDUAt3E5aluOC5T6 JzH0/1HvLW/xJZ7drwbFovLJRCc3dKJ5eCQI2VF/RVEwXqIIQ3nAjq9BmbdUbK3eEY2O SIzQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=z2qlj6jV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 19/27] target/arm: Pass MemOp to get_phys_addr Date: Sun, 13 Oct 2024 15:12:27 -0700 Message-ID: <20241013221235.1585193-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Zero is the safe do-nothing value for callers to use. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 ++- target/arm/ptw.c | 2 +- target/arm/tcg/m_helper.c | 8 ++++---- target/arm/tcg/tlb_helper.c | 2 +- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1e5da81ce9..2b16579fa5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1432,6 +1432,7 @@ typedef struct GetPhysAddrResult { * @env: CPUARMState * @address: virtual address to get physical address for * @access_type: 0 for read, 1 for write, 2 for execute + * @memop: memory operation feeding this access, or 0 for none * @mmu_idx: MMU index indicating required translation regime * @result: set on translation success. * @fi: set to fault info if the translation fails @@ -1450,7 +1451,7 @@ typedef struct GetPhysAddrResult { * value. */ bool get_phys_addr(CPUARMState *env, vaddr address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) __attribute__((nonnull)); diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 659855133c..373095a339 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3572,7 +3572,7 @@ bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, } bool get_phys_addr(CPUARMState *env, vaddr address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { S1Translate ptw = { diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 23d7f73035..f7354f3c6e 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -222,7 +222,7 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, int exc; bool exc_secure; - if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_DATA_STORE, 0, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type == ARMFault_QEMU_SFault) { if (mode == STACK_LAZYFP) { @@ -311,7 +311,7 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr, bool exc_secure; uint32_t value; - if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_DATA_LOAD, 0, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type == ARMFault_QEMU_SFault) { qemu_log_mask(CPU_LOG_INT, @@ -2009,7 +2009,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure, "...really SecureFault with SFSR.INVEP\n"); return false; } - if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_INST_FETCH, 0, mmu_idx, &res, &fi)) { /* the MPU lookup failed */ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure); @@ -2045,7 +2045,7 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx, ARMMMUFaultInfo fi = {}; uint32_t value; - if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_DATA_LOAD, 0, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type == ARMFault_QEMU_SFault) { qemu_log_mask(CPU_LOG_INT, diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 885bf4ec14..1d8b7bcaa2 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -344,7 +344,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, * return false. Otherwise populate fsr with ARM DFSR/IFSR fault * register format, and signal the fault. */ - ret = get_phys_addr(&cpu->env, address, access_type, + ret = get_phys_addr(&cpu->env, address, access_type, 0, core_to_arm_mmu_idx(&cpu->env, mmu_idx), &res, fi); if (likely(!ret)) { From patchwork Sun Oct 13 22:12:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835095 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1735151wrd; Sun, 13 Oct 2024 15:14:59 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWgPPNnV5sf/p6aQhX3hCh+UyJQHxVVRQOgI7rPK4c3eDEEpGRp/0qet+DCZPk1BHT+ul9Z6A==@linaro.org X-Google-Smtp-Source: AGHT+IFEizPVrsk9C6OO3osnS0giUmGclCVpmIZiK24GdsW0hLOwSWuVShbqPfuvmOA0dC/xyVvO X-Received: by 2002:a05:6214:4b09:b0:6cb:2f11:6b9 with SMTP id 6a1803df08f44-6cbeff6306cmr169292736d6.23.1728857699706; Sun, 13 Oct 2024 15:14:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728857699; cv=none; d=google.com; s=arc-20240605; b=CEJCvu1fOmiS7jq5bMEVJMG82KH7ATZTbKHVsgMiN6qYA9YbA5rFni5C/l/BVOSivN kox2T7zoGBtZ6fGI8kewkx88ieFcQF7AiFgWu/cF9xvWrKDS6eAbOXSWvIDI16tptAfu HQo9Ps9GwS7XtrX/Ij5fodorGyeKOel5o9Fb6heZN6j68tm1I8yvgOYUiAQE26hyZMKc LaPxJ+eyyAyjnOC916NJyzo4XN/dBmMZjvOs8+aX+RtroPxTVw2pmwqgxSIb0Juk8m5q 2291LAvR58Il4d0D4Mmx6OOHscxOXkzcoQTWhQoMEdiY+1Wos3PnI8GAa7xomhU/cyNw I/dQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=I928rOfU7rFS4/uAexBKDkmn1Lv4VMSl/VKyNRV9wmg=; fh=jPrxLhM/2+ATb52kRFb3bxuZkptRVHP7DuqEwlo+BX0=; b=XJUZdMlkqA3zoCST5uIYMuLlSnVTzXJto/eYp8JIHyxhPYFIuCpzc4vu4Ir5HP5pp/ co3oZcFB5RHUaRruKnRL6ouErROoIdwjDw0PQH7+XV8PHGLj6mDcnCYBjSB/gJljOHEZ j/x3SqaNxVRjm/QvjxRPutZqrx0BOOvIrq8xAm7iiGhVf736byaR5ek9IF1e1LHPVvae larPMrq2voCthAEWn8B7bOZAnGUzodsJllyfxz0CH3jIXpIYPegJvA/9Yg+6oWpC+I+z aNG4R32mfIekiWq+zPQYlxMQH7gaCGS9N+Om563gK7kQfFTpK6/24aTs/qrhTQygf7Mz 2Tuw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sAJxY6ZN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PULL 20/27] target/arm: Pass MemOp to get_phys_addr_with_space_nogpc Date: Sun, 13 Oct 2024 15:12:28 -0700 Message-ID: <20241013221235.1585193-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Zero is the safe do-nothing value for callers to use. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 ++- target/arm/helper.c | 9 +++++---- target/arm/ptw.c | 2 +- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 2b16579fa5..a6088d551c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1461,6 +1461,7 @@ bool get_phys_addr(CPUARMState *env, vaddr address, * @env: CPUARMState * @address: virtual address to get physical address for * @access_type: 0 for read, 1 for write, 2 for execute + * @memop: memory operation feeding this access, or 0 for none * @mmu_idx: MMU index indicating required translation regime * @space: security space for the access * @result: set on translation success. @@ -1470,7 +1471,7 @@ bool get_phys_addr(CPUARMState *env, vaddr address, * a Granule Protection Check on the resulting address. */ bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx, ARMSecuritySpace space, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3f77b40734..0a731a38e8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3599,11 +3599,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, GetPhysAddrResult res = {}; /* - * I_MXTJT: Granule protection checks are not performed on the final address - * of a successful translation. + * I_MXTJT: Granule protection checks are not performed on the final + * address of a successful translation. This is a translation not a + * memory reference, so "memop = none = 0". */ - ret = get_phys_addr_with_space_nogpc(env, value, access_type, mmu_idx, ss, - &res, &fi); + ret = get_phys_addr_with_space_nogpc(env, value, access_type, 0, + mmu_idx, ss, &res, &fi); /* * ATS operations only do S1 or S1+S2 translations, so we never diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 373095a339..9af86da597 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3559,7 +3559,7 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, } bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx, ARMSecuritySpace space, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) From patchwork Sun Oct 13 22:12:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835098 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1735363wrd; Sun, 13 Oct 2024 15:15:51 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW3pNsFrP3n6gWJWID9pAJJ3Yy+Sag6YcrsPpu/dmrQHu0XTenMo4UOTjMuqm81aZ7ewGLFxA==@linaro.org X-Google-Smtp-Source: AGHT+IEdpL3REAWQjQ4k5EtOHDYTwt4hQrYdFZpOY/7EQTnLm1im+OTcZXE4a4n5E9lKANC/8Rui X-Received: by 2002:a05:622a:1c18:b0:45d:83eb:6044 with SMTP id d75a77b69052e-4604bc2d802mr138648911cf.43.1728857751041; Sun, 13 Oct 2024 15:15:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728857751; cv=none; d=google.com; s=arc-20240605; b=AQeqmQMxI5PHH+uxtVadVL1YL8xNsN6xMgsbOwnke3LM9gL7Xp3BXkPYoWCZxcH8fh xh5NHxhquAKg6Cv38n++KvTqHkMRW/F0NrkeVHdDmyU7iOakXM5j2JN/n6Z+jFaK4jDe nV8VPf9sobNRTjTY2oTlfAqIrbDTgLhZYn1eRddTwgvLicrstZwnJIwhgEPBTgkjB/b9 xoR5jwRXYu38Qx+iUaryI+I0KaWX19ToLKU4sqY4hZUFphntD3bi4IaQLoPPnesZu1es gYfUy91Tppg7iPHWFmID3D4xE4GMz/EIxBaOaVduGOy7UpUtf7Kxrf7tFdmUAw7GQFi4 OAFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=617h4byv7OP/ct3y2kJCr5k6Qy1wZsttJUBcCYmwvNQ=; fh=jPrxLhM/2+ATb52kRFb3bxuZkptRVHP7DuqEwlo+BX0=; b=NwhfaGRByz1HvVA0Pdp6XSw3nOZ+4MEDa8mXV7FUSCNgKlRYJLidLdoKy/vGsv/9oV 8Npjq/4D8krhuxSSH6u7L2UWXb3irGiEKxfYwEOiqN5vtFWqHs7Z4lgp9/qEBoVQQf// j64YECvvMXhpaj5oOZgr/Uw1NmyF2Ez2h/YwOOXPb50/UWCQC6BbcvuJGX5N1SzaCGNJ xQcqHTEi0xfr4kAQetniT4jIH+aFbSly2dKUwuuSFeoSE0gpeUEEVmm9iT5hzdc9vmPf CJkamCfixTK4ueyjymyM2DVjVaV3Cn0Mxq78tlqNFQRpbUmt9ufnI8DyK83z4LD5EEsJ 4Ing==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="S7/pl+SZ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PULL 21/27] target/arm: Pass MemOp to get_phys_addr_gpc Date: Sun, 13 Oct 2024 15:12:29 -0700 Message-ID: <20241013221235.1585193-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Zero is the safe do-nothing value for callers to use. Pass the value through from get_phys_addr. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9af86da597..e92537d8f2 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -81,7 +81,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi); @@ -579,7 +579,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, }; GetPhysAddrResult s2 = { }; - if (get_phys_addr_gpc(env, &s2ptw, addr, MMU_DATA_LOAD, &s2, fi)) { + if (get_phys_addr_gpc(env, &s2ptw, addr, MMU_DATA_LOAD, 0, &s2, fi)) { goto fail; } @@ -3543,7 +3543,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { @@ -3641,7 +3641,8 @@ bool get_phys_addr(CPUARMState *env, vaddr address, } ptw.in_space = ss; - return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); + return get_phys_addr_gpc(env, &ptw, address, access_type, + memop, result, fi); } hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, @@ -3660,7 +3661,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, ARMMMUFaultInfo fi = {}; bool ret; - ret = get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi); + ret = get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, 0, &res, &fi); *attrs = res.f.attrs; if (ret) { From patchwork Sun Oct 13 22:12:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835089 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1734901wrd; Sun, 13 Oct 2024 15:13:58 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVtFO55HOWYRyn5BCMg9eSYufOYFHZS8c/ElQC+fmnt8VUcrSZ5BS12/pL30qZNJX7PWyJvFA==@linaro.org X-Google-Smtp-Source: AGHT+IEyguhRBMqrg0WCND2/6eBg07xWxudNr08DD9EXj/WhAV5F8+1nbEcSHdeMHpTnscJNKBC2 X-Received: by 2002:a05:620a:4622:b0:7ac:b1fb:35cc with SMTP id af79cd13be357-7b11a3a74c9mr1276740585a.40.1728857637956; Sun, 13 Oct 2024 15:13:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728857637; cv=none; d=google.com; s=arc-20240605; b=ktCiTjzf9hcsrr7Os1nmV1BhRNmn4EdHZWo0ecP+jeG4PUgsOtGyoqkG6FJveXtheW UVSJKc6c7aTOj5ajOkix0wFnblYcTyLaAU3oBCjYQD60xBkNcudehUrbuL5MXMPFCKeA obhNfqFNj4c+/ZUBg43j6Boy16Zh4VHpVAsH5ypSmN02e+X9F9GQNqs9RPNM8qsPgrTJ DHy9ROTolL7oCnjMNJgeevwHuOasStle5sU4/JBVJOHhDjmdxRmD55mE8p//id89fWz/ 5CvbPC1Bt7OIGqbis/R1tRurL4VB0/pYGKL5SB9AD5yqawNKFPCqKQc4950bmIqgJbcx IDwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HpCts7Lc7po90jMJZMaWUdEUzHFwVBTsaL90Hh3zO7Y=; fh=jPrxLhM/2+ATb52kRFb3bxuZkptRVHP7DuqEwlo+BX0=; b=Q6ue2hHhuArJ1TNo68kGJdprQzZ48tnq3Gx0PDYfmNHb+c6IyDvgAWq/IK8Xag/Dpt /GMQ63m9aGMQ8mm0qi2BExYk0ptJ/Sm5o7AudbiOgODBfeQJyZXFpNQu3jDjpdMZbEHx 7HeRUUxTRAS291D+aV1ZS1GplbxDxMRScfZqfiTBKZhDJ2M/WUCJmSqLFA3XKd/ZIb9o NaW/HsioCS7EnOua7bd3FEG9zyISYYM/WCkIWF2ZNSjajU+fQ7wG+QwwFVwZ8gCVE5aw M3cWlV0yDCMpZriTlBxBqLH0S2z+6MKO1R1jYNJbzmo8TJ/TSFbT2eWjZY98utJ/7nLJ 4YhQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bmn4ZD0z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PULL 22/27] target/arm: Pass MemOp to get_phys_addr_nogpc Date: Sun, 13 Oct 2024 15:12:30 -0700 Message-ID: <20241013221235.1585193-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Zero is the safe do-nothing value for callers to use. Pass the value through from get_phys_addr_gpc and get_phys_addr_with_space_nogpc. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e92537d8f2..0445c3ccf3 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -75,7 +75,7 @@ typedef struct S1Translate { static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi); @@ -3313,7 +3313,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ARMSecuritySpace ipa_space; uint64_t hcr; - ret = get_phys_addr_nogpc(env, ptw, address, access_type, result, fi); + ret = get_phys_addr_nogpc(env, ptw, address, access_type, 0, result, fi); /* If S1 fails, return early. */ if (ret) { @@ -3339,7 +3339,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, cacheattrs1 = result->cacheattrs; memset(result, 0, sizeof(*result)); - ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, result, fi); + ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, 0, result, fi); fi->s2addr = ipa; /* Combine the S1 and S2 perms. */ @@ -3406,7 +3406,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { @@ -3547,7 +3547,8 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - if (get_phys_addr_nogpc(env, ptw, address, access_type, result, fi)) { + if (get_phys_addr_nogpc(env, ptw, address, access_type, + memop, result, fi)) { return true; } if (!granule_protection_check(env, result->f.phys_addr, @@ -3568,7 +3569,8 @@ bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, .in_mmu_idx = mmu_idx, .in_space = space, }; - return get_phys_addr_nogpc(env, &ptw, address, access_type, result, fi); + return get_phys_addr_nogpc(env, &ptw, address, access_type, + memop, result, fi); } bool get_phys_addr(CPUARMState *env, vaddr address, From patchwork Sun Oct 13 22:12:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835107 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1735967wrd; Sun, 13 Oct 2024 15:18:10 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWiM2bHw7SPhLEQcwLPy47IW1Pmvr6UuvMmKaFJGE+EAUQohJobTONRcesaCZ71kAGzTCoOJw==@linaro.org X-Google-Smtp-Source: AGHT+IF5sdCOLU0ZDRxXUa7/hnityjsVmoxIwG2hqkBX8K5p5S/QoXorpT96qcd34eok0WMDxb1t X-Received: by 2002:ac8:7c46:0:b0:458:2b69:9496 with SMTP id d75a77b69052e-4604bc2ddd3mr155520671cf.38.1728857889990; Sun, 13 Oct 2024 15:18:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728857889; cv=none; d=google.com; s=arc-20240605; b=HMZneEeROu360T5f/PhQanQ50JGckuhkCCMj28Tgrx3edvHXXXF5PTR5GeO0f0lfye 9xyV5IVH+PccdQMrMNnsWyVL3dc/7PN6Cwc2UeKBZVSih04RqsJdFPh/MmULhYCJLUj+ jQbRhvkshdjtnlbH9qtmxBgK6abDG9jBYBYvaKtZng79pASvY+BZOyFxnEZtcvAMptw0 nkgcH3JLRa3EKbN5FLrRda1g021/EJNQo1xnOLTq/O8IbF040k/uTy6WW9gFlFzhyixU gW3ZlLD4dO58nwHAsxPfwvn3+6sJ8xymZ2yuJ4PgPxHqVdWEXZlV0aq0GZ3ssME6l1N8 5o5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nPsGlRApUHllpr7HECmYu85LwKI3gq1PeB/gQzKhtMY=; fh=jPrxLhM/2+ATb52kRFb3bxuZkptRVHP7DuqEwlo+BX0=; b=UQqAbR9dGzzJ4W3oc8m/IH4aUnvhzamQ3xVrB8eCwkHO2QOANQlxPthGFRv6yEo5/Z 7t9HFHh59kzzcsX6XZZ8DwhlGRT8v2IFNA2NTNEgrfMEtoSyQFtNrYdZ+DIfC2KB0/e+ GqD/Sr1glq/CmV+VC3bvu3VqYoGaEYJq9dbam+hajbFsP3Var4PSwX6hMt7gDtvLcB9E Yzq9NJTyjAwiF396jGI779AJylEeCJYmHEVbxVRWoaIPxFv407eGNO2Yr01v5U+DJTMl LiVJzxLl8dHCnL69LT85tKPwd4LNp+Dpu9U+xZc/9Trk3RQz1MMQn93qI7lm4SBwc6Pn ZEOg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a5eVqYWv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PULL 23/27] target/arm: Pass MemOp through get_phys_addr_twostage Date: Sun, 13 Oct 2024 15:12:31 -0700 Message-ID: <20241013221235.1585193-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass memop through get_phys_addr_twostage with its recursion with get_phys_addr_nogpc. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0445c3ccf3..f1fca086a4 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3301,7 +3301,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, vaddr address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { @@ -3313,7 +3313,8 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ARMSecuritySpace ipa_space; uint64_t hcr; - ret = get_phys_addr_nogpc(env, ptw, address, access_type, 0, result, fi); + ret = get_phys_addr_nogpc(env, ptw, address, access_type, + memop, result, fi); /* If S1 fails, return early. */ if (ret) { @@ -3339,7 +3340,8 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, cacheattrs1 = result->cacheattrs; memset(result, 0, sizeof(*result)); - ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, 0, result, fi); + ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, + memop, result, fi); fi->s2addr = ipa; /* Combine the S1 and S2 perms. */ @@ -3469,7 +3471,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, if (arm_feature(env, ARM_FEATURE_EL2) && !regime_translation_disabled(env, ARMMMUIdx_Stage2, ptw->in_space)) { return get_phys_addr_twostage(env, ptw, address, access_type, - result, fi); + memop, result, fi); } /* fall through */ From patchwork Sun Oct 13 22:12:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835094 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1735090wrd; Sun, 13 Oct 2024 15:14:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXcO8BPQIkndkhDh86GNsu7m0UAtFBS6x/Hb7IF3ZWovf+7a+VSUQ2pnF5Zv9HzU6dXL9Jjmw==@linaro.org X-Google-Smtp-Source: AGHT+IEWU0B7t1l4rvCs6+KyAzhQuFg8+O2PkgP57mWyYuKEYzjWnqdDqO68+Y2d3ZMVDFXihMZu X-Received: by 2002:a05:6214:2f0b:b0:6cb:e5ba:310b with SMTP id 6a1803df08f44-6cbeff4f94dmr166391536d6.19.1728857684819; Sun, 13 Oct 2024 15:14:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728857684; cv=none; d=google.com; s=arc-20240605; b=BRsLY9+zw50ODBiwMyc7bUdX3Qb6uxHSCnFER2pwvvMeSvOYNpEfSbkE/rpRNtqZLG gW95H/Rj1p5NS/GgCHlVMvLB0dd9XkPOgQMd04pazMQablT1f894FbueEIJ2onWT2g6l vaGpEFalwlt1sH6wjiuN2C2t2WwphoraZw0Gw8JFDA6bCoalfymis0gIUoBJ0Jvw9yGq KbEOQEPouSqoeWZPPrcmOs/WcuwW9yCFoJJ/h3dvh12K9i+L75/Yg6Ys+GJM+Y9dWwLR fFedFnFXPkJRL6ckcmwuUiX1UsNkLtUqgaLoI12Tsid5bVBWr8zzFq0ftWwKWTqC0gzH MrYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zDNpltdoK5BIHBCpA0bLYhC/fVRvo8Z+4KE41wqkR3g=; fh=jPrxLhM/2+ATb52kRFb3bxuZkptRVHP7DuqEwlo+BX0=; b=KF9hWHkAV7TZuRgLYxOqr5DIKotWlshTM91naSLrdidOITLi5c2U6YVxyo+9db50wg BSwWR4hh8xo96idRzhRyGabMTgx4H0SLVYzYRLspsqkBjSxzpw+waFoEgEiMkJwpcGN/ XrlskEjlby4gBTl4OQje9flNkgOyfAM6Zd7/p95A/r3Lp1MSZDzwgw6KYzd1fZ+xkv8a V+03cEBj8ghjx6jeMoJiGHH8GNjTvb03dL82pSLDequu7rjBB3uCkzEOztDuQcOKUlYZ Lq8Ydt4lfxHyXpTxmdI/0e0MxyMwtbl1Rb20wL40YKfsJciFX03bqzSmBwAw+Ps2BG0S cR6w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A5xhuLMD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PULL 24/27] target/arm: Pass MemOp to get_phys_addr_lpae Date: Sun, 13 Oct 2024 15:12:32 -0700 Message-ID: <20241013221235.1585193-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass the value through from get_phys_addr_nogpc. Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index f1fca086a4..238b2c92a9 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1684,12 +1684,13 @@ static bool nv_nv1_enabled(CPUARMState *env, S1Translate *ptw) * @ptw: Current and next stage parameters for the walk. * @address: virtual address to get physical address for * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH + * @memop: memory operation feeding this access, or 0 for none * @result: set on translation success, * @fi: set to fault info if the translation fails */ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t address, - MMUAccessType access_type, + MMUAccessType access_type, MemOp memop, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); @@ -3534,7 +3535,8 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, } if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, ptw, address, access_type, result, fi); + return get_phys_addr_lpae(env, ptw, address, access_type, + memop, result, fi); } else if (arm_feature(env, ARM_FEATURE_V7) || regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, ptw, address, access_type, result, fi); From patchwork Sun Oct 13 22:12:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835113 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1736568wrd; Sun, 13 Oct 2024 15:20:47 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWQ/gWKe08d6vwELAnpZmQkcaucasLOkhVTQRNjfWkekHF9QaiL0Yo1IcMkZC7k2ogAuWPjqQ==@linaro.org X-Google-Smtp-Source: AGHT+IFPOruxpZia/hHdvGMTYq0yiSB+qC0sBBklauP9AKG62xXGP7/Yuwi1TKD1cJikR52jlfaB X-Received: by 2002:a05:620a:4727:b0:7a9:b0b5:af4 with SMTP id af79cd13be357-7b11a3bcd5dmr1503653585a.41.1728858047245; Sun, 13 Oct 2024 15:20:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728858047; cv=none; d=google.com; s=arc-20240605; b=EnfJbIrsnlDScGZG9g9Lvr62UUiA+QYBTivDk8oxwCGp+8r8Nu5tbpQhtEZF3LKUqL Xr+j1aeWHeJBzS/FEA/yaGJL32s8D01ufQuVvFMrEM+mlJMV0ybKjiYJVFp1Qkwpz8/P Tiwld0T3rGF9UU6i2cMZVQDeFU63aVfakxygIC4K4jfwzPlFIu0K9a64PhG4Y+8ijlKz rKh4g+jzgHg+8eOK/gOR+LKXQ9N5PAb2IJTZk3UuAYWYbDhlEXI9VBjgqszjGhibAHJ9 plBJEZAoOs7E0Ei1kS7q+fr32o6KmBnp1PVrIkf6PymXtrbGfzaeKsrRGIspBowT29FQ UJBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oOELs1GBJLtlq8nQGFT7BbF8Y02om3aScvqBsVkX7+Q=; fh=tOREyZHlK9Diwyw/7bj5IUyLT4I5EVkj5DE8XDtMiTs=; b=MJqUTg+vttkDksQswLEzTBhx7QZgvMHUz3fNdwPUOcc779pb4IaAifP+uY+tDk5hY9 U+7V9nudDC/Yu3yrCxKEn8P4QKdTrhyJsiqknQoWVFccOdEINDp+N/TtluBViReWeSRN Q4dhdMHfEkfLWgryj3FNyW5YXCRo3asoZsNEoIMo64V8hE2sGtftlU2KcyElLkrH92tG roddUH3c5gCk3hoZDr8DKxzWCz9EEkMOHe931uIyUMNgduyIw9ZDmlxkm0DM9LVbMhQy xvIlYAz6VJjRhm+QOl/tsGzpLOYhkjCu+tq6caoEgiDqhFGxkDoL+arjCsjainVQrRxT 9piw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=t1H7PVN6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:12:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 25/27] target/arm: Move device detection earlier in get_phys_addr_lpae Date: Sun, 13 Oct 2024 15:12:33 -0700 Message-ID: <20241013221235.1585193-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Determine cache attributes, and thence Device vs Normal memory, earlier in the function. We have an existing regime_is_stage2 if block into which this can be slotted. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 49 ++++++++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 238b2c92a9..0a1a820362 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2029,8 +2029,20 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, xn = extract64(attrs, 53, 2); result->f.prot = get_S2prot(env, ap, xn, ptw->in_s1_is_el0); } + + result->cacheattrs.is_s2_format = true; + result->cacheattrs.attrs = extract32(attrs, 2, 4); + /* + * Security state does not really affect HCR_EL2.FWB; + * we only need to filter FWB for aa32 or other FEAT. + */ + device = S2_attrs_are_device(arm_hcr_el2_eff(env), + result->cacheattrs.attrs); } else { int nse, ns = extract32(attrs, 5, 1); + uint8_t attrindx; + uint64_t mair; + switch (out_space) { case ARMSS_Root: /* @@ -2102,6 +2114,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, */ result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, xn, pxn, result->f.attrs.space, out_space); + + /* Index into MAIR registers for cache attributes */ + attrindx = extract32(attrs, 2, 3); + mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; + assert(attrindx <= 7); + result->cacheattrs.is_s2_format = false; + result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); + + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { + result->f.extra.arm.guarded = extract64(attrs, 50, 1); /* GP */ + } + device = S1_attrs_are_device(result->cacheattrs.attrs); } if (!(result->f.prot & (1 << access_type))) { @@ -2131,30 +2156,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, result->f.attrs.space = out_space; result->f.attrs.secure = arm_space_is_secure(out_space); - if (regime_is_stage2(mmu_idx)) { - result->cacheattrs.is_s2_format = true; - result->cacheattrs.attrs = extract32(attrs, 2, 4); - /* - * Security state does not really affect HCR_EL2.FWB; - * we only need to filter FWB for aa32 or other FEAT. - */ - device = S2_attrs_are_device(arm_hcr_el2_eff(env), - result->cacheattrs.attrs); - } else { - /* Index into MAIR registers for cache attributes */ - uint8_t attrindx = extract32(attrs, 2, 3); - uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; - assert(attrindx <= 7); - result->cacheattrs.is_s2_format = false; - result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); - - /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { - result->f.extra.arm.guarded = extract64(attrs, 50, 1); /* GP */ - } - device = S1_attrs_are_device(result->cacheattrs.attrs); - } - /* * Enable alignment checks on Device memory. * From patchwork Sun Oct 13 22:12:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835097 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1735354wrd; Sun, 13 Oct 2024 15:15:49 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUY9NJvKSfSbdOTNgiFgSntXMX9lFrVG6n2XDVDk/kyzujFNStVJaoTWcycKfMO2AShPRaSLA==@linaro.org X-Google-Smtp-Source: AGHT+IH7Wmuvsc6G2jQVnxErtjeK39anZdNe0Z1FwPXFrxuBplYvmYS/n8k88L4FR+iPn4rhIbNa X-Received: by 2002:a05:622a:258d:b0:460:3ccb:75ed with SMTP id d75a77b69052e-4604bc4939emr149818881cf.52.1728857749274; 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:13:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 26/27] target/arm: Implement TCGCPUOps.tlb_fill_align Date: Sun, 13 Oct 2024 15:12:34 -0700 Message-ID: <20241013221235.1585193-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Fill in the tlb_fill_align hook. Handle alignment not due to memory type, since that's no longer handled by generic code. Pass memop to get_phys_addr. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 6 ++--- target/arm/cpu.c | 2 +- target/arm/tcg/cpu-v7m.c | 2 +- target/arm/tcg/tlb_helper.c | 49 ++++++++++++++----------------------- 4 files changed, 24 insertions(+), 35 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a6088d551c..299a96a81a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -816,9 +816,9 @@ void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr, MMUAccessType access_type, uintptr_t ra); #else -bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool arm_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t ra); #endif static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 19191c2391..1320fd8c8f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2663,7 +2663,7 @@ static const TCGCPUOps arm_tcg_ops = { .record_sigsegv = arm_cpu_record_sigsegv, .record_sigbus = arm_cpu_record_sigbus, #else - .tlb_fill = arm_cpu_tlb_fill, + .tlb_fill_align = arm_cpu_tlb_fill_align, .cpu_exec_interrupt = arm_cpu_exec_interrupt, .cpu_exec_halt = arm_cpu_exec_halt, .do_interrupt = arm_cpu_do_interrupt, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 5496f14dc1..58e54578d6 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -242,7 +242,7 @@ static const TCGCPUOps arm_v7m_tcg_ops = { .record_sigsegv = arm_cpu_record_sigsegv, .record_sigbus = arm_cpu_record_sigbus, #else - .tlb_fill = arm_cpu_tlb_fill, + .tlb_fill_align = arm_cpu_tlb_fill_align, .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, .cpu_exec_halt = arm_cpu_exec_halt, .do_interrupt = arm_v7m_cpu_do_interrupt, diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 1d8b7bcaa2..8841f039bc 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -318,14 +318,13 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } -bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool arm_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr address, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t ra) { ARMCPU *cpu = ARM_CPU(cs); GetPhysAddrResult res = {}; ARMMMUFaultInfo local_fi, *fi; - int ret; /* * Allow S1_ptw_translate to see any fault generated here. @@ -339,37 +338,27 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } /* - * Walk the page table and (if the mapping exists) add the page - * to the TLB. On success, return true. Otherwise, if probing, - * return false. Otherwise populate fsr with ARM DFSR/IFSR fault - * register format, and signal the fault. + * Per R_XCHFJ, alignment fault not due to memory type has + * highest precedence. Otherwise, walk the page table and + * and collect the page description. */ - ret = get_phys_addr(&cpu->env, address, access_type, 0, - core_to_arm_mmu_idx(&cpu->env, mmu_idx), - &res, fi); - if (likely(!ret)) { - /* - * Map a single [sub]page. Regions smaller than our declared - * target page size are handled specially, so for those we - * pass in the exact addresses. - */ - if (res.f.lg_page_size >= TARGET_PAGE_BITS) { - res.f.phys_addr &= TARGET_PAGE_MASK; - address &= TARGET_PAGE_MASK; - } - + if (address & ((1 << memop_alignment_bits(memop)) - 1)) { + fi->type = ARMFault_Alignment; + } else if (!get_phys_addr(&cpu->env, address, access_type, memop, + core_to_arm_mmu_idx(&cpu->env, mmu_idx), + &res, fi)) { res.f.extra.arm.pte_attrs = res.cacheattrs.attrs; res.f.extra.arm.shareability = res.cacheattrs.shareability; - - tlb_set_page_full(cs, mmu_idx, address, &res.f); + *out = res.f; return true; - } else if (probe) { - return false; - } else { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - arm_deliver_fault(cpu, address, access_type, mmu_idx, fi); } + if (probe) { + return false; + } + + /* Now we have a real cpu fault. */ + cpu_restore_state(cs, ra); + arm_deliver_fault(cpu, address, access_type, mmu_idx, fi); } #else void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, From patchwork Sun Oct 13 22:12:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835111 Delivered-To: patch@linaro.org Received: by 2002:adf:b352:0:b0:37d:45d0:187 with SMTP id k18csp1736550wrd; Sun, 13 Oct 2024 15:20:44 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXRVfkX15QE2bd7vV9UcIq2q73baCSNQbkUrlAGDq63BN/QvlTuRwR1ZUgfb7ErFBz6ZTbazQ==@linaro.org X-Google-Smtp-Source: AGHT+IGNlnJf8wryTXOgic09s/crim2AJT6PEMzdbPF4PyK4mxzEfxNEeNO7prnNjcY8ToLlNzUM X-Received: by 2002:ac8:7d47:0:b0:458:611b:ac34 with SMTP id d75a77b69052e-4604b27301cmr160513511cf.12.1728858044327; Sun, 13 Oct 2024 15:20:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728858044; cv=none; d=google.com; s=arc-20240605; b=Pwrz08x2FQwqTSpagmIjECJR+jDhV/dQ8bwVYejels4JX1o3CViGRIfaTl2zrqRzxf ikYw1QaKAyr9rAFastxJWmJMGcTHdMLDrTi2zgWueAJ5hfO03/20dEQ/B6eo1NwCwp2R XnJt/M9vq2sxlhANulpwMh0XSydwSEc1UOVTQckPgp+Vkv5dO/wmDELYWQAcDZqF9BhJ wKB5Utxc3391fa2eZ9baIEXBeyCDkNh0FuyDdYBwgm1JR/1VYb8l4WelQ46Yo5q5uGMg lHXqcZpNJIFrhnPa+zIZJ/igJyKnUQ+IhLKMNWRYhgDt66TvJBawSwuZ/6SnenWGOf55 WGFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=G2SEeBS4yBn5Ue1nQmA6MrWE5kNjL002NNNwwbKYNls=; fh=tOREyZHlK9Diwyw/7bj5IUyLT4I5EVkj5DE8XDtMiTs=; b=itCRXZeatt31Sn4AvTzbxMR896TDbi4c/4eGjaNBJC8xXGg/jAQ3pmIIsiriJVGMen y6AjUU2vLtkpB5COkrw8jjxXxEQfEGUYzaAtJvbRsGRu+QIpnJskonockUh7wfXXCWte YaXVdnwXOxnl463fIG7Pa0quisx+JRyV3XkfMqCMgbOalChE8sltZm562nXgdNYwXqBy o+PjasQe3qkU43fKEB+PlG5BVnY7TOsPwe+Xcm3iLeB91Fyz+DACQGQ2GUvpOh6bk40r SwSw0vdm1z/Y33RLeagoVsw3BccX3lDaWOA2I//jEeqA4hiBgpPC6EdkYNq2jUHp/WpI Gacg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="r/EMBe5s"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1eebsm7271958a91.17.2024.10.13.15.13.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 15:13:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 27/27] target/arm: Fix alignment fault priority in get_phys_addr_lpae Date: Sun, 13 Oct 2024 15:12:35 -0700 Message-ID: <20241013221235.1585193-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org> References: <20241013221235.1585193-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that we have the MemOp for the access, we can order the alignment fault caused by memory type before the permission fault for the page. For subsequent page hits, permission and stage 2 checks are known to pass, and so the TLB_CHECK_ALIGNED fault raised in generic code is not mis-ordered. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 51 ++++++++++++++++++++++++++++-------------------- 1 file changed, 30 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0a1a820362..dd40268397 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2129,6 +2129,36 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, device = S1_attrs_are_device(result->cacheattrs.attrs); } + /* + * Enable alignment checks on Device memory. + * + * Per R_XCHFJ, the correct ordering for alignment, permission, + * and stage 2 faults is: + * - Alignment fault caused by the memory type + * - Permission fault + * - A stage 2 fault on the memory access + * Perform the alignment check now, so that we recognize it in + * the correct order. Set TLB_CHECK_ALIGNED so that any subsequent + * softmmu tlb hit will also check the alignment; clear along the + * non-device path so that tlb_fill_flags is consistent in the + * event of restart_atomic_update. + * + * In v7, for a CPU without the Virtualization Extensions this + * access is UNPREDICTABLE; we choose to make it take the alignment + * fault as is required for a v7VE CPU. (QEMU doesn't emulate any + * CPUs with ARM_FEATURE_LPAE but not ARM_FEATURE_V7VE anyway.) + */ + if (device) { + unsigned a_bits = memop_atomicity_bits(memop); + if (address & ((1 << a_bits) - 1)) { + fi->type = ARMFault_Alignment; + goto do_fault; + } + result->f.tlb_fill_flags = TLB_CHECK_ALIGNED; + } else { + result->f.tlb_fill_flags = 0; + } + if (!(result->f.prot & (1 << access_type))) { fi->type = ARMFault_Permission; goto do_fault; @@ -2156,27 +2186,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, result->f.attrs.space = out_space; result->f.attrs.secure = arm_space_is_secure(out_space); - /* - * Enable alignment checks on Device memory. - * - * Per R_XCHFJ, this check is mis-ordered. The correct ordering - * for alignment, permission, and stage 2 faults should be: - * - Alignment fault caused by the memory type - * - Permission fault - * - A stage 2 fault on the memory access - * but due to the way the TCG softmmu TLB operates, we will have - * implicitly done the permission check and the stage2 lookup in - * finding the TLB entry, so the alignment check cannot be done sooner. - * - * In v7, for a CPU without the Virtualization Extensions this - * access is UNPREDICTABLE; we choose to make it take the alignment - * fault as is required for a v7VE CPU. (QEMU doesn't emulate any - * CPUs with ARM_FEATURE_LPAE but not ARM_FEATURE_V7VE anyway.) - */ - if (device) { - result->f.tlb_fill_flags |= TLB_CHECK_ALIGNED; - } - /* * For FEAT_LPA2 and effective DS, the SH field in the attributes * was re-purposed for output address bits. The SH attribute in