From patchwork Wed Oct 16 19:31:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835829 Delivered-To: patch@linaro.org Received: by 2002:a5d:6804:0:b0:37d:45d0:187 with SMTP id w4csp604521wru; Wed, 16 Oct 2024 12:35:20 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV6eHt/+O8NDjtYqlMKe92TseOGmclLPhehKSr43OZg1kvCsNZSgpQBO4xb+YHzg4kx0eObtA==@linaro.org X-Google-Smtp-Source: AGHT+IEYcs3p0SCGMt9EEhU3qvczWOT48IZErZI2CIXVMjKIjv+8WemiPp7GxEKdKfYwxgwVh2QX X-Received: by 2002:a05:622a:5c91:b0:458:4c4f:8088 with SMTP id d75a77b69052e-4608a4a6c01mr81045631cf.17.1729107319703; Wed, 16 Oct 2024 12:35:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729107319; cv=none; d=google.com; s=arc-20240605; b=Y5Gxn3b1KYtOdXG0ZcnJaBDxf5gH2rzaWbgy7DvxHdsGtmkG20ay0Wj2CPVcL53gvX +BOsfSEu18B5bS3068X34ClrdtfRq1qsMuy57P0alu6LVuHe0xjlX6MGQpLZ2WHXwzp+ nZ9oeSfoneukWXFL8HQyD7P8QsUSimXVsiwbGTTcTiEifIlN+cofEwmKPe/+ENqW2uU4 3UwkNKLBNh4j79/TqAaVzhv4yp+jtflfIcBaVFXbOeR6hIro1CbjwCZJidLO7qUE+dK4 QSniP1FHrSfkE0lwiBRoswzV4NiUrcC6NJ1ZAYaTka6zLBiT4+maCsrTbyQuHzWMe7R/ 8G8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=pAS56LpJLEvFceTFCBsO+yMHFwJ+VtaFv7L9YjE7ffs=; fh=JWUledwuIo29+yfO5j5zISL7nuTrlt+PJUK+0FeRjh4=; b=D3nHvK8qFCmKIfE1bXMOIS0Ix+Qn4CBzjyKjP/UD03WC6LPhSuzbIPEzachDaibdY8 RREgBIhqxkETSsLq19DTdjyWU/n5u+5+e13yeakRyxkDEuKGfSbowAKOSM4SGSQG34Wr LHZF2KJBRojFEto05aYJZksNMruNJ6lBSnYlm4mUZPCtYdYkY3/Oh9j1+6OcujGFAeNO XD/xAXo66sJpCS6jG51MjuTcyxxW8ini+HmJgjs6TcN8hi55gsVyroB8fQXEuHLbmtds OvCR9ZX+4dWNz7UzbdtELheOCHY4Ik5yURTlmHGgYTDzi3JgwFwzgA9U3RJAIfgId2VK Vgpg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OSvF6fMo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4607b0eda35si45956411cf.72.2024.10.16.12.35.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2024 12:35:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OSvF6fMo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t19kL-0002di-67; Wed, 16 Oct 2024 15:31:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t19kI-0002cZ-N5 for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:46 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t19kF-0003nJ-JK for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:46 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-208cf673b8dso1747495ad.3 for ; Wed, 16 Oct 2024 12:31:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729107102; x=1729711902; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pAS56LpJLEvFceTFCBsO+yMHFwJ+VtaFv7L9YjE7ffs=; b=OSvF6fMopQgsmWmUSA1xiO/3gUZlMxSse5XxAPZAbgtx4sOFZHk5H97BEPKWyKShSS 71tTJIzSEn8cIuDvk+gKqdOCrYDCXGDzvfhc7siB8EaeoJ0naaAAcDRxEAwYPwPUeGpe B34FAsMFA+QyXXNHlx3Tyhj6xTRX99/YisLQT5wo836Q8QfpjP1eIIwarr3sOHz8VWNz Vv1/zcWifzEw3ROTqUFX1Moi23qAGtyZqauSZBN48hODn+NEuZfYPktrpX+tqL881fPt SLQKezYzN7vxMjV8hltQPh438vsPyuOi9EiXaADJgCRQvIAbVzPP++ce+c/gaqqOps0v vWtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729107102; x=1729711902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pAS56LpJLEvFceTFCBsO+yMHFwJ+VtaFv7L9YjE7ffs=; b=V0k35BOwbB2Rnm/QEIDsXK2EIyzFWnrMmW/qKsxfXz/6VxGGpgpvxtUnbnrwGtAxMu eBEprxnBRPJO+eQNOvE8wy9CZvpH7l+3Wp6gqMfYK786q4gXIFvprVIjhuHzdwdjTx4w a4jaMOUFI3T8e6rtRZzJGaWevgZQeZkC7LQSq5kyAxhtwt4Qx2T8My+mz+kJ0Z+J2Jyw 0mDttyFdoYEUW8PqIDlI3n3h50secODq67EzsFVt+YbGZntDxJ+gTYBmw+8vxPSpxj1K Aah8f4NGB22IiT0bslxNYOvXxfLoCLbgF/8cuOeXUB9DTBv6DE4GAkqKguXYvDlU4MtG eLlA== X-Gm-Message-State: AOJu0Yye0chYvJUrsXMxye/78OKRDXRuc1ZZdYtkiE59jOBX59vaMf9Q mc98gpTIfy7CZpRg6IBiUraxfKGI5XMwC5ErFbQsaSzrnDeFiOlBzHIvlKNij49CAO2aqpjhGWv W X-Received: by 2002:a17:903:1c9:b0:20c:9d8d:1f65 with SMTP id d9443c01a7336-20d27ef315dmr71489035ad.30.1729107102081; Wed, 16 Oct 2024 12:31:42 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b6b1sm32323945ad.189.2024.10.16.12.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2024 12:31:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, zhiwei_liu@linux.alibaba.com, qemu-stable@nongnu.org Subject: [PATCH v6 01/14] tcg: Reset data_gen_ptr correctly Date: Wed, 16 Oct 2024 12:31:27 -0700 Message-ID: <20241016193140.2206352-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241016193140.2206352-1-richard.henderson@linaro.org> References: <20241016193140.2206352-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This pointer needs to be reset after overflow just like code_buf and code_ptr. Cc: qemu-stable@nongnu.org Fixes: 57a269469db ("tcg: Infrastructure for managing constant pools") Signed-off-by: Richard Henderson Acked-by: Alistair Francis Reviewed-by: Pierrick Bouvier Reviewed-by: LIU Zhiwei --- tcg/tcg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 5decd83cf4..0babae1b88 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1399,7 +1399,6 @@ TranslationBlock *tcg_tb_alloc(TCGContext *s) goto retry; } qatomic_set(&s->code_gen_ptr, next); - s->data_gen_ptr = NULL; return tb; } @@ -6172,6 +6171,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) */ s->code_buf = tcg_splitwx_to_rw(tb->tc.ptr); s->code_ptr = s->code_buf; + s->data_gen_ptr = NULL; #ifdef TCG_TARGET_NEED_LDST_LABELS QSIMPLEQ_INIT(&s->ldst_labels); From patchwork Wed Oct 16 19:31:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835820 Delivered-To: patch@linaro.org Received: by 2002:a5d:6804:0:b0:37d:45d0:187 with SMTP id w4csp603839wru; Wed, 16 Oct 2024 12:33:32 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXZwZc70cSi4cwTHO6rMCQx2UJoqX3b7rVEn6gMUNzfEz4qNAXJTW7e/FbZNcFK505OTA1cYA==@linaro.org X-Google-Smtp-Source: AGHT+IHi7Qa/GKv/T2+bdGjen++3vWBJECpNBD/lf9pgOsWpm9o8oTL+MWQHqrKKaWPJM5tg5k44 X-Received: by 2002:a05:622a:1c1b:b0:458:294c:39e3 with SMTP id d75a77b69052e-4605823f354mr288836061cf.0.1729107212007; Wed, 16 Oct 2024 12:33:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729107211; cv=none; d=google.com; s=arc-20240605; b=X2WnjmM9dZGbi16r19YG91iU2MOnTYNuE6oEj00gfriVhKSqyGbceG2RrE1a/gWpYV lGl1UPmUcy1SQiibFxs5lKsdaiQUPB8L4yXeAzLwPoYu916jt0C+gTAEu4GEJRuTtCfH MsgnjWe0KfxBgzVo8t8D83WHPjLMopiyzFOmnxLJVHKHjFThHwdBS/aircyy4ZVxX7Q2 jiijzuTG3iWTI4TeBhxDUT+C3O4zcohcTjEFEJ1c+gihtDOvBUnDP0cenatrmWVsw51r jDH4KyHIFHKAPexXBE7Up81v4eJ0YjdeuPKIQgkxvhFbg1EvG/bKMTAUYwURgVoID3BW JkVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hvpTPvpHazkQ0TVI9JimtqNfgw0t+6U1n7b/YyBhtQ4=; fh=q+UmP8eaNSfHMVi/tLyu+bWaEagrVMJ4PiBhkooBLxQ=; b=Bkq3KqXB5gfsp/b5Q+4xW091eBcOMpKvpUze4Riz3JMqCQEUKtytdjifVu/FgF8Wgi Headov6fs22vk7BUyfpcCONkqKGeX20xwHg7YQmbmMS5WsDSMOe35ocZy49RWWbrCFC8 NOp6XwWOMM1DdALVHDF/1sj8Q6xl2RDjZF+JVRFQwi0aYjOJP9QarOu5IKOr5uobeTXP q3c5/4hFug19bD18gQ7fZIyMFTOHkcyD2K+fL30400TFEt2i/DOBJfAVVlto77Db32lM X0tn5vibVt641SV7svYjMXh9UpqIwrww3cAMDPr9T3Maiq0SmpqcW14UU59wcmoMEO7C M7Ig==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iCKE+s4o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4607b4e7048si42397881cf.701.2024.10.16.12.33.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2024 12:33:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iCKE+s4o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t19kM-0002fs-8A; Wed, 16 Oct 2024 15:31:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t19kI-0002cc-Pw for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:47 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t19kG-0003nU-7m for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:46 -0400 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-2e3010478e6so143455a91.1 for ; Wed, 16 Oct 2024 12:31:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729107103; x=1729711903; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hvpTPvpHazkQ0TVI9JimtqNfgw0t+6U1n7b/YyBhtQ4=; b=iCKE+s4oHkOGdCICtWWhn1yK/uyDLV7FssOUP1YjQL7QsvBI9VbpBHoWFSa+MGAwc/ D3C4qq1p6kk5uW5Y00O5++C8cQ8cjF4E1dbfCt7uWZ7qHVU0HWFOOAL655/pW/WsazbO XJHy57/Gny9mmW2e1B20oIPxDvWQa5ufHlk9S8YAmdCRLQtfgu55Va685oNn9J+xGkU7 fdgGjZqegqVTl8TttEdrRqmKrDSFzYTYH7cR0rJtpb6Dh34R5pAlq/rMJRRfX21Bcj+L LqjV76m5ajxJmvHrEy770XGbnQr+qulozAyd01zCbk1Sox77OUAKhZCRgrLkHs5lxIZ9 6hag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729107103; x=1729711903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hvpTPvpHazkQ0TVI9JimtqNfgw0t+6U1n7b/YyBhtQ4=; b=u27m98U5RxFY0k12d765zjON5ns6mLkI35glcKKX5Y/OPVIaQb9DVPP89qY6xZjaKA iHOssT6PtT6QKvoR8SpiMWfqejFV1syueDvF2XrLa6Z9FqZxvOF04MY89o4GC6wVnULM 2vxmsApNXwp22hj3hH0G7aMwoGSIp14tKVSUnOuEmdHkml/OTaRKaWfzp0oszzR4pPRV blXFkaxedaO7G/VMuxybkbFrmf8BUWpOaWVD1HPmUkFOBKnHunCZ3CRs9DH8x/pH/2Qn M9xAoGu4Gcu2pjYdLuCOlMGB8DlvJuW7YYzl7wj3NrcPF82tGFUqtz4iFdRuyTcxi0kV W17A== X-Gm-Message-State: AOJu0YyWbaeFWbHi0lHV3I4KmnJrVH8TnnicLCBPF4qut7H9mwoapOEo hr8zt3Yp7k7bbxfZOZUgjm4dEBZAmXSP4V7ox4xqIqZmWKJq0+E5t+Y9JMdE6h6WjtD4lcNsp8X 6 X-Received: by 2002:a17:90b:1215:b0:2e0:894f:198e with SMTP id 98e67ed59e1d1-2e315357b40mr21424498a91.30.1729107102699; Wed, 16 Oct 2024 12:31:42 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b6b1sm32323945ad.189.2024.10.16.12.31.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2024 12:31:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, zhiwei_liu@linux.alibaba.com Subject: [PATCH v6 02/14] disas/riscv: Fix vsetivli disassembly Date: Wed, 16 Oct 2024 12:31:28 -0700 Message-ID: <20241016193140.2206352-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241016193140.2206352-1-richard.henderson@linaro.org> References: <20241016193140.2206352-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The first immediate field is unsigned, whereas operand_vimm extracts a signed value. There is no need to mask the result with 'u'; just print the immediate with 'i'. Fixes: 07f4964d178 ("disas/riscv.c: rvv: Add disas support for vector instructions") Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Pierrick Bouvier Reviewed-by: LIU Zhiwei --- disas/riscv.h | 2 +- disas/riscv.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/disas/riscv.h b/disas/riscv.h index 16a08e4895..0d1f89ce8a 100644 --- a/disas/riscv.h +++ b/disas/riscv.h @@ -290,7 +290,7 @@ enum { #define rv_fmt_fd_vs2 "O\t3,F" #define rv_fmt_vd_vm "O\tDm" #define rv_fmt_vsetvli "O\t0,1,v" -#define rv_fmt_vsetivli "O\t0,u,v" +#define rv_fmt_vsetivli "O\t0,i,v" #define rv_fmt_rs1_rs2_zce_ldst "O\t2,i(1)" #define rv_fmt_push_rlist "O\tx,-i" #define rv_fmt_pop_rlist "O\tx,i" diff --git a/disas/riscv.c b/disas/riscv.c index 5965574d87..fc0331b90b 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -4808,7 +4808,7 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa) break; case rv_codec_vsetivli: dec->rd = operand_rd(inst); - dec->imm = operand_vimm(inst); + dec->imm = extract32(inst, 15, 5); dec->vzimm = operand_vzimm10(inst); break; case rv_codec_zcb_lb: From patchwork Wed Oct 16 19:31:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835831 Delivered-To: patch@linaro.org Received: by 2002:a5d:6804:0:b0:37d:45d0:187 with SMTP id w4csp604774wru; Wed, 16 Oct 2024 12:36:00 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUDky/zqmbBI1gxgr+qulwv87L3kuHhcIKldrCTM6B1Un7rlpNm12bqg51TZZzhodA1VyTdaQ==@linaro.org X-Google-Smtp-Source: AGHT+IH3yGflbHxcDpp5vlK5BeeNE8mylLgu9sAweg90mCozxEat7OO0Qxg5SLjpKoLhm4HW1/lI X-Received: by 2002:a05:6102:3749:b0:4a4:938e:222c with SMTP id ada2fe7eead31-4a4938e23a9mr11546008137.17.1729107360432; Wed, 16 Oct 2024 12:36:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729107360; cv=none; d=google.com; s=arc-20240605; b=dbORtI/vTosWWPqhNXSC3F/q386EhS9hTrvgY+XM3HC3xUaui5vcuAmV3Xmd0ary8a HBeXb0FHFcpdsD+heA4Ef0QPegvpSH74t7GKQxfangREcbKGeSyV4GPSlRFamcK+MTmg nucGqq4vPDE0ggJZn9gxdEfCd7EsxS40x2laR5VxN7szQi8isAz+uuZIQOXC4JY/Sskt Ngt48V5a9ol/j+ADUCNDIp3OElK5di2IatO9ycuvcCAGMgqkFx6H0e4X3JFCf1NLqkcF +NBIsQqVgCvZ28bEKCh2UCHfaM39HCB/lv3d+DKa0CFqnUQnTdxrriYNOmDBD4xO4q20 5JfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=k9pm4mmiOJ3ePRNfWoDr3osUdbmj8mTSaBfTsfRhvEA=; fh=0y6cSxTabxslIGhKb2QlpT+4cpL34OsHjArvPUG+rq0=; b=kKEmJFLNC/ohCyOxy9OWr8ibu7kO13xCiAWQ3gustBdNUHsTfQwQQ6KRGxLLBIDLC7 KB64nE5TZoO/cQJBqlBjRS89Tfq4noS6v6NCl8VVXWKfbdLxQoAcwQL6d2Y4uoEDISne xhccYrcS04/384tChyd7RCFuEjtVsL7KZtS61iamEB7Ax7/zQUCEI+Z6jlvhtONQqSTA e8FU0twnY1McFL6X0PaXNhedrCCBUzXEreW6HibMLpq8HTGabbEEZtLprLVGRk62YnpH qpPnNtKAMX1o2b2Ki9O8Em6LguA125BKd0zPtJvPDSz0oA+3f+zh/8up5sbXyfG0PtfZ ThUA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H2mYNCwI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4607b4cab6dsi46396901cf.621.2024.10.16.12.36.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2024 12:36:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H2mYNCwI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t19kN-0002ft-22; Wed, 16 Oct 2024 15:31:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t19kK-0002dZ-BF for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:48 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t19kG-0003nf-NE for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:47 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-20bb39d97d1so1543885ad.2 for ; Wed, 16 Oct 2024 12:31:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729107103; x=1729711903; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=k9pm4mmiOJ3ePRNfWoDr3osUdbmj8mTSaBfTsfRhvEA=; b=H2mYNCwIjh2gWxzIwji23kcmFroPqhHUIbXVhEcdmYjmKHeEZKpXEPcXt3qSM50dUl VyPd5OefxqqwzesB0vOZOOrnqM4r37bqgu2rfqgwVXWNG3OT5vmy63bQ1KtkPoMFiTMJ zPODQEKln1nfN2OeLyUw+MZAF17ryT+KlD8R3QFH5JwheSeQepUuXwPU4w8q6gHkfKyR lb+d0tvy2LG6GnbmVl5GlMtYapRrnkD0y01NGsmqHALicH2Rw4Bb3Wlv+PHpIbw5y5pI sbZ+G6OTIGYeERAKqMfnKVGc0w9Z5vT7WDaFvwdr+TzJlQIwhdBg1M9qvqQMYFaWRZh5 Trtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729107103; x=1729711903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k9pm4mmiOJ3ePRNfWoDr3osUdbmj8mTSaBfTsfRhvEA=; b=gs2UhkyX8glUAddOCYx9ddN7JvLwfOdWzVbLaTvalNPFQ2UMZEraMpu3OVXp5st1wi iEjJ9GozbbjwPwbI3hEZdsnuKykGvv60hwwPbXF3EZJS6s1FZ77RvRMxVr8bX2gf+UTy 9CL0CtTW22FYq+7Af+/4PZ7Hqe2LH6LxdUXyiG4fUArIhwhEqDGFG0n8bpWgImhojTow ldwDADKFmum4fqSctFTwPaGhjsgWSD9uX/Rul3ilLI6QOHk7TkmzXLi1zdyGBDNl9CT4 fVPf5qFhpbA/dWV9fGYGNUq0H8fw7CIm2tgAQIJvU7ChPA9OkNra0hEWDpvKcEb4+vcm A73g== X-Gm-Message-State: AOJu0Yy1k5hUPXxCyQ9+juwBPRQ1md4Z+Ih3LXh2uIrotbmuAH3PGjVb Qqa9l3VN2+33ytLC2nHULjZJe2Zp5cTfy55ewE5Rtw7gCz1Y6X5J1STPgiMv7ckoB53rAmWWEIE S X-Received: by 2002:a17:903:2309:b0:20b:8907:b597 with SMTP id d9443c01a7336-20ca1682ab9mr258903615ad.28.1729107103360; Wed, 16 Oct 2024 12:31:43 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b6b1sm32323945ad.189.2024.10.16.12.31.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2024 12:31:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v6 03/14] util: Add RISC-V vector extension probe in cpuinfo Date: Wed, 16 Oct 2024 12:31:29 -0700 Message-ID: <20241016193140.2206352-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241016193140.2206352-1-richard.henderson@linaro.org> References: <20241016193140.2206352-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: TANG Tiancheng Add support for probing RISC-V vector extension availability in the backend. This information will be used when deciding whether to use vector instructions in code generation. Cache lg2(vlenb) for the backend. The storing of lg2(vlenb) means we can convert all of the division into subtraction. While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X, we use RISCV_HWPROBE_IMA_V instead. RISCV_HWPROBE_IMA_V is more strictly constrainted than RISCV_HWPROBE_EXT_ZVE64X. At least in current QEMU implemenation, the V vector extension depends on the zve64d extension. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Message-ID: <20241007025700.47259-2-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson Acked-by: Alistair Francis --- host/include/riscv/host/cpuinfo.h | 2 ++ util/cpuinfo-riscv.c | 24 ++++++++++++++++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cpuinfo.h index 2b00660e36..cdc784e7b6 100644 --- a/host/include/riscv/host/cpuinfo.h +++ b/host/include/riscv/host/cpuinfo.h @@ -10,9 +10,11 @@ #define CPUINFO_ZBA (1u << 1) #define CPUINFO_ZBB (1u << 2) #define CPUINFO_ZICOND (1u << 3) +#define CPUINFO_ZVE64X (1u << 4) /* Initialized with a constructor. */ extern unsigned cpuinfo; +extern unsigned riscv_lg2_vlenb; /* * We cannot rely on constructor ordering, so other constructors must diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c index 8cacc67645..16114ffd32 100644 --- a/util/cpuinfo-riscv.c +++ b/util/cpuinfo-riscv.c @@ -4,6 +4,7 @@ */ #include "qemu/osdep.h" +#include "qemu/host-utils.h" #include "host/cpuinfo.h" #ifdef CONFIG_ASM_HWPROBE_H @@ -13,6 +14,7 @@ #endif unsigned cpuinfo; +unsigned riscv_lg2_vlenb; static volatile sig_atomic_t got_sigill; static void sigill_handler(int signo, siginfo_t *si, void *data) @@ -34,7 +36,7 @@ static void sigill_handler(int signo, siginfo_t *si, void *data) /* Called both as constructor and (possibly) via other constructors. */ unsigned __attribute__((constructor)) cpuinfo_init(void) { - unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND; + unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND | CPUINFO_ZVE64X; unsigned info = cpuinfo; if (info) { @@ -50,6 +52,9 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) #endif #if defined(__riscv_arch_test) && defined(__riscv_zicond) info |= CPUINFO_ZICOND; +#endif +#if defined(__riscv_arch_test) && defined(__riscv_zve64x) + info |= CPUINFO_ZVE64X; #endif left &= ~info; @@ -65,7 +70,8 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) && pair.key >= 0) { info |= pair.value & RISCV_HWPROBE_EXT_ZBA ? CPUINFO_ZBA : 0; info |= pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0; - left &= ~(CPUINFO_ZBA | CPUINFO_ZBB); + info |= pair.value & RISCV_HWPROBE_IMA_V ? CPUINFO_ZVE64X : 0; + left &= ~(CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZVE64X); #ifdef RISCV_HWPROBE_EXT_ZICOND info |= pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICOND : 0; left &= ~CPUINFO_ZICOND; @@ -113,6 +119,20 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) assert(left == 0); } + if (info & CPUINFO_ZVE64X) { + /* + * We are guaranteed by RVV-1.0 that VLEN is a power of 2. + * We are guaranteed by Zve64x that VLEN >= 64, and that + * EEW of {8,16,32,64} are supported. + * + * Cache VLEN in a convenient form. + */ + unsigned long vlenb; + /* Read csr "vlenb" with "csrr %0, vlenb" : "=r"(vlenb) */ + asm volatile(".insn i 0x73, 0x2, %0, zero, -990" : "=r"(vlenb)); + riscv_lg2_vlenb = ctz32(vlenb); + } + info |= CPUINFO_ALWAYS; cpuinfo = info; return info; From patchwork Wed Oct 16 19:31:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835828 Delivered-To: patch@linaro.org Received: by 2002:a5d:6804:0:b0:37d:45d0:187 with SMTP id w4csp604298wru; Wed, 16 Oct 2024 12:34:43 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWnzy6So3ChCbHz9lZQXcZoWFYGJ1DrlqTl0kdDje9n1EZIARhBdtdD7PhLlKDFjg2a6A5T+A==@linaro.org X-Google-Smtp-Source: AGHT+IFJWR7COOz4E62yuvBIZ+JxAvPrUz1pw03p5P2dZTVT9o+4sEXMEzMnxeTLWqZA8lKDxBRj X-Received: by 2002:a05:6358:6f02:b0:1aa:b9f2:a0d2 with SMTP id e5c5f4694b2df-1c37840dbe5mr581746555d.10.1729107282878; Wed, 16 Oct 2024 12:34:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729107282; cv=none; d=google.com; s=arc-20240605; b=EcRqbUPf23xz8jBIymBtvLbfHdXpc/AfQh5hp8nMOaiDwVB4kUIeScCkNBe69nmBft U9lvf4c5KpzMjqgHedcvFVbZwET2ceTWIuaBgMjNZ34VcP3pHWBfnKr/VoWfrljPhWZn H2CFyhykTrY4BkqUuV6gCvXY+cYIEMEbkV2qJVuHudle+xLYGXUIRC8CMCjH6FeZhq92 mreVdgc4//6a1deaa7hrXLNreuMM8XpN/nzYZvdpI2pB0sdpJZecNdN5JAs5m+68VOLr S4YcZcgiF+55yjJggqMgXBz+46kgZ8IDmS7tXxZkspoG6RwomO55EVCI0RnZDHGa6Lbc /SSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DC9y0zX4FGXcxl44shwm/CevG9iZ9j82UlAnPEFCOs8=; fh=g/uXFTquhs+p/Lq/qFV0Mrz3QRFY547l4DMELx+lzGo=; b=jq1AmnJvrpr+tHwZOgsXC2XSkK+behYQgx/Ss4t8nv6BBLkWDoIJ/cfXRBLBum88pS T2AV3Xgs1GHCNlac76nlEWuoBmF1hqvKHCtFlrBIlKe4IUULvwBDx80bPq/tJCp/PmSc aaSimRiZBeB4gLwwzzdFy9Jo0pBaAhUhfjPlfcIn6ANVmLOQNwIESad6hbo53oJDhXQE zJtIylQdsSHXVujhu+qaBTu3NGpj6DsgVmrNTrD4uInHqDTM2eda9OMupIUJ1Bjk3u/4 3lGsuCQqMAkg2OnuhquHGAa+J/bgqIgpnSn67PWStzv4VWG9TRncicf2xg9B1Hy8ivFE OoEg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L5pwnHTj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7b148a8645esi141206485a.297.2024.10.16.12.34.42 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2024 12:34:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L5pwnHTj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t19kO-0002gx-Bj; Wed, 16 Oct 2024 15:31:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t19kL-0002ek-Dx for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:49 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t19kH-0003nw-Nq for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:49 -0400 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-2e2eba31d3aso119145a91.2 for ; Wed, 16 Oct 2024 12:31:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729107104; x=1729711904; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DC9y0zX4FGXcxl44shwm/CevG9iZ9j82UlAnPEFCOs8=; b=L5pwnHTjI3Np4MogX9KhwfquPCs1Q3bWIAak1sn017koFqWBiBXuUsxbn+1C+4BF42 XXsC/H5nFMMneOCDXJHWgKjuOeL6ltUVuTJKJGRcJfidIG0HD7TjKz5lchkTlC8JAOmI VpF3zRAKy8Kueom82mfjpSpz9Ry3nTWhbSsSIREdYN0fDLWZG2TtlzdQoGX/nS/kl4AB TB7l+IqrmW3hFpC6eDfLB4fp17m6OjsKs0JfxzyXRAdbqeuvqBdySsm90GlRaV8lRCwg A77OIJiU6BTAdqpEwhOzi4ONvAR5LkMYNl3NVZT5fY3dJ9B2Uy6e1eH8xsBcWcEgdyOC Nq0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729107104; x=1729711904; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DC9y0zX4FGXcxl44shwm/CevG9iZ9j82UlAnPEFCOs8=; b=ruxhPu7UJgtfZBkaXkmL6abaS5gTg6taQYMR9UuvbGkBzOUg7Wky8gov94A8XZdP3b 9ikt1UX6Q1GfsZ2OoUJYdrtfKa79A9E69JEROJKkztFzs0rmPrXFgtTGobOTP0NGoWSd hViozjOrvz1SuedylI4f4y7HNdWIf42UUZ+NcIyvpZAURdrQNklu3McvP2PQwIAwJvvk GFQQpqQPJONV9JWrfJEhF5XKxMPayqhT3NkXVA11aZ+rxZMoYgePvEY2JVH3sr2qPMgh 5cK0UTIL9E1nzBBHI/Qnr80mlSfNYB+poFUc8mJDu4Ooo/PNRyIhKXvc6/H9e4a1JSzN E/Fw== X-Gm-Message-State: AOJu0YyU0+ELlqBM1ef0x2aNMfNIuLKrn8GgIVOB62kulX/kdWLYEIUe 8nQmg/Mx5i09Z7soNi78nafMUNDumeG9ENjRnYNSxIe+q9W50Vbi52H0e/qUaQ2tdWXuGPQf1iM 3 X-Received: by 2002:a17:90b:216:b0:2e2:b64e:f4f7 with SMTP id 98e67ed59e1d1-2e3ab8bc7bcmr5617989a91.29.1729107104088; Wed, 16 Oct 2024 12:31:44 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b6b1sm32323945ad.189.2024.10.16.12.31.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2024 12:31:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, zhiwei_liu@linux.alibaba.com, Huang Shiyuan , TANG Tiancheng Subject: [PATCH v6 04/14] tcg/riscv: Add basic support for vector Date: Wed, 16 Oct 2024 12:31:30 -0700 Message-ID: <20241016193140.2206352-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241016193140.2206352-1-richard.henderson@linaro.org> References: <20241016193140.2206352-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Huang Shiyuan The RISC-V vector instruction set utilizes the LMUL field to group multiple registers, enabling variable-length vector registers. This implementation uses only the first register number of each group while reserving the other register numbers within the group. In TCG, each VEC_IR can have 3 types (TCG_TYPE_V64/128/256), and the host runtime needs to adjust LMUL based on the type to use different register groups. This presents challenges for TCG's register allocation. Currently, we avoid modifying the register allocation part of TCG and only expose the minimum number of vector registers. For example, when the host vlen is 64 bits and type is TCG_TYPE_V256, with LMUL equal to 4, we use 4 vector registers as one register group. We can use a maximum of 8 register groups, but the V0 register number is reserved as a mask register, so we can effectively use at most 7 register groups. Moreover, when type is smaller than TCG_TYPE_V256, only 7 registers are forced to be used. This is because TCG cannot yet dynamically constrain registers with type; likewise, when the host vlen is 128 bits and TCG_TYPE_V256, we can use at most 15 registers. There is not much pressure on vector register allocation in TCG now, so using 7 registers is feasible and will not have a major impact on code generation. This patch: 1. Reserves vector register 0 for use as a mask register. 2. When using register groups, reserves the additional registers within each group. Signed-off-by: Huang Shiyuan Co-authored-by: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Signed-off-by: Swung0x48 Message-ID: <20241007025700.47259-3-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 6 + tcg/riscv/tcg-target-con-set.h | 2 + tcg/riscv/tcg-target-con-str.h | 1 + tcg/riscv/tcg-target.h | 78 ++++--- tcg/riscv/tcg-target.opc.h | 12 + tcg/riscv/tcg-target.c.inc | 414 ++++++++++++++++++++++++++++++--- 6 files changed, 442 insertions(+), 71 deletions(-) create mode 100644 tcg/riscv/tcg-target.opc.h diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 824fb3560d..a77ed12b9d 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -521,6 +521,12 @@ struct TCGContext { struct qemu_plugin_insn *plugin_insn; #endif + /* For host-specific values. */ +#ifdef __riscv + MemOp riscv_cur_vsew; + TCGType riscv_cur_type; +#endif + GHashTable *const_table[TCG_TYPE_COUNT]; TCGTempSet free_temps[TCG_TYPE_COUNT]; TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index aac5ceee2b..d73a62b0f2 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -21,3 +21,5 @@ C_O1_I2(r, rZ, rZ) C_N1_I2(r, r, rM) C_O1_I4(r, r, rI, rM, rM) C_O2_I4(r, r, rZ, rZ, rM, rM) +C_O0_I2(v, r) +C_O1_I1(v, r) diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h index d5c419dff1..b2b3211bcb 100644 --- a/tcg/riscv/tcg-target-con-str.h +++ b/tcg/riscv/tcg-target-con-str.h @@ -9,6 +9,7 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) +REGS('v', ALL_VECTOR_REGS) /* * Define constraint letters for constants: diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 1a347eaf6e..12a7a37aaa 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -28,42 +28,28 @@ #include "host/cpuinfo.h" #define TCG_TARGET_INSN_UNIT_SIZE 4 -#define TCG_TARGET_NB_REGS 32 +#define TCG_TARGET_NB_REGS 64 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) typedef enum { - TCG_REG_ZERO, - TCG_REG_RA, - TCG_REG_SP, - TCG_REG_GP, - TCG_REG_TP, - TCG_REG_T0, - TCG_REG_T1, - TCG_REG_T2, - TCG_REG_S0, - TCG_REG_S1, - TCG_REG_A0, - TCG_REG_A1, - TCG_REG_A2, - TCG_REG_A3, - TCG_REG_A4, - TCG_REG_A5, - TCG_REG_A6, - TCG_REG_A7, - TCG_REG_S2, - TCG_REG_S3, - TCG_REG_S4, - TCG_REG_S5, - TCG_REG_S6, - TCG_REG_S7, - TCG_REG_S8, - TCG_REG_S9, - TCG_REG_S10, - TCG_REG_S11, - TCG_REG_T3, - TCG_REG_T4, - TCG_REG_T5, - TCG_REG_T6, + TCG_REG_ZERO, TCG_REG_RA, TCG_REG_SP, TCG_REG_GP, + TCG_REG_TP, TCG_REG_T0, TCG_REG_T1, TCG_REG_T2, + TCG_REG_S0, TCG_REG_S1, TCG_REG_A0, TCG_REG_A1, + TCG_REG_A2, TCG_REG_A3, TCG_REG_A4, TCG_REG_A5, + TCG_REG_A6, TCG_REG_A7, TCG_REG_S2, TCG_REG_S3, + TCG_REG_S4, TCG_REG_S5, TCG_REG_S6, TCG_REG_S7, + TCG_REG_S8, TCG_REG_S9, TCG_REG_S10, TCG_REG_S11, + TCG_REG_T3, TCG_REG_T4, TCG_REG_T5, TCG_REG_T6, + + /* RISC-V V Extension registers */ + TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, + TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, + TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, + TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, + TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, + TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, + TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, + TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, /* aliases */ TCG_AREG0 = TCG_REG_S0, @@ -156,6 +142,32 @@ typedef enum { #define TCG_TARGET_HAS_tst 0 +/* vector instructions */ +#define TCG_TARGET_HAS_v64 0 +#define TCG_TARGET_HAS_v128 0 +#define TCG_TARGET_HAS_v256 0 +#define TCG_TARGET_HAS_andc_vec 0 +#define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_nand_vec 0 +#define TCG_TARGET_HAS_nor_vec 0 +#define TCG_TARGET_HAS_eqv_vec 0 +#define TCG_TARGET_HAS_not_vec 0 +#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rots_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 +#define TCG_TARGET_HAS_shi_vec 0 +#define TCG_TARGET_HAS_shs_vec 0 +#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 0 + +#define TCG_TARGET_HAS_tst_vec 0 + #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/riscv/tcg-target.opc.h b/tcg/riscv/tcg-target.opc.h new file mode 100644 index 0000000000..b80b39e1e5 --- /dev/null +++ b/tcg/riscv/tcg-target.opc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) C-SKY Microsystems Co., Ltd. + * + * This work is licensed under the terms of the GNU GPL, version 2 or + * (at your option) any later version. + * + * See the COPYING file in the top-level directory for details. + * + * Target-specific opcodes for host vector expansion. These will be + * emitted by tcg_expand_vec_op. For those familiar with GCC internals, + * consider these to be UNSPEC with names. + */ diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index d334857226..38d71111c9 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -32,38 +32,14 @@ #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { - "zero", - "ra", - "sp", - "gp", - "tp", - "t0", - "t1", - "t2", - "s0", - "s1", - "a0", - "a1", - "a2", - "a3", - "a4", - "a5", - "a6", - "a7", - "s2", - "s3", - "s4", - "s5", - "s6", - "s7", - "s8", - "s9", - "s10", - "s11", - "t3", - "t4", - "t5", - "t6" + "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", + "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", + "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", + "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", }; #endif @@ -100,6 +76,16 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_A5, TCG_REG_A6, TCG_REG_A7, + + /* Vector registers and TCG_REG_V0 reserved for mask. */ + TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, TCG_REG_V4, + TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, TCG_REG_V8, + TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, TCG_REG_V12, + TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, TCG_REG_V16, + TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, TCG_REG_V20, + TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, TCG_REG_V24, + TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, TCG_REG_V28, + TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, }; static const int tcg_target_call_iarg_regs[] = { @@ -127,6 +113,9 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) #define TCG_CT_CONST_J12 0x1000 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) +#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) +#define ALL_DVECTOR_REG_GROUPS 0x5555555500000000 +#define ALL_QVECTOR_REG_GROUPS 0x1111111100000000 #define sextreg sextract64 @@ -176,6 +165,31 @@ static bool tcg_target_const_match(int64_t val, int ct, * RISC-V Base ISA opcodes (IM) */ +#define V_OPIVV (0x0 << 12) +#define V_OPFVV (0x1 << 12) +#define V_OPMVV (0x2 << 12) +#define V_OPIVI (0x3 << 12) +#define V_OPIVX (0x4 << 12) +#define V_OPFVF (0x5 << 12) +#define V_OPMVX (0x6 << 12) +#define V_OPCFG (0x7 << 12) + +/* NF <= 7 && NF >= 0 */ +#define V_NF(x) (x << 29) +#define V_UNIT_STRIDE (0x0 << 20) +#define V_UNIT_STRIDE_WHOLE_REG (0x8 << 20) + +typedef enum { + VLMUL_M1 = 0, /* LMUL=1 */ + VLMUL_M2, /* LMUL=2 */ + VLMUL_M4, /* LMUL=4 */ + VLMUL_M8, /* LMUL=8 */ + VLMUL_RESERVED, + VLMUL_MF8, /* LMUL=1/8 */ + VLMUL_MF4, /* LMUL=1/4 */ + VLMUL_MF2, /* LMUL=1/2 */ +} RISCVVlmul; + typedef enum { OPC_ADD = 0x33, OPC_ADDI = 0x13, @@ -271,6 +285,30 @@ typedef enum { /* Zicond: integer conditional operations */ OPC_CZERO_EQZ = 0x0e005033, OPC_CZERO_NEZ = 0x0e007033, + + /* V: Vector extension 1.0 */ + OPC_VSETVLI = 0x57 | V_OPCFG, + OPC_VSETIVLI = 0xc0000057 | V_OPCFG, + OPC_VSETVL = 0x80000057 | V_OPCFG, + + OPC_VLE8_V = 0x7 | V_UNIT_STRIDE, + OPC_VLE16_V = 0x5007 | V_UNIT_STRIDE, + OPC_VLE32_V = 0x6007 | V_UNIT_STRIDE, + OPC_VLE64_V = 0x7007 | V_UNIT_STRIDE, + OPC_VSE8_V = 0x27 | V_UNIT_STRIDE, + OPC_VSE16_V = 0x5027 | V_UNIT_STRIDE, + OPC_VSE32_V = 0x6027 | V_UNIT_STRIDE, + OPC_VSE64_V = 0x7027 | V_UNIT_STRIDE, + + OPC_VL1RE64_V = 0x2007007 | V_UNIT_STRIDE_WHOLE_REG | V_NF(0), + OPC_VL2RE64_V = 0x2007007 | V_UNIT_STRIDE_WHOLE_REG | V_NF(1), + OPC_VL4RE64_V = 0x2007007 | V_UNIT_STRIDE_WHOLE_REG | V_NF(3), + OPC_VL8RE64_V = 0x2007007 | V_UNIT_STRIDE_WHOLE_REG | V_NF(7), + + OPC_VS1R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(0), + OPC_VS2R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(1), + OPC_VS4R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(3), + OPC_VS8R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(7), } RISCVInsn; /* @@ -363,6 +401,35 @@ static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm) return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm); } +/* Type-OPIVV/OPMVV/OPIVX/OPMVX, Vector load and store */ + +static int32_t encode_v(RISCVInsn opc, TCGReg d, TCGReg s1, + TCGReg s2, bool vm) +{ + return opc | (d & 0x1f) << 7 | (s1 & 0x1f) << 15 | + (s2 & 0x1f) << 20 | (vm << 25); +} + +/* Vector vtype */ + +static uint32_t encode_vtype(bool vta, bool vma, + MemOp vsew, RISCVVlmul vlmul) +{ + return vma << 7 | vta << 6 | vsew << 3 | vlmul; +} + +static int32_t encode_vset(RISCVInsn opc, TCGReg rd, + TCGArg rs1, uint32_t vtype) +{ + return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (vtype & 0x7ff) << 20; +} + +static int32_t encode_vseti(RISCVInsn opc, TCGReg rd, + uint32_t uimm, uint32_t vtype) +{ + return opc | (rd & 0x1f) << 7 | (uimm & 0x1f) << 15 | (vtype & 0x3ff) << 20; +} + /* * RISC-V instruction emitters */ @@ -475,6 +542,38 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, } } +/* + * RISC-V vector instruction emitters + */ + +typedef struct VsetCache { + uint32_t movi_insn; + uint32_t vset_insn; +} VsetCache; + +static VsetCache riscv_vset_cache[3][4]; + +static void set_vtype(TCGContext *s, TCGType type, MemOp vsew) +{ + const VsetCache *p = &riscv_vset_cache[type - TCG_TYPE_V64][vsew]; + + s->riscv_cur_type = type; + s->riscv_cur_vsew = vsew; + + if (p->movi_insn) { + tcg_out32(s, p->movi_insn); + } + tcg_out32(s, p->vset_insn); +} + +static MemOp set_vtype_len(TCGContext *s, TCGType type) +{ + if (type != s->riscv_cur_type) { + set_vtype(s, type, MO_64); + } + return s->riscv_cur_vsew; +} + /* * TCG intrinsics */ @@ -681,18 +780,101 @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, } } +static void tcg_out_vec_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, + TCGReg addr, intptr_t offset) +{ + tcg_debug_assert(data >= TCG_REG_V0); + tcg_debug_assert(addr < TCG_REG_V0); + + if (offset) { + tcg_debug_assert(addr != TCG_REG_ZERO); + if (offset == sextreg(offset, 0, 12)) { + tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP0, addr, offset); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP0, addr); + } + addr = TCG_REG_TMP0; + } + tcg_out32(s, encode_v(opc, data, addr, 0, true)); +} + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { - RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_LW : OPC_LD; - tcg_out_ldst(s, insn, arg, arg1, arg2); + RISCVInsn insn; + + switch (type) { + case TCG_TYPE_I32: + tcg_out_ldst(s, OPC_LW, arg, arg1, arg2); + break; + case TCG_TYPE_I64: + tcg_out_ldst(s, OPC_LD, arg, arg1, arg2); + break; + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + if (type >= riscv_lg2_vlenb) { + static const RISCVInsn whole_reg_ld[] = { + OPC_VL1RE64_V, OPC_VL2RE64_V, OPC_VL4RE64_V, OPC_VL8RE64_V + }; + unsigned idx = type - riscv_lg2_vlenb; + + tcg_debug_assert(idx < ARRAY_SIZE(whole_reg_ld)); + insn = whole_reg_ld[idx]; + } else { + static const RISCVInsn unit_stride_ld[] = { + OPC_VLE8_V, OPC_VLE16_V, OPC_VLE32_V, OPC_VLE64_V + }; + MemOp prev_vsew = set_vtype_len(s, type); + + tcg_debug_assert(prev_vsew < ARRAY_SIZE(unit_stride_ld)); + insn = unit_stride_ld[prev_vsew]; + } + tcg_out_vec_ldst(s, insn, arg, arg1, arg2); + break; + default: + g_assert_not_reached(); + } } static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { - RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_SW : OPC_SD; - tcg_out_ldst(s, insn, arg, arg1, arg2); + RISCVInsn insn; + + switch (type) { + case TCG_TYPE_I32: + tcg_out_ldst(s, OPC_SW, arg, arg1, arg2); + break; + case TCG_TYPE_I64: + tcg_out_ldst(s, OPC_SD, arg, arg1, arg2); + break; + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + if (type >= riscv_lg2_vlenb) { + static const RISCVInsn whole_reg_st[] = { + OPC_VS1R_V, OPC_VS2R_V, OPC_VS4R_V, OPC_VS8R_V + }; + unsigned idx = type - riscv_lg2_vlenb; + + tcg_debug_assert(idx < ARRAY_SIZE(whole_reg_st)); + insn = whole_reg_st[idx]; + } else { + static const RISCVInsn unit_stride_st[] = { + OPC_VSE8_V, OPC_VSE16_V, OPC_VSE32_V, OPC_VSE64_V + }; + MemOp prev_vsew = set_vtype_len(s, type); + + tcg_debug_assert(prev_vsew < ARRAY_SIZE(unit_stride_st)); + insn = unit_stride_st[prev_vsew]; + } + tcg_out_vec_ldst(s, insn, arg, arg1, arg2); + break; + default: + g_assert_not_reached(); + } } static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, @@ -766,6 +948,23 @@ static void tcg_out_addsub2(TCGContext *s, } } +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, TCGReg src) +{ + return false; +} + +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, TCGReg base, intptr_t offset) +{ + return false; +} + +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, int64_t arg) +{ +} + static const struct { RISCVInsn op; bool swap; @@ -1104,12 +1303,19 @@ static void tcg_out_cltz(TCGContext *s, TCGType type, RISCVInsn insn, } } +static void init_setting_vtype(TCGContext *s) +{ + s->riscv_cur_type = TCG_TYPE_COUNT; +} + static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) { TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; ptrdiff_t offset = tcg_pcrel_diff(s, arg); int ret; + init_setting_vtype(s); + tcg_debug_assert((offset & 1) == 0); if (offset == sextreg(offset, 0, 20)) { /* short jump: -2097150 to 2097152 */ @@ -1247,6 +1453,8 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, ldst->oi = oi; ldst->addrlo_reg = addr_reg; + init_setting_vtype(s); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); @@ -1308,6 +1516,8 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, ldst->oi = oi; ldst->addrlo_reg = addr_reg; + init_setting_vtype(s); + /* We are expecting alignment max 7, so we can always use andi. */ tcg_debug_assert(a_mask == sextreg(a_mask, 0, 12)); tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); @@ -1881,6 +2091,46 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } } +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) +{ + TCGType type = vecl + TCG_TYPE_V64; + TCGArg a0, a1, a2; + + a0 = args[0]; + a1 = args[1]; + a2 = args[2]; + + switch (opc) { + case INDEX_op_ld_vec: + tcg_out_ld(s, type, a0, a1, a2); + break; + case INDEX_op_st_vec: + tcg_out_st(s, type, a0, a1, a2); + break; + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ + case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ + default: + g_assert_not_reached(); + } +} + +void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, + TCGArg a0, ...) +{ + g_assert_not_reached(); +} + +int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) +{ + switch (opc) { + default: + return 0; + } +} + static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { switch (op) { @@ -2020,6 +2270,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_qemu_st_a64_i64: return C_O0_I2(rZ, r); + case INDEX_op_st_vec: + return C_O0_I2(v, r); + case INDEX_op_ld_vec: + return C_O1_I1(v, r); default: g_assert_not_reached(); } @@ -2093,7 +2347,65 @@ static void tcg_target_qemu_prologue(TCGContext *s) static void tcg_out_tb_start(TCGContext *s) { - /* nothing to do */ + init_setting_vtype(s); +} + +static bool vtype_check(unsigned vtype) +{ + unsigned long tmp; + + /* vsetvl tmp, zero, vtype */ + asm(".insn r 0x57, 7, 0x40, %0, zero, %1" : "=r"(tmp) : "r"(vtype)); + return tmp != 0; +} + +static void probe_frac_lmul_1(TCGType type, MemOp vsew) +{ + VsetCache *p = &riscv_vset_cache[type - TCG_TYPE_V64][vsew]; + unsigned avl = tcg_type_size(type) >> vsew; + int lmul = type - riscv_lg2_vlenb; + unsigned vtype = encode_vtype(true, true, vsew, lmul & 7); + bool lmul_eq_avl = true; + + /* Guaranteed by Zve64x. */ + assert(lmul < 3); + + /* + * For LMUL < -3, the host vector size is so large that TYPE + * is smaller than the minimum 1/8 fraction. + * + * For other fractional LMUL settings, implementations must + * support SEW settings between SEW_MIN and LMUL * ELEN, inclusive. + * So if ELEN = 64, LMUL = 1/2, then SEW will support e8, e16, e32, + * but e64 may not be supported. In other words, the hardware only + * guarantees SEW_MIN <= SEW <= LMUL * ELEN. Check. + */ + if (lmul < 0 && (lmul < -3 || !vtype_check(vtype))) { + vtype = encode_vtype(true, true, vsew, VLMUL_M1); + lmul_eq_avl = false; + } + + if (avl < 32) { + p->vset_insn = encode_vseti(OPC_VSETIVLI, TCG_REG_ZERO, avl, vtype); + } else if (lmul_eq_avl) { + /* rd != 0 and rs1 == 0 uses vlmax */ + p->vset_insn = encode_vset(OPC_VSETVLI, TCG_REG_TMP0, TCG_REG_ZERO, vtype); + } else { + p->movi_insn = encode_i(OPC_ADDI, TCG_REG_TMP0, TCG_REG_ZERO, avl); + p->vset_insn = encode_vset(OPC_VSETVLI, TCG_REG_ZERO, TCG_REG_TMP0, vtype); + } +} + +static void probe_frac_lmul(void) +{ + /* Match riscv_lg2_vlenb to TCG_TYPE_V64. */ + QEMU_BUILD_BUG_ON(TCG_TYPE_V64 != 3); + + for (TCGType t = TCG_TYPE_V64; t <= TCG_TYPE_V256; t++) { + for (MemOp e = MO_8; e <= MO_64; e++) { + probe_frac_lmul_1(t, e); + } + } } static void tcg_target_init(TCGContext *s) @@ -2101,7 +2413,7 @@ static void tcg_target_init(TCGContext *s) tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; - tcg_target_call_clobber_regs = -1u; + tcg_target_call_clobber_regs = -1; tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); @@ -2123,6 +2435,32 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); + + if (cpuinfo & CPUINFO_ZVE64X) { + switch (riscv_lg2_vlenb) { + case TCG_TYPE_V64: + tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; + tcg_target_available_regs[TCG_TYPE_V128] = ALL_DVECTOR_REG_GROUPS; + tcg_target_available_regs[TCG_TYPE_V256] = ALL_QVECTOR_REG_GROUPS; + s->reserved_regs |= (~ALL_QVECTOR_REG_GROUPS & ALL_VECTOR_REGS); + break; + case TCG_TYPE_V128: + tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; + tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; + tcg_target_available_regs[TCG_TYPE_V256] = ALL_DVECTOR_REG_GROUPS; + s->reserved_regs |= (~ALL_DVECTOR_REG_GROUPS & ALL_VECTOR_REGS); + break; + default: + /* Guaranteed by Zve64x. */ + tcg_debug_assert(riscv_lg2_vlenb >= TCG_TYPE_V256); + tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; + tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; + tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS; + break; + } + tcg_regset_set_reg(s->reserved_regs, TCG_REG_V0); + probe_frac_lmul(); + } } typedef struct { From patchwork Wed Oct 16 19:31:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835818 Delivered-To: patch@linaro.org Received: by 2002:a5d:6804:0:b0:37d:45d0:187 with SMTP id w4csp603615wru; Wed, 16 Oct 2024 12:32:54 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXr0+dbTV1qd0sg0IbgIRaAvMqdPGzKal/DzKnKVC3iEoQ/VYrWmYLO50Z4qfP5VssznW810g==@linaro.org X-Google-Smtp-Source: AGHT+IGOpfVR7dtISKxhWu846hb5dGbopTHGpZAxcBSOAlqj1fCxYULu046kwld1Xx972wB0KHRM X-Received: by 2002:a05:6808:18a0:b0:3e3:a282:2a47 with SMTP id 5614622812f47-3e5d2206425mr11032154b6e.14.1729107174682; Wed, 16 Oct 2024 12:32:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729107174; cv=none; d=google.com; s=arc-20240605; b=NjtW4EfTdsyOXIy9nxfWCQlJSFLaYQCS+R7vvKQXWEZGNbTt3VZLrwX4g9JwRgmnes m7cISpCS0KAGCBmepLCSQWkvkaHZK2+P385TGWuhy3NK21u37BneACpxHBTqDE8DRVTS Bbm++SsdKPKZeP3UPRDS4NhymHhmW86CJbAueS/1oYfWm+B+DQdsm5P4ZjZPlZA/Mpoi 4a6DHe5qS9Mlh+8HbjLbOmFcB72rez1yNmZ8vddPMaLQXcKqC5rAIchEIGDx1JKqNAbS cFFCLVpUfZNo+xyYGBiSbEeX8GvzOPI17b88XSnbI2V51Tq2VoNLpXVLkkKj0DgZ6Q++ lsLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wGj9NIqRgmgSLRSzX3rBNungML5CHycRbRnnDre79Nc=; fh=0y6cSxTabxslIGhKb2QlpT+4cpL34OsHjArvPUG+rq0=; b=jk2F7b0CLUhndLQtWVDkA/KqgSxTfKr44lZnG/GIsNB99SQlIUjLu4hdDuJ+EtzKWy uTB5XabZGC6EjHLzNYyf/x0Gy/NO4EW4hmuyggxiSRl185Tj64EyiSik3LWd7ckqzKcd vz8DOOmVf2mADpawO3rc5VsuR+1A1sFXTVWLOqFTNkH4Yja0aGfVVZPfLDjw/2VSMzv8 F/Iq1Y99E6IUjXuG5kqAFqMlPXMNhrfbDlgKXznhl26oipRAODADyf+nFU+Ca4rTRXS1 G7T6rHXBzav/kheSnVf/wKRKuEJCfedMFqgNN978gIHYfntpCdFBZYTQbDp16IY/VrH7 xlNA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XY7Qs588; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6cc22a2d1c4si45323326d6.280.2024.10.16.12.32.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2024 12:32:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XY7Qs588; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t19kO-0002gy-EG; Wed, 16 Oct 2024 15:31:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t19kK-0002db-BO for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:48 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t19kI-0003oI-3I for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:47 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-20c6f492d2dso2154745ad.0 for ; Wed, 16 Oct 2024 12:31:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729107105; x=1729711905; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wGj9NIqRgmgSLRSzX3rBNungML5CHycRbRnnDre79Nc=; b=XY7Qs588gzT84j6Xu2jLLJGt4rIJldL/iflvc5z/N7WfX0bBbUp1QVvyhv08+RHAUr P+o5IHG+3C2hQkTgm4P6UkwtOv8Sf70UNGrdzH2L2NrTyn0pQ/4kuX14H35w0xdRB+p4 E+bLTnzKkxp3JV+JnHiCNPqF6MhvUFKOnM0vVByx4vDSDa1DqI3W5atrdmok86iUehKX xdw8YEvNt9vJfuCdJf0JHveiAsUBXOlz4L7NerQpSLhopI5UE5qxvoyJPZBXz584q4Vs CJhtHHF4xqV1jAtN58AqqHUfyoUVfpexauP+N5ynTn636WFffJ7i1JLnF4UWMQVT4PEF RbaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729107105; x=1729711905; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wGj9NIqRgmgSLRSzX3rBNungML5CHycRbRnnDre79Nc=; b=wr55r7ki76UqrKDBEC7bFcxcenIEMVGcZZTSG36TCTVRjEs7jNxNxT2+7x7ruCB6H2 CAMu9/pgG4WCpNpzhoanm+twjL6+Dgll5CP2B89/ZaFXPcaNaR52Af1edOED0z/9Nbpt 5uIGzaZ0y69Cp1G4napRKOmWM84nZaXImVlUXDMNown8FWqZXJv7RuFNJfos+eDZ9WYn yJeh8Oq1eD6N6QtJUowlLZgeLbhrz1CJkN3yUTiga994/qDbh+9jylpfaDj/A5V4wQmk 6hKhakoSaydVtndONjKrVCnLlje6WwsvCVGM9l6L0bZT1xoBodbO7Dalow7IpaZo5AuO ecfQ== X-Gm-Message-State: AOJu0YyySjW7prti5zlXjV2MyvHke6Vm3LzLGmwd7zpdtMdg68Jn9VuA 9Lwry5hruplXZgtb+XNOxpo/B5X5Lu9TWEAWPyviu+koKQovtSLSMkRysPp1DKizTxPyQh3kioE p X-Received: by 2002:a17:902:e887:b0:20b:b40b:3454 with SMTP id d9443c01a7336-20cba9ebb29mr224011425ad.0.1729107104743; Wed, 16 Oct 2024 12:31:44 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b6b1sm32323945ad.189.2024.10.16.12.31.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2024 12:31:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v6 05/14] tcg/riscv: Implement vector mov/dup{m/i} Date: Wed, 16 Oct 2024 12:31:31 -0700 Message-ID: <20241016193140.2206352-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241016193140.2206352-1-richard.henderson@linaro.org> References: <20241016193140.2206352-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Message-ID: <20241007025700.47259-5-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 76 +++++++++++++++++++++++++++++++++++++- 1 file changed, 74 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 38d71111c9..17fcc21b0e 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -309,6 +309,12 @@ typedef enum { OPC_VS2R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(1), OPC_VS4R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(3), OPC_VS8R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(7), + + OPC_VMV_V_V = 0x5e000057 | V_OPIVV, + OPC_VMV_V_I = 0x5e000057 | V_OPIVI, + OPC_VMV_V_X = 0x5e000057 | V_OPIVX, + + OPC_VMVNR_V = 0x9e000057 | V_OPIVI, } RISCVInsn; /* @@ -401,6 +407,16 @@ static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm) return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm); } + +/* Type-OPIVI */ + +static int32_t encode_vi(RISCVInsn opc, TCGReg rd, int32_t imm, + TCGReg vs2, bool vm) +{ + return opc | (rd & 0x1f) << 7 | (imm & 0x1f) << 15 | + (vs2 & 0x1f) << 20 | (vm << 25); +} + /* Type-OPIVV/OPMVV/OPIVX/OPMVX, Vector load and store */ static int32_t encode_v(RISCVInsn opc, TCGReg d, TCGReg s1, @@ -546,6 +562,24 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, * RISC-V vector instruction emitters */ +/* + * Vector registers uses the same 5 lower bits as GPR registers, + * and vm=0 (vm = false) means vector masking ENABLED. + * With RVV 1.0, vs2 is the first operand, while rs1/imm is the + * second operand. + */ +static void tcg_out_opc_vx(TCGContext *s, RISCVInsn opc, + TCGReg vd, TCGReg vs2, TCGReg rs1) +{ + tcg_out32(s, encode_v(opc, vd, rs1, vs2, true)); +} + +static void tcg_out_opc_vi(TCGContext *s, RISCVInsn opc, + TCGReg vd, TCGReg vs2, int32_t imm) +{ + tcg_out32(s, encode_vi(opc, vd, imm, vs2, true)); +} + typedef struct VsetCache { uint32_t movi_insn; uint32_t vset_insn; @@ -574,6 +608,13 @@ static MemOp set_vtype_len(TCGContext *s, TCGType type) return s->riscv_cur_vsew; } +static void set_vtype_len_sew(TCGContext *s, TCGType type, MemOp vsew) +{ + if (type != s->riscv_cur_type || vsew != s->riscv_cur_vsew) { + set_vtype(s, type, vsew); + } +} + /* * TCG intrinsics */ @@ -588,6 +629,15 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) case TCG_TYPE_I64: tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); break; + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + { + int lmul = type - riscv_lg2_vlenb; + int nf = 1 << MAX(lmul, 0); + tcg_out_opc_vi(s, OPC_VMVNR_V, ret, arg, nf - 1); + } + break; default: g_assert_not_reached(); } @@ -951,18 +1001,35 @@ static void tcg_out_addsub2(TCGContext *s, static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src) { - return false; + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vx(s, OPC_VMV_V_X, dst, 0, src); + return true; } static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg base, intptr_t offset) { - return false; + tcg_out_ld(s, TCG_TYPE_REG, TCG_REG_TMP0, base, offset); + return tcg_out_dup_vec(s, type, vece, dst, TCG_REG_TMP0); } static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, int64_t arg) { + /* Arg is replicated by VECE; extract the highest element. */ + arg >>= (-8 << vece) & 63; + + if (arg >= -16 && arg < 16) { + if (arg == 0 || arg == -1) { + set_vtype_len(s, type); + } else { + set_vtype_len_sew(s, type, vece); + } + tcg_out_opc_vi(s, OPC_VMV_V_I, dst, 0, arg); + return; + } + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, arg); + tcg_out_dup_vec(s, type, vece, dst, TCG_REG_TMP0); } static const struct { @@ -2104,6 +2171,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, a2 = args[2]; switch (opc) { + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + break; case INDEX_op_ld_vec: tcg_out_ld(s, type, a0, a1, a2); break; @@ -2272,6 +2342,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_st_vec: return C_O0_I2(v, r); + case INDEX_op_dup_vec: + case INDEX_op_dupm_vec: case INDEX_op_ld_vec: return C_O1_I1(v, r); default: From patchwork Wed Oct 16 19:31:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835822 Delivered-To: patch@linaro.org Received: by 2002:a5d:6804:0:b0:37d:45d0:187 with SMTP id w4csp603941wru; Wed, 16 Oct 2024 12:33:49 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVD///bTzFIxh+fuMPzQzpbDv14gEFd2snOHPPQxpCUxkUQ5kqcZJElNHHcWAxOx5xOgPFO+w==@linaro.org X-Google-Smtp-Source: AGHT+IF9W4d/WImzXr3hMKZ6JXDDZU0pAx0aroUajAJM/FhnsfoNgfDoQhaMMnmyPE/sPl28D7+v X-Received: by 2002:ac8:5f08:0:b0:456:802c:a67f with SMTP id d75a77b69052e-4604bb93e9bmr260583211cf.3.1729107229728; Wed, 16 Oct 2024 12:33:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729107229; cv=none; d=google.com; s=arc-20240605; b=bBQxl6bPcL4cDJVTM2KoOxWkE8LPe2GXqS7xk/OIj0B179kgPDq8If1iwgPV8L4M3+ PL6cXdiZ0e4kuGzfcklYhn+J0yx5kBbHRnEfWa6yXieNgitJACm8oIAkj5KBaJfebcz/ 1LfwrskGceFwubsZg+fCJA+f03/e95sGq/hGsywlEZXjz92Z2n3R3ES10PLnOERDSp4a +0JX9odRrVLt7bzMArNzjwk5EAFsOZXqr1IXiOVXHsz3uoVLwzD5pFDW2r0jkgjtR10v uyDPtYk1lpgtUzf+GMOdPhWSVMsb5pTAtsbQni/necDlboQx4duEyPvaHiZ3NQDaHNTj kBaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xhq+IoN6vCvTOOHHSITV2/VutlKjJMMqJDBjbqbk8YI=; fh=0y6cSxTabxslIGhKb2QlpT+4cpL34OsHjArvPUG+rq0=; b=Ct+HUj9lyu0TuRuYJVijlPgpZwo38Dqnagt5onboHgw1DZ82lxvBr1ZiGHe2V4JY4J 95UlC4z7zfcGMO5H2NyH2SA6DxdtdihcNShqnUvqjtiw9DL0vnIJPrbqfgtm9Tviv59f LJ/9Xk9nzpbWlARz0tkIoIgA1scQjf4BO8xzzbU3+aQihZGyIvJRWDIvzAuR8b03sNNI xCt8zI4Q+EkqOwmovlf8zkwb07zHbrA4YHyHqcNiJsI0rN7Nqcm6Rk64JdlI+346SzJ6 KBvW3dQpF5mKmKToWfvblJStzi0jbJqQDkjyKfovptY8bgAlRlomjkfd56KkLepZZU8y PiCg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XfjdqbIk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4608bd72f84si29957521cf.91.2024.10.16.12.33.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2024 12:33:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XfjdqbIk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t19kR-0002k1-RS; Wed, 16 Oct 2024 15:31:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t19kL-0002fQ-QV for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:50 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t19kI-0003oY-OQ for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:49 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-20c693b68f5so1917845ad.1 for ; Wed, 16 Oct 2024 12:31:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729107105; x=1729711905; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xhq+IoN6vCvTOOHHSITV2/VutlKjJMMqJDBjbqbk8YI=; b=XfjdqbIkxLojWx0O2thig6wnveVNqG4MI4YE1W1UR1Hbq9aT6nRkg43PC9z27XMssD acp9OhyXf1Gn9IjeJXMhO71pD73reEGgEO+XuKkPE8PHfEc2r1vNQhWIZWgWL6htsI69 s6/f+iYOjTvw3zRES0Cv2W3ta8tCRGJYMczioJNaQfPQPNvooU3BnL7xv6e/zdbz3MZG QreDFFDAmxDXHBTICtEFkByjTniqvubs370eTLONpMhg3Sngfg92KLsLAxSxmNyO6FK7 DN4LPQx0S6FthaZWdWqjABhZ2zLkr/s+DicIl8nvaxfpoCEF6rIMyatOuIJbGnw7LfIm i5dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729107105; x=1729711905; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xhq+IoN6vCvTOOHHSITV2/VutlKjJMMqJDBjbqbk8YI=; b=KfKgtIZT+pYPcpLkmTZkq29F7uB6uAvD33EahnRTmaAd38Xf64L433wMWzCXZ7l5Um DKK8Wf0uNGETC0GeFpoOLQWv0CWPeTqezYiCW3Y4113tjAsXWLJYsqfnuYj6YdshYIZq Slf9Gw+Aq1aKsCheLLfnPgV2WqVg2nn+oWi8KdGQjCTH/BY38SmvmmN9qRJnsgrQTBSn z8fN7rCruU0WtiSPD/Ml6YYMEMeHSa+BS5jukhzS3ZgLIDpcU1rF4Oim2AzcsVyS9IGy iN38uYul0CzudhrgA+asvr9YgSJJzx7SCo6efX9p8Oph2bOWtlFthO410Xl1z4OBOCOE ZmBg== X-Gm-Message-State: AOJu0YzXBuS95RNyWDpuCoSO5ilGimcVvA5szdYPirsjMONdq3n0ddpz V6qqCkiRvSnNwvfT01XfkaZp9BtDUOJIbxUxkWqIFPn9Jc2ocHN0+v4z4jjtu6qMLEkTC4RPSdo V X-Received: by 2002:a17:90a:fc8e:b0:2e2:bd72:543d with SMTP id 98e67ed59e1d1-2e2f0ddb967mr19237886a91.41.1729107105365; Wed, 16 Oct 2024 12:31:45 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b6b1sm32323945ad.189.2024.10.16.12.31.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2024 12:31:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v6 06/14] tcg/riscv: Add support for basic vector opcodes Date: Wed, 16 Oct 2024 12:31:32 -0700 Message-ID: <20241016193140.2206352-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241016193140.2206352-1-richard.henderson@linaro.org> References: <20241016193140.2206352-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Message-ID: <20241007025700.47259-6-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 3 ++ tcg/riscv/tcg-target-con-str.h | 1 + tcg/riscv/tcg-target.h | 2 +- tcg/riscv/tcg-target.c.inc | 80 ++++++++++++++++++++++++++++++++++ 4 files changed, 85 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index d73a62b0f2..6513cebc4c 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -23,3 +23,6 @@ C_O1_I4(r, r, rI, rM, rM) C_O2_I4(r, r, rZ, rZ, rM, rM) C_O0_I2(v, r) C_O1_I1(v, r) +C_O1_I1(v, v) +C_O1_I2(v, v, v) +C_O1_I2(v, v, vK) diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h index b2b3211bcb..0aaad7b753 100644 --- a/tcg/riscv/tcg-target-con-str.h +++ b/tcg/riscv/tcg-target-con-str.h @@ -17,6 +17,7 @@ REGS('v', ALL_VECTOR_REGS) */ CONST('I', TCG_CT_CONST_S12) CONST('J', TCG_CT_CONST_J12) +CONST('K', TCG_CT_CONST_S5) CONST('N', TCG_CT_CONST_N12) CONST('M', TCG_CT_CONST_M12) CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 12a7a37aaa..acb8dfdf16 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -151,7 +151,7 @@ typedef enum { #define TCG_TARGET_HAS_nand_vec 0 #define TCG_TARGET_HAS_nor_vec 0 #define TCG_TARGET_HAS_eqv_vec 0 -#define TCG_TARGET_HAS_not_vec 0 +#define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_roti_vec 0 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 17fcc21b0e..c8540f9a75 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -111,6 +111,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) #define TCG_CT_CONST_N12 0x400 #define TCG_CT_CONST_M12 0x800 #define TCG_CT_CONST_J12 0x1000 +#define TCG_CT_CONST_S5 0x2000 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) #define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) @@ -129,6 +130,10 @@ static bool tcg_target_const_match(int64_t val, int ct, if ((ct & TCG_CT_CONST_ZERO) && val == 0) { return 1; } + if (type >= TCG_TYPE_V64) { + /* Val is replicated by VECE; extract the highest element. */ + val >>= (-8 << vece) & 63; + } /* * Sign extended from 12 bits: [-0x800, 0x7ff]. * Used for most arithmetic, as this is the isa field. @@ -158,6 +163,13 @@ static bool tcg_target_const_match(int64_t val, int ct, if ((ct & TCG_CT_CONST_J12) && ~val >= -0x800 && ~val <= 0x7ff) { return 1; } + /* + * Sign extended from 5 bits: [-0x10, 0x0f]. + * Used for vector-immediate. + */ + if ((ct & TCG_CT_CONST_S5) && val >= -0x10 && val <= 0x0f) { + return 1; + } return 0; } @@ -310,6 +322,16 @@ typedef enum { OPC_VS4R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(3), OPC_VS8R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(7), + OPC_VADD_VV = 0x57 | V_OPIVV, + OPC_VADD_VI = 0x57 | V_OPIVI, + OPC_VSUB_VV = 0x8000057 | V_OPIVV, + OPC_VAND_VV = 0x24000057 | V_OPIVV, + OPC_VAND_VI = 0x24000057 | V_OPIVI, + OPC_VOR_VV = 0x28000057 | V_OPIVV, + OPC_VOR_VI = 0x28000057 | V_OPIVI, + OPC_VXOR_VV = 0x2c000057 | V_OPIVV, + OPC_VXOR_VI = 0x2c000057 | V_OPIVI, + OPC_VMV_V_V = 0x5e000057 | V_OPIVV, OPC_VMV_V_I = 0x5e000057 | V_OPIVI, OPC_VMV_V_X = 0x5e000057 | V_OPIVX, @@ -568,6 +590,12 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, * With RVV 1.0, vs2 is the first operand, while rs1/imm is the * second operand. */ +static void tcg_out_opc_vv(TCGContext *s, RISCVInsn opc, + TCGReg vd, TCGReg vs2, TCGReg vs1) +{ + tcg_out32(s, encode_v(opc, vd, vs1, vs2, true)); +} + static void tcg_out_opc_vx(TCGContext *s, RISCVInsn opc, TCGReg vd, TCGReg vs2, TCGReg rs1) { @@ -580,6 +608,16 @@ static void tcg_out_opc_vi(TCGContext *s, RISCVInsn opc, tcg_out32(s, encode_vi(opc, vd, imm, vs2, true)); } +static void tcg_out_opc_vv_vi(TCGContext *s, RISCVInsn o_vv, RISCVInsn o_vi, + TCGReg vd, TCGReg vs2, TCGArg vi1, int c_vi1) +{ + if (c_vi1) { + tcg_out_opc_vi(s, o_vi, vd, vs2, vi1); + } else { + tcg_out_opc_vv(s, o_vv, vd, vs2, vi1); + } +} + typedef struct VsetCache { uint32_t movi_insn; uint32_t vset_insn; @@ -2165,10 +2203,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, { TCGType type = vecl + TCG_TYPE_V64; TCGArg a0, a1, a2; + int c2; a0 = args[0]; a1 = args[1]; a2 = args[2]; + c2 = const_args[2]; switch (opc) { case INDEX_op_dupm_vec: @@ -2180,6 +2220,30 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_st_vec: tcg_out_st(s, type, a0, a1, a2); break; + case INDEX_op_add_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv_vi(s, OPC_VADD_VV, OPC_VADD_VI, a0, a1, a2, c2); + break; + case INDEX_op_sub_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2); + break; + case INDEX_op_and_vec: + set_vtype_len(s, type); + tcg_out_opc_vv_vi(s, OPC_VAND_VV, OPC_VAND_VI, a0, a1, a2, c2); + break; + case INDEX_op_or_vec: + set_vtype_len(s, type); + tcg_out_opc_vv_vi(s, OPC_VOR_VV, OPC_VOR_VI, a0, a1, a2, c2); + break; + case INDEX_op_xor_vec: + set_vtype_len(s, type); + tcg_out_opc_vv_vi(s, OPC_VXOR_VV, OPC_VXOR_VI, a0, a1, a2, c2); + break; + case INDEX_op_not_vec: + set_vtype_len(s, type); + tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1, -1); + break; case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: @@ -2196,6 +2260,13 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { switch (opc) { + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_not_vec: + return 1; default: return 0; } @@ -2346,6 +2417,15 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_dupm_vec: case INDEX_op_ld_vec: return C_O1_I1(v, r); + case INDEX_op_not_vec: + return C_O1_I1(v, v); + case INDEX_op_add_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + return C_O1_I2(v, v, vK); + case INDEX_op_sub_vec: + return C_O1_I2(v, v, v); default: g_assert_not_reached(); } From patchwork Wed Oct 16 19:31:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835825 Delivered-To: patch@linaro.org Received: by 2002:a5d:6804:0:b0:37d:45d0:187 with SMTP id w4csp604049wru; Wed, 16 Oct 2024 12:34:08 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVUDFUfvx/tDyqBwfuWOIP3uC19Hs2JwsvZENa84fHuewZOiDA7udOgopMuha0093ycMOYYCw==@linaro.org X-Google-Smtp-Source: AGHT+IH2m2nBU2n/a/ciF0oVCfG+AEpDy+rSiopC0k9umkoV0F9zQV1jfn+RYt9opgFgCbRwlK+7 X-Received: by 2002:a05:622a:5cb:b0:460:8930:bbe7 with SMTP id d75a77b69052e-4609b45749bmr11711531cf.3.1729107248049; Wed, 16 Oct 2024 12:34:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729107248; cv=none; d=google.com; s=arc-20240605; b=jl7FzyUTonavKiU6KzRj6lcU/hy7tXRFQndTvI1Kjf1f/DlrdJMbExdX9J9YLk3PQY wsoPW257RxRCdsazAl5eJbUXOE1HC6PICpflCVQejAxZ64n4/6QJD0gvh1FB8dzcEa30 Xewk7uAijPOjsRtdl/37/i92bv+zG9G9c1rwApLnj0NoXp1dgW+pW/28qBbizIDYPdfO fifWbzlpHygTL629kCpYlbLPPlntbsLtgzncrKKuLSRJ3b2ZgnYFK08dOyxegYfnRA7x tFdAwXhoON5PlYV6GLKhSpHLxV32BfrR8B5cu0LvEiYrDxsQVuWdVKHbIbqrDOziSO95 kIzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ejQ3abjWoK898OKlrmsQMhX9Q7Lzbw38F/N2+EDuzW0=; fh=0y6cSxTabxslIGhKb2QlpT+4cpL34OsHjArvPUG+rq0=; b=EicB4PfBK45yzFL5dZfeaS/XFhlBj2XeXq1X3ZtrInQ5Zz8LIz8xZmZGu8ps35TisT mTJRRjvHZX67FbczEidOHfTpUbe3Ppg8jjVi5YdE1uFaYbYuHes86xmKiE0YqJ7TQI+k 9X3F67mrOEv46Mm4GjRYjYC3ZJiXU0hbyq6Qda48eszknQSXWQtPQmZIyGWmFH3hchw2 qJdSG4dmYOmpBPy4ZrzpUmqXSxxp3QIcMVSyoter+x4X4WASCsQknuSnzSfyGPqow6Hq wbyDPQRKMv8kwpYkXlyvR6B1priDKM5EiP7uivE/DStBhoQyG6biCDorznGtTmNXWtft zabQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oS54llnW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4607b12dec3si48682101cf.168.2024.10.16.12.34.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2024 12:34:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oS54llnW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t19kR-0002k3-TJ; Wed, 16 Oct 2024 15:31:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t19kN-0002gf-Mz for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:51 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t19kJ-0003p9-MN for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:51 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-20cceb8d8b4so1047735ad.1 for ; Wed, 16 Oct 2024 12:31:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729107106; x=1729711906; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ejQ3abjWoK898OKlrmsQMhX9Q7Lzbw38F/N2+EDuzW0=; b=oS54llnWN+xP7dLRq271mlAQCPHL86/ryXZwQVe12ZwKBxhhTIuP+RVH8IDnBVCNgS 2QNyqigW5uSbISCNPsLTolf8zp+MAI62DYnw+G+c1nbAcNDRuOgxXqR3HfZCYkimvtkG 2buIWaoHpxtgIFUiYYBqdy8gRokuU7hy6ikINoJQTn3O2v2GsF4AwgDQ5JHdWmLf+hUj rBlesMDiNPM9nSuaQwOC/c37+xWc2Ud7HJAUgeA6Z3fh+mkfPQ1V/tBfsqCMwyzYsriO uSIYIWR38D6fa+Uhum9tJ8xbiLBNI6PkzP+qORjwsOfJvymC1BYXgwq73qquae6EywHI qkug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729107106; x=1729711906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ejQ3abjWoK898OKlrmsQMhX9Q7Lzbw38F/N2+EDuzW0=; b=D9IXfj1hflCafSOU7DMjRmIFuRQJu48o8CUG+/tWOmMGoDmfbFsA6Sbs8ybp+KXIEA Jxa9XLXZD90qnaIcwMsAcztEI8/DbaKEc3mbs0ymwd2IIqSVHv3bMPH40pc1WzoKECJ4 oj2qUCb5nBIHtuOGZe939x6uY4J9OzMsc7c5+zWMDvWoB9m7Lll5hLMCrT5azwq+5tXo X2f+qcjvbRontc1RMAiirKsJMOs5EWLKa5BVe/+lvK74wlX6pfJLF1zWXhrpOYuaNfVr 2yKnx29KhQdggpSc5pIUV4f+xtfT/OK1XhqpHnSGTFiB+i3LN+xvWAHoxTyKUv0zXuUD Zz6A== X-Gm-Message-State: AOJu0YzHWyaJ24PNzxQ4fsN3otCDRg3lWikerKzP6fc+nvyug5bJXBn4 7XonkBawOolJuXvbGWHpKgFtE7GpPqIEPf1qnvBh3OWHraFpE4Jzrkys69uMgx0U08LxgO2/r6B o X-Received: by 2002:a17:903:187:b0:20c:8839:c500 with SMTP id d9443c01a7336-20d4742c241mr9589535ad.12.1729107106166; Wed, 16 Oct 2024 12:31:46 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b6b1sm32323945ad.189.2024.10.16.12.31.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2024 12:31:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v6 07/14] tcg/riscv: Implement vector cmp/cmpsel ops Date: Wed, 16 Oct 2024 12:31:33 -0700 Message-ID: <20241016193140.2206352-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241016193140.2206352-1-richard.henderson@linaro.org> References: <20241016193140.2206352-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: TANG Tiancheng Extend comparison results from mask registers to SEW-width elements, following recommendations in The RISC-V SPEC Volume I (Version 20240411). This aligns with TCG's cmp_vec behavior by expanding compare results to full element width: all 1s for true, all 0s for false. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Message-ID: <20241007025700.47259-7-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 2 + tcg/riscv/tcg-target-con-str.h | 1 + tcg/riscv/tcg-target.h | 2 +- tcg/riscv/tcg-target.c.inc | 255 +++++++++++++++++++++++++-------- 4 files changed, 200 insertions(+), 60 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index 6513cebc4c..97e6ecdb0f 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -26,3 +26,5 @@ C_O1_I1(v, r) C_O1_I1(v, v) C_O1_I2(v, v, v) C_O1_I2(v, v, vK) +C_O1_I2(v, v, vL) +C_O1_I4(v, v, vL, vK, vK) diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h index 0aaad7b753..089efe96ca 100644 --- a/tcg/riscv/tcg-target-con-str.h +++ b/tcg/riscv/tcg-target-con-str.h @@ -18,6 +18,7 @@ REGS('v', ALL_VECTOR_REGS) CONST('I', TCG_CT_CONST_S12) CONST('J', TCG_CT_CONST_J12) CONST('K', TCG_CT_CONST_S5) +CONST('L', TCG_CT_CONST_CMP_VI) CONST('N', TCG_CT_CONST_N12) CONST('M', TCG_CT_CONST_M12) CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index acb8dfdf16..94034504b2 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -164,7 +164,7 @@ typedef enum { #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_HAS_bitsel_vec 0 -#define TCG_TARGET_HAS_cmpsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 1 #define TCG_TARGET_HAS_tst_vec 0 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index c8540f9a75..1893c419c6 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -106,12 +106,13 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) return TCG_REG_A0 + slot; } -#define TCG_CT_CONST_ZERO 0x100 -#define TCG_CT_CONST_S12 0x200 -#define TCG_CT_CONST_N12 0x400 -#define TCG_CT_CONST_M12 0x800 -#define TCG_CT_CONST_J12 0x1000 -#define TCG_CT_CONST_S5 0x2000 +#define TCG_CT_CONST_ZERO 0x100 +#define TCG_CT_CONST_S12 0x200 +#define TCG_CT_CONST_N12 0x400 +#define TCG_CT_CONST_M12 0x800 +#define TCG_CT_CONST_J12 0x1000 +#define TCG_CT_CONST_S5 0x2000 +#define TCG_CT_CONST_CMP_VI 0x4000 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) #define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) @@ -120,59 +121,6 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) #define sextreg sextract64 -/* test if a constant matches the constraint */ -static bool tcg_target_const_match(int64_t val, int ct, - TCGType type, TCGCond cond, int vece) -{ - if (ct & TCG_CT_CONST) { - return 1; - } - if ((ct & TCG_CT_CONST_ZERO) && val == 0) { - return 1; - } - if (type >= TCG_TYPE_V64) { - /* Val is replicated by VECE; extract the highest element. */ - val >>= (-8 << vece) & 63; - } - /* - * Sign extended from 12 bits: [-0x800, 0x7ff]. - * Used for most arithmetic, as this is the isa field. - */ - if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) { - return 1; - } - /* - * Sign extended from 12 bits, negated: [-0x7ff, 0x800]. - * Used for subtraction, where a constant must be handled by ADDI. - */ - if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) { - return 1; - } - /* - * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff]. - * Used by addsub2 and movcond, which may need the negative value, - * and requires the modified constant to be representable. - */ - if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) { - return 1; - } - /* - * Inverse of sign extended from 12 bits: ~[-0x800, 0x7ff]. - * Used to map ANDN back to ANDI, etc. - */ - if ((ct & TCG_CT_CONST_J12) && ~val >= -0x800 && ~val <= 0x7ff) { - return 1; - } - /* - * Sign extended from 5 bits: [-0x10, 0x0f]. - * Used for vector-immediate. - */ - if ((ct & TCG_CT_CONST_S5) && val >= -0x10 && val <= 0x0f) { - return 1; - } - return 0; -} - /* * RISC-V Base ISA opcodes (IM) */ @@ -322,6 +270,9 @@ typedef enum { OPC_VS4R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(3), OPC_VS8R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(7), + OPC_VMERGE_VIM = 0x5c000057 | V_OPIVI, + OPC_VMERGE_VVM = 0x5c000057 | V_OPIVV, + OPC_VADD_VV = 0x57 | V_OPIVV, OPC_VADD_VI = 0x57 | V_OPIVI, OPC_VSUB_VV = 0x8000057 | V_OPIVV, @@ -332,6 +283,29 @@ typedef enum { OPC_VXOR_VV = 0x2c000057 | V_OPIVV, OPC_VXOR_VI = 0x2c000057 | V_OPIVI, + OPC_VMSEQ_VV = 0x60000057 | V_OPIVV, + OPC_VMSEQ_VI = 0x60000057 | V_OPIVI, + OPC_VMSEQ_VX = 0x60000057 | V_OPIVX, + OPC_VMSNE_VV = 0x64000057 | V_OPIVV, + OPC_VMSNE_VI = 0x64000057 | V_OPIVI, + OPC_VMSNE_VX = 0x64000057 | V_OPIVX, + + OPC_VMSLTU_VV = 0x68000057 | V_OPIVV, + OPC_VMSLTU_VX = 0x68000057 | V_OPIVX, + OPC_VMSLT_VV = 0x6c000057 | V_OPIVV, + OPC_VMSLT_VX = 0x6c000057 | V_OPIVX, + OPC_VMSLEU_VV = 0x70000057 | V_OPIVV, + OPC_VMSLEU_VX = 0x70000057 | V_OPIVX, + OPC_VMSLE_VV = 0x74000057 | V_OPIVV, + OPC_VMSLE_VX = 0x74000057 | V_OPIVX, + + OPC_VMSLEU_VI = 0x70000057 | V_OPIVI, + OPC_VMSLE_VI = 0x74000057 | V_OPIVI, + OPC_VMSGTU_VI = 0x78000057 | V_OPIVI, + OPC_VMSGTU_VX = 0x78000057 | V_OPIVX, + OPC_VMSGT_VI = 0x7c000057 | V_OPIVI, + OPC_VMSGT_VX = 0x7c000057 | V_OPIVX, + OPC_VMV_V_V = 0x5e000057 | V_OPIVV, OPC_VMV_V_I = 0x5e000057 | V_OPIVI, OPC_VMV_V_X = 0x5e000057 | V_OPIVX, @@ -339,6 +313,101 @@ typedef enum { OPC_VMVNR_V = 0x9e000057 | V_OPIVI, } RISCVInsn; +static const struct { + RISCVInsn op; + bool swap; +} tcg_cmpcond_to_rvv_vv[] = { + [TCG_COND_EQ] = { OPC_VMSEQ_VV, false }, + [TCG_COND_NE] = { OPC_VMSNE_VV, false }, + [TCG_COND_LT] = { OPC_VMSLT_VV, false }, + [TCG_COND_GE] = { OPC_VMSLE_VV, true }, + [TCG_COND_GT] = { OPC_VMSLT_VV, true }, + [TCG_COND_LE] = { OPC_VMSLE_VV, false }, + [TCG_COND_LTU] = { OPC_VMSLTU_VV, false }, + [TCG_COND_GEU] = { OPC_VMSLEU_VV, true }, + [TCG_COND_GTU] = { OPC_VMSLTU_VV, true }, + [TCG_COND_LEU] = { OPC_VMSLEU_VV, false } +}; + +static const struct { + RISCVInsn op; + int min; + int max; + bool adjust; +} tcg_cmpcond_to_rvv_vi[] = { + [TCG_COND_EQ] = { OPC_VMSEQ_VI, -16, 15, false }, + [TCG_COND_NE] = { OPC_VMSNE_VI, -16, 15, false }, + [TCG_COND_GT] = { OPC_VMSGT_VI, -16, 15, false }, + [TCG_COND_LE] = { OPC_VMSLE_VI, -16, 15, false }, + [TCG_COND_LT] = { OPC_VMSLE_VI, -15, 16, true }, + [TCG_COND_GE] = { OPC_VMSGT_VI, -15, 16, true }, + [TCG_COND_LEU] = { OPC_VMSLEU_VI, 0, 15, false }, + [TCG_COND_GTU] = { OPC_VMSGTU_VI, 0, 15, false }, + [TCG_COND_LTU] = { OPC_VMSLEU_VI, 1, 16, true }, + [TCG_COND_GEU] = { OPC_VMSGTU_VI, 1, 16, true }, +}; + +/* test if a constant matches the constraint */ +static bool tcg_target_const_match(int64_t val, int ct, + TCGType type, TCGCond cond, int vece) +{ + if (ct & TCG_CT_CONST) { + return 1; + } + if ((ct & TCG_CT_CONST_ZERO) && val == 0) { + return 1; + } + if (type >= TCG_TYPE_V64) { + /* Val is replicated by VECE; extract the highest element. */ + val >>= (-8 << vece) & 63; + } + /* + * Sign extended from 12 bits: [-0x800, 0x7ff]. + * Used for most arithmetic, as this is the isa field. + */ + if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) { + return 1; + } + /* + * Sign extended from 12 bits, negated: [-0x7ff, 0x800]. + * Used for subtraction, where a constant must be handled by ADDI. + */ + if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) { + return 1; + } + /* + * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff]. + * Used by addsub2 and movcond, which may need the negative value, + * and requires the modified constant to be representable. + */ + if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) { + return 1; + } + /* + * Inverse of sign extended from 12 bits: ~[-0x800, 0x7ff]. + * Used to map ANDN back to ANDI, etc. + */ + if ((ct & TCG_CT_CONST_J12) && ~val >= -0x800 && ~val <= 0x7ff) { + return 1; + } + /* + * Sign extended from 5 bits: [-0x10, 0x0f]. + * Used for vector-immediate. + */ + if ((ct & TCG_CT_CONST_S5) && val >= -0x10 && val <= 0x0f) { + return 1; + } + /* + * Used for vector compare OPIVI instructions. + */ + if ((ct & TCG_CT_CONST_CMP_VI) && + val >= tcg_cmpcond_to_rvv_vi[cond].min && + val <= tcg_cmpcond_to_rvv_vi[cond].max) { + return true; + } + return 0; +} + /* * RISC-V immediate and instruction encoders (excludes 16-bit RVC) */ @@ -618,6 +687,18 @@ static void tcg_out_opc_vv_vi(TCGContext *s, RISCVInsn o_vv, RISCVInsn o_vi, } } +static void tcg_out_opc_vim_mask(TCGContext *s, RISCVInsn opc, TCGReg vd, + TCGReg vs2, int32_t imm) +{ + tcg_out32(s, encode_vi(opc, vd, imm, vs2, false)); +} + +static void tcg_out_opc_vvm_mask(TCGContext *s, RISCVInsn opc, TCGReg vd, + TCGReg vs2, TCGReg vs1) +{ + tcg_out32(s, encode_v(opc, vd, vs1, vs2, false)); +} + typedef struct VsetCache { uint32_t movi_insn; uint32_t vset_insn; @@ -1408,6 +1489,48 @@ static void tcg_out_cltz(TCGContext *s, TCGType type, RISCVInsn insn, } } +static void tcg_out_cmpsel(TCGContext *s, TCGType type, unsigned vece, + TCGCond cond, TCGReg ret, + TCGReg cmp1, TCGReg cmp2, bool c_cmp2, + TCGReg val1, bool c_val1, + TCGReg val2, bool c_val2) +{ + set_vtype_len_sew(s, type, vece); + + /* Use only vmerge_vim if possible, by inverting the test. */ + if (c_val2 && !c_val1) { + TCGArg temp = val1; + cond = tcg_invert_cond(cond); + val1 = val2; + val2 = temp; + c_val1 = true; + c_val2 = false; + } + + /* Perform the comparison into V0 mask. */ + if (c_cmp2) { + tcg_out_opc_vi(s, tcg_cmpcond_to_rvv_vi[cond].op, TCG_REG_V0, cmp1, + cmp2 - tcg_cmpcond_to_rvv_vi[cond].adjust); + } else if (tcg_cmpcond_to_rvv_vv[cond].swap) { + tcg_out_opc_vv(s, tcg_cmpcond_to_rvv_vv[cond].op, + TCG_REG_V0, cmp2, cmp1); + } else { + tcg_out_opc_vv(s, tcg_cmpcond_to_rvv_vv[cond].op, + TCG_REG_V0, cmp1, cmp2); + } + if (c_val1) { + if (c_val2) { + tcg_out_opc_vi(s, OPC_VMV_V_I, ret, 0, val2); + val2 = ret; + } + /* vd[i] == v0.mask[i] ? imm : vs2[i] */ + tcg_out_opc_vim_mask(s, OPC_VMERGE_VIM, ret, val2, val1); + } else { + /* vd[i] == v0.mask[i] ? vs1[i] : vs2[i] */ + tcg_out_opc_vvm_mask(s, OPC_VMERGE_VVM, ret, val2, val1); + } +} + static void init_setting_vtype(TCGContext *s) { s->riscv_cur_type = TCG_TYPE_COUNT; @@ -2244,6 +2367,14 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, set_vtype_len(s, type); tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1, -1); break; + case INDEX_op_cmp_vec: + tcg_out_cmpsel(s, type, vece, args[3], a0, a1, a2, c2, + -1, true, 0, true); + break; + case INDEX_op_cmpsel_vec: + tcg_out_cmpsel(s, type, vece, args[5], a0, a1, a2, c2, + args[3], const_args[3], args[4], const_args[4]); + break; case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: @@ -2266,6 +2397,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_or_vec: case INDEX_op_xor_vec: case INDEX_op_not_vec: + case INDEX_op_cmp_vec: + case INDEX_op_cmpsel_vec: return 1; default: return 0; @@ -2426,6 +2559,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) return C_O1_I2(v, v, vK); case INDEX_op_sub_vec: return C_O1_I2(v, v, v); + case INDEX_op_cmp_vec: + return C_O1_I2(v, v, vL); + case INDEX_op_cmpsel_vec: + return C_O1_I4(v, v, vL, vK, vK); default: g_assert_not_reached(); } From patchwork Wed Oct 16 19:31:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835830 Delivered-To: patch@linaro.org Received: by 2002:a5d:6804:0:b0:37d:45d0:187 with SMTP id w4csp604696wru; Wed, 16 Oct 2024 12:35:50 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW0BB9HgDmpjyS+8NcGrYdJEPfWxgtWmc6i+qg7zPyFwmMFOhRYkHACRVZsU9EyauJ01P1V9w==@linaro.org X-Google-Smtp-Source: AGHT+IHFxKgAA3qRRJaARw4vMwEJiIQ0iNHtRQmEqYjSsLFhHjl1WI/yEPOBcQ/pXxxuVMx6CBEf X-Received: by 2002:a05:6214:2f11:b0:6cb:f6a6:55a8 with SMTP id 6a1803df08f44-6cbf9d4b4d3mr294222306d6.27.1729107350539; Wed, 16 Oct 2024 12:35:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729107350; cv=none; d=google.com; s=arc-20240605; b=WDj5e8PpccbrXxFaOh6BmCU8j6pnMT2n6kuJ+T96ogVmEpCdke6dDiY/NrO9Ql8lHS ahnqu+Q8kl8Kd94QvILfhQu4k3waHXLHCBeXxswoh63ngK8TKqnfLMftcOkBhMnCblBq W8wkGvtrOxjj5vs/V5B0Lcw2KGvSTCo9IGpwtd0F2x/NUKrjx4Xf44kiCea7IGKhRE/Z Yy3/DdT7Q1vtImvAMV46JMx4wjEw43Z3qfYiKVxwMqGh0lqGfbta+60myMMGKFr01gf0 hABbPIotQHhg3LHC8sjQBCku6epmHTmu8R1Ip9Bdt2THkR/m9KPUdCT1mL678EF/MSBW /VBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=F16mOGOCEtDulhf7gkD6+zfYNl/76OFFUvZQ0M86ofc=; fh=0y6cSxTabxslIGhKb2QlpT+4cpL34OsHjArvPUG+rq0=; b=lqEVYZ3NNfWisblQq1hPx0f+9hDw4eGpcjfGZR0ERJFOzafHFOmvRppU/x0+Q9sh1b bDgYQwXmPWDn+wqZ4cmVpRZEoSoI0CUt1kA7c6Z6wRm6l62RfSJlfv02c6ZSLYeiGv1/ BFIupLiAWq3ctdJFXgtZQZgBSAiPlWvuSCiae3RwGJssMKv8r+QDuWpkzemJS6OUsWCF T9JNP1352LbUm+eQNsp6piKoC0aoGqHTbgz/wQXyGMUQLq84F/yEImXShh11j7M2Nflk FFGMLBogptuttYxGBLwrHGvDqrAAQRygma9UDTD+GpoTFVGXwL/HEjjN1Hcy6X1UeVaT 3Gqg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RUu26uCx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6cc22b3b56asi45432206d6.366.2024.10.16.12.35.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2024 12:35:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RUu26uCx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t19kT-0002kt-1x; Wed, 16 Oct 2024 15:31:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t19kN-0002g3-2V for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:51 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t19kK-0003pK-Ar for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:50 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-20cbcd71012so1487215ad.3 for ; Wed, 16 Oct 2024 12:31:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729107107; x=1729711907; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F16mOGOCEtDulhf7gkD6+zfYNl/76OFFUvZQ0M86ofc=; b=RUu26uCxYoDiJPFrG5Zj14mJC5PvjKLGbAoNJDRXVLB3GdnRBJoq2kxVNu5lJTBTf8 H6ltWkr3Fk0oWYHhjFrzvK+f89lgfS7xYu/wPszZl9C3bwi2F1u6Ubv73wK/dut9OSCq zIcpxvKDl6dtSXFgRb3Ppw1TDirzkY54B+ZrhaUBEOcRPoQjNuUTXvVvNz9KYYxCNOGK SLvt4bqDWY8PKpDMLQSGo4DemuQOnK5W1CMF7P/XNcb2suqj9HoT4UGPXv0rU5BDBQFw D9y7pWXDCWzyOeTQ1Pg4Yds9GtBUFUpzpdQETtzwDx/J+4/je0XsEEsV3x/nuwh1qa80 iUhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729107107; x=1729711907; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F16mOGOCEtDulhf7gkD6+zfYNl/76OFFUvZQ0M86ofc=; b=Co48UqZjz1F/mOlyoUMg5j4sXYDgUHxwbNxKCJqltOEMJGgEr4MtSp+LE1DRufCPFU yCrFyp3mub/dRUgv4klo8YteOj2j+45e0P+wJp24/LojTaUQ9eEv+R8ufxiaTf8y/xoV WlSGQSt9QwIWrOyFjVX5PVKGbwH8IMjWh5IbORDKzqqEu23BpUDB7g9vRKRa027IY+Ke k6D9AVKiud5YpZIqUADNVW12OTSJmb603HSXIMAxEmcoIoi5u0Ie/WdprXUKDkVTw6SH z9LP8nHpHiI0jkgezASGj/FlF9/jSl+nzWhfpjHeZy1UjiN6jfD4CLjQzDYgxuarzeIq qEyA== X-Gm-Message-State: AOJu0Yz2xV2CzMQAqOr0kzv2weTBIEs0mr06FC/K6r+wuqKxR+mq3nNF BZwlNvFY7nli2lw8DEVKSMLJmpAIat2Rd4NngIusXzs6SSlFnaSTgpi4zA2MXwAOaqCmlAnWcx9 9 X-Received: by 2002:a17:902:f54d:b0:20c:ecd8:d092 with SMTP id d9443c01a7336-20cecd8d2edmr147712825ad.30.1729107106895; Wed, 16 Oct 2024 12:31:46 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b6b1sm32323945ad.189.2024.10.16.12.31.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2024 12:31:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v6 08/14] tcg/riscv: Implement vector neg ops Date: Wed, 16 Oct 2024 12:31:34 -0700 Message-ID: <20241016193140.2206352-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241016193140.2206352-1-richard.henderson@linaro.org> References: <20241016193140.2206352-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Message-ID: <20241007025700.47259-8-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 2 +- tcg/riscv/tcg-target.c.inc | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 94034504b2..ae10381e02 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -152,7 +152,7 @@ typedef enum { #define TCG_TARGET_HAS_nor_vec 0 #define TCG_TARGET_HAS_eqv_vec 0 #define TCG_TARGET_HAS_not_vec 1 -#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_rots_vec 0 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 1893c419c6..ce8d6d0293 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -276,6 +276,7 @@ typedef enum { OPC_VADD_VV = 0x57 | V_OPIVV, OPC_VADD_VI = 0x57 | V_OPIVI, OPC_VSUB_VV = 0x8000057 | V_OPIVV, + OPC_VRSUB_VI = 0xc000057 | V_OPIVI, OPC_VAND_VV = 0x24000057 | V_OPIVV, OPC_VAND_VI = 0x24000057 | V_OPIVI, OPC_VOR_VV = 0x28000057 | V_OPIVV, @@ -2367,6 +2368,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, set_vtype_len(s, type); tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1, -1); break; + case INDEX_op_neg_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a1, 0); + break; case INDEX_op_cmp_vec: tcg_out_cmpsel(s, type, vece, args[3], a0, a1, a2, c2, -1, true, 0, true); @@ -2397,6 +2402,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_or_vec: case INDEX_op_xor_vec: case INDEX_op_not_vec: + case INDEX_op_neg_vec: case INDEX_op_cmp_vec: case INDEX_op_cmpsel_vec: return 1; @@ -2550,6 +2556,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_dupm_vec: case INDEX_op_ld_vec: return C_O1_I1(v, r); + case INDEX_op_neg_vec: case INDEX_op_not_vec: return C_O1_I1(v, v); case INDEX_op_add_vec: From patchwork Wed Oct 16 19:31:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835824 Delivered-To: patch@linaro.org Received: by 2002:a5d:6804:0:b0:37d:45d0:187 with SMTP id w4csp604053wru; Wed, 16 Oct 2024 12:34:08 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWf9E9O93J1fZVMCTHHyXs739NncjlW7leaDsrjipU9QbIIwN+gHwGNWZpxuX0mjZFIcVTY8g==@linaro.org X-Google-Smtp-Source: AGHT+IGVOGIwCI/Z9tojdo6zY9mZXGHSrZFOdUduaB9ZZbHwOGSnuw7mKlQciIQ6zboHTaD0gqk1 X-Received: by 2002:a05:6214:5b82:b0:6cb:8339:3443 with SMTP id 6a1803df08f44-6cbf9d0cb9emr262465876d6.7.1729107248534; Wed, 16 Oct 2024 12:34:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729107248; cv=none; d=google.com; s=arc-20240605; b=K07l5xZrD1u0kUm1pgzwL79ucBselmA/nzGE03iINSb0GyxYu0N7+dxyqKDpBJLtIh 5CBNecY7LQ4pU+xrbp5PiiAWfQJ0x48Uvq56TfI0uT1kPV6PgwZlnonjDNZL42nOlJKp IL8T6lZfBRDnpXBnrhkeOF6Jt4iCTj0n8yhx55pkeELdWm5PlvkOpJs2WGS+9TsS9MIY +3rcU6UyG4RagIfHGWk9QOMknA1+5Y53lBN0oWhbtz2JLv8FAaH6J9hhkbOdtAgR1XHU Woe+WQjGPrRVtBJYRV5cPxLxR97wwlXTwH8JEJEHpJYgkySuqXI+yoY2Zti8wZsaPZRv t7rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dv6u2nNWkqx2QinOJ+QPs2qTyVh0lqH2PTx6QeDWZY8=; fh=q+UmP8eaNSfHMVi/tLyu+bWaEagrVMJ4PiBhkooBLxQ=; b=KJl0lvfh1LMyD6JX9obE3s6B/j6mdOtuUfF0e7KXgbZc0G90sM1sVGxS00iBXaAHJ2 qYWzPueiKS6C6G/P/YpXvSu29c7fVHvKRzudV+nERY072vm+j3JlXvhLKQgMaqgFpaRg NN5RusOwkPrEV1K05uIFPHbdJgFLUMbzAAG/+hxDZPJxj3cgCl9M1gVzVPLhtkfm4g+g J9iU4qj0PafT0hF6XxfFqWuigDIYNpmjiEIcAc0LbxrDyDfImWGQtyVo6IYbgW/sPmPn OXZsDWKGEVQ3d3EHX8h90qPaqrcAni1u7vIEdRQRvIZ9vb5qfj29kJM9I/pozc4S/EkI tgLw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uSSZKaA6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6cc22b93a1asi44594476d6.522.2024.10.16.12.34.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2024 12:34:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uSSZKaA6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t19kS-0002k8-07; Wed, 16 Oct 2024 15:31:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t19kN-0002gM-Ad for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:51 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t19kL-0003pk-7u for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:51 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-20ca7fc4484so1177025ad.3 for ; Wed, 16 Oct 2024 12:31:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729107108; x=1729711908; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dv6u2nNWkqx2QinOJ+QPs2qTyVh0lqH2PTx6QeDWZY8=; b=uSSZKaA6+KJoidJNDTv/ELK+EPe5RsWQVJwsPRivPBZRShEL390guUPWVyl5Qd95sK 51M9pqmQI0qv2O/bNIthBy6nvDE6FSckKb6iB7sKF/5fozv2aYfa9FxnOXR+i0e+Vaqe nG6D3XcotDqwZOxukONEB4pJxhGDUk17R87WE9Mehehi6CRcTvN4UYOWgBeGjlGvyQpm T1ydfoCD+0rtbgs8dvTDHX2tLbRnMf/OkbbH72uw0GrdliIeEdmXm6By3neiZ/O/eZRd OtNIvS1Lq42kzgle6sHk7iSyHIQoIHQ2BtFGN7a+iguP3RXCITVG3eN/KhxIR4v/A8ze O7IA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729107108; x=1729711908; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dv6u2nNWkqx2QinOJ+QPs2qTyVh0lqH2PTx6QeDWZY8=; b=L/F2I9dZ88VA4wJt9HKqQ+9/qgICVsUDuh2YVEGa7pm4x+RHTBjrxJ3qZT5N0/q1Ob VW9GDFaRlHSeScesLYa8wHy8skgwhycujwYAO1Agu/+kcSPDZZzN2mcua6X4fb+IjwMJ xFkL9OQ8imMHmlz0AXvln3DFW/KZgnyGqrzXHIJLKbH7+ZkyUIeeRlGz37u2Un76IRAR TCpjf2V/g9Z9W+Yfk38flDl59AOb1Yx0EKkPThnhWPgMKJEHXjlfxwPN9lWVfsdTDtL+ no+kuWUsySjfMDaPE4hdqxaDhR6GoDXLCE8kNO09IWK6Kzn1DXDtdbaRjdm1McHWxhrH QkLQ== X-Gm-Message-State: AOJu0YzuPRwe9NXaCLm5HFn5TbUiTDztjsYkq93pZyO+BJ9+rVp6Tp4v Nb/iX86NgBI9SyPQ4W6oBZcDZ1kfAJ9/EyUUI6OmXYh1ZEcN5ZlveMZB2eJjPZK8CJ8VT1txBfN L X-Received: by 2002:a17:902:e80d:b0:20c:7d7d:7ba8 with SMTP id d9443c01a7336-20cbb22f1e8mr232167085ad.46.1729107107502; Wed, 16 Oct 2024 12:31:47 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b6b1sm32323945ad.189.2024.10.16.12.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2024 12:31:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, zhiwei_liu@linux.alibaba.com Subject: [PATCH v6 09/14] tcg/riscv: Accept constant first argument to sub_vec Date: Wed, 16 Oct 2024 12:31:35 -0700 Message-ID: <20241016193140.2206352-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241016193140.2206352-1-richard.henderson@linaro.org> References: <20241016193140.2206352-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use vrsub.vi to subtract from a constant. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 8 ++++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index 97e6ecdb0f..d8ce5414f5 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -25,6 +25,7 @@ C_O0_I2(v, r) C_O1_I1(v, r) C_O1_I1(v, v) C_O1_I2(v, v, v) +C_O1_I2(v, vK, v) C_O1_I2(v, v, vK) C_O1_I2(v, v, vL) C_O1_I4(v, v, vL, vK, vK) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index ce8d6d0293..1ce2f291d3 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -2350,7 +2350,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_sub_vec: set_vtype_len_sew(s, type, vece); - tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2); + if (const_args[1]) { + tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a2, a1); + } else { + tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2); + } break; case INDEX_op_and_vec: set_vtype_len(s, type); @@ -2565,7 +2569,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_xor_vec: return C_O1_I2(v, v, vK); case INDEX_op_sub_vec: - return C_O1_I2(v, v, v); + return C_O1_I2(v, vK, v); case INDEX_op_cmp_vec: return C_O1_I2(v, v, vL); case INDEX_op_cmpsel_vec: From patchwork Wed Oct 16 19:31:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835827 Delivered-To: patch@linaro.org Received: by 2002:a5d:6804:0:b0:37d:45d0:187 with SMTP id w4csp604287wru; Wed, 16 Oct 2024 12:34:41 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVQEBTXzvIEAuPj2RUbirWedloOu9BdWzSQ3JG59XR6rvwXiSSs/Zc5NKcksyxxjmuQUyS+sA==@linaro.org X-Google-Smtp-Source: AGHT+IG7fiMBHNYhotwUVdCW2TjQWs7hMYZYGNpr0ReuhmdpQoaIkSKfZRiKLK1p3pFtCAJLPvFu X-Received: by 2002:a05:620a:4491:b0:7a9:b049:1c3c with SMTP id af79cd13be357-7b144ad226fmr554676885a.59.1729107281633; Wed, 16 Oct 2024 12:34:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729107281; cv=none; d=google.com; s=arc-20240605; b=dR1jGWIosuEyheAbRbgIKBz5/BQaYjWu2XuusFg9xFZKR8VzfanHr/yaVhzo1dydLO cJwqWUfyAtiyx9uKzNEsPl/412vPIa7zF66RBF06xR7B5qijWuatCr6zyuM9XRlo8tzR WiBTfHIdwlOY0WwSMt+3B9J1lNwTODndgwFMWXP5FsgW07ymVEwcLXn6j+ao/kDmtlKJ ZNURIsMMs/Ipk06jKcmOXlmYeOupuz3AgsrRwo5Gi+3GJ9ctteqyjRyz+Ny/b390jp8y RvXxsTLIx6dR01G6xOiDL5rsGsoXjy7Aw0A2VvXze80CuY6Ij/WIy8JX0pBpo0bDkZbx 73Tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dluUCaEndjBCunQfjOsd/2zhh5fJAnoMBhZPYS0jDTY=; fh=0y6cSxTabxslIGhKb2QlpT+4cpL34OsHjArvPUG+rq0=; b=HkjFm6cPAZr7YFPy8VPeyFUBv7pN1GyZWklBJRvIwtKosK1IuLIIVymJpOLWcnx/ma MHvN/40g1FjAv+ZG71IgjHXBTDuTFk2IXM2VEt5X6UrMdzknRNVmRykDUCqCiC87EW1p nv0bFrnCrKhUsrMsL9O69PxxbP3H0zZaK6oPBBuR+kkb/qyRWDcBmh1LlzUrvKBfrPgA HK14Ys14RPWMZNNMXQwxZEP1F19uyRERlvwrOafIzhvUsST/sfvbcfTIsmmxQhcxB4Tv 546BbuAIahkXWs1t0Rc4NQ0kjqiQJB8c/lgWy/QI4YeTmaEjwFFnCsAz4vfeTMKCgm+P 46bA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s7GsZPax; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4607b4f5c56si46613581cf.767.2024.10.16.12.34.41 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2024 12:34:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s7GsZPax; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t19kT-0002lZ-H9; Wed, 16 Oct 2024 15:31:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t19kO-0002hf-Pq for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:53 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t19kL-0003pu-MT for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:52 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-20c6f492d2dso2155405ad.0 for ; Wed, 16 Oct 2024 12:31:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729107108; x=1729711908; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dluUCaEndjBCunQfjOsd/2zhh5fJAnoMBhZPYS0jDTY=; b=s7GsZPaxxkxY9mrAShlFoEkdDaGA1fSqSQsCnG55hHPlVJHxhJV9kRBdu0QmG4jvcc c0pGWoeNEcBwR7xrmcUhe+mMpHaU+Q2eQAqvbl3rVmfJ1L6RbZuKPwUQxVSm6QysqLjw I632etlBZi/UQOgpLoXDFApfNz/MD94VwSaxQmzGy3/5Dtl9CwZJZQ5HyWniinaMjqrX e5iT7vEeL4bLLGVm7UNE69zWUP7H53mMgN6+EFz9gRHWdqqJQRCJoPmfnXBBuDmg4Dqj dLe4hB7+RC2EL/dFz+R+wZGma2LaDIQhyra3zgy3DbKW2daZ6jmG0gux/VjE1yhQkr96 ECYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729107108; x=1729711908; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dluUCaEndjBCunQfjOsd/2zhh5fJAnoMBhZPYS0jDTY=; b=vcTTbQi9G3hOYjsQWPe2dbdhneiykqrxxtb5Inzxa0cAhhxJOJtRX5rWCpD4xXpPf6 RtwLgB2S6wncKh6f6dPbzWhr7u5GwSWYW3RF62BeLhYpJ1hfEx63iWWmlodyN3D5/Wp3 QektMdAVAb+Ndo9LnAF4s/7aH9lojjyON6NtoEnkJlTrgu5gUSwlw52cjRqBRAe+hLTJ QBc8FycN3csI9fB1w/b6oMfYcxp/TZ/AGvgiIktiFPMZbsXhIlNenhcDmCE/rwHFDTpa 01XEMMvtzt8jyOAMo0ZTSvieS9ox3X0dKN7i679HsVMrEToJB5JVOCX4MYxGfl2cs3jz GRYw== X-Gm-Message-State: AOJu0YwpEeNUOLjjiyiZwwCbwrb+BtSWgFMRh7Dw2Hy+mDVV5fZzlYRl WnbqcoRHwpMlQjNVe+6ijR2Qp5V4mtEYOrHwRmiBO5agKSbfsyRPnaKX+qWan14j5EbnkM+Ajnx U X-Received: by 2002:a17:902:e951:b0:20b:59be:77b with SMTP id d9443c01a7336-20cbb1a9654mr260092385ad.6.1729107108225; Wed, 16 Oct 2024 12:31:48 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b6b1sm32323945ad.189.2024.10.16.12.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2024 12:31:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v6 10/14] tcg/riscv: Implement vector sat/mul ops Date: Wed, 16 Oct 2024 12:31:36 -0700 Message-ID: <20241016193140.2206352-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241016193140.2206352-1-richard.henderson@linaro.org> References: <20241016193140.2206352-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Message-ID: <20241007025700.47259-9-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 4 ++-- tcg/riscv/tcg-target.c.inc | 41 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index ae10381e02..1d4d8878ce 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -160,8 +160,8 @@ typedef enum { #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 -#define TCG_TARGET_HAS_mul_vec 0 -#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_mul_vec 1 +#define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 1 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 1ce2f291d3..4758555565 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -284,6 +284,16 @@ typedef enum { OPC_VXOR_VV = 0x2c000057 | V_OPIVV, OPC_VXOR_VI = 0x2c000057 | V_OPIVI, + OPC_VMUL_VV = 0x94000057 | V_OPMVV, + OPC_VSADD_VV = 0x84000057 | V_OPIVV, + OPC_VSADD_VI = 0x84000057 | V_OPIVI, + OPC_VSSUB_VV = 0x8c000057 | V_OPIVV, + OPC_VSSUB_VI = 0x8c000057 | V_OPIVI, + OPC_VSADDU_VV = 0x80000057 | V_OPIVV, + OPC_VSADDU_VI = 0x80000057 | V_OPIVI, + OPC_VSSUBU_VV = 0x88000057 | V_OPIVV, + OPC_VSSUBU_VI = 0x88000057 | V_OPIVI, + OPC_VMSEQ_VV = 0x60000057 | V_OPIVV, OPC_VMSEQ_VI = 0x60000057 | V_OPIVI, OPC_VMSEQ_VX = 0x60000057 | V_OPIVX, @@ -2376,6 +2386,26 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, set_vtype_len_sew(s, type, vece); tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a1, 0); break; + case INDEX_op_mul_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv(s, OPC_VMUL_VV, a0, a1, a2); + break; + case INDEX_op_ssadd_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv_vi(s, OPC_VSADD_VV, OPC_VSADD_VI, a0, a1, a2, c2); + break; + case INDEX_op_sssub_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv_vi(s, OPC_VSSUB_VV, OPC_VSSUB_VI, a0, a1, a2, c2); + break; + case INDEX_op_usadd_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv_vi(s, OPC_VSADDU_VV, OPC_VSADDU_VI, a0, a1, a2, c2); + break; + case INDEX_op_ussub_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv_vi(s, OPC_VSSUBU_VV, OPC_VSSUBU_VI, a0, a1, a2, c2); + break; case INDEX_op_cmp_vec: tcg_out_cmpsel(s, type, vece, args[3], a0, a1, a2, c2, -1, true, 0, true); @@ -2407,6 +2437,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_xor_vec: case INDEX_op_not_vec: case INDEX_op_neg_vec: + case INDEX_op_mul_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: case INDEX_op_cmp_vec: case INDEX_op_cmpsel_vec: return 1; @@ -2567,9 +2602,15 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_and_vec: case INDEX_op_or_vec: case INDEX_op_xor_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: return C_O1_I2(v, v, vK); case INDEX_op_sub_vec: return C_O1_I2(v, vK, v); + case INDEX_op_mul_vec: + return C_O1_I2(v, v, v); case INDEX_op_cmp_vec: return C_O1_I2(v, v, vL); case INDEX_op_cmpsel_vec: From patchwork Wed Oct 16 19:31:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835823 Delivered-To: patch@linaro.org Received: by 2002:a5d:6804:0:b0:37d:45d0:187 with SMTP id w4csp604041wru; Wed, 16 Oct 2024 12:34:07 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXzyL37big/HdGfGhiV34DEmwygYJr7aHkYekqT4XNL0s5mVAyXfMRd+ewXDanUDPLQ7iMsJg==@linaro.org X-Google-Smtp-Source: AGHT+IF5oN+8vMIjDQ0v9DN0rqZdHrhEULclcky9DbslVQFnBIUaOWcTe0Fd6kpeJnvARVDa8cJg X-Received: by 2002:a05:622a:40c6:b0:458:4b8b:1517 with SMTP id d75a77b69052e-4608a4e3967mr70148141cf.18.1729107246752; Wed, 16 Oct 2024 12:34:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729107246; cv=none; d=google.com; s=arc-20240605; b=AlzfJPfh8PXsL6zyOWktD78dCagqTojK1AoSAKcHu4MDsAFSwl8LxWcOTMfqnKSQC0 JtQUgRhYrdpWHRwIjvhv4zDHbVS8Qyae0thEhopqw0SWylRz7pPeYddPq0ssJZYrRTMF oSZ9e4unsZT5H6pKs50Nb2ggbelXOUGMRpk6iYJrSkeH5GrceH/bd/f76t8ZNaIEOKZW 9Y5bX4RpeFE+nyRjymk50kE2HCdKvZcon5bQRj6RklVxxp7UR8dyLhQvG4IxI5yCQU05 bw93RcVgXP3ZckG7FtqoUrQbnYFPIPXVhye+HKEXk2zam9/KU16n0XDCtJs902OQN6WT zeLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=C2l5tEjtrAAJ1z36wG6T8MRNWs0qyEl5t+tOFHscABs=; fh=0y6cSxTabxslIGhKb2QlpT+4cpL34OsHjArvPUG+rq0=; b=js+TFtVyfLZtliJBATdAHsCpcRpv1wjdVNHDxFEaOY1hdc+sBwEB+EwZ7kAwVNr7zH Ewa7d20RDerk4MezbcRdyfCPVT1MhcS45u5xxE9Ij9m8KrYyJhK7B+yJHLjw7cZ0bSVg ISTkDdVFbSbZVIuk6RnLfWtQdVXNzNb/wXEtgX5Li3mIJ5jlk8UN0nkv4gv2UnnTLwwB WWH8g/LdJSwNWJ47YM0X4plQvfvCbqoOyFzNEMnr/7uX+xVdd8JBbLBvgKawqruaPUOO 1JcC6/H4g6sdMpusirAN7KZnnBbfHkFkxgEKeRAEGb5rxlzrQj3HpN4WVhQNOC+eB1gQ T+8w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YEc4eecF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4607eb17f53si39631681cf.318.2024.10.16.12.34.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2024 12:34:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YEc4eecF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t19kW-0002om-1d; Wed, 16 Oct 2024 15:32:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t19kO-0002hp-Up for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:53 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t19kM-0003qJ-DW for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:52 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-20cb7139d9dso1607465ad.1 for ; Wed, 16 Oct 2024 12:31:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729107109; x=1729711909; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C2l5tEjtrAAJ1z36wG6T8MRNWs0qyEl5t+tOFHscABs=; b=YEc4eecFzjc5UTf7feocWov9uKgZADCErmCJeQxkaLByEg48OWCzE4WM5SKwzaEMzp C4/DUsexNIDFyyJKX3goC9deYRPbEabtvdyPXRx8dZQDp8FQGU6Do0ojQGbWxtXsgmFz /kk+nkt2cE3j+HS70wXvrVq2EhkLSTsmlU6EdU6AmC3nBjBQNI3LEx8DF7aHALhMwIcq GgFTtE7ziEJdfrpvwG8UuTi/Q9ubPztfRVNq8u5WgAwKTh0/Z/NF3glGaPgkgtbBMr9/ cRU6vd0CqI8e85mP22IhlfzkH5U3lC/wH2Pl1xmPAmDo2vCOP8g/PFV1xwIhnrl0Ifur zNSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729107109; x=1729711909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C2l5tEjtrAAJ1z36wG6T8MRNWs0qyEl5t+tOFHscABs=; b=RbZh/gRR5I1YNKzDq8a3kS9THQYagk4U4JYXANG1XMX7DUAeg9uwx93ToM3PgKgTyr UWwNt+k0B/VhSCSQf+bcJGP5reFTrOanN//0guSKCs3Dz22neQGsl1LGaPwz/M9CY4RV QAPRjQV941dY+drqn3iA5a3mIunyoxQG+arg/Sz80JH8Pwat8DnfZvz7Fn4/Wd2Uh3vY A36Wp8U4A9GrogZxG3k4VHya+XbkFwzdZKVD30idChPvNeClJPnAoIVtbrhVmHeqonE8 2fHNU3t8xP2OTJWawN/pj0gQEF4Yt4N+ucHWM7+vB/f71HY3eCMkH/oq7srB++HN8NoR iHBQ== X-Gm-Message-State: AOJu0Yw0wRRNbxCxscs0wF/vVklp5b0VYs8vvdLDX7i/6Gm4JnLNm2rV gBPDaJ51nyyN/a6waWfIjGZiqt83qJo2An9ewchLfJaHT7OZyMAew6pZrGpiX/hD3ASMthOD5JA I X-Received: by 2002:a17:902:e802:b0:20c:bcd8:5ccb with SMTP id d9443c01a7336-20d27ecae36mr59790865ad.30.1729107108896; Wed, 16 Oct 2024 12:31:48 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b6b1sm32323945ad.189.2024.10.16.12.31.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2024 12:31:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v6 11/14] tcg/riscv: Implement vector min/max ops Date: Wed, 16 Oct 2024 12:31:37 -0700 Message-ID: <20241016193140.2206352-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241016193140.2206352-1-richard.henderson@linaro.org> References: <20241016193140.2206352-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Message-ID: <20241007025700.47259-10-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 2 +- tcg/riscv/tcg-target.c.inc | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 1d4d8878ce..7005099810 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -162,7 +162,7 @@ typedef enum { #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 -#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 1 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 4758555565..35b244b7a2 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -294,6 +294,15 @@ typedef enum { OPC_VSSUBU_VV = 0x88000057 | V_OPIVV, OPC_VSSUBU_VI = 0x88000057 | V_OPIVI, + OPC_VMAX_VV = 0x1c000057 | V_OPIVV, + OPC_VMAX_VI = 0x1c000057 | V_OPIVI, + OPC_VMAXU_VV = 0x18000057 | V_OPIVV, + OPC_VMAXU_VI = 0x18000057 | V_OPIVI, + OPC_VMIN_VV = 0x14000057 | V_OPIVV, + OPC_VMIN_VI = 0x14000057 | V_OPIVI, + OPC_VMINU_VV = 0x10000057 | V_OPIVV, + OPC_VMINU_VI = 0x10000057 | V_OPIVI, + OPC_VMSEQ_VV = 0x60000057 | V_OPIVV, OPC_VMSEQ_VI = 0x60000057 | V_OPIVI, OPC_VMSEQ_VX = 0x60000057 | V_OPIVX, @@ -2406,6 +2415,22 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, set_vtype_len_sew(s, type, vece); tcg_out_opc_vv_vi(s, OPC_VSSUBU_VV, OPC_VSSUBU_VI, a0, a1, a2, c2); break; + case INDEX_op_smax_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv_vi(s, OPC_VMAX_VV, OPC_VMAX_VI, a0, a1, a2, c2); + break; + case INDEX_op_smin_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv_vi(s, OPC_VMIN_VV, OPC_VMIN_VI, a0, a1, a2, c2); + break; + case INDEX_op_umax_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv_vi(s, OPC_VMAXU_VV, OPC_VMAXU_VI, a0, a1, a2, c2); + break; + case INDEX_op_umin_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv_vi(s, OPC_VMINU_VV, OPC_VMINU_VI, a0, a1, a2, c2); + break; case INDEX_op_cmp_vec: tcg_out_cmpsel(s, type, vece, args[3], a0, a1, a2, c2, -1, true, 0, true); @@ -2442,6 +2467,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: case INDEX_op_cmp_vec: case INDEX_op_cmpsel_vec: return 1; @@ -2606,6 +2635,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return C_O1_I2(v, v, vK); case INDEX_op_sub_vec: return C_O1_I2(v, vK, v); From patchwork Wed Oct 16 19:31:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835819 Delivered-To: patch@linaro.org Received: by 2002:a5d:6804:0:b0:37d:45d0:187 with SMTP id w4csp603760wru; Wed, 16 Oct 2024 12:33:17 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXA/9EM24uwBll4nGMOknu7i/awm3w7OWg4liPl4DHJAqWflyObqSxQY54+FfvPczDccTjG7g==@linaro.org X-Google-Smtp-Source: AGHT+IH65TayO1FZUjIBnlJTDrpqmEEnLOhkWeSrjjR4MGr9a70HLYInL/sfZB9R7xSgC3dlm/LB X-Received: by 2002:a05:620a:41c:b0:7b1:43d7:12a8 with SMTP id af79cd13be357-7b143d71542mr350927285a.8.1729107196840; Wed, 16 Oct 2024 12:33:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729107196; cv=none; d=google.com; s=arc-20240605; b=hL/ZQwECWz8CxT0rpYa3mdCADxqZeBMI/dlN6lwtcCqoANhUrOe/JlWVPF7WVr7i2y nliAXKF0mUja2xYcw2ZyGfGMtkl9H1bV9CSqOEjwzLM8KObj7L50ZH7z2V+IgixDJwL/ K7XrtcVePOsR2oQ5ANa4LdGBrJ4ue1klJV/SWf37o8rVqy7SfpIxSMbKPW1vHXPcd0Qr N/ga1i4qIvhNVgxjc7iYT5hSyDQK11EUyqX/y3h6GAlbgAaKHmzWY8Mnu0Ofm3UsnhC3 rhzpMROjO654elDo+HXHiVHWiT5OrcvntQM4Jo/QITn+ZHX+d3niBwtIg9P6HSMd7ZqY pM1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=aQsTX6H4v2TuWOGDvoBRa/6B8ljDNLzgCo0hPVyXZRg=; fh=0y6cSxTabxslIGhKb2QlpT+4cpL34OsHjArvPUG+rq0=; b=RBj+rlZR0/RKHDxIsXNQUREkgFFq4TYJIjkOsdJStWm+2Onlkjjzi2ESUZus2CWKUo JGDQPpo4Lk5kMObsbqVcaNBq8WTB42rdDVxB1OlJcYWx8Xx2owc3GOm+DOOiJ6Hiqv0Z yzNTLFoDQJMuSnidJM1sFbPiXQOY3xiPKYQnsz6yos1o68Q/fFhZ8HkZnIVx5byffEbi Cf5QoAtw2fmiNP2v15/w0QVcKRb9ME3glbLixUuNL0y73eCZOUw24GxczOC9gXrlfuW9 gk0dOk0JjJuKa4sepvE/QcQ4uCQbY/SbzFR0NNg6vzDpLvys7W8+XNKmUWini1YN01eg Z5aA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kFC7ZsLO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7b149b2eb27si113962485a.85.2024.10.16.12.33.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2024 12:33:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kFC7ZsLO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t19kU-0002nG-Aw; Wed, 16 Oct 2024 15:31:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t19kP-0002iL-RZ for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:53 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t19kM-0003qi-Ve for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:53 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-20cf3e36a76so1930315ad.0 for ; Wed, 16 Oct 2024 12:31:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729107110; x=1729711910; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aQsTX6H4v2TuWOGDvoBRa/6B8ljDNLzgCo0hPVyXZRg=; b=kFC7ZsLOYxsv7E3SsGqNKYE4EIuLx7grBb6kENxNXhih1WZP3cqbgPjbCHTBLyxGqY dvh42AdwspO5xxSlb78uKw8fHvGgZ/kyLdRoQDRe1k98HRu2pzkeAjO9W/GWmv4BHGWq klsI0k/3w+jSzKmGcArX3ctK65+dJUycRlhkly0Eh8csjfRYQVFyhcF26OrAGySpv6KD nBqBDcFA9kUdQ1HK1xe3GIYglnRAKCNTNTumG2ZaWIAR5PjwhKT8RL6WQQCdyxV/1Vm9 Nbe3AS9CeODgaMu/oIBeeI5nwCO3VjHW8oZVe1HZMoA3k5Pueag+FvKrsIRqYYl/2GTH I+rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729107110; x=1729711910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aQsTX6H4v2TuWOGDvoBRa/6B8ljDNLzgCo0hPVyXZRg=; b=VBuDR6tYJB/qcVSgdYKOKShA4TtRXqEiUQYZ/MTheCaVodEbPk3ipn96uc+Za9fnQO vXygExdfdxB2ZeWlNltFnxmcMJltSXtqBFVSeUUlQwZFW+PN5LRcH5UhqTvXK8bm+NGq AKhHHqmeFwnq7WZG7smoCyk61AxCiJLTK9SQEU47sdEhedKTlyuNaXQLPEgv6xj9AfhF FO/HbpiTJEba3ufYBUSEKKvsFtXYnXmTjp3wuzsFfUULjdOSOh3jEHELHwpfkTL/ZFsz VdBTgaHT/XoIR0bqPPLnTTLLDGkZ6aQgcKO+IVeW7VPxSJq4FMwfGhD7bJMTKuEElvMm cSLQ== X-Gm-Message-State: AOJu0YzCrsiFwOzlm0k3z+8bd2j68N+PVXDSyXkG4R/ekNmXCvmEomrM ZAjtiMTYfPIs1gVQzTBycbaagyRq0CywxttbsEYLESXbKoYercoLDfr2g2vkTDmrn3rdXVyRqN7 6 X-Received: by 2002:a17:903:40ce:b0:20c:70ab:b9c3 with SMTP id d9443c01a7336-20ca147b50dmr207874865ad.34.1729107109662; Wed, 16 Oct 2024 12:31:49 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b6b1sm32323945ad.189.2024.10.16.12.31.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2024 12:31:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v6 12/14] tcg/riscv: Implement vector shi/s/v ops Date: Wed, 16 Oct 2024 12:31:38 -0700 Message-ID: <20241016193140.2206352-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241016193140.2206352-1-richard.henderson@linaro.org> References: <20241016193140.2206352-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Message-ID: <20241007025700.47259-11-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.h | 6 +-- tcg/riscv/tcg-target.c.inc | 76 ++++++++++++++++++++++++++++++++++ 3 files changed, 80 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index d8ce5414f5..3c4ef44eb0 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -24,6 +24,7 @@ C_O2_I4(r, r, rZ, rZ, rM, rM) C_O0_I2(v, r) C_O1_I1(v, r) C_O1_I1(v, v) +C_O1_I2(v, v, r) C_O1_I2(v, v, v) C_O1_I2(v, vK, v) C_O1_I2(v, v, vK) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 7005099810..76d30e789b 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -157,9 +157,9 @@ typedef enum { #define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 -#define TCG_TARGET_HAS_shi_vec 0 -#define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_shi_vec 1 +#define TCG_TARGET_HAS_shs_vec 1 +#define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 35b244b7a2..2c78ea6507 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -326,6 +326,16 @@ typedef enum { OPC_VMSGT_VI = 0x7c000057 | V_OPIVI, OPC_VMSGT_VX = 0x7c000057 | V_OPIVX, + OPC_VSLL_VV = 0x94000057 | V_OPIVV, + OPC_VSLL_VI = 0x94000057 | V_OPIVI, + OPC_VSLL_VX = 0x94000057 | V_OPIVX, + OPC_VSRL_VV = 0xa0000057 | V_OPIVV, + OPC_VSRL_VI = 0xa0000057 | V_OPIVI, + OPC_VSRL_VX = 0xa0000057 | V_OPIVX, + OPC_VSRA_VV = 0xa4000057 | V_OPIVV, + OPC_VSRA_VI = 0xa4000057 | V_OPIVI, + OPC_VSRA_VX = 0xa4000057 | V_OPIVX, + OPC_VMV_V_V = 0x5e000057 | V_OPIVV, OPC_VMV_V_I = 0x5e000057 | V_OPIVI, OPC_VMV_V_X = 0x5e000057 | V_OPIVX, @@ -1551,6 +1561,17 @@ static void tcg_out_cmpsel(TCGContext *s, TCGType type, unsigned vece, } } +static void tcg_out_vshifti(TCGContext *s, RISCVInsn opc_vi, RISCVInsn opc_vx, + TCGReg dst, TCGReg src, unsigned imm) +{ + if (imm < 32) { + tcg_out_opc_vi(s, opc_vi, dst, src, imm); + } else { + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP0, imm); + tcg_out_opc_vx(s, opc_vx, dst, src, TCG_REG_TMP0); + } +} + static void init_setting_vtype(TCGContext *s) { s->riscv_cur_type = TCG_TYPE_COUNT; @@ -2431,6 +2452,42 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, set_vtype_len_sew(s, type, vece); tcg_out_opc_vv_vi(s, OPC_VMINU_VV, OPC_VMINU_VI, a0, a1, a2, c2); break; + case INDEX_op_shls_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vx(s, OPC_VSLL_VX, a0, a1, a2); + break; + case INDEX_op_shrs_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vx(s, OPC_VSRL_VX, a0, a1, a2); + break; + case INDEX_op_sars_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vx(s, OPC_VSRA_VX, a0, a1, a2); + break; + case INDEX_op_shlv_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv(s, OPC_VSLL_VV, a0, a1, a2); + break; + case INDEX_op_shrv_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv(s, OPC_VSRL_VV, a0, a1, a2); + break; + case INDEX_op_sarv_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv(s, OPC_VSRA_VV, a0, a1, a2); + break; + case INDEX_op_shli_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_vshifti(s, OPC_VSLL_VI, OPC_VSLL_VX, a0, a1, a2); + break; + case INDEX_op_shri_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_vshifti(s, OPC_VSRL_VI, OPC_VSRL_VX, a0, a1, a2); + break; + case INDEX_op_sari_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_vshifti(s, OPC_VSRA_VI, OPC_VSRA_VX, a0, a1, a2); + break; case INDEX_op_cmp_vec: tcg_out_cmpsel(s, type, vece, args[3], a0, a1, a2, c2, -1, true, 0, true); @@ -2471,6 +2528,15 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + case INDEX_op_sars_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + case INDEX_op_shri_vec: + case INDEX_op_shli_vec: + case INDEX_op_sari_vec: case INDEX_op_cmp_vec: case INDEX_op_cmpsel_vec: return 1; @@ -2626,6 +2692,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) return C_O1_I1(v, r); case INDEX_op_neg_vec: case INDEX_op_not_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + case INDEX_op_sari_vec: return C_O1_I1(v, v); case INDEX_op_add_vec: case INDEX_op_and_vec: @@ -2643,7 +2712,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_sub_vec: return C_O1_I2(v, vK, v); case INDEX_op_mul_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return C_O1_I2(v, v, v); + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + case INDEX_op_sars_vec: + return C_O1_I2(v, v, r); case INDEX_op_cmp_vec: return C_O1_I2(v, v, vL); case INDEX_op_cmpsel_vec: From patchwork Wed Oct 16 19:31:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835826 Delivered-To: patch@linaro.org Received: by 2002:a5d:6804:0:b0:37d:45d0:187 with SMTP id w4csp604067wru; Wed, 16 Oct 2024 12:34:10 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVFfq1ch/A5V2cemk97dRIyuvK6iRG2jM2Q6L7ZrJ46oAIj9ji/Ox7CAXPqbhGIfk6tHe7Cxw==@linaro.org X-Google-Smtp-Source: AGHT+IH7XhUz66+r+3zuvHf2hQnuO/Xb6//h2Jc0bRqwEJH2xq+0Xtgtdh7TeqBXlJ7rTAMBnyMj X-Received: by 2002:a05:620a:319c:b0:7ac:c348:6a52 with SMTP id af79cd13be357-7b11a387137mr2906782685a.34.1729107250660; Wed, 16 Oct 2024 12:34:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729107250; cv=none; d=google.com; s=arc-20240605; b=XjjUo4Dt7Wp7Jn9eTFom31m2IuoCRa4KX033qbPzCdDjBhWGDQ0sa4z+IgeuhTK6rz MvGPNytiSBAp8Le8Lamgh28V8kGBz8FEfKEHueEY7BA3Cgz5dCSUOqxU40w02QNqr0aj Mk3nwBjIxWrFAhYcCPDn+QR/Dj1E5AReKRFzWKY0Zizfxmr7CB4HsZbK7UnUTr8uui/D owJwAnC+MaQZ3knHPJjPmielAwsXP9YFT2EDnDREjgpD//hznkhpNmrQ+u0KR8PdnQT8 bMEtpsSb7Yt3elKKb4w4+1P+5ppfUTBvm/GfMw4RVJcTu03QTMYNiZkTtclYoEJMXM8s cTXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6H4o7TRLnsRJPcQeLHBRIU6aVhm6+5BjLCNGhX0wWuw=; fh=0y6cSxTabxslIGhKb2QlpT+4cpL34OsHjArvPUG+rq0=; b=ZCR/8scZRaRyb3aelWofN/wQjbeFcVSP4UTvK6kG6uHVmaRZOdAGj0Dzr2P45Wo4wh yTEn++k8ppXOGK2Whfm7dbd6cUXcafBZabRNKJPlssCNdhBv7z721L3GrgmkX1QoWZQj I4EAJuX0SLkAEDCfMjHEjL7zxwg0sQVzNgiomSEiQRICLJbTnfbCkt96nFKHEJ6mE1ut 4sGiBVO67B5+uUn+bnvPPdDNYa4uuSN/uWyhTloli10pKBZzqBMgUd9bR4Llh2x2m7ud qACT24k2N2rJGPkHrGR3LEwKgCQc3zY2dzntT8ZwK1do61KwIqx6VJRs5HrdoK4MaDsE kpsQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="L/o/rlEy"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7b14b35e42csi68884385a.255.2024.10.16.12.34.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2024 12:34:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="L/o/rlEy"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t19kU-0002nh-RG; Wed, 16 Oct 2024 15:31:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t19kQ-0002jH-Bl for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:54 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t19kN-0003qv-P6 for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:54 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-20cd76c513cso1609515ad.3 for ; Wed, 16 Oct 2024 12:31:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729107110; x=1729711910; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6H4o7TRLnsRJPcQeLHBRIU6aVhm6+5BjLCNGhX0wWuw=; b=L/o/rlEyhNAgVGjyorwnpU9hcJ1k5Bt6wx4/7ml0DJR0EOVQ8HEejeYCEriUGYTT96 TyTWkeqp6T2VVx9uuDY/W89WGgFFZqZbiNpB9iSMcAY4AUQhvNAkxrL3GJXpwx5Lqn57 XhkX88AdHrzcKD0lb7+Vyq41jP7eMVra04bR9CksqzP7DE8+KNbBsG/WxH+DCh7Kr2cZ qlu92xaA7FG9TcJ0y8P2lDXnjGC8ABvx/1OX5wkVyT+0Im7TpB8QU6fey3XLvNR0g0br vZz05+CZsV3sLgrUsuc8g7udE8yMLi0vHgCl+8zZHTCEZIeU1Cdag/656096jI10w9lr E9wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729107110; x=1729711910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6H4o7TRLnsRJPcQeLHBRIU6aVhm6+5BjLCNGhX0wWuw=; b=Q5au1bL37YngM5TnYOUmDApoMm4HRgp//Ee7wMUPLDrjpHq5KC+mhy8cfG5LP2utdx yGOKufON80XHZMSZHlgTgYPlCxV20qliEez8HcRXiXCX9xOgsdZnGI7TyGHK+THZRUrs g5YPCIZ1Jo6TePH+Mm7qIcP9u0/peIrlBWth5k8hdn5KBzqGAsyPVYHVmQPyrbvpJvkE vKsDDrjIunlAHgnJP6dhSb+LvfRMravAOpApUm2rNeQARMWyn+bW1zkXE6OzpBajmTab Jv1FF3mdJIoNMt4OdZrB1rklX+OgNBYhdScNti9+EDegLPDig4KIiy/1NhZqrdq+RBtN SHUg== X-Gm-Message-State: AOJu0YyM3R72+abYrJprrxuIpaNSFaut3FE1QmNTdY0qDUfnigLx/tDl BlCUTMJWBkSTeABP54sK7JJhOGLaaOxZvuRFevl8Vkwi+usBAmiwmXP5sO1zjYu8DSs1waCdPtO F X-Received: by 2002:a17:902:ce09:b0:20d:2e83:6995 with SMTP id d9443c01a7336-20d2e836aa1mr57558115ad.47.1729107110253; Wed, 16 Oct 2024 12:31:50 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b6b1sm32323945ad.189.2024.10.16.12.31.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2024 12:31:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v6 13/14] tcg/riscv: Implement vector roti/v/x ops Date: Wed, 16 Oct 2024 12:31:39 -0700 Message-ID: <20241016193140.2206352-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241016193140.2206352-1-richard.henderson@linaro.org> References: <20241016193140.2206352-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Message-ID: <20241007025700.47259-12-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 6 +++--- tcg/riscv/tcg-target.c.inc | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 76d30e789b..e6d66cd1b9 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -154,9 +154,9 @@ typedef enum { #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_abs_vec 0 -#define TCG_TARGET_HAS_roti_vec 0 -#define TCG_TARGET_HAS_rots_vec 0 -#define TCG_TARGET_HAS_rotv_vec 0 +#define TCG_TARGET_HAS_roti_vec 1 +#define TCG_TARGET_HAS_rots_vec 1 +#define TCG_TARGET_HAS_rotv_vec 1 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 2c78ea6507..f8331e4688 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -2488,6 +2488,34 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, set_vtype_len_sew(s, type, vece); tcg_out_vshifti(s, OPC_VSRA_VI, OPC_VSRA_VX, a0, a1, a2); break; + case INDEX_op_rotli_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_vshifti(s, OPC_VSLL_VI, OPC_VSLL_VX, TCG_REG_V0, a1, a2); + tcg_out_vshifti(s, OPC_VSRL_VI, OPC_VSRL_VX, a0, a1, + -a2 & ((8 << vece) - 1)); + tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0); + break; + case INDEX_op_rotls_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vx(s, OPC_VSLL_VX, TCG_REG_V0, a1, a2); + tcg_out_opc_reg(s, OPC_SUBW, TCG_REG_TMP0, TCG_REG_ZERO, a2); + tcg_out_opc_vx(s, OPC_VSRL_VX, a0, a1, TCG_REG_TMP0); + tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0); + break; + case INDEX_op_rotlv_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vi(s, OPC_VRSUB_VI, TCG_REG_V0, a2, 0); + tcg_out_opc_vv(s, OPC_VSRL_VV, TCG_REG_V0, a1, TCG_REG_V0); + tcg_out_opc_vv(s, OPC_VSLL_VV, a0, a1, a2); + tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0); + break; + case INDEX_op_rotrv_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vi(s, OPC_VRSUB_VI, TCG_REG_V0, a2, 0); + tcg_out_opc_vv(s, OPC_VSLL_VV, TCG_REG_V0, a1, TCG_REG_V0); + tcg_out_opc_vv(s, OPC_VSRL_VV, a0, a1, a2); + tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0); + break; case INDEX_op_cmp_vec: tcg_out_cmpsel(s, type, vece, args[3], a0, a1, a2, c2, -1, true, 0, true); @@ -2537,6 +2565,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_shri_vec: case INDEX_op_shli_vec: case INDEX_op_sari_vec: + case INDEX_op_rotls_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: + case INDEX_op_rotli_vec: case INDEX_op_cmp_vec: case INDEX_op_cmpsel_vec: return 1; @@ -2695,6 +2727,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: + case INDEX_op_rotli_vec: return C_O1_I1(v, v); case INDEX_op_add_vec: case INDEX_op_and_vec: @@ -2715,10 +2748,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: return C_O1_I2(v, v, v); case INDEX_op_shls_vec: case INDEX_op_shrs_vec: case INDEX_op_sars_vec: + case INDEX_op_rotls_vec: return C_O1_I2(v, v, r); case INDEX_op_cmp_vec: return C_O1_I2(v, v, vL); From patchwork Wed Oct 16 19:31:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 835832 Delivered-To: patch@linaro.org Received: by 2002:a5d:6804:0:b0:37d:45d0:187 with SMTP id w4csp604799wru; Wed, 16 Oct 2024 12:36:03 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXN6HfakyDWFO9j+d0G5ivKTNzQsX/Y/RHAhoRfbSspLpfsG4GE8Dn/cb+HNvYZVGQUbqKTyA==@linaro.org X-Google-Smtp-Source: AGHT+IEO7SjjD4OlVb7CaxhsIJO+BLg7t2wPJcPvypzG72Wp5+Z7FqBCS3QqYVpMHcCKxi6k2CuO X-Received: by 2002:a05:622a:293:b0:45f:784:1b5d with SMTP id d75a77b69052e-4604bbc0714mr254567501cf.24.1729107363040; Wed, 16 Oct 2024 12:36:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729107363; cv=none; d=google.com; s=arc-20240605; b=ZRy2a74oedxyHZEViAiZypsC2yvQHRheCP+LAzhvSdYIESEI/JpYnqK2rvRkW2S+7F 6oxibgM9bbR45Wrh+/tQgT4fCZl8d2MihpYq1o/El+Pc5gaaC9R98+ZWWNV4WfQ8Us57 LC3oHwUplxCpUOOYn05F6eg9eLMCHrE7IPGKLkqgWUksm/WC/JeX9jsUz2cR69IEK6BO oGOrb1cav8zafQgmPhGZm8dV8i8s26CgbOVFNskQN6qxrw3nToGpxO8y/WA+/6Z2bk0w RKNNzwnb28N9YlPpNLUvdKLx4fE4K4/BSdPilNIALLV3MggDslIPw6dDvDDWW/kPMc6U Fafw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9wtdGS6j59IEw6lp5Sp3jQrC+uEbTCdVdwYMkROoHlk=; fh=0y6cSxTabxslIGhKb2QlpT+4cpL34OsHjArvPUG+rq0=; b=ZpzwH7VoRmy8Ef+WBtX6J1YPIU1f1WAFivezP/geVdw/XCAY/APhMqUi9+wH3v6CgK fGQqs5enm881aLVNoGifBOhsgsAfH4xRIbZRQpGV5QhdzWyjf60ORuwLNKSUPKYjFMKa QVmi8y94Ca+oAabMABoeEyswiXKRGtUhw19fk1wtZBEeR5h+0GlgSA6KV1+KRC6LhkEa MnjQYu9PSfbAfUTmpO64QKz5k+LUaX/9Q49yyqBtOcnGdAFhI0nA74+NF3bC7vuOJk9P uSsNCucT8x2dXY4fLimAJe88Ggd2Jm4nWfhvIB3nvCVGVLUNsO2VEcrOtaFdoQSM7DcK 1iRg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xvGMgC2k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4609b47f340si4265771cf.272.2024.10.16.12.36.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2024 12:36:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xvGMgC2k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t19kX-0002qR-Ut; Wed, 16 Oct 2024 15:32:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t19kQ-0002jN-HL for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:55 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t19kO-0003rS-NO for qemu-devel@nongnu.org; Wed, 16 Oct 2024 15:31:54 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-20c77459558so1574775ad.0 for ; Wed, 16 Oct 2024 12:31:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729107111; x=1729711911; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9wtdGS6j59IEw6lp5Sp3jQrC+uEbTCdVdwYMkROoHlk=; b=xvGMgC2kl9BwTc+YSZeLMjiJZszcwUdB51kC0VQBzX8Rq6tpXf1gdNMLlu+Jw2Y60E xvjTvYkZtd/vQnRCKh6FsFjmW5XD5k/FKeyhy6Kz/cZlgGZZ41JueNI9J3nTlFhWplAB v+/fm7Lz1b2c7Njl6Qm1+576WwpES2IuspNyVGV77m32ZBBuNs6tXwU8JHzVNKDb18RC +n2g3YaRZ3b0BIfZb5Retwz75dBd7c/PVc1yVRUoIXwLOrQPE5IZb6vVmX7mgP7uPw6U RL3aBs7K+eiL9rLM+tQZLWls0/wKNSd2fe6wac9WGRporqQhULzMMmOKIhYmVTBF66RN UU0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729107111; x=1729711911; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9wtdGS6j59IEw6lp5Sp3jQrC+uEbTCdVdwYMkROoHlk=; b=iHmGdJBRlQbTyjbyK9rt+rEth0B/VTSTSbCUiy0/DHSdC1b3kUfRpRfsEA3z9KSzAL wVuoJES12tB+oWCn/ek9KtLdWe1Xyvz22bZ50V75PLcji2pFcZJ/AlBXBBlBJweg7Cp1 aawdvCE31VZ2wIUKIaiPkVbi/ioQDMh1SabXzqBaLWD8yqqXXU6WtySlN477isJ9JPW/ ErK1GAuuaIYwK9rFB8+eenntTOxMHn/Wvo0S9F/tHUtz82PPus+X5P3HN8CFgv98obIN LzpDyMENlONsDbFdqeYbxHXassWVQRvtXq1UTtvNc8YqD7DTIlwe6bbshRDU3Qg5kDTr 5nrw== X-Gm-Message-State: AOJu0Yy9/9B9gEM47bm4Z2Scsj9FNEwGLqA1X2mDMKL48+a6EHcgTvrs /rt/ex9cOrTB81iIIqHi7Kb0+WVXAT7Qjv/RDwKe+F0Q/b9efi02jqrP+om557TCmDN/YgUHVb+ 7 X-Received: by 2002:a17:903:2311:b0:20c:950f:f45d with SMTP id d9443c01a7336-20ca17261e2mr185693895ad.61.1729107111110; Wed, 16 Oct 2024 12:31:51 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b6b1sm32323945ad.189.2024.10.16.12.31.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2024 12:31:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v6 14/14] tcg/riscv: Enable native vector support for TCG host Date: Wed, 16 Oct 2024 12:31:40 -0700 Message-ID: <20241016193140.2206352-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241016193140.2206352-1-richard.henderson@linaro.org> References: <20241016193140.2206352-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Message-ID: <20241007025700.47259-13-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index e6d66cd1b9..334c37cbe6 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -143,9 +143,9 @@ typedef enum { #define TCG_TARGET_HAS_tst 0 /* vector instructions */ -#define TCG_TARGET_HAS_v64 0 -#define TCG_TARGET_HAS_v128 0 -#define TCG_TARGET_HAS_v256 0 +#define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_ZVE64X) +#define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_ZVE64X) +#define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_ZVE64X) #define TCG_TARGET_HAS_andc_vec 0 #define TCG_TARGET_HAS_orc_vec 0 #define TCG_TARGET_HAS_nand_vec 0