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Tue, 15 Oct 2024 12:08:21 GMT Received: from hu-jseerapu-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 15 Oct 2024 05:08:16 -0700 From: Jyothi Kumar Seerapu To: Vinod Koul , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Bjorn Andersson" , Konrad Dybcio , Andi Shyti , Sumit Semwal , =?utf-8?q?Christian_K=C3=B6nig?= CC: , , , , , , , , , , Subject: [PATCH v1 2/5] arm64: dts: qcom: Add support for configuring channel TRE size Date: Tue, 15 Oct 2024 17:37:47 +0530 Message-ID: <20241015120750.21217-3-quic_jseerapu@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241015120750.21217-1-quic_jseerapu@quicinc.com> References: <20241015120750.21217-1-quic_jseerapu@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: X6G_FitGyw9X2VxUdzoYGsYIxqQ7wTX0 X-Proofpoint-GUID: X6G_FitGyw9X2VxUdzoYGsYIxqQ7wTX0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 phishscore=0 malwarescore=0 clxscore=1015 spamscore=0 adultscore=0 mlxlogscore=999 impostorscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410150082 When high performance with multiple i2c messages in a single transfer is required, employ Block Event Interrupt (BEI) to trigger interrupts after specific messages transfer and the last message transfer, thereby reducing interrupts. For each i2c message transfer, a series of Transfer Request Elements(TREs) must be programmed, including config tre for frequency configuration, go tre for holding i2c address and dma tre for holding dma buffer address, length as per the hardware programming guide. For transfer using BEI, multiple I2C messages may necessitate the preparation of config, go, and tx DMA TREs. However, a channel TRE size of 64 is often insufficient, potentially leading to failures due to inadequate memory space. Adjust the channel TRE size through the device tree. The default size is 64, but clients can modify this value based on their heigher channel TRE size requirements. Signed-off-by: Jyothi Kumar Seerapu --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 132 +++++++++++++-------------- 1 file changed, 66 insertions(+), 66 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 3d8410683402..c7c0e15ff9d3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1064,7 +1064,7 @@ }; gpi_dma0: dma-controller@900000 { - #dma-cells = <3>; + #dma-cells = <4>; compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00900000 0 0x60000>; interrupts = , @@ -1114,8 +1114,8 @@ "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; - dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, - <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C 64>, + <&gpi_dma0 1 0 QCOM_GPI_I2C 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1135,8 +1135,8 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, - <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI 64>, + <&gpi_dma0 1 0 QCOM_GPI_SPI 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1174,8 +1174,8 @@ "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; - dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, - <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C 64>, + <&gpi_dma0 1 1 QCOM_GPI_I2C 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1195,8 +1195,8 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, - <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI 64>, + <&gpi_dma0 1 1 QCOM_GPI_SPI 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1234,8 +1234,8 @@ "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; - dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, - <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C 64>, + <&gpi_dma0 1 2 QCOM_GPI_I2C 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1255,8 +1255,8 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, - <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI 64>, + <&gpi_dma0 1 2 QCOM_GPI_SPI 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1294,8 +1294,8 @@ "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; - dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, - <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C 64>, + <&gpi_dma0 1 3 QCOM_GPI_I2C 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1315,8 +1315,8 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, - <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI 64>, + <&gpi_dma0 1 3 QCOM_GPI_SPI 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1354,8 +1354,8 @@ "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; - dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, - <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C 64>, + <&gpi_dma0 1 4 QCOM_GPI_I2C 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1375,8 +1375,8 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, - <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI 64>, + <&gpi_dma0 1 4 QCOM_GPI_SPI 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1414,8 +1414,8 @@ "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; - dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, - <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C 64>, + <&gpi_dma0 1 5 QCOM_GPI_I2C 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1435,8 +1435,8 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, - <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI 64>, + <&gpi_dma0 1 5 QCOM_GPI_SPI 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1474,8 +1474,8 @@ "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; - dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, - <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C 64>, + <&gpi_dma0 1 6 QCOM_GPI_I2C 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1495,8 +1495,8 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, - <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI 64>, + <&gpi_dma0 1 6 QCOM_GPI_SPI 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1534,8 +1534,8 @@ "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; - dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, - <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C 64>, + <&gpi_dma0 1 7 QCOM_GPI_I2C 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1555,8 +1555,8 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, - <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI 64>, + <&gpi_dma0 1 7 QCOM_GPI_SPI 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1579,7 +1579,7 @@ }; gpi_dma1: dma-controller@a00000 { - #dma-cells = <3>; + #dma-cells = <4>; compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00a00000 0 0x60000>; interrupts = , @@ -1629,8 +1629,8 @@ "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; - dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, - <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C 64>, + <&gpi_dma1 1 0 QCOM_GPI_I2C 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1650,8 +1650,8 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, - <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI 64>, + <&gpi_dma1 1 0 QCOM_GPI_SPI 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1689,8 +1689,8 @@ "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; - dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, - <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C 64>, + <&gpi_dma1 1 1 QCOM_GPI_I2C 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1710,8 +1710,8 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, - <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI 64>, + <&gpi_dma1 1 1 QCOM_GPI_SPI 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1749,8 +1749,8 @@ "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; - dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, - <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C 64>, + <&gpi_dma1 1 2 QCOM_GPI_I2C 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1770,8 +1770,8 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, - <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI 64>, + <&gpi_dma1 1 2 QCOM_GPI_SPI 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1809,8 +1809,8 @@ "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; - dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, - <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C 64>, + <&gpi_dma1 1 3 QCOM_GPI_I2C 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1830,8 +1830,8 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, - <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI 64>, + <&gpi_dma1 1 3 QCOM_GPI_SPI 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1869,8 +1869,8 @@ "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; - dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, - <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C 64>, + <&gpi_dma1 1 4 QCOM_GPI_I2C 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1890,8 +1890,8 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, - <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI 64>, + <&gpi_dma1 1 4 QCOM_GPI_SPI 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1929,8 +1929,8 @@ "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; - dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, - <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C 64>, + <&gpi_dma1 1 5 QCOM_GPI_I2C 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1950,8 +1950,8 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, - <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI 64>, + <&gpi_dma1 1 5 QCOM_GPI_SPI 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1989,8 +1989,8 @@ "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; - dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, - <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C 64>, + <&gpi_dma1 1 6 QCOM_GPI_I2C 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -2010,8 +2010,8 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, - <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI 64>, + <&gpi_dma1 1 6 QCOM_GPI_SPI 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -2049,8 +2049,8 @@ "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; - dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, - <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C 64>, + <&gpi_dma1 1 7 QCOM_GPI_I2C 64>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -2070,8 +2070,8 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; - dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, - <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI 64>, + <&gpi_dma1 1 7 QCOM_GPI_SPI 64>; dma-names = "tx", "rx"; status = "disabled"; }; From patchwork Tue Oct 15 12:07:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyothi Kumar Seerapu X-Patchwork-Id: 836485 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 792CB1F890F; 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Tue, 15 Oct 2024 12:08:33 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49FC8XRY027419 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 15 Oct 2024 12:08:33 GMT Received: from hu-jseerapu-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 15 Oct 2024 05:08:27 -0700 From: Jyothi Kumar Seerapu To: Vinod Koul , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Bjorn Andersson" , Konrad Dybcio , Andi Shyti , Sumit Semwal , =?utf-8?q?Christian_K=C3=B6nig?= CC: , , , , , , , , , , Subject: [PATCH v1 4/5] dmaengine: qcom: gpi: Add GPI Block event interrupt support Date: Tue, 15 Oct 2024 17:37:49 +0530 Message-ID: <20241015120750.21217-5-quic_jseerapu@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241015120750.21217-1-quic_jseerapu@quicinc.com> References: <20241015120750.21217-1-quic_jseerapu@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: aEFO6pLAIX0YeBZ9ROqnvKFdp91C0S1f X-Proofpoint-GUID: aEFO6pLAIX0YeBZ9ROqnvKFdp91C0S1f X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 priorityscore=1501 clxscore=1015 adultscore=0 lowpriorityscore=0 mlxlogscore=999 phishscore=0 malwarescore=0 suspectscore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410150083 GSI hardware generates an interrupt for each transfer completion. For multiple messages within a single transfer, this results in receiving N interrupts for N messages, which can introduce significant software interrupt latency. To mitigate this latency, utilize Block Event Interrupt (BEI) only when an interrupt is necessary. When using BEI, consider splitting a single multi-message transfer into chunks of 64. This approach can enhance overall transfer time and efficiency. Signed-off-by: Jyothi Kumar Seerapu --- drivers/dma/qcom/gpi.c | 49 ++++++++++++++++++++++++++++++++ include/linux/dma/qcom-gpi-dma.h | 37 ++++++++++++++++++++++++ 2 files changed, 86 insertions(+) diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index 3c89b4a88ac1..b8ca119114d2 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -1694,6 +1694,9 @@ static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc, tre->dword[3] = u32_encode_bits(TRE_TYPE_DMA, TRE_FLAGS_TYPE); tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOT); + + if (i2c->flags & QCOM_GPI_BLOCK_EVENT_IRQ) + tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_BEI); } for (i = 0; i < tre_idx; i++) @@ -2099,6 +2102,52 @@ static int gpi_find_avail_gpii(struct gpi_dev *gpi_dev, u32 seid) return -EIO; } +/** + * gpi_multi_desc_process() - Process received transfers from GSI HW + * @dev: pointer to the corresponding dev node + * @multi_xfer: pointer to the gpi_multi_xfer + * @num_xfers: total number of transfers + * @transfer_timeout_msecs: transfer timeout value + * @transfer_comp: completion object of the transfer + * + * This function is used to process the received transfers based on the + * completion events + * + * Return: On success returns 0, otherwise return error code + */ +int gpi_multi_desc_process(struct device *dev, struct gpi_multi_xfer *multi_xfer, + u32 num_xfers, u32 transfer_timeout_msecs, + struct completion *transfer_comp) +{ + int i; + u32 max_irq_cnt, time_left; + + max_irq_cnt = num_xfers / NUM_MSGS_PER_IRQ; + if (num_xfers % NUM_MSGS_PER_IRQ) + max_irq_cnt++; + + /* + * Wait for the interrupts of the processed transfers in multiple + * of 64 and for the last transfer. If the hardware is fast and + * already processed all the transfers then no need to wait. + */ + for (i = 0; i < max_irq_cnt; i++) { + reinit_completion(transfer_comp); + if (max_irq_cnt != multi_xfer->irq_cnt) { + time_left = wait_for_completion_timeout(transfer_comp, + transfer_timeout_msecs); + if (!time_left) { + dev_err(dev, "%s: Transfer timeout\n", __func__); + return -ETIMEDOUT; + } + } + if (num_xfers > multi_xfer->msg_idx_cnt) + return 0; + } + return 0; +} +EXPORT_SYMBOL_GPL(gpi_multi_desc_process); + /* gpi_of_dma_xlate: open client requested channel */ static struct dma_chan *gpi_of_dma_xlate(struct of_phandle_args *args, struct of_dma *of_dma) diff --git a/include/linux/dma/qcom-gpi-dma.h b/include/linux/dma/qcom-gpi-dma.h index 6680dd1a43c6..ca0465627a21 100644 --- a/include/linux/dma/qcom-gpi-dma.h +++ b/include/linux/dma/qcom-gpi-dma.h @@ -15,6 +15,12 @@ enum spi_transfer_cmd { SPI_DUPLEX, }; +#define QCOM_GPI_BLOCK_EVENT_IRQ BIT(0) + +#define QCOM_GPI_MAX_NUM_MSGS 200 +#define NUM_MSGS_PER_IRQ 64 +#define MIN_NUM_OF_MSGS_MULTI_DESC 4 + /** * struct gpi_spi_config - spi config for peripheral * @@ -51,6 +57,29 @@ enum i2c_op { I2C_READ, }; +/** + * struct gpi_multi_xfer - Used for multi transfer support + * + * @msg_idx_cnt: message index for the transfer + * @buf_idx: dma buffer index + * @unmap_msg_cnt: unampped transfer index + * @freed_msg_cnt: freed transfer index + * @irq_cnt: received interrupt count + * @irq_msg_cnt: transfer message count for the received irqs + * @dma_buf: virtual address of the buffer + * @dma_addr: dma address of the buffer + */ +struct gpi_multi_xfer { + u32 msg_idx_cnt; + u32 buf_idx; + u32 unmap_msg_cnt; + u32 freed_msg_cnt; + u32 irq_cnt; + u32 irq_msg_cnt; + void *dma_buf[QCOM_GPI_MAX_NUM_MSGS]; + dma_addr_t *dma_addr[QCOM_GPI_MAX_NUM_MSGS]; +}; + /** * struct gpi_i2c_config - i2c config for peripheral * @@ -65,6 +94,8 @@ enum i2c_op { * @rx_len: receive length for buffer * @op: i2c cmd * @muli-msg: is part of multi i2c r-w msgs + * @flags: true for block event interrupt support + * @multi_xfer: indicates transfer has multi messages */ struct gpi_i2c_config { u8 set_config; @@ -78,6 +109,12 @@ struct gpi_i2c_config { u32 rx_len; enum i2c_op op; bool multi_msg; + u8 flags; + struct gpi_multi_xfer multi_xfer; }; +int gpi_multi_desc_process(struct device *dev, struct gpi_multi_xfer *multi_xfer, + u32 num_xfers, u32 tranfer_timeout_msecs, + struct completion *transfer_comp); + #endif /* QCOM_GPI_DMA_H */