From patchwork Mon Dec 2 14:41:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 180608 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp43711ile; Mon, 2 Dec 2019 06:41:26 -0800 (PST) X-Google-Smtp-Source: APXvYqwRbzMmgxUMxmfsb44z45atNxY/a7TXABas4ijwQOeBdz2FDiSinjw9yKL3q6QKo/KjSyfm X-Received: by 2002:a17:906:7704:: with SMTP id q4mr1986283ejm.89.1575297686416; Mon, 02 Dec 2019 06:41:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575297686; cv=none; d=google.com; s=arc-20160816; b=dchSx0Dr2XgPwRYPn8uH2nMf7swDhs0vP3+WvaP/zzMU0erz+IjNo6R+IVuYAgD6FT nsnP0f8MyPaSKGqNJuz8BEmsomMhNfW7OdAx4inP4DHnwdTSzbJYuGryWPUynjl6SMQf 9kK3JSYL1MdxfWVtEymYZkmIG6U0jVHdeHUkGeC6kv9A4jbetIdLkN1ba4pA3lZg4IVF 8IShg4dweeSpwHCsIHEvVrMB7ZFEsxywi/Yv2wXlHCiE7BsyyzSyKFNYggXRkAiXqGQN bz2wyuMnPyGs2TuU7TCsh6rczZqq9+JRWmejedpBbqmMd0d7p4y9OuWltJvAlJjRm5AR JbFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:to:from:dkim-signature; bh=w/Mrna2Khv21UvkkLKLf8+wkF9y7ELMmGnTl9xg6qEs=; b=xebT/pbhfrMEJvmxNN0bOYto07dZB4PlkrvL5oSqqo42g7J6i75exZZV5/zndlzT7r 0bMQ65vYeALzHY2GvAYd8v+uFKUvZ1PMJf9CLwbA3rkF5jrBPoeAATKRo8j8ncnKXGPx 0ofgk5zMNxkB8UhbEWLSXUYnywJl1zoj07sPKnK9QkNlmTMLi3F7BZIo+TDK1/rrQ0k8 cAJudt4zy95zU9wl9GOS3CxY7SuNmtFZzgPH0kCIZDSCyqOTLDTqDrVHKBOezGYnr2wq DiZnIM0NUbcGEBfWCFsHy7VugzEuvaPtqk6oQFKzGMYYCjSvRdLXCI7TIi6vd3lLaX+m o0bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Oh/2eLfC"; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[66.175.222.153]) by smtp.gmail.com with ESMTPSA id f30sm33985090pga.20.2019.12.02.06.41.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 06:41:23 -0800 (PST) From: Jun Nie To: ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, adrian.hunter@intel.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/4] mmc: sdhci: Add delay after power off Date: Mon, 2 Dec 2019 22:41:01 +0800 Message-Id: <20191202144104.5069-2-jun.nie@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202144104.5069-1-jun.nie@linaro.org> References: <20191202144104.5069-1-jun.nie@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add delay after power off to ensure that full power cycle is successful. Otherwise, some controllers, at lease for Hisilicon eMMC controller, may not be unstable sometimes for full power cycle operation. Signed-off-by: Jun Nie --- drivers/mmc/host/sdhci.c | 7 +++++++ drivers/mmc/host/sdhci.h | 2 ++ 2 files changed, 9 insertions(+) -- 2.17.1 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 3140fe2e5dba..a654f0aeb438 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1761,6 +1761,13 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) sdhci_runtime_pm_bus_off(host); + + /* + * Some controllers need an extra 100ms delay to secure + * full power cycle is successful. + */ + if (host->quirks2 & SDHCI_QUIRK2_DELAY_AFTER_POWER_OFF) + msleep(100); } else { /* * Spec says that we should clear the power reg before setting diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 0ed3e0eaef5f..0e6f97eaa796 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -482,6 +482,8 @@ struct sdhci_host { * block count. */ #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) +/* Controllers need an extra 100ms delay to make sure power off completely */ +#define SDHCI_QUIRK2_DELAY_AFTER_POWER_OFF (1<<19) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ From patchwork Mon Dec 2 14:41:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 180609 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp43755ile; Mon, 2 Dec 2019 06:41:28 -0800 (PST) X-Google-Smtp-Source: APXvYqw0i/SeIg7VMrbwFWPg04ZaDSk7xMjFjGLSi0pR6epCbm4NFmFdVNJay/WXBlVJaGTqdOtW X-Received: by 2002:a5d:4d06:: with SMTP id z6mr18674676wrt.339.1575297688321; Mon, 02 Dec 2019 06:41:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575297688; cv=none; d=google.com; s=arc-20160816; b=gFk8aLhmp5fGNo2PACHW4Aeql4rL68I4HUnJefRUADK4HkQ6nAhBbOwSu6eY7amC7e Bfn2xUlWCexac+BA3rUUDrNkx5BMJ/UqWCXYxfx5nDBosiTPIm1au7zBTNuINe0IymmN 3jiEeHHusAsOuNX7vgf/iQdyiYgZi9Na8UIv/VojJ9raC89a453A8gfe9gTO0WW4/ohm o2LGxJ+eKTtoQfOA54ua+TUvey1xRPU8Ac9a5xPvQtoEJUXXgADUkAaGcBJSGbQ/lb30 AEjpp14wxoyZJjpaZOafoyU6rER3iS7RU44o1ryH3lhi32yU5QuFRzKf6/bq53oBbj4s MtSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:to:from:dkim-signature; bh=ynHcIuOVTswBCOhsCj7rfF7reyKlOrh1x0LK0XaYbgU=; b=gMf64ZQEicp09LV9A5ZOoprn3eFoq6mGKY+SOB++YI9nQUZzjRcR3gyYXuU8XJXsqZ 7jzvhWS/vPWYH0FmfGiOq471miM0l/rysOnl+yWll7nkvfn0zRVjRzv1dDR1D71PBwCq HO8YoHKofPf71MLVrRLUmFIXZm+0P40J+TnLCmKxZ1BLjvw1TTJpyHcp08mrwmkKMhBM Gbvkj0ASSc8AgAXn/UFqnNqY+bFi1cBycGKZjTtruBPrDJtJKCZXlF6fBS/f3DcRr089 TsCPsC0+44XF+m0HnUM4UGPtsDn+iVrxExeLxQoH0l7df169LF9z7tn7+So8mLZ3V0Zd pWLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Vd7wNQxL; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[66.175.222.153]) by smtp.gmail.com with ESMTPSA id f30sm33985090pga.20.2019.12.02.06.41.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 06:41:26 -0800 (PST) From: Jun Nie To: ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, adrian.hunter@intel.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/4] mmc: sdhci: dt: Add DMA boundary and HS400 properties Date: Mon, 2 Dec 2019 22:41:02 +0800 Message-Id: <20191202144104.5069-3-jun.nie@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202144104.5069-1-jun.nie@linaro.org> References: <20191202144104.5069-1-jun.nie@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org DMA memory cannot cross specific boundary on some controller, such as 128MB on SDHCI Designware. Add sdhci-dma-mem-boundary property to split DMA operation in such case. sdhci-ctrl-hs400 specify the HS400 mode setting for register SDHCI_HOST_CONTROL2(offset 0x3E:bit[2:0]). Because this value is not defined in SDHC Standard specification. Signed-off-by: Jun Nie --- Documentation/devicetree/bindings/mmc/sdhci.txt | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/mmc/sdhci.txt b/Documentation/devicetree/bindings/mmc/sdhci.txt index 0e9923a64024..e6d7feb9a741 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci.txt @@ -11,3 +11,11 @@ Optional properties: - sdhci-caps: The sdhci capabilities register is incorrect. This 64bit property corresponds to the bits in the sdhci capability register. If the bit is on in the property then the bit should be turned on. +- sdhci-dma-mem-boundary: The sdhci controller DMA memory space boundary. + If the controller's DMA cannot cross a specific memory space boundary, + such as 128MB, set this value in dt and driver will split the DMA + operation when crossing such boundary. +- sdhci-ctrl-hs400: The HS400 is not defined in SDHC Standard specification + for SDHCI_HOST_CONTROL2(offset 0x3E:bit[2:0]). Different controllers have + have different value for HS400 mode. If 0x5 is not the HS400 mode value + for your controller, you should specify the value with this property.