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[209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-46132115d37si48377221cf.140.2024.10.26.10.55.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 26 Oct 2024 10:55:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VTHV8y87; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4kzH-0008Or-QP; Sat, 26 Oct 2024 13:54:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4kzF-0008Ns-Gm for qemu-devel@nongnu.org; Sat, 26 Oct 2024 13:54:05 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4kzD-0003js-O5 for qemu-devel@nongnu.org; Sat, 26 Oct 2024 13:54:05 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-20c805a0753so29554265ad.0 for ; Sat, 26 Oct 2024 10:54:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729965242; x=1730570042; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KpfAMGmyWm4pigvyIOxRZMUq0CTvdaeELUk7R48DMKQ=; b=VTHV8y87dPbSTG2T6XnXMR9xtzQjgJYLGU51nvj7CY3D8cLKsA7pM0a0iVl99oyO1i cJYTFeB0NubPG8wet7QYvH/MzdQjFL/hdy2GEbXZh5plahoDqPNNKBarfdBKGzEoJ/DY AKCKx/pbjIMuiEIJCsSDyiaCdPkpUtYMfB0gXCFj6MmQtOfr0s+DVX2uCI2SDrlvRFK3 OqqwZLaNthOtzkQbbXpBhmSx+QGqf/ikSfzu88bLWsJJNEmDbJ1KiiWQ514KybV3H7hw 7pBMZ5lwP1JhpzoGBpRSEWl+sNtvReOeWtuZoeaBg2JIsSwBWSlmXS3ZfU8ETS81U/j2 vQpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729965242; x=1730570042; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KpfAMGmyWm4pigvyIOxRZMUq0CTvdaeELUk7R48DMKQ=; b=kAowXKggxhcosuaj4KJ39OhLQItEbbomulfRT6EDh4zX5u+eNG8gavZDCw5+mdhTaK HtwU/HImFO1b0Yz4yx+0dGISxAk8HZmWr3z80rj+3IARlu//Hf3Milft3LZSTI+ouZ4/ 2xR+tti7rCTXEBMXufUth+KfNy1+IXj9nslF1O7ETrJUEHn/tNRjpRvelJuP4wEjvsU/ XwmP34dHhY45pIt7SaHp2fNz1MYrJjMDFSDBlP7iwUYTx3/N0uWy6QpczJWMDFSzO8Vp kCZZ3w6Wa01pFyWAF9uwGNLRITYkdzcB5tErhgp4Owu/juZP4TB9T4tXBa6HDmRVudy8 g9FQ== X-Gm-Message-State: AOJu0Yzjmt1/92Bjitvgaim/eVGHW9Q1VehkvGJimAbfl8lMJecsW5d2 TW7vbM45v7rlKzmpgDJeZgK4QvzxF/NX8njq8LTp1c03JWh6pxpAvA1Hzp+vAdi4q1sC0g/t/W0 Y X-Received: by 2002:a17:902:dac9:b0:20e:57c8:6aae with SMTP id d9443c01a7336-210c6879841mr50526365ad.3.1729965241944; Sat, 26 Oct 2024 10:54:01 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.169]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-210bbf84597sm26208485ad.111.2024.10.26.10.54.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 26 Oct 2024 10:54:01 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Aleksandar Rikalo Subject: [PATCH v3 1/9] target/mips: Extract decode_64bit_enabled() helper Date: Sat, 26 Oct 2024 14:53:41 -0300 Message-ID: <20241026175349.84523-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241026175349.84523-1-philmd@linaro.org> References: <20241026175349.84523-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Extract the decode_64bit_enabled() helper which detects whether CPUs can run 64-bit instructions. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/mips/tcg/translate.h | 2 ++ target/mips/tcg/translate.c | 7 ++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 5d196e69ac4..ae6c25aa0c4 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -217,6 +217,8 @@ void msa_translate_init(void); void mxu_translate_init(void); bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); +bool decode_64bit_enabled(DisasContext *ctx); + /* decodetree generated */ bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index d92fc418edd..6c881af5618 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1645,13 +1645,18 @@ static inline void check_ps(DisasContext *ctx) check_cp1_64bitmode(ctx); } +bool decode_64bit_enabled(DisasContext *ctx) +{ + return ctx->hflags & MIPS_HFLAG_64; +} + /* * This code generates a "reserved instruction" exception if cpu is not * 64-bit or 64-bit instructions are not enabled. */ void check_mips_64(DisasContext *ctx) { - if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) { + if (unlikely((TARGET_LONG_BITS != 64) || !decode_64bit_enabled(ctx))) { gen_reserved_instruction(ctx); } } From patchwork Sat Oct 26 17:53:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 838775 Delivered-To: patch@linaro.org Received: by 2002:adf:e287:0:b0:37d:45d0:187 with SMTP id v7csp876303wri; Sat, 26 Oct 2024 10:55:06 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUCPW5zecEq/P9Zs8M5IreU7/loJbK2oKiSbitvQsMUlgNZvNhWOpILlPQXdLLyQixLwH2QPA==@linaro.org X-Google-Smtp-Source: AGHT+IEhistdRAAcnQ7HdULolhmFZJNF46KChxH/R1tmNF9tX2ydbJTYW5jITSoTn1wclP68rByb X-Received: by 2002:a05:622a:289:b0:458:1578:56a6 with SMTP id d75a77b69052e-4613c015ca8mr46595811cf.24.1729965306091; Sat, 26 Oct 2024 10:55:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729965306; cv=none; d=google.com; s=arc-20240605; b=d9e8JBmRSu4S5D1pU6u2So3WabCY1HVg7g6TC9pQ18EprQcpOOV0OOpLZzscqTwIq7 6vUhtyal45uBZiS8ujNVRoEoTaaWk5grca6tjRA10zRq5KhYEFFl9m61ShbWotGj2m6E Be8DUeddGw+inQvXTFx0pQUDfG05LFwYpGsOLKBpkZvlaXmTpr99gAmkXZ0Az3IDuuen 73tgmDgVpt/x9YVCRUe0OxYgWkaRXeYKEJ7wc1l1oCXB+iOFluQuHLp5KqWPy4Imb9b9 sMWmvu1a6SKG+WlT3iT+GLzlnojFB8m9TUNqhtloEGBUKHot8SY2ng/zBMneVAClW5Pp AIhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GUXo3gWo9LQ++O+bqUolSjJXO8UGvTh+04+/9wrBtPo=; fh=0YP3uPMu7Jgy5kpRVY48qEhRb1hLSBhQ2cCWY0uXjCU=; b=KuAjp+5VsrUeDYgLHykTh2x57zOesQf33sRoAYgUSNzhzk3EpizTV++BLcNpq/2e0K LBasbXWytxtnEtZZRGOCbDvoIFdaXXjDmoZuYinMoaUIEurejxmkOfWySaK7MFHW8r02 AC3pEtw9/OYvwEdsM472l7nflCiHjuGRFjFoGkz22WY3GsLGDG3ZWgFLQxqIXgZpju0U dvvy/PxnH0TP9+IUCTPlo6WK1BJC1M+0qZ1Ij+Y38tX9rL2AX41KVh7XO+DTaHbD6uhi kXXBwo1kKAVpFHyFySo56IqJFEA5iYqEVVzlvOFd7xI9JUbciBNBjokJrM5LamMUQgQo do7w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="woda/0xH"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-46132392fcesi43870701cf.502.2024.10.26.10.55.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 26 Oct 2024 10:55:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="woda/0xH"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4kzQ-0008QP-6o; Sat, 26 Oct 2024 13:54:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4kzO-0008Q3-0C for qemu-devel@nongnu.org; Sat, 26 Oct 2024 13:54:14 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4kzL-0003lw-Rx for qemu-devel@nongnu.org; Sat, 26 Oct 2024 13:54:13 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-71e625b00bcso2322412b3a.3 for ; Sat, 26 Oct 2024 10:54:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729965250; x=1730570050; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GUXo3gWo9LQ++O+bqUolSjJXO8UGvTh+04+/9wrBtPo=; b=woda/0xHGTgQ+NyZvItHWiCHsDBUhcrxifMMriP8b/PNZ7k8o0nG/+seKWmyeHA0jk NsbXZ9e/7f9hdcg6RP2iAMyv9QNrdvU+F9r9eSNYhceK5im6CA+i/bOq83C52MEY//vg TU+2Tf58xYGPd9hzkrOlVw6xoinnfTlHVwdiVsTlVkqBYRTjjuMCY+iwlTW5M3w6Ny7I dc1KD7IOzH4kDlw76GnxaGoxjGUW78X/siCnb0Hv/xzf+dGUCRSezbwqreg8JuEkDiAe M83zzb6zQxhAMONwSLsPTVNjA0/cFBjVbpOi+g7VDIOtROydx6xytWOvu7CAjqnKjd3O ooRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729965250; x=1730570050; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GUXo3gWo9LQ++O+bqUolSjJXO8UGvTh+04+/9wrBtPo=; b=pcRILLe9lZFFMpgKLCUF+YmzB5fyRnF7vOVw1APoTsj2NKV1ECxsWBH9TmWZsqQwmZ sGLprOg9w+qnifCaKGmIDWX2k8HdeQfWfxtXC/0DME0CeFiBVGv8VjGMB8u2BXYkYcAf ikW8n4z0z5+BoTRkNYL90EXw8mZvckC9tLkul7pM2kiU9sy6FUhD6qFbVFQCGAK7OjX3 K4Q9q8UHjUNlbu78a26e5iWWSNYng9mhi9mFdt21Nr/TCrHpguSl9eZb+8FkeQbSgMuz UV/gBWV4NQo2v1BosRucVDzAfe4LLN1LRMSQQH3BuQAVjOULFb7hXrCIdUBt4KDy5La7 NGpw== X-Gm-Message-State: AOJu0YwxwjTdjymvVJBDM6h2Qx17Pn49V7U7BdJYzkZdKKsp6SB/oUhh ZnqPwsuAFKKvO8IK7/tFth8Blc9pRyaQY3Az8vpMKHg/Hf8NZZo3x1qIoPmCvbSf/j5ZxbJoJZV y X-Received: by 2002:a05:6a00:2389:b0:71e:8049:4730 with SMTP id d2e1a72fcca58-72062f85458mr5161984b3a.3.1729965250369; Sat, 26 Oct 2024 10:54:10 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.169]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7edc86a8b37sm3029998a12.56.2024.10.26.10.54.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 26 Oct 2024 10:54:10 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Aleksandar Rikalo , Richard Henderson Subject: [PATCH v3 2/9] target/mips: Simplify Loongson MULTU.G opcode Date: Sat, 26 Oct 2024 14:53:42 -0300 Message-ID: <20241026175349.84523-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241026175349.84523-1-philmd@linaro.org> References: <20241026175349.84523-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since MULTU opcodes don't record the most significant bits of the infinite result, sign-extending the sources make no difference in the result. Once we remove the sign extension of source registers, MULT and MULTU are identical (as are DMULT and DMULTU). Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 6c881af5618..6d7e913263e 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -3615,8 +3615,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, break; case OPC_MULTU_G_2E: case OPC_MULTU_G_2F: - tcg_gen_ext32u_tl(t0, t0); - tcg_gen_ext32u_tl(t1, t1); tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); break; From patchwork Sat Oct 26 17:53:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 838780 Delivered-To: patch@linaro.org Received: by 2002:adf:e287:0:b0:37d:45d0:187 with SMTP id v7csp876454wri; Sat, 26 Oct 2024 10:55:42 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWuOBufhirlZUz5/Apy8yF1zujpS5Q6621Ei2bbhqURxl4yPcDuzMo3UKr6gGTWrWCuik2PvQ==@linaro.org X-Google-Smtp-Source: AGHT+IEQdIfHrWS9OeFH/t5v0VJtYy3W2+zYh488n+7zjZYzzbWXx53J6MaIu4DGUyj/5cFG4mQY X-Received: by 2002:a05:620a:4691:b0:7ae:6169:d8f2 with SMTP id af79cd13be357-7b193f38ba6mr484258085a.44.1729965342086; Sat, 26 Oct 2024 10:55:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729965342; cv=none; d=google.com; s=arc-20240605; b=QVdrM5LrI5O76+DsW4uXFcd+a7lVuNDRQEoUlj7gv26KFZlpaafmjqEKlgtF2wNeUO 8UCbl22bFPj3ljO8aceoXb7135Td7y8i3qpLWkdi0RGzE2niKH8JRAjrUZp2eetHrnWD WCb/SEv3QDduRbnyC3z3Sk3eFfKdOMREEs6KTcKvblAfbW2z1FXCadNRMOTxk6Lzpmrp 4OxwquFTfzaXqnWTJOkDZjUF0jp9bnCeJPwUX8RZrOsQezPH/BEZ9aFsLnQhqmG7BY/e GkwZ2MKmlvJRZMNXbsUI3DWCsVDPQ+3gHOzSc8eQA5gvma+qkStc53G9G/hg0cCm5Log elug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=F9rUKSeMJCa0vu/2TgEevCLC7enoeVuoehiK9K/0kes=; fh=xXrcSe4hTyQYCXsOI2FwoMUFvkxcKPmFfOAYwJ3xzYE=; b=IcNLVMKWB3boMa3R1FFzlLvbiOvx/KKRTkcCMPnsE3RPCJp6YHp86iJ1w7WagduQNf P1kpEToV/ngdx/VORQ26bax7cDL5UhgS24vZA1ozqy9TlDD0hnN2Ot1cJqMlSqTNQOLa kFgPSXJO5reKjNiV5SMP3WLOy5bkjC/exv1A8xfebFYfBLM6Gvkq+ef6+vWxJ9sRUKVm N9SvcfSa2C+Esv1IUYmSZVgqyJLZuskf+mWFHpblU2QPvnMTITd1T4ceUtTqc+UsQjol Cm4wXZasXy9pFCB9VymqUimV3GJkNRxXxdOyI1lKelLz368Xt1RHtEkPuPk3WmW/dvKb r/0g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q1rqdKb7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7b18d290c0bsi504148385a.185.2024.10.26.10.55.41 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 26 Oct 2024 10:55:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q1rqdKb7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4kzX-0008RH-LE; Sat, 26 Oct 2024 13:54:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4kzV-0008Qq-AA for qemu-devel@nongnu.org; Sat, 26 Oct 2024 13:54:21 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4kzT-0003mX-Qn for qemu-devel@nongnu.org; Sat, 26 Oct 2024 13:54:21 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-20e576dbc42so30832285ad.0 for ; Sat, 26 Oct 2024 10:54:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729965258; x=1730570058; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F9rUKSeMJCa0vu/2TgEevCLC7enoeVuoehiK9K/0kes=; b=Q1rqdKb7HxRHrVbTZe+aHWhyuFGe6QWSMWs6/HU1Yod8ugnze4rwbbsz+Ockt3/JYF 3RkvV9WkDDBIsE+IJil2leeiG+9QY1HFL98LDHveuwRwvB2KxtjDfDv26sixC8Atjyic T3FlFLbxsST4ak6Pf3MssvTUYaTkSADULW8AftEIfLjP6X8RDXmZLC7RI9UfW5VnmbR0 l30eHDBIX9U1dTf4AsQBLbqBKLcihEwRIp8I/c5Roz7vQiFMjlpFeQ9WJf/1goxrmMYL RfdWvzk+PJjlzmS7O1Y+PclFuoatsqP8e9sAvD5zxC3WywWA93x5Vv3jncEP1Bl7tbi+ a2KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729965258; x=1730570058; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F9rUKSeMJCa0vu/2TgEevCLC7enoeVuoehiK9K/0kes=; b=dwa0KkqYE77jLsf9r3qsQhxXcQPPcDogv+LHNYP3/vFip4yesj1qU4MxWduoiMmzV5 Gfi0dfPkoYUorr4eAi9MEhLF6eDZZBZe6k/7j0OT0sEi1SYbm2PuTYXRt0v0KVlKdI0A 7mOn5+VB8G41GErhntB85GiGFDkHL4lGRoEekBIjZDtZYx5wRXkE4ao5VFTI6hR2SuoL IfqXIqo3Qr6BelnxIZnX7qYJr2nceB3wgQZ7Ql7ubtBvBibedJRp15d2UYUV3WNbjyig tP4G/dAKhizkjF6/jAo+mAqGIyz9jtJRTA+rgpnSefC6FeyoIl130EXMwtTGyge2xuDn 6yXA== X-Gm-Message-State: AOJu0YwfcIDztGZE1vQOIuE9ah2L4Bq8KO1teo4ZAWl51pd3hj5R7Rcj XzZ5lqupd2/Yf7HHb3DUDRKOI60Yr3CFE7grIklrE8gVMDne2/2xbBZtcgDa2LzG9SvU+K5p/2a U X-Received: by 2002:a17:902:c951:b0:20b:5231:cd61 with SMTP id d9443c01a7336-210c6c3469dmr43265665ad.24.1729965258177; Sat, 26 Oct 2024 10:54:18 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.169]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-210bbf6d5c2sm26502365ad.94.2024.10.26.10.54.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 26 Oct 2024 10:54:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson Subject: [PATCH v3 3/9] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP Date: Sat, 26 Oct 2024 14:53:43 -0300 Message-ID: <20241026175349.84523-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241026175349.84523-1-philmd@linaro.org> References: <20241026175349.84523-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé There is no issue having multiple enum declarations with the same value. As we are going to remove the OPC_MULT_G_2E definition in few commits, restore the OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP definitions and use them where they belong. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 6d7e913263e..509488fdc7a 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -389,16 +389,14 @@ enum { OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3, OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3, OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3, - /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */ - /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */ + OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3, OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3, /* MIPS DSP GPR-Based Shift Sub-class */ OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3, OPC_SHLL_OB_DSP = 0x17 | OPC_SPECIAL3, /* MIPS DSP Multiply Sub-class insns */ - /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */ - /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */ + OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3, OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3, /* DSP Bit/Manipulation Sub-class */ @@ -556,7 +554,6 @@ enum { OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP, }; -#define OPC_ADDUH_QB_DSP OPC_MULT_G_2E #define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { /* MIPS DSP Arithmetic Sub-class */ @@ -11587,8 +11584,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2, gen_load_gpr(v2_t, v2); switch (op1) { - /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */ - case OPC_MULT_G_2E: + case OPC_ADDUH_QB_DSP: check_dsp_r2(ctx); switch (op2) { case OPC_ADDUH_QB: @@ -12271,11 +12267,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2, gen_load_gpr(v2_t, v2); switch (op1) { - /* - * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have - * the same mask and op1. - */ - case OPC_MULT_G_2E: + case OPC_MUL_PH_DSP: check_dsp_r2(ctx); switch (op2) { case OPC_MUL_PH: @@ -13811,7 +13803,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have * the same mask and op1. */ - if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MULT_G_2E)) { + if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MUL_PH_DSP)) { op2 = MASK_ADDUH_QB(ctx->opcode); switch (op2) { case OPC_ADDUH_QB: From patchwork Sat Oct 26 17:53:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 838778 Delivered-To: patch@linaro.org Received: by 2002:adf:e287:0:b0:37d:45d0:187 with SMTP id v7csp876324wri; Sat, 26 Oct 2024 10:55:14 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW2jjljRtnxKFVaK21p5dmpJjAYrJ3tcL3yIm+p16qDRguCWYe+uT0unVvVEEyAKVj6qLSt8Q==@linaro.org X-Google-Smtp-Source: AGHT+IGgH+6DxSw7eo+3kk4bVMmBsrqFKJkWaz9ClJ2hA6wFwNnHLjnJgTvvZ25qI3J5ZS1K8Iq8 X-Received: by 2002:a0c:e6c9:0:b0:6d1:85a7:3cc0 with SMTP id 6a1803df08f44-6d185a73d65mr43135926d6.12.1729965314101; Sat, 26 Oct 2024 10:55:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729965314; cv=none; d=google.com; s=arc-20240605; b=dwkqnBds5qroT8tO+e0XtKodxElhV6u/WL5uz5sG+nKv7RXxJIWj1MjFbI9tWPzr1S rM6C4DTiRYZ1Pk16/8FkJA8wTmuoVBFVl6jEg2DyDZE9WV68OvKL5f5jA08TQID7i3k4 2XdaF6sjBu7XvFdRAoPN8IZdoLFHtMPdrT4D3gn8To84/nqpHPFVlycdSG8zpC+Dimse 4fmfe2ohepMZkTHolkevtJ/0ZzlP7ouFMaDOkm94AVeGVVe4HkrX5PPEm0zLNls/J4fa uygSEBi6utmvyPFoVQAm6+3oDgP5qYu4LO35030O/tRvunz+6ISwXCMxasqsMeDRFz7B CExg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZLKH8qIZ6l9ObxKjf4HCu+I3Sr8Uxz9tO1wwFdX0DlI=; fh=xXrcSe4hTyQYCXsOI2FwoMUFvkxcKPmFfOAYwJ3xzYE=; b=RgAa4vCBxfGswYdAvSAF/j1q9E0wq+hqlmDV4R4Guo6rLu4ieKpRbk5zp4n7SuISNB 0jh6n/4GCfRFow/j3jstRV8Y7diaiNJakqUsdiR6Py2jte5IfuokzMMabohCUi468xf8 r38ZaEhs6GEMdSKp5VLThgoIAwQSAKaatWi8kMqod78NtNieZGNyMB22lX6oJxCE9ROW 985afwS9SQ7T/sNFyf3QleeSu0OYvi7S6/OLUi80kOUiqCB8qmbfTSmqPl815e+eOdOE sRlGbHeacpBdEgIOUQLmIxCNS/kP95pFwjb16wYMdxGEPjq9JRfga/68DFi6KoevlYt4 4fEQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=toUGYn+f; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6d179a49e69si46662926d6.403.2024.10.26.10.55.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 26 Oct 2024 10:55:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=toUGYn+f; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4kzi-0008S0-V2; Sat, 26 Oct 2024 13:54:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4kze-0008RY-2e for qemu-devel@nongnu.org; Sat, 26 Oct 2024 13:54:31 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4kzc-0003n0-70 for qemu-devel@nongnu.org; Sat, 26 Oct 2024 13:54:29 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-71e592d7f6eso2045480b3a.3 for ; Sat, 26 Oct 2024 10:54:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729965266; x=1730570066; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZLKH8qIZ6l9ObxKjf4HCu+I3Sr8Uxz9tO1wwFdX0DlI=; b=toUGYn+f7dXoKGWVsomYVmxwgECKus9H/k7L/fEsy0e/S2TAG84kIs7aN7sFODKOVx oMbz2tte5pw6YVdFx+aQegkz53vuPI6WipS1TRpfPICSXO30SsRCTETO0v91r7P2GK3P 8RhOj1b5ZZJ7kvoMo/Fw5K7z1JGxfjxKa5Jl6dExmyUFox26I1N6uJ1h5tHpzkHC4Nbj NtALiVphNjOkIVpHVFNP9FbUzo9fkAocHcZ3q6c2JOxQf2AjfV9BkVC/oNgyQCixBvny TenBn3MUPLzWyu114Pgnf7wj7pRfak1qjxDICrNGlfmGwDotBTAeYy3Zb7cfazUZ9dec eF4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729965266; x=1730570066; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZLKH8qIZ6l9ObxKjf4HCu+I3Sr8Uxz9tO1wwFdX0DlI=; b=l06d82EKM8euDZrEaj+guchYqLL8Vhpz5a3zKrRxLozL5IJx5zKkjThuwL8Wyf0Pu3 QAFJjnmfVUWVmZSZniuN4b9UbBgrCZKcvLcCh0eQOP2wKqNy/So2roF9gQO+rnRSnAtt /3EooGWT+mA0E7BKi9TJn4NkEnJDbz1a87oex7Ax0CUaTpx6sgvMw+ZK99edg5o4aic3 VbaLXLQ1uyapZw0koSiLL3mCk0WnOTIWpw9AL1/fLTQvf41lxaMsfxSk1047ewEdrxCO TLIp3tOHANsjD1I6RDLxIIIMctqD+FrcSSxum2CYckCqUM8XLOrRmp1dW9dfx+GtWKUo nXVA== X-Gm-Message-State: AOJu0YyNmULQ7L64//Gkn3KBO7hsFUPLmn4/Sp4FSwjI5LM7rhATHR0j 3wgSe8Hex5VX0Djd+LTu/auE2637s3gqsozT8lfv1alC73TvIA1Z+VKbMi7TF6Q306GQkZV1k67 J X-Received: by 2002:a05:6a00:3c87:b0:71e:21c:bf1b with SMTP id d2e1a72fcca58-72062fb2df2mr5663146b3a.14.1729965265995; Sat, 26 Oct 2024 10:54:25 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.169]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72057a1fe82sm2947086b3a.164.2024.10.26.10.54.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 26 Oct 2024 10:54:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson Subject: [PATCH v3 4/9] target/mips: Convert Loongson DDIV.G opcodes to decodetree Date: Sat, 26 Oct 2024 14:53:44 -0300 Message-ID: <20241026175349.84523-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241026175349.84523-1-philmd@linaro.org> References: <20241026175349.84523-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Introduce decode_loongson() to decode all Loongson vendor specific opcodes. Start converting a single opcode: DDIV.G (divide 64-bit signed integers). Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 1 + target/mips/tcg/godson2.decode | 16 ++++++ target/mips/tcg/loong-ext.decode | 17 ++++++ target/mips/tcg/loong_translate.c | 86 +++++++++++++++++++++++++++++++ target/mips/tcg/translate.c | 26 ++-------- target/mips/tcg/meson.build | 3 ++ 6 files changed, 126 insertions(+), 23 deletions(-) create mode 100644 target/mips/tcg/godson2.decode create mode 100644 target/mips/tcg/loong-ext.decode create mode 100644 target/mips/tcg/loong_translate.c diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index ae6c25aa0c4..23a489c0f38 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -223,6 +223,7 @@ bool decode_64bit_enabled(DisasContext *ctx); bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); +bool decode_ext_loongson(DisasContext *ctx, uint32_t insn); #if defined(TARGET_MIPS64) bool decode_ase_lcsr(DisasContext *ctx, uint32_t insn); bool decode_ext_tx79(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode new file mode 100644 index 00000000000..47ea5a1c438 --- /dev/null +++ b/target/mips/tcg/godson2.decode @@ -0,0 +1,16 @@ +# Godson2 64-bit Integer instructions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# Godson-2E Software Manual +# (Document Number: godson2e-user-manual-V0.6) +# + +&muldiv rs rt rd + +@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv + +DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd diff --git a/target/mips/tcg/loong-ext.decode b/target/mips/tcg/loong-ext.decode new file mode 100644 index 00000000000..8b78ec48599 --- /dev/null +++ b/target/mips/tcg/loong-ext.decode @@ -0,0 +1,17 @@ +# Loongson 64-bit Extension instructions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# STLS2F01 User Manual +# Appendix A: new integer instructions +# (Document Number: UM0447) +# + +&muldiv rs rt rd !extern + +@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv + +DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_translate.c new file mode 100644 index 00000000000..53e4047cfa0 --- /dev/null +++ b/target/mips/tcg/loong_translate.c @@ -0,0 +1,86 @@ +/* + * MIPS Loongson 64-bit translation routines + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2011 Richard Henderson + * Copyright (c) 2021 Philippe Mathieu-Daudé + * + * This code is licensed under the GNU GPLv2 and later. + */ + +#include "qemu/osdep.h" +#include "translate.h" + +/* Include the auto-generated decoder. */ +#include "decode-godson2.c.inc" +#include "decode-loong-ext.c.inc" + +/* + * Word or double-word Fixed-point instructions. + * --------------------------------------------- + * + * Fixed-point multiplies and divisions write only + * one result into general-purpose registers. + */ + +static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt) +{ + TCGv t0, t1; + TCGLabel *l1, *l2, *l3; + + if (TARGET_LONG_BITS != 64) { + return false; + } + check_mips_64(s); + + if (rd == 0) { + /* Treat as NOP. */ + return true; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + l1 = gen_new_label(); + l2 = gen_new_label(); + l3 = gen_new_label(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_br(l3); + gen_set_label(l1); + + tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); + tcg_gen_mov_tl(cpu_gpr[rd], t0); + + tcg_gen_br(l3); + gen_set_label(l2); + tcg_gen_div_tl(cpu_gpr[rd], t0, t1); + gen_set_label(l3); + + return true; +} + +static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_DIV_G(s, a->rt, a->rs, a->rd); +} + +bool decode_ext_loongson(DisasContext *ctx, uint32_t insn) +{ + if (!decode_64bit_enabled(ctx)) { + return false; + } + if ((ctx->insn_flags & INSN_LOONGSON2E) && decode_godson2(ctx, ctx->opcode)) { + return true; + } + if ((ctx->insn_flags & ASE_LEXT) && decode_loong_ext(ctx, ctx->opcode)) { + return true; + } + return false; +} diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 509488fdc7a..73445dd9074 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -333,7 +333,6 @@ enum { OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2, OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2, OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2, - OPC_DDIV_G_2F = 0x15 | OPC_SPECIAL2, OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2, OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2, OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2, @@ -375,7 +374,6 @@ enum { OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3, OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3, OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3, - OPC_DDIV_G_2E = 0x1E | OPC_SPECIAL3, OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3, OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3, OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, @@ -3698,25 +3696,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, case OPC_DMULTU_G_2F: tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); break; - case OPC_DDIV_G_2E: - case OPC_DDIV_G_2F: - { - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - TCGLabel *l3 = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l3); - gen_set_label(l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); - tcg_gen_mov_tl(cpu_gpr[rd], t0); - tcg_gen_br(l3); - gen_set_label(l2); - tcg_gen_div_tl(cpu_gpr[rd], t0, t1); - gen_set_label(l3); - } - break; case OPC_DDIVU_G_2E: case OPC_DDIVU_G_2F: { @@ -13654,7 +13633,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) break; case OPC_DMULT_G_2F: case OPC_DMULTU_G_2F: - case OPC_DDIV_G_2F: case OPC_DDIVU_G_2F: case OPC_DMOD_G_2F: case OPC_DMODU_G_2F: @@ -14061,7 +14039,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) } break; #if defined(TARGET_MIPS64) - case OPC_DDIV_G_2E: case OPC_DDIVU_G_2E: case OPC_DMULT_G_2E: case OPC_DMULTU_G_2E: @@ -15262,6 +15239,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) { return; } + if (TARGET_LONG_BITS == 64 && decode_ext_loongson(ctx, ctx->opcode)) { + return; + } #if defined(TARGET_MIPS64) if (ase_lcsr_available(env) && decode_ase_lcsr(ctx, ctx->opcode)) { return; diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index ea7fb582f2a..fd91148df74 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,4 +1,6 @@ gen = [ + decodetree.process('godson2.decode', extra_args: ['--static-decode=decode_godson2']), + decodetree.process('loong-ext.decode', extra_args: ['--static-decode=decode_loong_ext']), decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']), decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), @@ -28,6 +30,7 @@ mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'tx79_translate.c', 'octeon_translate.c', 'lcsr_translate.c', + 'loong_translate.c', ), if_false: files( 'mxu_translate.c', )) From patchwork Sat Oct 26 17:53:45 2024 Content-Type: text/plain; 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Provide gen_lext_DIV_G() a 'is_double' argument so it can generate DIV.G (divide 32-bit signed integers). With this commit we explicit the template used to generate opcode for 32/64-bit word variants. Next commits will be less verbose by providing both variants at once. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/godson2.decode | 1 + target/mips/tcg/loong-ext.decode | 1 + target/mips/tcg/loong_translate.c | 28 ++++++++++++++++++++++------ target/mips/tcg/translate.c | 26 -------------------------- 4 files changed, 24 insertions(+), 32 deletions(-) diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode index 47ea5a1c438..cbf24ed88da 100644 --- a/target/mips/tcg/godson2.decode +++ b/target/mips/tcg/godson2.decode @@ -13,4 +13,5 @@ @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv +DIV_G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd diff --git a/target/mips/tcg/loong-ext.decode b/target/mips/tcg/loong-ext.decode index 8b78ec48599..9397606beb6 100644 --- a/target/mips/tcg/loong-ext.decode +++ b/target/mips/tcg/loong-ext.decode @@ -14,4 +14,5 @@ @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv +DIV_G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_translate.c index 53e4047cfa0..7c405078795 100644 --- a/target/mips/tcg/loong_translate.c +++ b/target/mips/tcg/loong_translate.c @@ -25,15 +25,18 @@ * one result into general-purpose registers. */ -static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt) +static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt, + bool is_double) { TCGv t0, t1; TCGLabel *l1, *l2, *l3; - if (TARGET_LONG_BITS != 64) { - return false; + if (is_double) { + if (TARGET_LONG_BITS != 64) { + return false; + } + check_mips_64(s); } - check_mips_64(s); if (rd == 0) { /* Treat as NOP. */ @@ -49,26 +52,39 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt) gen_load_gpr(t0, rs); gen_load_gpr(t1, rt); + if (!is_double) { + tcg_gen_ext32s_tl(t0, t0); + tcg_gen_ext32s_tl(t1, t1); + } tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); tcg_gen_movi_tl(cpu_gpr[rd], 0); tcg_gen_br(l3); gen_set_label(l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS == 64 + ? LLONG_MIN : INT_MIN, l2); tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); tcg_gen_mov_tl(cpu_gpr[rd], t0); tcg_gen_br(l3); gen_set_label(l2); tcg_gen_div_tl(cpu_gpr[rd], t0, t1); + if (!is_double) { + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } gen_set_label(l3); return true; } +static bool trans_DIV_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_DIV_G(s, a->rt, a->rs, a->rd, false); +} + static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a) { - return gen_lext_DIV_G(s, a->rt, a->rs, a->rd); + return gen_lext_DIV_G(s, a->rt, a->rs, a->rd, true); } bool decode_ext_loongson(DisasContext *ctx, uint32_t insn) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 73445dd9074..1c38e893d31 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -332,7 +332,6 @@ enum { OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2, OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2, OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2, - OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2, OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2, OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2, OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2, @@ -370,7 +369,6 @@ enum { /* Loongson 2E */ OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3, OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3, - OPC_DIV_G_2E = 0x1A | OPC_SPECIAL3, OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3, OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3, OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3, @@ -3613,28 +3611,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); break; - case OPC_DIV_G_2E: - case OPC_DIV_G_2F: - { - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - TCGLabel *l3 = gen_new_label(); - tcg_gen_ext32s_tl(t0, t0); - tcg_gen_ext32s_tl(t1, t1); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l3); - gen_set_label(l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); - tcg_gen_mov_tl(cpu_gpr[rd], t0); - tcg_gen_br(l3); - gen_set_label(l2); - tcg_gen_div_tl(cpu_gpr[rd], t0, t1); - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - gen_set_label(l3); - } - break; case OPC_DIVU_G_2E: case OPC_DIVU_G_2F: { @@ -13598,7 +13574,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_MUL: gen_arith(ctx, op1, rd, rs, rt); break; - case OPC_DIV_G_2F: case OPC_DIVU_G_2F: case OPC_MULT_G_2F: case OPC_MULTU_G_2F: @@ -13771,7 +13746,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) op1 = MASK_SPECIAL3(ctx->opcode); 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Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/godson2.decode | 2 ++ target/mips/tcg/loong-ext.decode | 2 ++ target/mips/tcg/loong_translate.c | 54 +++++++++++++++++++++++++++++++ target/mips/tcg/translate.c | 37 --------------------- 4 files changed, 58 insertions(+), 37 deletions(-) diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode index cbf24ed88da..581cb9c8608 100644 --- a/target/mips/tcg/godson2.decode +++ b/target/mips/tcg/godson2.decode @@ -14,4 +14,6 @@ @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv DIV_G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd +DIVU_G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd +DDIVU_G 011111 ..... ..... ..... 00000 011111 @rs_rt_rd diff --git a/target/mips/tcg/loong-ext.decode b/target/mips/tcg/loong-ext.decode index 9397606beb6..e222167af56 100644 --- a/target/mips/tcg/loong-ext.decode +++ b/target/mips/tcg/loong-ext.decode @@ -16,3 +16,5 @@ DIV_G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd +DIVU_G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd +DDIVU_G 011100 ..... ..... ..... 00000 010111 @rs_rt_rd diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_translate.c index 7c405078795..903d242e7cc 100644 --- a/target/mips/tcg/loong_translate.c +++ b/target/mips/tcg/loong_translate.c @@ -87,6 +87,60 @@ static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a) return gen_lext_DIV_G(s, a->rt, a->rs, a->rd, true); } +static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt, + bool is_double) +{ + TCGv t0, t1; + TCGLabel *l1, *l2; + + if (is_double) { + if (TARGET_LONG_BITS != 64) { + return false; + } + check_mips_64(s); + } + + if (rd == 0) { + /* Treat as NOP. */ + return true; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + l1 = gen_new_label(); + l2 = gen_new_label(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + if (!is_double) { + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + } + tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); + if (!is_double) { + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } + gen_set_label(l2); + + return true; +} + +static bool trans_DIVU_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_DIVU_G(s, a->rt, a->rs, a->rd, false); +} + +static bool trans_DDIVU_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_DIVU_G(s, a->rt, a->rs, a->rd, true); +} + bool decode_ext_loongson(DisasContext *ctx, uint32_t insn) { if (!decode_64bit_enabled(ctx)) { diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 1c38e893d31..53bbbb761f8 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -332,8 +332,6 @@ enum { OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2, OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2, OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2, - OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2, - OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2, OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2, OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2, OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2, @@ -369,10 +367,8 @@ enum { /* Loongson 2E */ OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3, OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3, - OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3, OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3, OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3, - OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3, OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3, OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3, @@ -3611,22 +3607,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); break; - case OPC_DIVU_G_2E: - case OPC_DIVU_G_2F: - { - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - tcg_gen_ext32u_tl(t0, t0); - tcg_gen_ext32u_tl(t1, t1); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - gen_set_label(l2); - } - break; case OPC_MOD_G_2E: case OPC_MOD_G_2F: { @@ -3672,19 +3652,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, case OPC_DMULTU_G_2F: tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); break; - case OPC_DDIVU_G_2E: - case OPC_DDIVU_G_2F: - { - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); - gen_set_label(l2); - } - break; case OPC_DMOD_G_2E: case OPC_DMOD_G_2F: { @@ -13574,7 +13541,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_MUL: gen_arith(ctx, op1, rd, rs, rt); break; - case OPC_DIVU_G_2F: case OPC_MULT_G_2F: case OPC_MULTU_G_2F: case OPC_MOD_G_2F: @@ -13608,7 +13574,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) break; case OPC_DMULT_G_2F: case OPC_DMULTU_G_2F: - case OPC_DDIVU_G_2F: case OPC_DMOD_G_2F: case OPC_DMODU_G_2F: check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); @@ -13746,7 +13711,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) op1 = MASK_SPECIAL3(ctx->opcode); switch (op1) { - case OPC_DIVU_G_2E: case OPC_MOD_G_2E: case OPC_MODU_G_2E: case OPC_MULT_G_2E: @@ -14013,7 +13977,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) } break; #if defined(TARGET_MIPS64) - case OPC_DDIVU_G_2E: case OPC_DMULT_G_2E: case OPC_DMULTU_G_2E: case OPC_DMOD_G_2E: From patchwork Sat Oct 26 17:53:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 838783 Delivered-To: patch@linaro.org Received: by 2002:adf:e287:0:b0:37d:45d0:187 with SMTP id v7csp876563wri; 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Sat, 26 Oct 2024 10:54:49 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson Subject: [PATCH v3 7/9] target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree Date: Sat, 26 Oct 2024 14:53:47 -0300 Message-ID: <20241026175349.84523-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241026175349.84523-1-philmd@linaro.org> References: <20241026175349.84523-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=philmd@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Convert the following opcodes to decodetree: - MOD.G - mod 32-bit signed integers - MODU.G - mod 32-bit unsigned integers - DMOD.G - mod 64-bit signed integers - DMODU.G - mod 64-bit unsigned integers Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/godson2.decode | 5 ++ target/mips/tcg/loong-ext.decode | 5 ++ target/mips/tcg/loong_translate.c | 111 ++++++++++++++++++++++++++++++ target/mips/tcg/translate.c | 82 ---------------------- 4 files changed, 121 insertions(+), 82 deletions(-) diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode index 581cb9c8608..c03c8b717d9 100644 --- a/target/mips/tcg/godson2.decode +++ b/target/mips/tcg/godson2.decode @@ -17,3 +17,8 @@ DIV_G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd DIVU_G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd DDIVU_G 011111 ..... ..... ..... 00000 011111 @rs_rt_rd + +MOD_G 011111 ..... ..... ..... 00000 100010 @rs_rt_rd +MODU_G 011111 ..... ..... ..... 00000 100011 @rs_rt_rd +DMOD_G 011111 ..... ..... ..... 00000 100110 @rs_rt_rd +DMODU_G 011111 ..... ..... ..... 00000 100111 @rs_rt_rd diff --git a/target/mips/tcg/loong-ext.decode b/target/mips/tcg/loong-ext.decode index e222167af56..f0fd36c9218 100644 --- a/target/mips/tcg/loong-ext.decode +++ b/target/mips/tcg/loong-ext.decode @@ -18,3 +18,8 @@ DIV_G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd DIVU_G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd DDIVU_G 011100 ..... ..... ..... 00000 010111 @rs_rt_rd + +MOD_G 011100 ..... ..... ..... 00000 011100 @rs_rt_rd +DMOD_G 011100 ..... ..... ..... 00000 011101 @rs_rt_rd +MODU_G 011100 ..... ..... ..... 00000 011110 @rs_rt_rd +DMODU_G 011100 ..... ..... ..... 00000 011111 @rs_rt_rd diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_translate.c index 903d242e7cc..76c1a8cef2d 100644 --- a/target/mips/tcg/loong_translate.c +++ b/target/mips/tcg/loong_translate.c @@ -141,6 +141,117 @@ static bool trans_DDIVU_G(DisasContext *s, arg_muldiv *a) return gen_lext_DIVU_G(s, a->rt, a->rs, a->rd, true); } +static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt, + bool is_double) +{ + TCGv t0, t1; + TCGLabel *l1, *l2, *l3; + + if (is_double) { + if (TARGET_LONG_BITS != 64) { + return false; + } + check_mips_64(s); + } + + if (rd == 0) { + /* Treat as NOP. */ + return true; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + l1 = gen_new_label(); + l2 = gen_new_label(); + l3 = gen_new_label(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + if (!is_double) { + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + } + tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS == 64 + ? LLONG_MIN : INT_MIN, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); + gen_set_label(l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_br(l3); + gen_set_label(l2); + tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); + if (!is_double) { + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } + gen_set_label(l3); + + return true; +} + +static bool trans_MOD_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_MOD_G(s, a->rt, a->rs, a->rd, false); +} + +static bool trans_DMOD_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_MOD_G(s, a->rt, a->rs, a->rd, true); +} + +static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt, + bool is_double) +{ + TCGv t0, t1; + TCGLabel *l1, *l2; + + if (is_double) { + if (TARGET_LONG_BITS != 64) { + return false; + } + check_mips_64(s); + } + + if (rd == 0) { + /* Treat as NOP. */ + return true; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + l1 = gen_new_label(); + l2 = gen_new_label(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + if (!is_double) { + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + } + tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); + tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); + if (!is_double) { + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } + gen_set_label(l2); + + return true; +} + +static bool trans_MODU_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_MODU_G(s, a->rt, a->rs, a->rd, false); +} + +static bool trans_DMODU_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_MODU_G(s, a->rt, a->rs, a->rd, true); +} + bool decode_ext_loongson(DisasContext *ctx, uint32_t insn) { if (!decode_64bit_enabled(ctx)) { diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 53bbbb761f8..4abc30a6a5f 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -332,10 +332,6 @@ enum { OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2, OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2, OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2, - OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2, - OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2, - OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2, - OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2, /* Misc */ OPC_CLZ = 0x20 | OPC_SPECIAL2, OPC_CLO = 0x21 | OPC_SPECIAL2, @@ -369,10 +365,6 @@ enum { OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3, OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3, OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3, - OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3, - OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, - OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3, - OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3, /* MIPS DSP Load */ OPC_LX_DSP = 0x0A | OPC_SPECIAL3, @@ -3607,42 +3599,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); break; - case OPC_MOD_G_2E: - case OPC_MOD_G_2F: - { - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - TCGLabel *l3 = gen_new_label(); - tcg_gen_ext32u_tl(t0, t0); - tcg_gen_ext32u_tl(t1, t1); - tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); - gen_set_label(l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l3); - gen_set_label(l2); - tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - gen_set_label(l3); - } - break; - case OPC_MODU_G_2E: - case OPC_MODU_G_2F: - { - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - tcg_gen_ext32u_tl(t0, t0); - tcg_gen_ext32u_tl(t1, t1); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - gen_set_label(l2); - } - break; #if defined(TARGET_MIPS64) case OPC_DMULT_G_2E: case OPC_DMULT_G_2F: @@ -3652,36 +3608,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, case OPC_DMULTU_G_2F: tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); break; - case OPC_DMOD_G_2E: - case OPC_DMOD_G_2F: - { - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - TCGLabel *l3 = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); - gen_set_label(l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l3); - gen_set_label(l2); - tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); - gen_set_label(l3); - } - break; - case OPC_DMODU_G_2E: - case OPC_DMODU_G_2F: - { - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); - gen_set_label(l2); - } - break; #endif } } @@ -13543,8 +13469,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) break; case OPC_MULT_G_2F: case OPC_MULTU_G_2F: - case OPC_MOD_G_2F: - case OPC_MODU_G_2F: check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); gen_loongson_integer(ctx, op1, rd, rs, rt); break; @@ -13574,8 +13498,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) break; case OPC_DMULT_G_2F: case OPC_DMULTU_G_2F: - case OPC_DMOD_G_2F: - case OPC_DMODU_G_2F: check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); gen_loongson_integer(ctx, op1, rd, rs, rt); break; @@ -13711,8 +13633,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) op1 = MASK_SPECIAL3(ctx->opcode); switch (op1) { - case OPC_MOD_G_2E: - case OPC_MODU_G_2E: case OPC_MULT_G_2E: case OPC_MULTU_G_2E: /* @@ -13979,8 +13899,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) #if defined(TARGET_MIPS64) case OPC_DMULT_G_2E: case OPC_DMULTU_G_2E: - case OPC_DMOD_G_2E: - case OPC_DMODU_G_2E: check_insn(ctx, INSN_LOONGSON2E); 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Sat, 26 Oct 2024 10:54:58 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson Subject: [PATCH v3 8/9] target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree Date: Sat, 26 Oct 2024 14:53:48 -0300 Message-ID: <20241026175349.84523-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241026175349.84523-1-philmd@linaro.org> References: <20241026175349.84523-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Convert the following opcodes to decodetree: - MULT.G - multiply 32-bit signed integers - MULTU.G - multiply 32-bit unsigned integers - DMULT.G - multiply 64-bit signed integers - DMULTU.G - multiply 64-bit unsigned integers Now that all opcodes from the extension have been converted, we can remove completely gen_loongson_integer() and its 2 calls in decode_opc_special2_legacy() and decode_opc_special3_legacy(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/godson2.decode | 3 ++ target/mips/tcg/loong-ext.decode | 3 ++ target/mips/tcg/loong_translate.c | 41 +++++++++++++++++ target/mips/tcg/translate.c | 73 +------------------------------ 4 files changed, 49 insertions(+), 71 deletions(-) diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode index c03c8b717d9..25b396b6822 100644 --- a/target/mips/tcg/godson2.decode +++ b/target/mips/tcg/godson2.decode @@ -13,6 +13,9 @@ @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv +MULTu_G 011111 ..... ..... ..... 00000 01100- @rs_rt_rd +DMULTu_G 011111 ..... ..... ..... 00000 01110- @rs_rt_rd + DIV_G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd DIVU_G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd diff --git a/target/mips/tcg/loong-ext.decode b/target/mips/tcg/loong-ext.decode index f0fd36c9218..b43979d0ef5 100644 --- a/target/mips/tcg/loong-ext.decode +++ b/target/mips/tcg/loong-ext.decode @@ -14,6 +14,9 @@ @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv +MULTu_G 011100 ..... ..... ..... 00000 0100-0 @rs_rt_rd +DMULTu_G 011100 ..... ..... ..... 00000 0100-1 @rs_rt_rd + DIV_G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd DIVU_G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_translate.c index 76c1a8cef2d..c02e60bb15b 100644 --- a/target/mips/tcg/loong_translate.c +++ b/target/mips/tcg/loong_translate.c @@ -252,6 +252,47 @@ static bool trans_DMODU_G(DisasContext *s, arg_muldiv *a) return gen_lext_MODU_G(s, a->rt, a->rs, a->rd, true); } +static bool gen_lext_MULT_G(DisasContext *s, int rd, int rs, int rt, + bool is_double) +{ + TCGv t0, t1; + + if (is_double) { + if (TARGET_LONG_BITS != 64) { + return false; + } + check_mips_64(s); + } + + if (rd == 0) { + /* Treat as NOP. */ + return true; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); + if (!is_double) { + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } + + return true; +} + +static bool trans_MULTu_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, false); +} + +static bool trans_DMULTu_G(DisasContext *s, arg_muldiv *a) +{ + return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, true); +} + bool decode_ext_loongson(DisasContext *ctx, uint32_t insn) { if (!decode_64bit_enabled(ctx)) { diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 4abc30a6a5f..2d01f5c4a8b 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -327,11 +327,6 @@ enum { OPC_MUL = 0x02 | OPC_SPECIAL2, OPC_MSUB = 0x04 | OPC_SPECIAL2, OPC_MSUBU = 0x05 | OPC_SPECIAL2, - /* Loongson 2F */ - OPC_MULT_G_2F = 0x10 | OPC_SPECIAL2, - OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2, - OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2, - OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2, /* Misc */ OPC_CLZ = 0x20 | OPC_SPECIAL2, OPC_CLO = 0x21 | OPC_SPECIAL2, @@ -360,12 +355,6 @@ enum { OPC_RDHWR = 0x3B | OPC_SPECIAL3, OPC_GINV = 0x3D | OPC_SPECIAL3, - /* Loongson 2E */ - OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3, - OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3, - OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3, - OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3, - /* MIPS DSP Load */ OPC_LX_DSP = 0x0A | OPC_SPECIAL3, /* MIPS DSP Arithmetic */ @@ -3572,46 +3561,6 @@ static void gen_cl(DisasContext *ctx, uint32_t opc, } } -/* Godson integer instructions */ -static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, - int rd, int rs, int rt) -{ - TCGv t0, t1; - - if (rd == 0) { - /* Treat as NOP. */ - return; - } - - t0 = tcg_temp_new(); - t1 = tcg_temp_new(); - gen_load_gpr(t0, rs); - gen_load_gpr(t1, rt); - - switch (opc) { - case OPC_MULT_G_2E: - case OPC_MULT_G_2F: - tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - break; - case OPC_MULTU_G_2E: - case OPC_MULTU_G_2F: - tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - break; -#if defined(TARGET_MIPS64) - case OPC_DMULT_G_2E: - case OPC_DMULT_G_2F: - tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); - break; - case OPC_DMULTU_G_2E: - case OPC_DMULTU_G_2F: - tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); - break; -#endif - } -} - /* Loongson multimedia instructions */ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) { @@ -13467,11 +13416,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_MUL: gen_arith(ctx, op1, rd, rs, rt); break; - case OPC_MULT_G_2F: - case OPC_MULTU_G_2F: - check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); - gen_loongson_integer(ctx, op1, rd, rs, rt); - break; case OPC_CLO: case OPC_CLZ: check_insn(ctx, ISA_MIPS_R1); @@ -13496,11 +13440,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); break; - case OPC_DMULT_G_2F: - case OPC_DMULTU_G_2F: - check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); - gen_loongson_integer(ctx, op1, rd, rs, rt); - break; #endif default: /* Invalid */ MIPS_INVAL("special2_legacy"); @@ -13633,10 +13572,9 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) op1 = MASK_SPECIAL3(ctx->opcode); switch (op1) { - case OPC_MULT_G_2E: - case OPC_MULTU_G_2E: + case OPC_MUL_PH_DSP: /* - * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have + * OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have * the same mask and op1. */ if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MUL_PH_DSP)) { @@ -13667,8 +13605,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) gen_reserved_instruction(ctx); break; } - } else if (ctx->insn_flags & INSN_LOONGSON2E) { - gen_loongson_integer(ctx, op1, rd, rs, rt); } else { gen_reserved_instruction(ctx); } @@ -13897,11 +13833,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) } break; #if defined(TARGET_MIPS64) - case OPC_DMULT_G_2E: - case OPC_DMULTU_G_2E: - check_insn(ctx, INSN_LOONGSON2E); - gen_loongson_integer(ctx, op1, rd, rs, rt); - break; case OPC_ABSQ_S_QH_DSP: op2 = MASK_ABSQ_S_QH(ctx->opcode); switch (op2) { From patchwork Sat Oct 26 17:53:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 838779 Delivered-To: patch@linaro.org Received: by 2002:adf:e287:0:b0:37d:45d0:187 with SMTP id v7csp876384wri; Sat, 26 Oct 2024 10:55:27 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVaQBrFy6jnnMzz28M2VPpDcZzEBYUXEKE2xJIi67Slk0bz7sENA8F6LtRKOpS7kLA2KajDHA==@linaro.org X-Google-Smtp-Source: AGHT+IFFng5Ls6bHmVQPQgCYXNeAFh6fAiBuF1s5m5RXFivdfrTyF6piSFVtEq8n7cgDdswI9wYL X-Received: by 2002:a05:6214:3a8c:b0:6cc:113c:894b with SMTP id 6a1803df08f44-6d1856f1519mr50724636d6.2.1729965326919; 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Simplify by removing the 32-bit checks. Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/mips/tcg/loong_translate.c | 41 ++----------------------------- 1 file changed, 2 insertions(+), 39 deletions(-) diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_translate.c index c02e60bb15b..a005c279a3e 100644 --- a/target/mips/tcg/loong_translate.c +++ b/target/mips/tcg/loong_translate.c @@ -31,13 +31,6 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt, TCGv t0, t1; TCGLabel *l1, *l2, *l3; - if (is_double) { - if (TARGET_LONG_BITS != 64) { - return false; - } - check_mips_64(s); - } - if (rd == 0) { /* Treat as NOP. */ return true; @@ -61,8 +54,7 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt, tcg_gen_br(l3); gen_set_label(l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS == 64 - ? LLONG_MIN : INT_MIN, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2); tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); tcg_gen_mov_tl(cpu_gpr[rd], t0); @@ -93,13 +85,6 @@ static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt, TCGv t0, t1; TCGLabel *l1, *l2; - if (is_double) { - if (TARGET_LONG_BITS != 64) { - return false; - } - check_mips_64(s); - } - if (rd == 0) { /* Treat as NOP. */ return true; @@ -147,13 +132,6 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt, TCGv t0, t1; TCGLabel *l1, *l2, *l3; - if (is_double) { - if (TARGET_LONG_BITS != 64) { - return false; - } - check_mips_64(s); - } - if (rd == 0) { /* Treat as NOP. */ return true; @@ -173,8 +151,7 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt, tcg_gen_ext32u_tl(t1, t1); } tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS == 64 - ? LLONG_MIN : INT_MIN, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2); tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); gen_set_label(l1); tcg_gen_movi_tl(cpu_gpr[rd], 0); @@ -205,13 +182,6 @@ static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt, TCGv t0, t1; TCGLabel *l1, *l2; - if (is_double) { - if (TARGET_LONG_BITS != 64) { - return false; - } - check_mips_64(s); - } - if (rd == 0) { /* Treat as NOP. */ return true; @@ -257,13 +227,6 @@ static bool gen_lext_MULT_G(DisasContext *s, int rd, int rs, int rt, { TCGv t0, t1; - if (is_double) { - if (TARGET_LONG_BITS != 64) { - return false; - } - check_mips_64(s); - } - if (rd == 0) { /* Treat as NOP. */ return true;