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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:49 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 01/18] arm/kvm: add support for MTE Date: Tue, 29 Oct 2024 15:10:31 +0000 Message-Id: <20241029151048.1047247-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Cornelia Huck Extend the 'mte' property for the virt machine to cover KVM as well. For KVM, we don't allocate tag memory, but instead enable the capability. If MTE has been enabled, we need to disable migration, as we do not yet have a way to migrate the tags as well. Therefore, MTE will stay off with KVM unless requested explicitly. [gankulkarni: This patch is rework of commit b320e21c48 which broke TCG since it made the TCG -cpu max report the presence of MTE to the guest even if the board hadn't enabled MTE by wiring up the tag RAM. This meant that if the guest then tried to use MTE QEMU would segfault accessing the non-existent tag RAM.] Signed-off-by: Cornelia Huck Reviewed-by: Gustavo Romero Signed-off-by: Ganapatrao Kulkarni Message-id: 20241008114302.4855-1-gankulkarni@os.amperecomputing.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/kvm_arm.h | 19 +++++++++++ hw/arm/virt.c | 76 +++++++++++++++++++++++++------------------- target/arm/cpu.c | 14 ++++++-- target/arm/kvm.c | 58 +++++++++++++++++++++++++++++++++ 5 files changed, 134 insertions(+), 35 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f065756c5c7..8fc8b6398f7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -922,6 +922,8 @@ struct ArchCPU { /* CPU has memory protection unit */ bool has_mpu; + /* CPU has MTE enabled in KVM mode */ + bool kvm_mte; /* PMSAv7 MPU number of supported regions */ uint32_t pmsav7_dregion; /* PMSAv8 MPU number of supported hyp regions */ diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index cfaa0d9bc71..4d293618a78 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -188,6 +188,13 @@ bool kvm_arm_pmu_supported(void); */ bool kvm_arm_sve_supported(void); +/** + * kvm_arm_mte_supported: + * + * Returns: true if KVM can enable MTE, and false otherwise. + */ +bool kvm_arm_mte_supported(void); + /** * kvm_arm_get_max_vm_ipa_size: * @ms: Machine state handle @@ -214,6 +221,8 @@ void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa); int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); +void kvm_arm_enable_mte(Object *cpuobj, Error **errp); + #else /* @@ -235,6 +244,11 @@ static inline bool kvm_arm_sve_supported(void) return false; } +static inline bool kvm_arm_mte_supported(void) +{ + return false; +} + /* * These functions should never actually be called without KVM support. */ @@ -283,6 +297,11 @@ static inline uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu) g_assert_not_reached(); } +static inline void kvm_arm_enable_mte(Object *cpuobj, Error **errp) +{ + g_assert_not_reached(); +} + #endif #endif diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 8b2b991d978..1a381e9a2bd 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2213,7 +2213,7 @@ static void machvirt_init(MachineState *machine) exit(1); } - if (vms->mte && (kvm_enabled() || hvf_enabled())) { + if (vms->mte && hvf_enabled()) { error_report("mach-virt: %s does not support providing " "MTE to the guest CPU", current_accel_name()); @@ -2283,39 +2283,51 @@ static void machvirt_init(MachineState *machine) } if (vms->mte) { - /* Create the memory region only once, but link to all cpus. */ - if (!tag_sysmem) { - /* - * The property exists only if MemTag is supported. - * If it is, we must allocate the ram to back that up. - */ - if (!object_property_find(cpuobj, "tag-memory")) { - error_report("MTE requested, but not supported " - "by the guest CPU"); + if (tcg_enabled()) { + /* Create the memory region only once, but link to all cpus. */ + if (!tag_sysmem) { + /* + * The property exists only if MemTag is supported. + * If it is, we must allocate the ram to back that up. + */ + if (!object_property_find(cpuobj, "tag-memory")) { + error_report("MTE requested, but not supported " + "by the guest CPU"); + exit(1); + } + + tag_sysmem = g_new(MemoryRegion, 1); + memory_region_init(tag_sysmem, OBJECT(machine), + "tag-memory", UINT64_MAX / 32); + + if (vms->secure) { + secure_tag_sysmem = g_new(MemoryRegion, 1); + memory_region_init(secure_tag_sysmem, OBJECT(machine), + "secure-tag-memory", + UINT64_MAX / 32); + + /* As with ram, secure-tag takes precedence over tag. */ + memory_region_add_subregion_overlap(secure_tag_sysmem, + 0, tag_sysmem, -1); + } + } + + object_property_set_link(cpuobj, "tag-memory", + OBJECT(tag_sysmem), &error_abort); + if (vms->secure) { + object_property_set_link(cpuobj, "secure-tag-memory", + OBJECT(secure_tag_sysmem), + &error_abort); + } + } else if (kvm_enabled()) { + if (!kvm_arm_mte_supported()) { + error_report("MTE requested, but not supported by KVM"); exit(1); } - - tag_sysmem = g_new(MemoryRegion, 1); - memory_region_init(tag_sysmem, OBJECT(machine), - "tag-memory", UINT64_MAX / 32); - - if (vms->secure) { - secure_tag_sysmem = g_new(MemoryRegion, 1); - memory_region_init(secure_tag_sysmem, OBJECT(machine), - "secure-tag-memory", UINT64_MAX / 32); - - /* As with ram, secure-tag takes precedence over tag. */ - memory_region_add_subregion_overlap(secure_tag_sysmem, 0, - tag_sysmem, -1); - } - } - - object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), - &error_abort); - if (vms->secure) { - object_property_set_link(cpuobj, "secure-tag-memory", - OBJECT(secure_tag_sysmem), - &error_abort); + kvm_arm_enable_mte(cpuobj, &error_abort); + } else { + error_report("MTE requested, but not supported "); + exit(1); } } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1320fd8c8fe..5b751439bdc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2390,14 +2390,22 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) #ifndef CONFIG_USER_ONLY /* - * If we do not have tag-memory provided by the machine, - * reduce MTE support to instructions enabled at EL0. + * If we run with TCG and do not have tag-memory provided by + * the machine, then reduce MTE support to instructions enabled at EL0. * This matches Cortex-A710 BROADCASTMTE input being LOW. */ - if (cpu->tag_memory == NULL) { + if (tcg_enabled() && cpu->tag_memory == NULL) { cpu->isar.id_aa64pfr1 = FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); } + + /* + * If MTE is supported by the host, however it should not be + * enabled on the guest (i.e mte=off), clear guest's MTE bits." + */ + if (kvm_enabled() && !cpu->kvm_mte) { + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); + } #endif } diff --git a/target/arm/kvm.c b/target/arm/kvm.c index f1f1b5b375a..000afa03631 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -39,6 +39,7 @@ #include "hw/acpi/acpi.h" #include "hw/acpi/ghes.h" #include "target/arm/gtimer.h" +#include "migration/blocker.h" const KVMCapabilityInfo kvm_arch_required_capabilities[] = { KVM_CAP_LAST_INFO @@ -119,6 +120,21 @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, if (vmfd < 0) { goto err; } + + /* + * The MTE capability must be enabled by the VMM before creating + * any VCPUs in order to allow the MTE bits of the ID_AA64PFR1 + * register to be probed correctly, as they are masked if MTE + * is not enabled. + */ + if (kvm_arm_mte_supported()) { + KVMState kvm_state; + + kvm_state.fd = kvmfd; + kvm_state.vmfd = vmfd; + kvm_vm_enable_cap(&kvm_state, KVM_CAP_ARM_MTE, 0); + } + cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); if (cpufd < 0) { goto err; @@ -1793,6 +1809,11 @@ bool kvm_arm_sve_supported(void) return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); } +bool kvm_arm_mte_supported(void) +{ + return kvm_check_extension(kvm_state, KVM_CAP_ARM_MTE); +} + QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1); uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu) @@ -2417,3 +2438,40 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) } return 0; } + +void kvm_arm_enable_mte(Object *cpuobj, Error **errp) +{ + static bool tried_to_enable; + static bool succeeded_to_enable; + Error *mte_migration_blocker = NULL; + ARMCPU *cpu = ARM_CPU(cpuobj); + int ret; + + if (!tried_to_enable) { + /* + * MTE on KVM is enabled on a per-VM basis (and retrying doesn't make + * sense), and we only want a single migration blocker as well. + */ + tried_to_enable = true; + + ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_ARM_MTE, 0); + if (ret) { + error_setg_errno(errp, -ret, "Failed to enable KVM_CAP_ARM_MTE"); + return; + } + + /* TODO: Add migration support with MTE enabled */ + error_setg(&mte_migration_blocker, + "Live migration disabled due to MTE enabled"); + if (migrate_add_blocker(&mte_migration_blocker, errp)) { + error_free(mte_migration_blocker); + return; + } + + succeeded_to_enable = true; + } + + if (succeeded_to_enable) { + cpu->kvm_mte = true; + } +} From patchwork Tue Oct 29 15:10:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 839337 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:4593:b0:37d:45d0:187 with SMTP id gb19csp426303wrb; Tue, 29 Oct 2024 08:12:00 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU+OK/RNROVRgOlp1MTbQRkIXr9TdI0KLs/49rWR7VymvSpzcD9Uw4AwlNxuMeDfYoiH+dtfw==@linaro.org X-Google-Smtp-Source: AGHT+IHgwCm1gllTk/NdX8Fp2VSQz8aqFWh6604k3Bb183i3daCF0FaPm0LWLS1iW/u6t3sMf3Zg X-Received: by 2002:a05:622a:352:b0:461:70cc:3793 with SMTP id d75a77b69052e-46170cc3c43mr2590871cf.43.1730214720250; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:50 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 02/18] docs/system/cpu-hotplug: Update example's socket-id/core-id Date: Tue, 29 Oct 2024 15:10:32 +0000 Message-Id: <20241029151048.1047247-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::130; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x130.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The example of how to do vCPU hotplug and hot-unlpug in the cpu-hotplug documentation no longer works, because the way we allocate socket-id and core-id to CPUs by default has changed at some point. The output also no longer matches what current QEMU produces in some more cosmetic ways. Update the example to match current QEMU. The differences are: * the second CPU is now socket-id=0 core-id=1, not socket-id=1 core-id=0 * the order of fields in QMP responses is now in alphabetical order * the "arch" member is no longer present in the query-cpus-fast output (it was removed in QEMU 6.0) Signed-off-by: Peter Maydell Acked-by: Igor Mammedov Message-id: 20241010131800.3210161-1-peter.maydell@linaro.org Message-id: 20240819144303.37852-1-peter.maydell@linaro.org --- docs/system/cpu-hotplug.rst | 56 ++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 29 deletions(-) diff --git a/docs/system/cpu-hotplug.rst b/docs/system/cpu-hotplug.rst index 015ce2b6ec3..cc50937c36c 100644 --- a/docs/system/cpu-hotplug.rst +++ b/docs/system/cpu-hotplug.rst @@ -33,23 +33,23 @@ vCPU hotplug { "return": [ { - "type": "IvyBridge-IBRS-x86_64-cpu", - "vcpus-count": 1, "props": { - "socket-id": 1, - "core-id": 0, + "core-id": 1, + "socket-id": 0, "thread-id": 0 - } + }, + "type": "IvyBridge-IBRS-x86_64-cpu", + "vcpus-count": 1 }, { + "props": { + "core-id": 0, + "socket-id": 0, + "thread-id": 0 + }, "qom-path": "/machine/unattached/device[0]", "type": "IvyBridge-IBRS-x86_64-cpu", - "vcpus-count": 1, - "props": { - "socket-id": 0, - "core-id": 0, - "thread-id": 0 - } + "vcpus-count": 1 } ] } @@ -58,18 +58,18 @@ vCPU hotplug (4) The ``query-hotpluggable-cpus`` command returns an object for CPUs that are present (containing a "qom-path" member) or which may be hot-plugged (no "qom-path" member). From its output in step (3), we - can see that ``IvyBridge-IBRS-x86_64-cpu`` is present in socket 0, - while hot-plugging a CPU into socket 1 requires passing the listed + can see that ``IvyBridge-IBRS-x86_64-cpu`` is present in socket 0 core 0, + while hot-plugging a CPU into socket 0 core 1 requires passing the listed properties to QMP ``device_add``:: - (QEMU) device_add id=cpu-2 driver=IvyBridge-IBRS-x86_64-cpu socket-id=1 core-id=0 thread-id=0 + (QEMU) device_add id=cpu-2 driver=IvyBridge-IBRS-x86_64-cpu socket-id=0 core-id=1 thread-id=0 { "execute": "device_add", "arguments": { - "socket-id": 1, + "core-id": 1, "driver": "IvyBridge-IBRS-x86_64-cpu", "id": "cpu-2", - "core-id": 0, + "socket-id": 0, "thread-id": 0 } } @@ -83,34 +83,32 @@ vCPU hotplug (QEMU) query-cpus-fast { - "execute": "query-cpus-fast", "arguments": {} + "execute": "query-cpus-fast", } { "return": [ { - "qom-path": "/machine/unattached/device[0]", - "target": "x86_64", - "thread-id": 11534, "cpu-index": 0, "props": { - "socket-id": 0, "core-id": 0, + "socket-id": 0, "thread-id": 0 }, - "arch": "x86" + "qom-path": "/machine/unattached/device[0]", + "target": "x86_64", + "thread-id": 28957 }, { - "qom-path": "/machine/peripheral/cpu-2", - "target": "x86_64", - "thread-id": 12106, "cpu-index": 1, "props": { - "socket-id": 1, - "core-id": 0, + "core-id": 1, + "socket-id": 0, "thread-id": 0 }, - "arch": "x86" + "qom-path": "/machine/peripheral/cpu-2", + "target": "x86_64", + "thread-id": 29095 } ] } @@ -123,10 +121,10 @@ From the 'qmp-shell', invoke the QMP ``device_del`` command:: (QEMU) device_del id=cpu-2 { - "execute": "device_del", "arguments": { "id": "cpu-2" } + "execute": "device_del", } { "return": {} From patchwork Tue Oct 29 15:10:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 839342 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:4593:b0:37d:45d0:187 with SMTP id gb19csp427933wrb; Tue, 29 Oct 2024 08:14:32 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVLkgLZQPL5HbI1iKHw0/iRj1eLCubSIW5ZuBoYW7D+lpFYZhxXbigiJ9t4hL36ngJrGOREfg==@linaro.org X-Google-Smtp-Source: AGHT+IH1bTgWzEAz/4fYnrj9v7qySCmESjjpSdTV8khxWQoGlUAkGy7aY1HQS/e8jHgbHlLG517J X-Received: by 2002:a05:622a:18a9:b0:461:3834:b79d with SMTP id d75a77b69052e-46167f3744amr45749661cf.0.1730214872069; Tue, 29 Oct 2024 08:14:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1730214872; cv=none; d=google.com; s=arc-20240605; b=iiFz31yrLlXZk6jJN+WBFe0FkWov/9BI9EsuFJEwgry6edZC39p9a3dgg2al9aWWOc LRBvFi4j2HrN32yTWGG1nKyBNYcD3BTTKrwemPqu3R1D9TE6x0IztYCFlD7m8+iWtYj0 hVSRp5GPqqpRpZW+m3JCkdwbxP8hMHUx7TrLmjdZyjXJFjU9jXvNnfbUKCs5nMaNguyT cVi0PxX6KUxpc+ryPLXQ/txUzPAtR5GJv6arziMuUSO/ioBxoq8DxnXb59VJ64pBleaP e8fA+WDA+4JXnijWjaP8u+vCrODHcM73pq4MA9pPW10TJkNGm88+OySWt8GyYy7B6wMC HjAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dknCWSvVj+vWyVYJJ1Ez77BInxMJDBp2lSUr7yhH5zA=; fh=qGH6gF5SfJefYWQesGwa016vFO5pQM+lEr3XTTtyKos=; b=ls/atM/GF7I2O+Qy6dzyncoCCbOGpEbGu3u+ubRoyTmLMj6deSx5g61HG44DwuDLH8 C3Zw0whT8hN2oak2vEbLxu7crltd5z7PCyVU2Acp+p9XlNGewYpU+LqWz8no1RYkenAp EVwggQI6yf8i5zk58YmD/JkpG7LtBXqyZCGl/BCoSgs8wbaCjiBQx8Y4TqzkLIHba8TU BjnTg5daWXJpfCvIbBIJVjYxxRilgqVUnDVaQ2jWptQZvNuF2NGc4/Ri9VIhi8bIG0Mv 9XN8uPunvoOYysCl4i9QIpxbUjuilp0Ht8j/NQM71RAwdnaOwGReGZNuicuBHB49Y2D9 fRyA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yHW6Wtft; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:50 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 03/18] target/arm: Store FPSR cumulative exception bits in env->vfp.fpsr Date: Tue, 29 Oct 2024 15:10:33 +0000 Message-Id: <20241029151048.1047247-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently we store the FPSR cumulative exception bits in the float_status fields, and use env->vfp.fpsr only for the NZCV bits. (The QC bit is stored in env->vfp.qc[].) This works for TCG, but if QEMU was built without CONFIG_TCG (i.e. with KVM support only) then we use the stub versions of vfp_get_fpsr_from_host() and vfp_set_fpsr_to_host() which do nothing, throwing away the cumulative exception bit state. The effect is that if the FPSR state is round-tripped from KVM to QEMU then we lose the cumulative exception bits. In particular, this will happen if the VM is migrated. There is no user-visible bug when using KVM with a QEMU binary that was built with CONFIG_TCG. Fix this by always storing the cumulative exception bits in env->vfp.fpsr. If we are using TCG then we may also keep pending cumulative exception information in the float_status fields, so we continue to fold that in on reads. This change will also be helpful for implementing FEAT_AFP later, because that includes a feature where in some situations we want to cause input denormals to be flushed to zero without affecting the existing state of the FPSR.IDC bit, so we need a place to store IDC which is distinct from the various float_status fields. (Note for stable backports: the bug goes back to 4a15527c9fee but this code was refactored in commits ea8618382aba..a8ab8706d4cc461, so fixing it in branches without those refactorings will mean either backporting the refactor or else implementing a conceptually similar fix for the old code.) Cc: qemu-stable@nongnu.org Fixes: 4a15527c9fee ("target/arm/vfp_helper: Restrict the SoftFloat use to TCG") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241011162401.3672735-1-peter.maydell@linaro.org --- target/arm/vfp_helper.c | 56 ++++++++++++----------------------------- 1 file changed, 16 insertions(+), 40 deletions(-) diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 203d37303bd..62638d2b1f9 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -59,32 +59,6 @@ static inline int vfp_exceptbits_from_host(int host_bits) return target_bits; } -/* Convert vfp exception flags to target form. */ -static inline int vfp_exceptbits_to_host(int target_bits) -{ - int host_bits = 0; - - if (target_bits & 1) { - host_bits |= float_flag_invalid; - } - if (target_bits & 2) { - host_bits |= float_flag_divbyzero; - } - if (target_bits & 4) { - host_bits |= float_flag_overflow; - } - if (target_bits & 8) { - host_bits |= float_flag_underflow; - } - if (target_bits & 0x10) { - host_bits |= float_flag_inexact; - } - if (target_bits & 0x80) { - host_bits |= float_flag_input_denormal; - } - return host_bits; -} - static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) { uint32_t i; @@ -99,15 +73,14 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) return vfp_exceptbits_from_host(i); } -static void vfp_set_fpsr_to_host(CPUARMState *env, uint32_t val) +static void vfp_clear_float_status_exc_flags(CPUARMState *env) { /* - * The exception flags are ORed together when we read fpscr so we - * only need to preserve the current state in one of our - * float_status values. + * Clear out all the exception-flag information in the float_status + * values. The caller should have arranged for env->vfp.fpsr to + * be the architecturally up-to-date exception flag information first. */ - int i = vfp_exceptbits_to_host(val); - set_float_exception_flags(i, &env->vfp.fp_status); + set_float_exception_flags(0, &env->vfp.fp_status); set_float_exception_flags(0, &env->vfp.fp_status_f16); set_float_exception_flags(0, &env->vfp.standard_fp_status); set_float_exception_flags(0, &env->vfp.standard_fp_status_f16); @@ -164,7 +137,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) return 0; } -static void vfp_set_fpsr_to_host(CPUARMState *env, uint32_t val) +static void vfp_clear_float_status_exc_flags(CPUARMState *env) { } @@ -216,8 +189,6 @@ void vfp_set_fpsr(CPUARMState *env, uint32_t val) { ARMCPU *cpu = env_archcpu(env); - vfp_set_fpsr_to_host(env, val); - if (arm_feature(env, ARM_FEATURE_NEON) || cpu_isar_feature(aa32_mve, cpu)) { /* @@ -231,13 +202,18 @@ void vfp_set_fpsr(CPUARMState *env, uint32_t val) } /* - * The only FPSR bits we keep in vfp.fpsr are NZCV: - * the exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in - * fp_status, and QC is in vfp.qc[]. Store the NZCV bits there, - * and zero any of the other FPSR bits. + * NZCV lives only in env->vfp.fpsr. The cumulative exception flags + * IOC|DZC|OFC|UFC|IXC|IDC also live in env->vfp.fpsr, with possible + * extra pending exception information that hasn't yet been folded in + * living in the float_status values (for TCG). + * Since this FPSR write gives us the up to date values of the exception + * flags, we want to store into vfp.fpsr the NZCV and CEXC bits, zeroing + * anything else. We also need to clear out the float_status exception + * information so that the next vfp_get_fpsr does not fold in stale data. */ - val &= FPSR_NZCV_MASK; + val &= FPSR_NZCV_MASK | FPSR_CEXC_MASK; env->vfp.fpsr = val; + vfp_clear_float_status_exc_flags(env); } static void vfp_set_fpcr_masked(CPUARMState *env, uint32_t val, uint32_t mask) From patchwork Tue Oct 29 15:10:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 839338 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:4593:b0:37d:45d0:187 with SMTP id gb19csp426763wrb; Tue, 29 Oct 2024 08:12:41 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV4R09IZuJ4eQauSSygoxleI4Xl6q+1FFoboSyk2zLlFF1rnw1ih1JintEPdTBGgYcqMcOnPQ==@linaro.org X-Google-Smtp-Source: AGHT+IEx+8sDMHKQiX35g9oeXu+cr5eqcafm6+b94f4SR8yTFz28GvQt7QsofWORzrZ+2deWfjm9 X-Received: by 2002:a05:622a:486:b0:45e:ff67:e058 with SMTP id d75a77b69052e-4613c19dd98mr201792491cf.44.1730214761065; Tue, 29 Oct 2024 08:12:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1730214761; cv=none; d=google.com; s=arc-20240605; b=HbzlmO0+lfVv3w13E84j0IBroI26iKEWSMT/DjE/NdUpCshlIaA8xDx+b0puuBw+9C vmWYPNvdJzuBVZMvv/NcAw3jBc1rtI6P2FLQ9lP8iKH3P/PU9LQ9Sb/NTB4VpKgHXpWF nYyxoh8zvdDZqyfh5t+TP9XF2FHh8H0DrcK2u2MQzLBVpANNnCctWYGJ4i+7hr04dAF5 oKxinaA5fLO32cMZXIPDmadMZ2zSZNRadQZabwP+fjzaMKI5VvshWCvHOPX0jOjKLlD0 pjbTFjdLL/qck2XxiKOLzasegodIqeAbmA9f7tFR57u6ewdfP7MAkiuPMexnv7xG+PAR TCiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=f2QKx5PpJ0hXtnqWhwoUN1/2lKp8MIaOWL67xtGys9o=; fh=bwgUiM8UkB6YpfaQbghgQxRB9BFj8QZwPlZgmtmTEGA=; b=B0yzgGkf6iBhqol6RIbRkkdO3chrzc5mq5GRmtOP6rAE8+fQQHd7352fEnWh6sP5rH KQ4LYmvKvas5RCtPxkPCJ27hukrtOG7WeToQMAIfqcR8+7akXl+ac5QyLNKe4fdrYpfi xG5HLB8Lm9OFxUz2nMRZsTOByprMSIzu6tUViAbHjiCtnO7oV8uWJo97cAdYnywscEfi AsmkmULEXNsL58sAf6Xzo6g9o4AFvDe8MB+dwrJWVclE8Ag71KKb4hJ5AalgkOFc0hcN J7wEx0qKI2ZKzJ5iv/mfqUQ6hhZaQqGTwLU6XrazDL34WcD0JhUV9gNtm01iIH+RVl+e VmjA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E1Nyz3Ym; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:51 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 04/18] target/arm: Don't assert in regime_is_user() for E10 mmuidx values Date: Tue, 29 Oct 2024 15:10:34 +0000 Message-Id: <20241029151048.1047247-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::130; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x130.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In regime_is_user() we assert if we're passed an ARMMMUIdx_E10_* mmuidx value. This used to make sense because we only used this function in ptw.c and would never use it on this kind of stage 1+2 mmuidx, only for an individual stage 1 or stage 2 mmuidx. However, when we implemented FEAT_E0PD we added a callsite in aa64_va_parameters(), which means this can now be called for stage 1+2 mmuidx values if the guest sets the TCG_ELX.{E0PD0,E0PD1} bits to enable use of the feature. This will then result in an assertion failure later, for instance on a TLBI operation: #6 0x00007ffff6d0e70f in g_assertion_message_expr (domain=0x0, file=0x55555676eeba "../../target/arm/internals.h", line=978, func=0x555556771d48 <__func__.5> "regime_is_user", expr=) at ../../../glib/gtestutils.c:3279 #7 0x0000555555f286d2 in regime_is_user (env=0x555557f2fe00, mmu_idx=ARMMMUIdx_E10_0) at ../../target/arm/internals.h:978 #8 0x0000555555f3e31c in aa64_va_parameters (env=0x555557f2fe00, va=18446744073709551615, mmu_idx=ARMMMUIdx_E10_0, data=true, el1_is_aa32=false) at ../../target/arm/helper.c:12048 #9 0x0000555555f3163b in tlbi_aa64_get_range (env=0x555557f2fe00, mmuidx=ARMMMUIdx_E10_0, value=106721347371041) at ../../target/arm/helper.c:5214 #10 0x0000555555f317e8 in do_rvae_write (env=0x555557f2fe00, value=106721347371041, idxmap=21, synced=true) at ../../target/arm/helper.c:5260 #11 0x0000555555f31925 in tlbi_aa64_rvae1is_write (env=0x555557f2fe00, ri=0x555557fbeae0, value=106721347371041) at ../../target/arm/helper.c:5302 #12 0x0000555556036f8f in helper_set_cp_reg64 (env=0x555557f2fe00, rip=0x555557fbeae0, value=106721347371041) at ../../target/arm/tcg/op_helper.c:965 Since we do know whether these mmuidx values are for usermode or not, we can easily make regime_is_user() handle them: ARMMMUIdx_E10_0 is user, and the other two are not. Cc: qemu-stable@nongnu.org Fixes: e4c93e44ab103f ("target/arm: Implement FEAT_E0PD") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Tested-by: Alex Bennée Message-id: 20241017172331.822587-1-peter.maydell@linaro.org --- target/arm/internals.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 299a96a81a7..fd8f7c82aa3 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -963,6 +963,7 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { + case ARMMMUIdx_E10_0: case ARMMMUIdx_E20_0: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: @@ -972,10 +973,6 @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) return true; default: return false; - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - g_assert_not_reached(); } } From patchwork Tue Oct 29 15:10:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 839343 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:4593:b0:37d:45d0:187 with SMTP id gb19csp427953wrb; Tue, 29 Oct 2024 08:14:33 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWQveeOajRVjXHb0KQKA9gdGVkT0OIBquZSX3ctvZuAH1JVG6K4S0nl3yinRs5cyAH42tv0sw==@linaro.org X-Google-Smtp-Source: AGHT+IGARIcH7Exbv/LYf4ViJ/Ja7zJIpzvXqBJuBfYEv9Nx5dzF0z+qV/TyucQhDr4gsa0ey7xB X-Received: by 2002:a05:620a:17a4:b0:7b1:448d:ea53 with SMTP id af79cd13be357-7b193eeaf01mr1658926485a.21.1730214873344; Tue, 29 Oct 2024 08:14:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1730214873; cv=none; d=google.com; s=arc-20240605; b=f99+4JCyCaLa2PTmWSgDfDIrNza3NSkEj67YX+Qg02CLHUIcBHieFQv9D9ErAITfdz RMTHM4O/E2feAg7T30LimsgMdE/uX012yoniBA2/6zbAbRPSVAPNeiQvx0rki7v2w+Og zqDP86dT9YONEIRSO4IYaPeQujZaW19uHc9o8nr4d1CKJ4flSREkbPjLmFPwS7NWKk3U 0ALo+EIR6MNShkuKOBWWDnuXYxKrKMQOBZrniHXUqEDQLXge8HvZJa/N9rwQLeF+tqkS o55jhjv4DYDBdpj2C19wogzN4+915B8ZhKJmK2K4yNPbIPHsDFQsREGfonD3EcQ51NGW fHNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Mn+Xz1D2FUsiusPJC2SlclU8g8noCDEQAV1urES3kd8=; fh=+TQikudlZNl5uMe/uvxYdn4PP31GRrkYtFNz1Jnv6E4=; b=j2pwCB5jyIsnxl2hiipy6UXh7Gn/h5KRJiFTemK5oHLe57FtJN3zw2yehqguw1e/Ug fTPO5KPV0LI5aKCDokvBz4I8/Y7bOTANYbuzo5FdjXrpChKjN5O9ArMUQj2T1bTaiCc9 OW5/fr19de/ePPcf9ex/jeypyRvTKtp+ERngq9HvXHCi7+8ir4fBcyRZ1d7EV0WCOxye BkHqlOC+tfPptXNh+YRCiM+fuDxtDmbT2nFQA+c5grdYyUqV/suoN5kQrF6XBQPFJawZ kkvECU7+dchCGzG0uzmCLqQDs+x+7m0Li/2i42A4NUASOkjne+SM8MKLr5iSgT6ea8nG T1lA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b0t7fMnr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:52 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 05/18] hw/sd/omap_mmc: Don't use sd_cmd_type_t Date: Tue, 29 Oct 2024 15:10:35 +0000 Message-Id: <20241029151048.1047247-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In commit 1ab08790bb75e4 we did some refactoring of the SD card implementation, which included a rearrangement of the sd_cmd_type_t enum values. Unfortunately we didn't notice that this enum is not used solely inside the SD card model itself, but is also used by the OMAP MMC controller device. In the OMAP MMC controller, it is used to implement the handling of the Type field of the MMC_CMD register, so changing the enum values so that they no longer lined up with the bit definitions for that register field broke the controller model. The effect is that Linux fails to boot from an SD card on the "sx1" machine. Give omap-mmc its own enum which we can document as needing to match the encoding used in this device's register, so it isn't sharing sd_cmd_type_t with the SD card model any more. We can then move sd_cmd_type_t's definition out of sd.h and into sd.c, which is the only place that uses it. Cc: qemu-stable@nongnu.org Fixes: 1ab08790bb75 ("hw/sd/sdcard: Store command type in SDProto") Signed-off-by: Peter Maydell Tested-by: Guenter Roeck Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241017162755.710698-1-peter.maydell@linaro.org --- include/hw/sd/sd.h | 8 -------- hw/sd/omap_mmc.c | 22 ++++++++++++++++------ hw/sd/sd.c | 8 ++++++++ 3 files changed, 24 insertions(+), 14 deletions(-) diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h index d35a839f5ef..f2458f37b3c 100644 --- a/include/hw/sd/sd.h +++ b/include/hw/sd/sd.h @@ -75,14 +75,6 @@ typedef enum { UHS_III = 3, /* currently not supported */ } sd_uhs_mode_t; -typedef enum { - sd_spi, - sd_bc, /* broadcast -- no response */ - sd_bcr, /* broadcast with response */ - sd_ac, /* addressed -- no data transfer */ - sd_adtc, /* addressed with data transfer */ -} sd_cmd_type_t; - typedef struct { uint8_t cmd; uint32_t arg; diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c index 91e9a3f1c6a..1d4e30e6b7b 100644 --- a/hw/sd/omap_mmc.c +++ b/hw/sd/omap_mmc.c @@ -103,6 +103,7 @@ static void omap_mmc_fifolevel_update(struct omap_mmc_s *host) } } +/* These must match the encoding of the MMC_CMD Response field */ typedef enum { sd_nore = 0, /* no response */ sd_r1, /* normal response command */ @@ -112,8 +113,17 @@ typedef enum { sd_r1b = -1, } sd_rsp_type_t; +/* These must match the encoding of the MMC_CMD Type field */ +typedef enum { + SD_TYPE_BC = 0, /* broadcast -- no response */ + SD_TYPE_BCR = 1, /* broadcast with response */ + SD_TYPE_AC = 2, /* addressed -- no data transfer */ + SD_TYPE_ADTC = 3, /* addressed with data transfer */ +} MMCCmdType; + static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir, - sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init) + MMCCmdType type, int busy, + sd_rsp_type_t resptype, int init) { uint32_t rspstatus, mask; int rsplen, timeout; @@ -128,7 +138,7 @@ static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir, if (resptype == sd_r1 && busy) resptype = sd_r1b; - if (type == sd_adtc) { + if (type == SD_TYPE_ADTC) { host->fifo_start = 0; host->fifo_len = 0; host->transfer = 1; @@ -433,10 +443,10 @@ static void omap_mmc_write(void *opaque, hwaddr offset, for (i = 0; i < 8; i ++) s->rsp[i] = 0x0000; omap_mmc_command(s, value & 63, (value >> 15) & 1, - (sd_cmd_type_t) ((value >> 12) & 3), - (value >> 11) & 1, - (sd_rsp_type_t) ((value >> 8) & 7), - (value >> 7) & 1); + (MMCCmdType)((value >> 12) & 3), + (value >> 11) & 1, + (sd_rsp_type_t) ((value >> 8) & 7), + (value >> 7) & 1); omap_mmc_update(s); break; diff --git a/hw/sd/sd.c b/hw/sd/sd.c index a5d2d929a8a..b2e2d58e013 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -71,6 +71,14 @@ typedef enum { sd_illegal = -2, } sd_rsp_type_t; +typedef enum { + sd_spi, + sd_bc, /* broadcast -- no response */ + sd_bcr, /* broadcast with response */ + sd_ac, /* addressed -- no data transfer */ + sd_adtc, /* addressed with data transfer */ +} sd_cmd_type_t; + enum SDCardModes { sd_inactive, sd_card_identification_mode, From patchwork Tue Oct 29 15:10:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 839339 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:4593:b0:37d:45d0:187 with SMTP id gb19csp427314wrb; Tue, 29 Oct 2024 08:13:31 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWIdroK79nggCEgPFlYxbY02KLDmvD6IHSuHiqWW4PIN9G9BnAEO/1qcq99nEdfY3UkvOvsig==@linaro.org X-Google-Smtp-Source: AGHT+IEZ7aPQ4RAcgJ7S6OIHt5W8ing2+FpV3lbw05lM7V2jVO6dpOn07jSN0vJWlScepvHkeeuR X-Received: by 2002:a05:620a:49e:b0:7b1:ae79:be2b with SMTP id af79cd13be357-7b1ae79bf6cmr30790485a.6.1730214811167; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:52 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 06/18] tests/functional: Add a functional test for the collie board Date: Tue, 29 Oct 2024 15:10:36 +0000 Message-Id: <20241029151048.1047247-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12f; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a functional test for the collie board that uses the kernel and rootfs provided by Guenter Roeck in the linux-test-downloads repo: https://github.com/groeck/linux-test-downloads/ This just boots Linux with a userspace that immediately reboots the board, so we wait for the reboot log line. Signed-off-by: Peter Maydell Reviewed-by: Thomas Huth Message-id: 20241017163247.711244-2-peter.maydell@linaro.org --- MAINTAINERS | 1 + tests/functional/meson.build | 1 + tests/functional/test_arm_collie.py | 31 +++++++++++++++++++++++++++++ 3 files changed, 33 insertions(+) create mode 100755 tests/functional/test_arm_collie.py diff --git a/MAINTAINERS b/MAINTAINERS index f48d9142b8a..6b1fa225d6e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -929,6 +929,7 @@ F: hw/arm/strongarm* F: hw/gpio/zaurus.c F: include/hw/arm/sharpsl.h F: docs/system/arm/collie.rst +F: tests/functional/test_arm_collie.py Stellaris M: Peter Maydell diff --git a/tests/functional/meson.build b/tests/functional/meson.build index 97c1c597e86..9538e103d6e 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -54,6 +54,7 @@ tests_alpha_system_thorough = [ tests_arm_system_thorough = [ 'arm_aspeed', 'arm_canona1100', + 'arm_collie', 'arm_integratorcp', 'arm_raspi2', 'arm_vexpress', diff --git a/tests/functional/test_arm_collie.py b/tests/functional/test_arm_collie.py new file mode 100755 index 00000000000..7e144a0a8fb --- /dev/null +++ b/tests/functional/test_arm_collie.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# +# Functional test that boots a Linux kernel on a collie machine +# and checks the console +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import LinuxKernelTest, Asset +from qemu_test.utils import archive_extract + +class CollieTest(LinuxKernelTest): + + ASSET_ZIMAGE = Asset( + 'https://github.com/groeck/linux-test-downloads/raw/225223f2ad7d637b34426810bf6c3b727b76a718/collie/zImage', + '10ace8abf9e0875ef8a83b8829cc3b5b50bc6d7bc3ca29f19f49f5673a43c13b') + + ASSET_ROOTFS = Asset( + 'https://github.com/groeck/linux-test-downloads/raw/225223f2ad7d637b34426810bf6c3b727b76a718/collie/rootfs-sa110.cpio', + '89ccaaa5c6b33331887047e1618ffe81b0f55909173944347d5d2426f3bcc1f2') + + def test_arm_collie(self): + self.set_machine('collie') + zimage_path = self.ASSET_ZIMAGE.fetch() + rootfs_path = self.ASSET_ROOTFS.fetch() + self.vm.add_args('-append', 'rdinit=/sbin/init console=ttySA1') + self.launch_kernel(zimage_path, + initrd=rootfs_path, + wait_for='reboot: Restarting system') + +if __name__ == '__main__': + LinuxKernelTest.main() From patchwork Tue Oct 29 15:10:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 839352 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:4593:b0:37d:45d0:187 with SMTP id gb19csp430529wrb; Tue, 29 Oct 2024 08:18:56 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX4msQAd3wTmf6tO3cblYu7C8ASgB0KlG5Ni9Jl7+HW6Lc/SNodKwXxx/VwsmvLdh2wwwOpfw==@linaro.org X-Google-Smtp-Source: AGHT+IF3em7jnF8CzJHdbL6fYdLqHBR76vNQNfAaQwP2ApSIcrJnATeKpLmoJu6DXSQUQiFIcHka X-Received: by 2002:a05:6808:4488:b0:3e6:24ec:d6f5 with SMTP id 5614622812f47-3e6384401ddmr12327210b6e.1.1730215136140; Tue, 29 Oct 2024 08:18:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1730215136; cv=none; d=google.com; s=arc-20240605; b=ARZvFIeSrxJFw5Ch+XEReRYAdr62vWNb7dY6eDVp2N2oZOCwuH1psHLvB80rWcVoLd hPqbeS7zuKVTPmbvJuYg8cE0rvLx4+yvvGv9M8ZyQ2QAiAUSrRTRLc3nr5C6HpTbrsY+ OaZoYa6zo07F7hGeRNYGkQpRVhE9mk+WAfuehe8rGlVEfcd9juqUMXfeROyJEIk7szYC 8OSQxaVK684jUjv1mOzVYOaHkM+BO9DrCMwuXDsiP6Sd8tMabPm7EEt0PAXryvRSi5a7 lTV1x8DcReJffWqZ23I0suoYlvfYRufxIdtTpJZfOz+IjvcKnPuv5uF4LKJyC9qqMo+d rqVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JhCeGWwX+tCxadLKUoZwKSNi6auX4Bcb310fZRJpZwY=; fh=ud05Ei1gWKu3WkLu4GDdg4C27BhUF4wNXwtyTfUxNZE=; b=D7eHX4x0O+C2qWOoeTCNUahXQDLViUhb9dC5uQnKAL4wpXcLcPWEIeoKOcgnoDM3Qa Q3eTmc1hLPMBU3EuoOtqp+x57/NHFuhwYDLljSnmlLB9MlREFeEHu81JN2n+YpoHpnkq rxA2ARIEj9QTEpz+gQNpLOPxt9q62NIUVNr0LTUkarbPhWWZzh9bg1S++/zLkBP3+N03 F1GySVK2YYmS8lnhj7GSKgGClZuNgXsAieId+qAJ4VpGYwrAZoB1pTJ9zI4so40yln3X udB1vN7z1CmRwKtKrM+AfwlFnq7Up+L7B1YimL/Gr1be+9jk7BLRIjnGkL5UTUxoGzqM ZMkA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nvg4SirY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:53 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 07/18] tests/functional: Add a functional test for the sx1 board Date: Tue, 29 Oct 2024 15:10:37 +0000 Message-Id: <20241029151048.1047247-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a functional test for the sx1 board that uses the kernel and rootfs provided by Guenter Roeck in the linux-test-downloads repo: https://github.com/groeck/linux-test-downloads/ We have three variants of the test for this board: * just boot initrd * boot with filesystem on SD card * boot from flash In all cases these images have a userspace that is configured to immediately reboot the system on successful boot, and the board itself supports telling QEMU to do the reboot, so we only need to wait for QEMU to exit (via -no-reboot). Since there are three subtests, the test as a whole takes about 80s on my local machine. That's about the same as the aarch64_virt test, so give it the same overall test timeout as that one. Signed-off-by: Peter Maydell Reviewed-by: Thomas Huth Message-id: 20241017163247.711244-3-peter.maydell@linaro.org --- tests/functional/meson.build | 2 + tests/functional/test_arm_sx1.py | 72 ++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) create mode 100755 tests/functional/test_arm_sx1.py diff --git a/tests/functional/meson.build b/tests/functional/meson.build index 9538e103d6e..84a07970d41 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -18,6 +18,7 @@ test_timeouts = { 'arm_aspeed' : 600, 'arm_raspi2' : 120, 'arm_tuxrun' : 120, + 'arm_sx1' : 360, 'mips_malta' : 120, 'netdev_ethtool' : 180, 'ppc_40p' : 240, @@ -57,6 +58,7 @@ tests_arm_system_thorough = [ 'arm_collie', 'arm_integratorcp', 'arm_raspi2', + 'arm_sx1', 'arm_vexpress', 'arm_tuxrun', ] diff --git a/tests/functional/test_arm_sx1.py b/tests/functional/test_arm_sx1.py new file mode 100755 index 00000000000..2d86405831e --- /dev/null +++ b/tests/functional/test_arm_sx1.py @@ -0,0 +1,72 @@ +#!/usr/bin/env python3 +# +# Copyright (c) 2024 Linaro Ltd. +# +# Functional test that boots a Linux kernel on an sx1 machine +# and checks the console. We have three variants: +# * just boot initrd +# * boot with filesystem on SD card +# * boot from flash +# In all cases these images have a userspace that is configured +# to immediately reboot the system on successful boot, so we +# only need to wait for QEMU to exit (via -no-reboot). +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import LinuxKernelTest, Asset +from qemu_test.utils import archive_extract + +class SX1Test(LinuxKernelTest): + + ASSET_ZIMAGE = Asset( + 'https://github.com/groeck/linux-test-downloads/raw/225223f2ad7d637b34426810bf6c3b727b76a718/sx1/zImage', + 'a0271899a8dc2165f9e0adb2d0a57fc839ae3a469722ffc56c77e108a8887615') + + ASSET_INITRD = Asset( + 'https://github.com/groeck/linux-test-downloads/raw/225223f2ad7d637b34426810bf6c3b727b76a718/sx1/rootfs-armv4.cpio', + '35b0721249821aa544cd85b85d3cb8901db4c6d128eed86ab261e5d9e37d58f8') + + ASSET_SD_FS = Asset( + 'https://github.com/groeck/linux-test-downloads/raw/225223f2ad7d637b34426810bf6c3b727b76a718/sx1/rootfs-armv4.ext2', + 'c1db7f43ef92469ebc8605013728c8950e7608439f01d13678994f0ce101c3a8') + + ASSET_FLASH = Asset( + 'https://github.com/groeck/linux-test-downloads/raw/225223f2ad7d637b34426810bf6c3b727b76a718/sx1/flash', + '17e6a2758fa38efd2666be0879d4751fd37d194f25168a8deede420df519b676') + + CONSOLE_ARGS = 'console=ttyS0,115200 earlycon=uart8250,mmio32,0xfffb0000,115200n8' + + def test_arm_sx1_initrd(self): + self.set_machine('sx1') + zimage_path = self.ASSET_ZIMAGE.fetch() + initrd_path = self.ASSET_INITRD.fetch() + self.vm.add_args('-append', f'kunit.enable=0 rdinit=/sbin/init {self.CONSOLE_ARGS}') + self.vm.add_args('-no-reboot') + self.launch_kernel(zimage_path, + initrd=initrd_path) + self.vm.wait() + + def test_arm_sx1_sd(self): + self.set_machine('sx1') + zimage_path = self.ASSET_ZIMAGE.fetch() + sd_fs_path = self.ASSET_SD_FS.fetch() + self.vm.add_args('-append', f'kunit.enable=0 root=/dev/mmcblk0 rootwait {self.CONSOLE_ARGS}') + self.vm.add_args('-no-reboot') + self.vm.add_args('-snapshot') + self.vm.add_args('-drive', f'format=raw,if=sd,file={sd_fs_path}') + self.launch_kernel(zimage_path) + self.vm.wait() + + def test_arm_sx1_flash(self): + self.set_machine('sx1') + zimage_path = self.ASSET_ZIMAGE.fetch() + flash_path = self.ASSET_FLASH.fetch() + self.vm.add_args('-append', f'kunit.enable=0 root=/dev/mtdblock3 rootwait {self.CONSOLE_ARGS}') + self.vm.add_args('-no-reboot') + self.vm.add_args('-snapshot') + self.vm.add_args('-drive', f'format=raw,if=pflash,file={flash_path}') + self.launch_kernel(zimage_path) + self.vm.wait() + +if __name__ == '__main__': + LinuxKernelTest.main() From patchwork Tue Oct 29 15:10:38 2024 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:53 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 08/18] scripts/symlink-install-tree.py: Fix MESONINTROSPECT parsing Date: Tue, 29 Oct 2024 15:10:38 +0000 Message-Id: <20241029151048.1047247-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Akihiko Odaki The arguments in MESONINTROSPECT are quoted with shlex.quote() so it must be parsed with shlex.split(). Otherwise the script will fail if the build directory has a character like "~" in it. Note: this fix cannot be backported directly to any stable branch that doesn't require Meson version 1.4.0 or better; otherwise it will work OK on Linux but will break on Windows hosts. (Unfortunately, Meson prior to version 1.4.0 was inconsistent between host OSes about how it quoted arguments, and used a different quoting process on Windows hosts. Our current git trunk already requires 1.5.0 as of commit 07f0d32641e ("Require meson version 1.5.0"), but the stable branches are still on older Meson.) Fixes: cf60ccc330 ("cutils: Introduce bundle mechanism") Reported-by: Michael Tokarev Signed-off-by: Akihiko Odaki Signed-off-by: Peter Maydell Reviewed-by: Pierrick Bouvier Tested-by: Pierrick Bouvier Message-id: 20241018130852.931509-1-peter.maydell@linaro.org [PMM: Updated commit message to give all the detail about the Meson version compability requirements.] Signed-off-by: Peter Maydell --- scripts/symlink-install-tree.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/scripts/symlink-install-tree.py b/scripts/symlink-install-tree.py index 8ed97e3c943..b72563895c5 100644 --- a/scripts/symlink-install-tree.py +++ b/scripts/symlink-install-tree.py @@ -4,6 +4,7 @@ import errno import json import os +import shlex import subprocess import sys @@ -14,7 +15,7 @@ def destdir_join(d1: str, d2: str) -> str: return str(PurePath(d1, *PurePath(d2).parts[1:])) introspect = os.environ.get('MESONINTROSPECT') -out = subprocess.run([*introspect.split(' '), '--installed'], +out = subprocess.run([*shlex.split(introspect), '--installed'], stdout=subprocess.PIPE, check=True).stdout for source, dest in json.loads(out).items(): bundle_dest = destdir_join('qemu-bundle', dest) From patchwork Tue Oct 29 15:10:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 839351 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:4593:b0:37d:45d0:187 with SMTP id gb19csp430530wrb; Tue, 29 Oct 2024 08:18:56 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXp6VyyCYxz4zKNNnXPEfj/4MOoWFSclcsaB4ZpMZWzt8wxfSibEjsyW96eTwsr0wIvVjl03Q==@linaro.org X-Google-Smtp-Source: AGHT+IGU5CtovzB0bsIHYJOccfOdEAEQE+d7jRPQYssAmrIFoE1DVkPFB9KBRb5j/fTaqjMhTNj8 X-Received: by 2002:a05:6122:3bd1:b0:50d:8248:83bf with SMTP id 71dfb90a1353d-510150e2e06mr9020398e0c.9.1730215136052; Tue, 29 Oct 2024 08:18:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1730215136; cv=none; d=google.com; s=arc-20240605; b=OC7KLF+dNPzsp4f5O7BpymXxteKJysqHQvyWieA46p4UVU4MvCFPCYjULH9BEtZszy DTKTVPe6ETFjt4uMrBLer8nAdqN/IZk12g9DZlYcy6MbN9h78p5kLywAgebOMYP51SQX XtwQBnWT3mm5hE9wS1QlrGzWzvfIsdOFv4D520t0lvU6Z+ZiYpPxKt7U1+nd3eVJtJa5 9JDMAmhAoxOh8YLQKC5mOlR2wzU1QeUrzQOggq+TYGWvzeV3KYkU+XBHvP0wobPc0fK1 Gs5oQC6PYuv8BwkK/tYIx3JlyJqRhzHsv48hYIQXrD2YvsjHeAcGe2nZZEeAuhCuaU90 BljA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5gzoNBFS1PLdNZcKXEgXxV1vP4J/3wc0pQNMQSx1OQQ=; fh=esJkQLgjUlYEHGKfCJFpdH8UjBEhjuM1JC6jprPBCTY=; b=LqewF58lp+NGRhGjFDzTUu0xxbbRon9JHQwJB2bHLvAhhfHowtjuiS6jEvKxGRrz6H qUuhp6VFSGxtmQHXHAMG0RXQxpccX1ufDCYukYdrQTxlKMDYW0fe5UQuKwMfSjo7ggVr 5Q7TzyqAn+ncud4SEfDPMSldEYsOXC0wqN4EfKwOYZkEMFWom88e2FEK9Crw0oyHokKX Ug8OPUS0oDvvvg3bVhiBUdzf/XbzSef3zhLg2tRUalfUn9xAJgGBKJKTsVPMjzh3qi0h Cko0OEgCGtONsnDcGp2kEEuZdBS//D/ywmzTc8vYX0RvTNzyTaKhQpr6kcRISgiW7XQw uVSg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QCRyY+uD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:54 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 09/18] docs/system/arm/stm32: List olimex-stm32-h405 in document title Date: Tue, 29 Oct 2024 15:10:39 +0000 Message-Id: <20241029151048.1047247-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org List the olimex-stm32-h405 board in the document title, so that the board name appears in the table of contents in system/target-arm.rst. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Cédric Le Goater Message-id: 20241018141332.942844-2-peter.maydell@linaro.org --- docs/system/arm/stm32.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst index ca7a55841b4..511e3eb9ac1 100644 --- a/docs/system/arm/stm32.rst +++ b/docs/system/arm/stm32.rst @@ -1,5 +1,5 @@ -STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``stm32vldiscovery``) -======================================================================================== +STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olimex-stm32-h405``, ``stm32vldiscovery``) +=============================================================================================================== The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by STMicroelectronics. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:54 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 10/18] docs/system/arm: Don't use wildcard '*-bmc' in doc titles Date: Tue, 29 Oct 2024 15:10:40 +0000 Message-Id: <20241029151048.1047247-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We have two Arm board doc files which both use '*-bmc' in their documentation title. The result is that when you read the table of contents in system/target-arm.html you don't know which boards are covered by which file. Expand out the board names entirely in the document titles. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Cédric Le Goater Message-id: 20241018141332.942844-3-peter.maydell@linaro.org --- docs/system/arm/aspeed.rst | 4 ++-- docs/system/arm/nuvoton.rst | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 6733ffd2b94..968ba88b997 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -1,5 +1,5 @@ -Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``) -=================================================================================== +Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``) +======================================================================================================================================================================================================================================================================================================================================================================================================== The QEMU Aspeed machines model BMCs of various OpenPOWER systems and Aspeed evaluation boards. They are based on different releases of the diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index 0424cae4b01..05059378e55 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -1,5 +1,5 @@ -Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``) -================================================================ +Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj``) +===================================================================================================== The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are designed to be used as Baseboard Management Controllers (BMCs) in various From patchwork Tue Oct 29 15:10:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 839341 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:4593:b0:37d:45d0:187 with SMTP id gb19csp427853wrb; Tue, 29 Oct 2024 08:14:24 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUUtpYNLeXFQn71APwoAjg26xZKQ2STGYda11InARo7pKyaJEMrLNz4zbbSiVg2ydoluVJtYw==@linaro.org X-Google-Smtp-Source: AGHT+IE5bR0IJyeLzKedhSBDR/yPppC0TdkIQPsYjdaemK0B9GWw4RhlS+MGFCm+zYnJdlNwtHua X-Received: by 2002:a05:6214:5783:b0:6c3:5833:260f with SMTP id 6a1803df08f44-6d18587e93dmr205131746d6.39.1730214864009; Tue, 29 Oct 2024 08:14:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1730214863; cv=none; d=google.com; s=arc-20240605; b=ZoeJfMCtFIHCSnel9ALGbWata0/s7MDB1lfhSy0bxwF70Ku5PfNZ32psuK8DjJEVeQ QBlerThzT2OKTPBMCnjWQ2fw+er5qWIMoaiZS8uZ4UbSUHViFg1YVy8iV4DN21J7pIiZ dLjQWa/LJkPg3V1AvHMpXEbQ7Ut9pO2mgq2hRdmPfbbGHdJTqIthY8ozb5FsPNdDtSLC /RE4LCKFFJKl5DSBSog93xgoPxGN5L2Jgu+AtpHOkcPUr3jn7zn1PRIPQWDIX4d/t9f6 U7X+9MiDx+M+IbQBosJf6iHSFwhN+a5TnV9Cp5BTjeK+WKdLX1+0arQdXMez1TV7UnYf fxyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Le5KO4n1JBHxVJ58eqGZ4EhoqdvJDYpjRshzm7ZvnO8=; fh=FJEKdKDhuTiAEfyZLUOYI8L4LiWeSVgnAZ2Ue/4ic1I=; b=kKJc8kyyVHEVFPjqlsjFtfz4y2wVTwH2GkR4vsPu1maA4pRDXfuh83dsSmwvjIkmRy urB3QpEob4+N60V5Q5IjlKsSaKcVUzPNJXYNZhcfsxs6p5oMlPkJ5vRlTnvwMFdLWBht YzlDt1o5PrW7oDUVQWMSa27+pgBmiUhKAoNCAVlAuW62DkSp9itE/dT4XvuFTGZKuGE3 i+OVkQXV4tHiVaydCKX8RzUYmO7hH9nUDFBGZlONuxlWrA10JHDn/RckiQbjEUr538mw iHsSKw9Q6+TwsSidO1HE1GKsT1uCZ2/O6LhSDE4gutnDGaTquJxmgh6q8HKSE3xH6Nv3 oi9A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f95HTwa7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 11/18] docs/system/arm: Split fby35 out from aspeed.rst Date: Tue, 29 Oct 2024 15:10:41 +0000 Message-Id: <20241029151048.1047247-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The fby35 machine is not implemented in hw/arm/aspeed.c, but its documentation is currently stuck at the end of aspeed.rst, formatted in a way that it gets its own heading in the top-level list of boards in target-arm.html. We don't have any other boards that we document like this; split it out into its own rst file. This improves consistency with other board docs and means we can have the entry in the target-arm list be in the correct alphabetical order. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Cédric Le Goater Message-id: 20241018141332.942844-4-peter.maydell@linaro.org --- MAINTAINERS | 1 + docs/system/arm/aspeed.rst | 48 -------------------------------------- docs/system/arm/fby35.rst | 47 +++++++++++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + 4 files changed, 49 insertions(+), 48 deletions(-) create mode 100644 docs/system/arm/fby35.rst diff --git a/MAINTAINERS b/MAINTAINERS index 6b1fa225d6e..e74d16bcf1d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1123,6 +1123,7 @@ F: include/hw/*/*aspeed* F: hw/net/ftgmac100.c F: include/hw/net/ftgmac100.h F: docs/system/arm/aspeed.rst +F: docs/system/arm/fby35.rst F: tests/*/*aspeed* F: tests/*/*ast2700* F: hw/arm/fby35.c diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 968ba88b997..63910d382fe 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -257,51 +257,3 @@ To boot a kernel directly from a Zephyr build tree: $ qemu-system-arm -M ast1030-evb -nographic \ -kernel zephyr.elf - -Facebook Yosemite v3.5 Platform and CraterLake Server (``fby35``) -================================================================== - -Facebook has a series of multi-node compute server designs named -Yosemite. The most recent version released was -`Yosemite v3 `__. - -Yosemite v3.5 is an iteration on this design, and is very similar: there's a -baseboard with a BMC, and 4 server slots. The new server board design termed -"CraterLake" includes a Bridge IC (BIC), with room for expansion boards to -include various compute accelerators (video, inferencing, etc). At the moment, -only the first server slot's BIC is included. - -Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds -can be fit into a chassis. See `here `__ -for an example. - -In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC -runs `OpenBMC `__, and the BIC runs -`OpenBIC `__. - -Firmware images can be retrieved from the Github releases or built from the -source code, see the README's for instructions on that. This image uses the -"fby35" machine recipe from OpenBMC, and the "yv35-cl" target from OpenBIC. -Some reference images can also be found here: - -.. code-block:: bash - - $ wget https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd - $ wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf - -Since this machine has multiple SoC's, each with their own serial console, the -recommended way to run it is to allocate a pseudoterminal for each serial -console and let the monitor use stdio. Also, starting in a paused state is -useful because it allows you to attach to the pseudoterminals before the boot -process starts. - -.. code-block:: bash - - $ qemu-system-arm -machine fby35 \ - -drive file=fby35.mtd,format=raw,if=mtd \ - -device loader,file=Y35BCL.elf,addr=0,cpu-num=2 \ - -serial pty -serial pty -serial mon:stdio \ - -display none -S - $ screen /dev/tty0 # In a separate TMUX pane, terminal window, etc. - $ screen /dev/tty1 - $ (qemu) c # Start the boot process once screen is setup. diff --git a/docs/system/arm/fby35.rst b/docs/system/arm/fby35.rst new file mode 100644 index 00000000000..742b887d44c --- /dev/null +++ b/docs/system/arm/fby35.rst @@ -0,0 +1,47 @@ +Facebook Yosemite v3.5 Platform and CraterLake Server (``fby35``) +================================================================== + +Facebook has a series of multi-node compute server designs named +Yosemite. The most recent version released was +`Yosemite v3 `__. + +Yosemite v3.5 is an iteration on this design, and is very similar: there's a +baseboard with a BMC, and 4 server slots. The new server board design termed +"CraterLake" includes a Bridge IC (BIC), with room for expansion boards to +include various compute accelerators (video, inferencing, etc). At the moment, +only the first server slot's BIC is included. + +Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds +can be fit into a chassis. See `here `__ +for an example. + +In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC +runs `OpenBMC `__, and the BIC runs +`OpenBIC `__. + +Firmware images can be retrieved from the Github releases or built from the +source code, see the README's for instructions on that. This image uses the +"fby35" machine recipe from OpenBMC, and the "yv35-cl" target from OpenBIC. +Some reference images can also be found here: + +.. code-block:: bash + + $ wget https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd + $ wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf + +Since this machine has multiple SoC's, each with their own serial console, the +recommended way to run it is to allocate a pseudoterminal for each serial +console and let the monitor use stdio. Also, starting in a paused state is +useful because it allows you to attach to the pseudoterminals before the boot +process starts. + +.. code-block:: bash + + $ qemu-system-arm -machine fby35 \ + -drive file=fby35.mtd,format=raw,if=mtd \ + -device loader,file=Y35BCL.elf,addr=0,cpu-num=2 \ + -serial pty -serial pty -serial mon:stdio \ + -display none -S + $ screen /dev/tty0 # In a separate TMUX pane, terminal window, etc. + $ screen /dev/tty1 + $ (qemu) c # Start the boot process once screen is setup. diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 3c0a5848453..9c01e66ffa9 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -90,6 +90,7 @@ undocumented; you can get a complete list by running arm/digic arm/cubieboard arm/emcraft-sf2 + arm/fby35 arm/musicpal arm/kzm arm/nrf From patchwork Tue Oct 29 15:10:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 839336 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:4593:b0:37d:45d0:187 with SMTP id gb19csp425984wrb; Tue, 29 Oct 2024 08:11:29 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV2gEk4JN0mieQYApQq/4tX6112+L7REI2/fPaQ6sLUOTzaisdnFtHEKL3yuigdTCojAO6V7Q==@linaro.org X-Google-Smtp-Source: AGHT+IFcEBns/IP9PMMuMKTHPdLB1V29aJ8jybr/SWL1ObqUlexH6Sj8KVm3HxG37Uolv0/TmlfG X-Received: by 2002:a05:6214:5783:b0:6c3:5833:260f with SMTP id 6a1803df08f44-6d18587e93dmr204995836d6.39.1730214689725; Tue, 29 Oct 2024 08:11:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1730214689; cv=none; d=google.com; s=arc-20240605; b=Mc0HXWJoSelUp1jPAttIh2r+Fwn8WjFE++DfpKSYVok9xIJN+MhuyNamS+LLinEVpS vHvEjMkklkl0z43Dk877k1c0xp3AAAUoBnXkNzdArgT6cxsb0rD4nBVezIhBpbNa9vUP SBxeujro5QLcSR67JVGtwiQXxlrpHh/KB4sWuRMszqltl0X1E4SYJoBXKmhIFyKE4n6a UFyywETJorzPoM5E0JNdkBdqG8LFBLSCYJajaIwYCWrG4mnfUKH01thni1EpdibjUcmO qZ90EDHdQ5k14e9+l55tCIhUpdk44ZFMAGTNyFUlrhHKgvingCrqk7EhKqqoDKIQwM1A FgPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Bt3TVOiuCfVWs2EI3zsc1F1KzgFJR+PP7ljtiyNrGF0=; fh=Lm+ucA6ODisdSYhK6bKs47Wv14N27FdDwWZppa47P3I=; b=KClsnG/cxMTG+JW0tDgofnnWKb4I/psJ/3V8sSl8K/33VAhHU6aGYhsAxZkORSs3c0 PgD70Q6Ga4LnkNGGqHNH8rjH6El5eRMVSA4rKt9zH6Eikeg0UIqtP+usjRhj+x8w4rjx cAdxG4guPoaKxD2YBQIc9cUU9gmr2F+CbgxGYmv5s5K55R4PLei0vCWjp7gY5Wb2JxUi wyeYI/BUaU5db86p/Iszv0lgCqjlaaLzUAxLSRrJ7Q8H+vFqJBpYWoTjrUN7mI/QqznL 5ivKfiPcbw4mx7OLfAirTm9TVygw9D4ko1tI7vBYcEAklxcqsKvgQ6Ch29Sa7JinOOm+ /A/w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tm0v3vnw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 12/18] docs/system/arm: Add placeholder doc for exynos4 boards Date: Tue, 29 Oct 2024 15:10:42 +0000 Message-Id: <20241029151048.1047247-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a placeholder doc for the exynos4 boards nuri and smdkc210. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Cédric Le Goater Message-id: 20241018141332.942844-5-peter.maydell@linaro.org --- MAINTAINERS | 1 + docs/system/arm/exynos.rst | 9 +++++++++ docs/system/target-arm.rst | 1 + 3 files changed, 11 insertions(+) create mode 100644 docs/system/arm/exynos.rst diff --git a/MAINTAINERS b/MAINTAINERS index e74d16bcf1d..2b524d7af54 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -716,6 +716,7 @@ L: qemu-arm@nongnu.org S: Odd Fixes F: hw/*/exynos* F: include/hw/*/exynos* +F: docs/system/arm/exynos.rst Calxeda Highbank M: Rob Herring diff --git a/docs/system/arm/exynos.rst b/docs/system/arm/exynos.rst new file mode 100644 index 00000000000..86894bc02b7 --- /dev/null +++ b/docs/system/arm/exynos.rst @@ -0,0 +1,9 @@ +Exynos4 boards (``nuri``, ``smdkc210``) +======================================= + +These are machines which use the Samsung Exynos4210 SoC, which has Cortex-A9 CPUs. + +``nuri`` models the Samsung NURI board. + +``smdkc210`` models the Samsung SMDKC210 board. + diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 9c01e66ffa9..a7f88c8f317 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -90,6 +90,7 @@ undocumented; you can get a complete list by running arm/digic arm/cubieboard arm/emcraft-sf2 + arm/exynos arm/fby35 arm/musicpal arm/kzm From patchwork Tue Oct 29 15:10:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 839347 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:4593:b0:37d:45d0:187 with SMTP id gb19csp428887wrb; Tue, 29 Oct 2024 08:16:00 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXMTr8J8AZmYmJfl1i8Eg68CHjJm8ysv0wng52KtzX9o75WysikzC7IWbRmBjBJ4l59Dv4hlQ==@linaro.org X-Google-Smtp-Source: AGHT+IEoKb8+z4lfVfkD6IpU0eEOtJj71V6ZptH8ikLCQs8alQEtqGhsX6WpRCv7nIekp3hIvEIg X-Received: by 2002:a05:6214:311e:b0:6cb:a355:10a9 with SMTP id 6a1803df08f44-6d18587ecabmr156045146d6.34.1730214960728; Tue, 29 Oct 2024 08:16:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1730214960; cv=none; d=google.com; s=arc-20240605; b=O6ATpFfaMd5h4WuAw9s8d1t4mkFms/ybFXwRn48KPJxj4/y9Ir8xrdRViH54yAN676 8XE/N3ls85uM0v/izfVRWSYU+CAPg5JvnYlxsK3cE+o7wj7yf8Cet913Xo7SpbWtzLcG E1TdGUF9JI2OB6EE9qPOy7xi5u5P6aHFCG3pPjTuwpHotZLlw3R0nVoq8mMw1++YQ3Y1 s+XHPgpW5KZHT0GamFyWCKKdRcXJlaYAEf402vw0eZ5vCzP6E4tM9aAkMtAgmsSEo1E/ a7YD06zK5FjZPc4Agm88PMOkY1xa6LKJV79LE0ybxmIgoS0EjME5r3hpIaEzA2Cgu5jS 4cAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=y+/gn5PrRHI6aUAYrICmiO61nI9SeFkHZ/jV7ZOSLYc=; fh=yZhXkKuTQnPc9+tlBwMmnb8Hv6eiMihiu/3IK36kbUk=; b=kzyDXTRRwwITsmk7glD7wZcZfngApEw29fL9KpS+Hw/VFQhJgnmyRjv3s2IUUE96p6 LlRx1AHDFKDVP6pmI+fD9sfUWsXR7DwOHtAsYADr8bHiUGBfTYv3847vYXvWvtLuWXXb YSF6aNYbKj3KrXeBCGvohab1iaAE8zzmmd276A/symRmaDvOQpyO2o0qcORWzRPanfwK gxEHX9fRUG11qkzyZ93grflZPmkYjewGXMp+Cy4Thgt4N5JpyJ8HuvlH/ipkLvvoZjFP XgLyKg3kyc5p+5MbTLRKnd6R1X08NrmArS5KHstZv0VSCa/BSZu+Lu7CCHwaPrpArB0U 1Dmg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cgi33KTs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:56 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 13/18] docs/system/arm: Add placeholder doc for xlnx-zcu102 board Date: Tue, 29 Oct 2024 15:10:43 +0000 Message-Id: <20241029151048.1047247-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a placeholder doc for the xlnx-zcu102 board. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Cédric Le Goater Reviewed-by: Alistair Francis Message-id: 20241018141332.942844-6-peter.maydell@linaro.org --- MAINTAINERS | 1 + docs/system/arm/xlnx-zcu102.rst | 19 +++++++++++++++++++ docs/system/target-arm.rst | 1 + 3 files changed, 21 insertions(+) create mode 100644 docs/system/arm/xlnx-zcu102.rst diff --git a/MAINTAINERS b/MAINTAINERS index 2b524d7af54..66c7572c27b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1018,6 +1018,7 @@ F: include/hw/ssi/xilinx_spips.h F: hw/display/dpcd.c F: include/hw/display/dpcd.h F: docs/system/arm/xlnx-versal-virt.rst +F: docs/system/arm/xlnx-zcu102.rst Xilinx Versal OSPI M: Francisco Iglesias diff --git a/docs/system/arm/xlnx-zcu102.rst b/docs/system/arm/xlnx-zcu102.rst new file mode 100644 index 00000000000..534cd1dc887 --- /dev/null +++ b/docs/system/arm/xlnx-zcu102.rst @@ -0,0 +1,19 @@ +Xilinx ZynqMP ZCU102 (``xlnx-zcu102``) +====================================== + +The ``xlnx-zcu102`` board models the Xilinx ZynqMP ZCU102 board. +This board has 4 Cortex-A53 CPUs and 2 Cortex-R5F CPUs. + +Machine-specific options +"""""""""""""""""""""""" + +The following machine-specific options are supported: + +secure + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the + Arm Security Extensions (TrustZone). The default is ``off``. + +virtualization + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the + Arm Virtualization Extensions. The default is ``off``. + diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index a7f88c8f317..ace36d1b17d 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -107,6 +107,7 @@ undocumented; you can get a complete list by running arm/xenpvh arm/xlnx-versal-virt arm/xlnx-zynq + arm/xlnx-zcu102 Emulated CPU architecture support ================================= From patchwork Tue Oct 29 15:10:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 839353 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:4593:b0:37d:45d0:187 with SMTP id gb19csp430656wrb; Tue, 29 Oct 2024 08:19:09 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV9TiTz+M1Eavn+xbECdb193hxEtSyaIUdX79rtpLCiA7tj1iHisXuQ1G+6JLbM8o5qdbUnkw==@linaro.org X-Google-Smtp-Source: AGHT+IFyd8KbdG5k5qNraLl5EKPHxm99NWTo2nfpkjtA+pqhpCvve9D9asVIaaSZjNaecP3Ys+1N X-Received: by 2002:a05:6102:512c:b0:4a4:7161:5e4 with SMTP id ada2fe7eead31-4a8cf9e9d58mr11955709137.0.1730215149001; Tue, 29 Oct 2024 08:19:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1730215148; cv=none; d=google.com; s=arc-20240605; b=aqGij2alqOfygwn6xRl7lkkJifNw/KWjhSp0SGhJjS9/RFrKBv8855ok7jXXqTofIZ cmDkVmI6x36BoEnsI6v2wVWdhUE2ugbGGAX6TVrSrpgZ+11Bhjv9onE2Sy5J1a30ALXs Ge3nmn3IiCFMwabt12mrn+v671K9qlfjSDm6OqIM8dxuERLbVPsvlrAJyQz9D2/bv9/B nuSzmhLxvmRGUAAILK7M+INUxsPpBGJQkHHLwn/W8LdyK5F7q1YGlloYQXjrUJzjZ98T uDAdHSWFL0QC8I4w93BjIcS5PDpdlkcHv7fmYYq8tAkIqgmBpbixuIh4+qAwqr59CLfu 6Wcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=t1ofx0L3R12Y3Qfk5twMRKrNngXzbSoAXzZlWcI4ZBk=; fh=rQdQhhWcKdmTIXgHfT+sshBl7C5SaPtPTD6PfSGLuTQ=; b=IKXYZKRtf4iQF35IU9tT2OtNMIZSZaY5LZYTILZYcjcXmrdAgfDznVVnRwTJhcKrCp Ee5vCRrnI+fKc2jn1FnJ3wSisOLY3D4ttVkC65zeRvJAGANREusRFNJxhFpU9hWakRu9 tqoQilaIImt0C5wvodBUI13QC61QrNd27+SAuHHuV0weGw6oY6np9MvVEiu665fsFJnH gO5tg9gCCqkCLjW+/ZxBy6gcYEuTJquXq8r2CyTn0yk3oavlxgtQ5Vpgz13CLc3c3DOP GbKXxlpIydkKwqEI0tBUCsq8L5cIWykR2k51RBrgr4KZ17KSaJWAmvxpGG7avbQO8c36 RmcA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="vgm/JWXI"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:56 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 14/18] docs/system/arm: Add placeholder docs for mcimx6ul-evk and mcimx7d-sabre Date: Tue, 29 Oct 2024 15:10:44 +0000 Message-Id: <20241029151048.1047247-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add placeholder docs for the mcimx6ul-evk and mcimx7d-sabre boards. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Cédric Le Goater Reviewed-by: Alistair Francis Message-id: 20241018141332.942844-7-peter.maydell@linaro.org --- MAINTAINERS | 2 ++ docs/system/arm/mcimx6ul-evk.rst | 5 +++++ docs/system/arm/mcimx7d-sabre.rst | 5 +++++ docs/system/target-arm.rst | 2 ++ 4 files changed, 14 insertions(+) create mode 100644 docs/system/arm/mcimx6ul-evk.rst create mode 100644 docs/system/arm/mcimx7d-sabre.rst diff --git a/MAINTAINERS b/MAINTAINERS index 66c7572c27b..1e88b5738cb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -791,6 +791,7 @@ F: hw/arm/fsl-imx6ul.c F: hw/misc/imx6ul_ccm.c F: include/hw/arm/fsl-imx6ul.h F: include/hw/misc/imx6ul_ccm.h +F: docs/system/arm/mcimx6ul-evk.rst MCIMX7D SABRE / i.MX7 M: Peter Maydell @@ -804,6 +805,7 @@ F: include/hw/arm/fsl-imx7.h F: include/hw/misc/imx7_*.h F: hw/pci-host/designware.c F: include/hw/pci-host/designware.h +F: docs/system/arm/mcimx7d-sabre.rst MPS2 / MPS3 M: Peter Maydell diff --git a/docs/system/arm/mcimx6ul-evk.rst b/docs/system/arm/mcimx6ul-evk.rst new file mode 100644 index 00000000000..8871138ab3e --- /dev/null +++ b/docs/system/arm/mcimx6ul-evk.rst @@ -0,0 +1,5 @@ +NXP MCIMX6UL-EVK (``mcimx6ul-evk``) +=================================== + +The ``mcimx6ul-evk`` machine models the NXP i.MX6UltraLite Evaluation Kit +MCIMX6UL-EVK development board. It has a single Cortex-A7 CPU. diff --git a/docs/system/arm/mcimx7d-sabre.rst b/docs/system/arm/mcimx7d-sabre.rst new file mode 100644 index 00000000000..c5d35af1d44 --- /dev/null +++ b/docs/system/arm/mcimx7d-sabre.rst @@ -0,0 +1,5 @@ +NXP MCIMX7D Sabre (``mcimx7d-sabre``) +===================================== + +The ``mcimx7d-sabre`` machine models the NXP SABRE Board MCIMX7SABRE, +based an an i.MX7Dual SoC. diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index ace36d1b17d..1f806cf4a46 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -97,6 +97,8 @@ undocumented; you can get a complete list by running arm/nrf arm/nuvoton arm/imx25-pdk + arm/mcimx6ul-evk + arm/mcimx7d-sabre arm/orangepi arm/raspi arm/collie From patchwork Tue Oct 29 15:10:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 839344 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:4593:b0:37d:45d0:187 with SMTP id gb19csp428447wrb; Tue, 29 Oct 2024 08:15:19 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV8NhBmInu/dBrOgzb2mtfwnPZBCrA7Iwzmqqkl+HlnW8ax6UmGNcaQBB3mfrVGMjfWMmX1Yg==@linaro.org X-Google-Smtp-Source: AGHT+IF5Z3MtY5fTZ+Ek8nXsPmMsnPM21VrTYcqxfTMtUQA1I5OPZ/ZolabzpKBHX2j5NFqpm21T X-Received: by 2002:a05:6102:374a:b0:4a5:6f41:2138 with SMTP id ada2fe7eead31-4a8cfd29483mr9794643137.20.1730214919650; Tue, 29 Oct 2024 08:15:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1730214919; cv=none; d=google.com; s=arc-20240605; b=VDv4POvRfDNqq7pOs/FPgcudBI4/8oCh2y3TZetHYMHkKaxnfeMOvZdsM+u0hNTcCU ZKxWzTNiPMxSsCd6vj/nm4ICiQy4ztpUq2FgsLB4JfS55Og4fwAQGPh8UcO6iSmhsjTT N/4SwusWqh8fPbMPpZsX1ybHbBjlKACPavuiwFM6LBBUO2eSC56uouj2L2JcxHgYWHeT Tf6iO5LVECzqoSBwZEPHWkNUeJTcSmGt1+8EscWx9j/pcjLb1t4Ho8QhsdFn+HuMOC4q qtDJTJm7fytzoCuxmIodnkWUXljdFRg4j1aWRk4L26hGzaiHjwChiL8eWnXto2R30/Vx 31Qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pxi72wEBVWIssBlyuwhwklhEOKwU4BGfiI/BxT6XvHQ=; fh=l0qHoFCu5YuwbqQCjpJY6y5s+IY/JpXwCtXCYZxVPyc=; b=LY0oXGzaMXGWDBBQui8bMoZFL8caH/Wk0FYuDPt8fAcSMhrU4gREDTHHA2emn2/617 Dpw3L7IFoiMD6cvrYR16oXn3ah4vDJ5dxRodG6EGc7UM9I0xTuIT/y1KiQtykDL//mgD 3HSRgwPaRPoz3hYt7p75YOJzKKjP1gUWdEG8tdMq0uZriTLwScUPM/ZbumRFAF25PB6K OX7mOY9fMRUoEu7tuB8hFvq6wUuI1ts98kRGrZIhUIDs+Vd8m2EYsxTQaIgvR2DcmXPo Apipep7aR6nOlHjJW9JtLyPOox5SukzLPAkJjPk/X6PobGw5NHOn2lIFrKKSd69kWqyr Iq1w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vYcNeXQ9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:57 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 15/18] docs/system/target-arm.rst: Remove "many boards are undocumented" note Date: Tue, 29 Oct 2024 15:10:45 +0000 Message-Id: <20241029151048.1047247-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We now have at least placeholder documentation for every Arm board, so we can remove the apologetic note that says that there are undocumented ones which you can only find out about via the ``--machine help`` option. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Cédric Le Goater Reviewed-by: Alistair Francis Message-id: 20241018141332.942844-8-peter.maydell@linaro.org --- docs/system/target-arm.rst | 4 ---- 1 file changed, 4 deletions(-) diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 1f806cf4a46..9aaa9c414c9 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -63,10 +63,6 @@ large amounts of RAM. It also supports 64-bit CPUs. Board-specific documentation ============================ -Unfortunately many of the Arm boards QEMU supports are currently -undocumented; you can get a complete list by running -``qemu-system-aarch64 --machine help``. - .. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:57 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 16/18] target/arm: Fix arithmetic underflow in SETM instruction Date: Tue, 29 Oct 2024 15:10:46 +0000 Message-Id: <20241029151048.1047247-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ido Plat Pass the stage size to step function callback, otherwise do_setm would hang when size is larger then page size because stage size would underflow. This fix changes do_setm to be more inline with do_setp. Cc: qemu-stable@nongnu.org Fixes: 0e92818887dee ("target/arm: Implement the SET* instructions") Signed-off-by: Ido Plat Reviewed-by: Richard Henderson Message-id: 20241025024909.799989-1-ido.plat1@ibm.com Signed-off-by: Peter Maydell --- target/arm/tcg/helper-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 56b431faf57..8f42a28d07b 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -1348,7 +1348,7 @@ static void do_setm(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc, /* Do the actual memset: we leave the last partial page to SETE */ stagesetsize = setsize & TARGET_PAGE_MASK; while (stagesetsize > 0) { - step = stepfn(env, toaddr, setsize, data, memidx, &mtedesc, ra); + step = stepfn(env, toaddr, stagesetsize, data, memidx, &mtedesc, ra); toaddr += step; setsize -= step; stagesetsize -= step; From patchwork Tue Oct 29 15:10:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 839345 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:4593:b0:37d:45d0:187 with SMTP id gb19csp428757wrb; Tue, 29 Oct 2024 08:15:48 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV1JjxipIL/HuQDhV1ZGtZUuJdDFoxK2pN0PfPfCuIOpOMFYzyRkBu5dtRCMMll3dOCDX4iaA==@linaro.org X-Google-Smtp-Source: AGHT+IGgGQ0BgH/RHALVaRQ7Anqol2+VrFVu6NDALtjuKThbERNxSZSViIUkJMbO8N56LEPUpBx4 X-Received: by 2002:a05:6214:2f13:b0:6cc:255:2037 with SMTP id 6a1803df08f44-6d1856e537amr158293266d6.24.1730214947826; Tue, 29 Oct 2024 08:15:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1730214947; cv=none; d=google.com; s=arc-20240605; b=K8HX0BnYJy+DRYBuSOUyhYXvRgS6v+3MpDj4PsbfLx6gpzpsMFvMEVscuWD1E3w394 f0mrtiPFlqQJ/y42/3RV7M5+sgHKlZVYT4VoShLLXspqnOl6L9M91H2GN8H5MnPK0hit RtCAyL87/kkTeMGwz3cln3OtHS4XInN1HPbA6IBCiapKdUDAsoiomHjqZtwZYIcMdPMp m5fS6z5ZCt+slbqXpwK1UyF0Z4ntlZfdzaHRj1NIbF9RKuYITDZ03nZUfxx0Bg0fTqT0 8eTwP8CLNBDO5yhyp1GQSbAr2FW2G5hemMYCsn+RtDz4cWCOPeWFNFDL+as0maS/Y01q MKqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hIn8TWQshR4xk0eH6ep1S0A+hm2DkFGROZexRTXqVg4=; fh=1RYHK4SJq2te3jb2IMxsGsg2jz7OSqQkMqfucYDbzCc=; b=gDvsYDwW7EHeX6L3PMhkVAQ3dWvZAO5gcu24dnH7os3F25FzJLO4OFO5leDPicd/s+ 9GpRIA+dt2tlr68OqzUu+oZO3rfmd/krFyWDJ07dc1oiApY0Z2KzV3HVOWaxte311jPS gBIMCh9LVkUhC9ExpbnD6TbawRjdWcSaUwNbuD6+IeUhh9s2NBjtFLVkBm2CjNu3YYJ1 5b2X8zB+GHhj4e7ryb3fUGPn6PWV/44FfM9CHpwIuhhBXLNDbobDZ+EhD1Rx5KnsPaIF m3d2KYbJSJAnwcl99NXX6VNZwzN+ogGu4pCn5PP9WUr33kRuttzIlIfWugUypgERgTEx x9Ow==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H4lExa5A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:58 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 17/18] docs/devel/reset: Fix minor grammatical error Date: Tue, 29 Oct 2024 15:10:47 +0000 Message-Id: <20241029151048.1047247-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Fix a minor grammatical error in the reset documentation: a couple of missing words and a singular/plural swap. Signed-off-by: Axel Heider Message-id: 173006362760.28451.11319467059840843945-1@git.sr.ht [PMM: squashed two patches into one, tweaked commit message] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/devel/reset.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst index 74c7c0171ad..adefd59ef97 100644 --- a/docs/devel/reset.rst +++ b/docs/devel/reset.rst @@ -286,8 +286,8 @@ every reset child of the given resettable object. All children must be resettable too. Additional parameters (a reset type and an opaque pointer) must be passed to the callback too. -In ``DeviceClass`` and ``BusClass`` the ``ResettableState`` is located -``DeviceState`` and ``BusState`` structure. ``child_foreach()`` is implemented +In ``DeviceClass`` and ``BusClass`` the ``ResettableState`` is located in the +``DeviceState`` and ``BusState`` structures. ``child_foreach()`` is implemented to follow the bus hierarchy; for a bus, it calls the function on every child device; for a device, it calls the function on every bus child. When we reset the main system bus, we reset the whole machine bus tree. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:58 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 18/18] target/arm: kvm: require KVM_CAP_DEVICE_CTRL Date: Tue, 29 Oct 2024 15:10:48 +0000 Message-Id: <20241029151048.1047247-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Paolo Bonzini The device control API was added in 2013, assume that it is present. Signed-off-by: Paolo Bonzini Message-id: 20241024113126.44343-1-pbonzini@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 16 +++++++--------- hw/intc/arm_gic_kvm.c | 9 +-------- target/arm/kvm.c | 17 +++++------------ 3 files changed, 13 insertions(+), 29 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 4d293618a78..2e6b49bf137 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -22,17 +22,15 @@ * @devid: the KVM device ID * @group: device control API group for setting addresses * @attr: device control API address type - * @dev_fd: device control device file descriptor (or -1 if not supported) + * @dev_fd: device control device file descriptor * @addr_ormask: value to be OR'ed with resolved address * - * Remember the memory region @mr, and when it is mapped by the - * machine model, tell the kernel that base address using the - * KVM_ARM_SET_DEVICE_ADDRESS ioctl or the newer device control API. @devid - * should be the ID of the device as defined by KVM_ARM_SET_DEVICE_ADDRESS or - * the arm-vgic device in the device control API. - * The machine model may map - * and unmap the device multiple times; the kernel will only be told the final - * address at the point where machine init is complete. + * Remember the memory region @mr, and when it is mapped by the machine + * model, tell the kernel that base address using the device control API. + * @devid should be the ID of the device as defined by the arm-vgic device + * in the device control API. The machine model may map and unmap the device + * multiple times; the kernel will only be told the final address at the + * point where machine init is complete. */ void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group, uint64_t attr, int dev_fd, uint64_t addr_ormask); diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 53defee7d59..e2a73337b1e 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -547,17 +547,10 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp) KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); } - } else if (kvm_check_extension(kvm_state, KVM_CAP_DEVICE_CTRL)) { + } else { error_setg_errno(errp, -ret, "error creating in-kernel VGIC"); error_append_hint(errp, "Perhaps the host CPU does not support GICv2?\n"); - } else if (ret != -ENODEV && ret != -ENOTSUP) { - /* - * Very ancient kernel without KVM_CAP_DEVICE_CTRL: assume that - * ENODEV or ENOTSUP mean "can't create GICv2 with KVM_CREATE_DEVICE", - * and that we will get a GICv2 via KVM_CREATE_IRQCHIP. - */ - error_setg_errno(errp, -ret, "error creating in-kernel VGIC"); return; } diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 000afa03631..7b6812c0de2 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -42,6 +42,7 @@ #include "migration/blocker.h" const KVMCapabilityInfo kvm_arch_required_capabilities[] = { + KVM_CAP_INFO(DEVICE_CTRL), KVM_CAP_LAST_INFO }; @@ -691,19 +692,11 @@ static void kvm_arm_set_device_addr(KVMDevice *kd) { struct kvm_device_attr *attr = &kd->kdattr; int ret; + uint64_t addr = kd->kda.addr; - /* If the device control API is available and we have a device fd on the - * KVMDevice struct, let's use the newer API - */ - if (kd->dev_fd >= 0) { - uint64_t addr = kd->kda.addr; - - addr |= kd->kda_addr_ormask; - attr->addr = (uintptr_t)&addr; - ret = kvm_device_ioctl(kd->dev_fd, KVM_SET_DEVICE_ATTR, attr); - } else { - ret = kvm_vm_ioctl(kvm_state, KVM_ARM_SET_DEVICE_ADDR, &kd->kda); - } + addr |= kd->kda_addr_ormask; + attr->addr = (uintptr_t)&addr; + ret = kvm_device_ioctl(kd->dev_fd, KVM_SET_DEVICE_ATTR, attr); if (ret < 0) { fprintf(stderr, "Failed to set device address: %s\n",