From patchwork Mon Dec 9 09:21:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 180993 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4097901ile; Mon, 9 Dec 2019 01:21:08 -0800 (PST) X-Google-Smtp-Source: APXvYqxXFo0ZruUeBlOcJjVO6bnp+jz+VBG3KoxXGnK7XEwA5PO78hZus/+BBTRflxdbOt0027uA X-Received: by 2002:aca:6186:: with SMTP id v128mr24181908oib.17.1575883268393; Mon, 09 Dec 2019 01:21:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575883268; cv=none; d=google.com; s=arc-20160816; b=EC034Ovhe7ppanx5x4Tm0XhEKZTzLD4WiP9jgiXAc1uyO8jYzWF0CZSgljrxjtXIkG zaVjSU+82BwkxQ8EG6qZ8nwmZC1BG9SmMWIEMzVUJl3f2/5k4PGmFx0jXJc/5iKR15vZ oapk5l+kKF+b34CX6EcBIgx+HCDzAHNlJvzRnC4Zl5clrYMzVc3YeudCMBovYBzDzA3v 18+FyTecWXLuIWytQA+qoGl9WdwsusqZpL76qVjk0L3FGf29EB61PJSs32kKap9o2Zxu a24adf0so9R+bf/CMkX5zWfW3SKHjOHxGV8ueKzfPdr+fcKzJs9OvhYk1c5lNB8uBY/w C/9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=OzxHiwIOPUOFBA7qrD6Vb+QLFWB9Mt5CRNKBBT7ftNQ=; b=QFCgBIgkv4zbJMVxNUPdw9cylf5iVfOVMaRNwdT1sRhbw2jRoJGla0oEpAG57GsVFJ bVwzPrbnw3A3XkVjpRnNeAQ9YoHOw3mT9yQga+O6BDJ8IrQ/0zt8dZrupr4Fi+QSZNUI amKChng/n/NEHkiy/Oon1xGYb26Q5iK153O8n8phdEVLzJPFMT62uLKI6ducSlthBKf6 2uTBC/ATNsMqYgft737Llu/wE050lKr7lGtwgZGgFy89imHKP11PlFlFMHRXSPUgBsV/ KAYjULZOngXAXORZ7991on+43YCcFUaPqeqz4nIeQFt53tlkDlk92dBnYeG+8OSGGtFL m36g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=zMp0dskh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f4si11432613oto.169.2019.12.09.01.21.08; Mon, 09 Dec 2019 01:21:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=zMp0dskh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727605AbfLIJVH (ORCPT + 27 others); Mon, 9 Dec 2019 04:21:07 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:59874 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727579AbfLIJVE (ORCPT ); Mon, 9 Dec 2019 04:21:04 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99KuVN045988; Mon, 9 Dec 2019 03:20:56 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575883256; bh=OzxHiwIOPUOFBA7qrD6Vb+QLFWB9Mt5CRNKBBT7ftNQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=zMp0dskhFl7i6gKryWLdosqPB/ECwjUPm/lXAmyQ7JJb5FWW8Fe5fubmhJlEE3wwd gt0uezj7i0l19EVK6rx56mmikUauYQcdDWiNrgzoWd5yLECaWE2Ugj6S7WeyWp+K+F GRTsJs0Fc12wo6xh1WLi4RYFdk+cQhjGB1xTmf+Y= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB99KutT063290 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Dec 2019 03:20:56 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:20:55 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:20:55 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99Kcd2087697; Mon, 9 Dec 2019 03:20:52 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Arnd Bergmann , Andrew Murray CC: , , , , Kishon Vijay Abraham I Subject: [PATCH 04/13] PCI: cadence: Add support to start link and verify link status Date: Mon, 9 Dec 2019 14:51:38 +0530 Message-ID: <20191209092147.22901-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191209092147.22901-1-kishon@ti.com> References: <20191209092147.22901-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add cdns_pcie_ops to start link and verify link status. The registers to start link and to check link status is in Platform specific PCIe wrapper. Add support for platform specific drivers to add callback functions for the PCIe Cadence core to start link and verify link status. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/cadence/pcie-cadence-ep.c | 8 ++++++ .../controller/cadence/pcie-cadence-host.c | 28 +++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 23 +++++++++++++++ 3 files changed, 59 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index 560f22b4d165..088394b6be04 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -355,8 +355,10 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; + struct device *dev = pcie->dev; struct pci_epf *epf; u32 cfg; + int ret; /* * BIT(0) is hardwired to 1, hence function 0 is always enabled @@ -367,6 +369,12 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) cfg |= BIT(epf->func_no); cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg); + ret = cdns_pcie_start_link(pcie, true); + if (ret) { + dev_err(dev, "Failed to start link\n"); + return ret; + } + return 0; } diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index ccf55e143e1d..0929554f5a81 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -3,6 +3,7 @@ // Cadence PCIe host controller driver. // Author: Cyrille Pitchen +#include #include #include #include @@ -201,6 +202,23 @@ static int cdns_pcie_host_init(struct device *dev, return err; } +static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) +{ + struct device *dev = pcie->dev; + int retries; + + /* Check if the link is up or not */ + for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (cdns_pcie_is_link_up(pcie)) { + dev_info(dev, "Link up\n"); + return 0; + } + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + } + + return -ETIMEDOUT; +} + int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) { struct device *dev = rc->pcie.dev; @@ -254,6 +272,16 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) pcie->mem_res = res; + ret = cdns_pcie_start_link(pcie, true); + if (ret) { + dev_err(dev, "Failed to start link\n"); + return ret; + } + + ret = cdns_pcie_host_wait_for_link(pcie); + if (ret) + dev_dbg(dev, "PCIe link never came up\n"); + ret = cdns_pcie_host_init(dev, &resources, rc); if (ret) goto err_init; diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index d0d91c69fa1d..f0395eaf9df5 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -10,6 +10,11 @@ #include #include +/* Parameters for the waiting for link up routine */ +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_USLEEP_MIN 90000 +#define LINK_WAIT_USLEEP_MAX 100000 + /* * Local Management Registers */ @@ -226,6 +231,8 @@ enum cdns_pcie_msg_routing { struct cdns_pcie_ops { u32 (*read)(void __iomem *addr, int size); void (*write)(void __iomem *addr, int size, u32 value); + int (*start_link)(struct cdns_pcie *pcie, bool start); + bool (*is_link_up)(struct cdns_pcie *pcie); }; /** @@ -447,6 +454,22 @@ static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) return readl(addr); } +static inline int cdns_pcie_start_link(struct cdns_pcie *pcie, bool start) +{ + if (pcie->ops->start_link) + return pcie->ops->start_link(pcie, start); + + return 0; +} + +static inline bool cdns_pcie_is_link_up(struct cdns_pcie *pcie) +{ + if (pcie->ops->is_link_up) + return pcie->ops->is_link_up(pcie); + + return true; +} + #ifdef CONFIG_PCIE_CADENCE_HOST int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); #else From patchwork Mon Dec 9 09:21:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 180994 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4097932ile; Mon, 9 Dec 2019 01:21:10 -0800 (PST) X-Google-Smtp-Source: APXvYqzF442kB5EDaCdPmiiY4o0sVVKLyTWC3/F6yZYhIPLR+NEGNWzRSaPc7bPK3t60yqxUIWGy X-Received: by 2002:a05:6830:16c6:: with SMTP id l6mr21077483otr.186.1575883270842; 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[209.132.180.67]) by mx.google.com with ESMTP id f4si11432613oto.169.2019.12.09.01.21.10; Mon, 09 Dec 2019 01:21:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=GCpEm5+D; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727617AbfLIJVJ (ORCPT + 27 others); Mon, 9 Dec 2019 04:21:09 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:59884 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727598AbfLIJVG (ORCPT ); Mon, 9 Dec 2019 04:21:06 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99Kxfc046007; Mon, 9 Dec 2019 03:20:59 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575883259; bh=6XFbTAUZNjwfB+XXzjz0shhOgKng/V2zDEQmkwRYYTY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=GCpEm5+DP1Fjc4PrP2sa17KpQEPowhR1kSN+uDmICrxU64tQje2IY/y7SGqmSlOm9 36yAPuJNyrfk4o9kxfin5pN+Nz2xJt9scWhzQgrmd0E7oE1L856+uhWxMQ71u6x7fo 1jKcP8V1HbY+B6nP6+CX4zVQS5gMVT6REi9fBlmY= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB99KxfV042447 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Dec 2019 03:20:59 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:20:58 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:20:58 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99Kcd3087697; Mon, 9 Dec 2019 03:20:56 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Arnd Bergmann , Andrew Murray CC: , , , , Kishon Vijay Abraham I Subject: [PATCH 05/13] PCI: cadence: Add read and write accessors to perform only 32-bit accesses Date: Mon, 9 Dec 2019 14:51:39 +0530 Message-ID: <20191209092147.22901-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191209092147.22901-1-kishon@ti.com> References: <20191209092147.22901-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Certain platforms like TI's J721E allow only 32-bit register accesses. Add read and write accessors to perform only 32-bit accesses in order to support platfroms like TI's J721E. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/pcie-cadence.c | 40 +++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 2 + 2 files changed, 42 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c index cd795f6fc1e2..de5b3b06f2d0 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -7,6 +7,46 @@ #include "pcie-cadence.h" +u32 cdns_pcie_read32(void __iomem *addr, int size) +{ + void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); + unsigned int offset = (unsigned long)addr & 0x3; + u32 val = readl(aligned_addr); + + if (!IS_ALIGNED((uintptr_t)addr, size)) { + pr_err("Invalid Address in function:%s\n", __func__); + return 0; + } + + if (size > 2) + return val; + + return (val >> (8 * offset)) & ((1 << (size * 8)) - 1); +} + +void cdns_pcie_write32(void __iomem *addr, int size, u32 value) +{ + void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); + unsigned int offset = (unsigned long)addr & 0x3; + u32 mask; + u32 val; + + if (!IS_ALIGNED((uintptr_t)addr, size)) { + pr_err("Invalid Address in function:%s\n", __func__); + return; + } + + if (size > 2) { + writel(value, addr); + return; + } + + mask = ~(((1 << (size * 8)) - 1) << (offset * 8)); + val = readl(aligned_addr) & mask; + val |= value << (offset * 8); + writel(val, aligned_addr); +} + void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn, u32 r, bool is_io, u64 cpu_addr, u64 pci_addr, size_t size) diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index f0395eaf9df5..5171d0da37da 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -498,6 +498,8 @@ void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r); void cdns_pcie_disable_phy(struct cdns_pcie *pcie); int cdns_pcie_enable_phy(struct cdns_pcie *pcie); int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); +u32 cdns_pcie_read32(void __iomem *addr, int size); +void cdns_pcie_write32(void __iomem *addr, int size, u32 value); extern const struct dev_pm_ops cdns_pcie_pm_ops; #endif /* _PCIE_CADENCE_H */ From patchwork Mon Dec 9 09:21:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 180996 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4098045ile; Mon, 9 Dec 2019 01:21:19 -0800 (PST) X-Google-Smtp-Source: APXvYqw3a/9+hHUxcRsmpboTDIzmNR3GJOSc8QTiy88LGmRxyWlSFf/urMnwzeAtiSu3qNtffMtT X-Received: by 2002:a9d:768b:: with SMTP id j11mr20840918otl.116.1575883279642; Mon, 09 Dec 2019 01:21:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575883279; cv=none; d=google.com; s=arc-20160816; b=LjdMfk2REKc2bN5/gdwNnnWMJmm/lsWypqxHBtqOCfeXQXZRG2n7ekNiRkW1tBUSMN 6yZJiHsp/Kr8Zie9nKSicXfysT9Ssa+Tqy6o8vtzNGTpX4xYdcA9OuCqTMxE9W+6EVnP be/79SyEtEhLz27/E2+LklscK1swhqSAG6tbWE1QDaY8BnZwUAYkS8ergJ0ST15X7XcA wTZwncEfadBg8CxMas0QezvZ4HTCq7W67aRijOGPwZdXeLpn29ZyZLc4oRbZZ2eolyYN MjCqBF52FWbyzT9FEnB66xJTnIdgFLtGr9km63eopyXxfegABirjTYdFx96NBY+VWOZ+ q+Jw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=VZbwOGovQ4NFoflgIXWD16/wHBPSJqutZdf3/MJ6Owc=; b=Xh5IsJuFnWYANOkMbbPqUym43vgYTzhJsZ2SkSSbvTFtBFyDiKnF7oNw5Fqh4MndFs bthAmr6nHxo4wTaEYMniUWWsCDV2rV6S+39vsTNwcTvvdNpLV/JWkHdtCajINePLJ6Cf XqGyhj87J9J1ciwwxzZd27w8ZMcE3uLBWKB/f0reNfd0DLl+rcyWL/vVoygfC8mihq7d RPYj61Kvqnk+uC29y0ev3pLOBN32O+Jw/UIxsh38izbK3gnbktMI0AjJDj47CQxBRFtC HW9TBon+2yegr25UDZwF0A4G8EOD1RJyyxCTPYIQ544z2Cb4uwab7eSrSvT8aIYZw4jy vCGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="tBlKps1/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x7si11420552oia.165.2019.12.09.01.21.19; Mon, 09 Dec 2019 01:21:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="tBlKps1/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727649AbfLIJVR (ORCPT + 27 others); Mon, 9 Dec 2019 04:21:17 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:49928 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727619AbfLIJVQ (ORCPT ); Mon, 9 Dec 2019 04:21:16 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99L6FI080929; Mon, 9 Dec 2019 03:21:06 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575883266; bh=VZbwOGovQ4NFoflgIXWD16/wHBPSJqutZdf3/MJ6Owc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tBlKps1/rXdvKaWuN4kH+4hRxEb3a/RBfvX1CpXla6e6TjLL99B4KeXV3CMRCVOFN KZh2RFMZWkvcIQWVEZWViqkbR7agu87lOHIIw6LHzDWOiqobttHcdh8HOiLhCf5mlr dlwIs+DEsE3sWhDy3ZCZ88ljSGbzJNqAoh+fLUgs= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB99L6H7005774 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Dec 2019 03:21:06 -0600 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:21:05 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:21:05 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99Kcd5087697; Mon, 9 Dec 2019 03:21:02 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Arnd Bergmann , Andrew Murray CC: , , , , Kishon Vijay Abraham I Subject: [PATCH 07/13] PCI: cadence: Add new *ops* for CPU addr fixup Date: Mon, 9 Dec 2019 14:51:41 +0530 Message-ID: <20191209092147.22901-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191209092147.22901-1-kishon@ti.com> References: <20191209092147.22901-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Cadence driver uses "mem" memory resource to obtain the offset of configuration space address region, memory space address region and message space address region. The obtained offset is used to program the Address Translation Unit (ATU). However certain platforms like TI's J721E SoC require the absolute address to be programmed in the ATU and not just the offset. The same problem was solved in designware driver using a platform specific ops for CPU addr fixup in commit a660083eb06c5bb0 ("PCI: dwc: designware: Add new *ops* for CPU addr fixup"). Follow a similar mechanism in Cadence too instead of directly using "mem" memory resource in Cadence PCIe core. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/cadence/pcie-cadence-host.c | 15 ++++----------- drivers/pci/controller/cadence/pcie-cadence.c | 8 ++++++-- drivers/pci/controller/cadence/pcie-cadence.h | 1 + 3 files changed, 11 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 2efc33b1cade..cf817be237af 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -105,15 +105,14 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie = &rc->pcie; - struct resource *mem_res = pcie->mem_res; struct resource *bus_range = rc->bus_range; struct resource *cfg_res = rc->cfg_res; struct device *dev = pcie->dev; struct device_node *np = dev->of_node; struct of_pci_range_parser parser; + u64 cpu_addr = cfg_res->start; struct of_pci_range range; u32 addr0, addr1, desc1; - u64 cpu_addr; int r, err; /* @@ -126,7 +125,9 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1); cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1); - cpu_addr = cfg_res->start - mem_res->start; + if (pcie->ops->cpu_addr_fixup) + cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); + addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) | (lower_32_bits(cpu_addr) & GENMASK(31, 8)); addr1 = upper_32_bits(cpu_addr); @@ -264,14 +265,6 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) } rc->cfg_res = res; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem"); - if (!res) { - dev_err(dev, "missing \"mem\"\n"); - return -EINVAL; - } - - pcie->mem_res = res; - ret = cdns_pcie_start_link(pcie, true); if (ret) { dev_err(dev, "Failed to start link\n"); diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c index de5b3b06f2d0..bd93d0f92f55 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -113,7 +113,9 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn, cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1); /* Set the CPU address */ - cpu_addr -= pcie->mem_res->start; + if (pcie->ops->cpu_addr_fixup) + cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); + addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | (lower_32_bits(cpu_addr) & GENMASK(31, 8)); addr1 = upper_32_bits(cpu_addr); @@ -140,7 +142,9 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn, } /* Set the CPU address */ - cpu_addr -= pcie->mem_res->start; + if (pcie->ops->cpu_addr_fixup) + cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); + addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) | (lower_32_bits(cpu_addr) & GENMASK(31, 8)); addr1 = upper_32_bits(cpu_addr); diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index c879dd3d2893..ffa8b9f78ff8 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -233,6 +233,7 @@ struct cdns_pcie_ops { void (*write)(void __iomem *addr, int size, u32 value); int (*start_link)(struct cdns_pcie *pcie, bool start); bool (*is_link_up)(struct cdns_pcie *pcie); + u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); }; /** From patchwork Mon Dec 9 09:21:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 180998 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4098100ile; Mon, 9 Dec 2019 01:21:23 -0800 (PST) X-Google-Smtp-Source: APXvYqy810xZaUfTl48DF++0MHBYjARkDqJW2ALemKjyh0Sq7GBdkArRS2KOPXJOH95S6KHkk6WW X-Received: by 2002:aca:5708:: with SMTP id l8mr20890937oib.162.1575883283086; Mon, 09 Dec 2019 01:21:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575883283; cv=none; d=google.com; s=arc-20160816; b=i+WQfbPnvV2IW87vHa8VqU0zGV+sAcnnmpRQH2eFVs6iE4Yvceiy+kRtLKIF4LJWzK VjYN1eZGwNdn3WBNNpUujam8A+dH1ubGD9d6dYP38RZasNcbEbB7+ubWAcB+bn8z7IDV NdEQyM9ttX8hRdJOkHvAEjxPC0QfcjgGMoyVBOf4EnSYrko0AEhzmw4NRAjRSyUnMiOV 2HJApGx1ur1YdmMcWQ38YSV3WJltPoZ6sb6OOoxcQTRXe9IwTwI4hzRJh2DD+h8AEF0M DXIZN9IzH3tPk7dFjJd8jFr5g6b6aqAPlC27Fsk53PsZZ4wvzGIYBENW9WQre774BNQb Orjg== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id x7si11420552oia.165.2019.12.09.01.21.22; Mon, 09 Dec 2019 01:21:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=kPXOQTQe; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727669AbfLIJVW (ORCPT + 27 others); Mon, 9 Dec 2019 04:21:22 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:49940 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727645AbfLIJVS (ORCPT ); Mon, 9 Dec 2019 04:21:18 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99L9pp080936; Mon, 9 Dec 2019 03:21:09 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575883269; bh=/PpQ+RidTBHG04c4iEDkQBvUqEr7xWf2hoOmAhrMbcg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kPXOQTQevNFekDH7vNn15mo/bcHWWNTdezF7k/Ir2ORXjFHIyA3f2I3fbxKVpFTl5 0NxbyBBGgS7P/szYecTWRQsiG09e+JuPucP6RWxyFVAYPGEGxMsJcKAKrCEOaAoESd VF2h2AsSmfNJ48zMUwO11INHcOJyOjDfAPcY/Wi8= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB99L9s6005863 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Dec 2019 03:21:09 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:21:08 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:21:08 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99Kcd6087697; Mon, 9 Dec 2019 03:21:06 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Arnd Bergmann , Andrew Murray CC: , , , , Kishon Vijay Abraham I Subject: [PATCH 08/13] PCI: cadence: Use local management register to configure Vendor ID Date: Mon, 9 Dec 2019 14:51:42 +0530 Message-ID: <20191209092147.22901-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191209092147.22901-1-kishon@ti.com> References: <20191209092147.22901-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PCI_VENDOR_ID in root port configuration space is read-only register and writing to it will have no effect. Use local management register to configure Vendor ID and Subsystem Vendor ID. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/pcie-cadence-host.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index cf817be237af..afb2c96a6538 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -71,6 +71,7 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie = &rc->pcie; u32 value, ctrl; + u32 id; /* * Set the root complex BAR configuration register: @@ -90,8 +91,12 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value); /* Set root port configuration space */ - if (rc->vendor_id != 0xffff) - cdns_pcie_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id); + if (rc->vendor_id != 0xffff) { + id = CDNS_PCIE_LM_ID_VENDOR(rc->vendor_id) | + CDNS_PCIE_LM_ID_SUBSYS(rc->vendor_id); + cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); + } + if (rc->device_id != 0xffff) cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id); From patchwork Mon Dec 9 09:21:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 180999 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4098177ile; Mon, 9 Dec 2019 01:21:29 -0800 (PST) X-Google-Smtp-Source: APXvYqwPQ4QCCTII3BRWy87OSaHhjJHnQZ/4YULwpVNEvKn3xq+ZhcmV6pay4viA1wHM4s69hVuK X-Received: by 2002:aca:4e87:: with SMTP id c129mr22479714oib.153.1575883288974; Mon, 09 Dec 2019 01:21:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575883288; cv=none; d=google.com; s=arc-20160816; b=owJvKhQPWWx2a8t/KoEKQfB18sn+pMMB2X2BUDYUz5MEoOa87aPSSDVWKIhsFAJTM5 /xQ/pASgaKDZfKRyEcDqfo3ir1nlQUIVpnmKMfprgoBXVL8ZySx9McAnrTZEdnX2DKEc Ska0hgKBn4Mlq2EAxDk+E7WiDHE/4saz5JFADwHWMqcVV7E9yEt5Jxqep9xNERHoL4r9 /QHRJ6KZJINnDwQ+JuA9wOTv37J8CF1yrrqlhUj7B6gtHXbvAaJF1OaAoJFtKt2snyIV xxlumPJtsKgqJguuclqZdeoZOnDrX65Epkl+sRNBfsvZzbrlt7obougO0U6RSMBkj8E3 G4Jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=TuZ57XKo41i7btprk/EutM6dRU+uO6XJ5X6yFXEDUbE=; b=y0WjaCFL7QFCMYbYElEk8+CC9xLMfFsBh8ELCCoF4qNzJxOMaHT/4SDd99DjmLvOw9 7cgo+mFxCDSB3RPRUqIXJbSr8/FW8uvihjUvFeiEVng14vwLPed4ffglhgcz5WSyw4wq lzizuCimBcpmbECS2k7FgHg8RPu+64b21QFqfCIyFOop4gFLQixeYhKlFKZez6dHDe4a b9/dyvrqEPUp2XvaEMm2KU0AksCiId4s4cmgkqy3c75YEU8rY6hgyIemD7yA6VsNYKsd sSR5cTCdfNPifwx/SwIW9Py7bxU1n8sSge+AMU9LEbZJDQX9Jyhqn10cZkKNOHWdO2/F K+Wg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=AkG+v2Ub; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s6si10884628otp.126.2019.12.09.01.21.28; Mon, 09 Dec 2019 01:21:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=AkG+v2Ub; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727700AbfLIJV1 (ORCPT + 27 others); Mon, 9 Dec 2019 04:21:27 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:54462 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727680AbfLIJVY (ORCPT ); Mon, 9 Dec 2019 04:21:24 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99LHTi100989; Mon, 9 Dec 2019 03:21:17 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575883277; bh=TuZ57XKo41i7btprk/EutM6dRU+uO6XJ5X6yFXEDUbE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AkG+v2UbtWswA0hBjZjeJyZbpKQrEUMIYDSv9q75fzjjFsu1YgDmHDxmt7l42lEn4 9sigJahY3daiYmLUTwszZRlMP+QQd0gmFV4mJ3tOC77dCY8X18nUOlk0YUaTTzshiU tGNnwhCo/kamfCld4nFbqNMZOUozub3Ws2fDioAI= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99LHWH127889; Mon, 9 Dec 2019 03:21:17 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:21:15 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:21:15 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99Kcd8087697; Mon, 9 Dec 2019 03:21:12 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Arnd Bergmann , Andrew Murray CC: , , , , Kishon Vijay Abraham I Subject: [PATCH 10/13] dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC Date: Mon, 9 Dec 2019 14:51:44 +0530 Message-ID: <20191209092147.22901-11-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191209092147.22901-1-kishon@ti.com> References: <20191209092147.22901-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add PCIe EP mode dt-bindings for TI's J721E SoC. Cc: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- .../bindings/pci/ti,j721e-pci-ep.yaml | 113 ++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml new file mode 100644 index 000000000000..4e2af4733998 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI J721E PCI EP (PCIe Wrapper) + +maintainers: + - Kishon Vijay Abraham I + +properties: + compatible: + enum: + - ti,j721e-pcie-ep + + reg: + maxItems: 4 + + reg-names: + items: + - const: intd_cfg + - const: user_cfg + - const: reg + - const: mem + + ti,syscon-pcie-ctrl: + description: Phandle to the SYSCON entry required for configuring PCIe mode + and link speed. + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle + + max-link-speed: + minimum: 1 + maximum: 3 + + num-lanes: + minimum: 1 + maximum: 2 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + description: clock-specifier to represent input to the PCIe + + clock-names: + items: + - const: fck + + cdns,max-outbound-regions: + description: As defined in + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt + allOf: + - $ref: /schemas/types.yaml#/definitions/int32 + - enum: [16] + + max-functions: + minimum: 1 + maximum: 6 + + dma-coherent: + description: Indicates that the PCIe IP block can ensure the coherency + + phys: + description: As defined in + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt + + phy-names: + description: As defined in + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt + +required: + - compatible + - reg + - reg-names + - ti,syscon-pcie-ctrl + - max-link-speed + - num-lanes + - power-domains + - clocks + - clock-names + - cdns,max-outbound-regions + - dma-coherent + - max-functions + - phys + - phy-names + +examples: + - | + #include + + pcie0_ep: pcie-ep@d000000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + dma-coherent; + phys = <&serdes0_pcie_link>; + phy-names = "pcie_phy"; + }; From patchwork Mon Dec 9 09:21:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181000 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4098233ile; Mon, 9 Dec 2019 01:21:31 -0800 (PST) X-Google-Smtp-Source: APXvYqxcsYuu0QZbzRXrms1C+iEIBGZ1wP3pjochhWN1w0vXn65WYDLZdVlnAwXeF86XAi4oCiri X-Received: by 2002:a05:6808:35a:: with SMTP id j26mr17770347oie.163.1575883291416; Mon, 09 Dec 2019 01:21:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575883291; cv=none; d=google.com; s=arc-20160816; b=gHJrWX5aTZlpkzmizyTar5/DmB9XtS5n9106WCdc2UxAxx+kYoF3ODLALZjHMQsK6c yZ4RzYczJcou2S/BXH9H6nUzuHlotFt1FrrPE8K7LJjiOVkGrcqmQFEwRgb1B02J//jg hRCDFa7pcSumgrgt1mVk/S91HsASSBj3yoWswlEoG1YqS36bTzKDX6CMUmfvQn/suznj tjB5JULKzfzJVEn5l7ymLAqJCyjRRs2SyixefDCQ7qM5rB0UvDeDxUrvQXsJvMS/kVK6 Su5wxvD6aAW24nY/lJydvwzZ6xJq83d37HjY1ZW852fErnINjEEA72Ys7dvY89PEjzBG f6UA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=EZPfoTf4Aa5aSnifxHST/Im23c+PKIqzTC9d+P2gKXI=; b=NvzEKms/yqCOoZiBTjpl6oSj+NOwUF8Ma7eoQRjSDhNzUwoK1OFooMd8+NUTTdfz4M qaTm7SoXpfdJxpjVA9Ohm+Lry4o0Q0oufZ7IGNcfpQLW73CJ4KDQH8+mAvaXMlSgMM0K ZRcZTGB46/nJu8C3C4hnHgHBSEn+pqKmLGYEHOMo10L4M9QhS6P7VcKUCYuEgmxOYTkz 9YiWzxueBF9CsUZUhN/L60t2nOs1+T88bIMpOt+Kk6/I3UygdZNE3tbbu3BmPA+g77sN pHMumkrJC/6Y8RNN+4Dz2DUCXl2kJW4VDJJpSnvymIXMaaCe+jFVc7FLYaslhlcWCJo5 +GKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=lK75gbPP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s6si10884628otp.126.2019.12.09.01.21.31; Mon, 09 Dec 2019 01:21:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=lK75gbPP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727710AbfLIJVa (ORCPT + 27 others); Mon, 9 Dec 2019 04:21:30 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:54468 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727690AbfLIJV0 (ORCPT ); Mon, 9 Dec 2019 04:21:26 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99LJsO101007; Mon, 9 Dec 2019 03:21:19 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575883279; bh=EZPfoTf4Aa5aSnifxHST/Im23c+PKIqzTC9d+P2gKXI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lK75gbPPp9lPZBgQSJQLQawul7SBfbRkmNrXp3F8o3T5uoyv214rGL2Yd8VlVDjg2 iS8R0Cocyj3TziOWxTo9pTJRcj8tpcHVDNhH4pzOEPqzIEFggoIqT/Q+otwbgZ8qsG nmVjMSFq1I/T0Bw7HApK3K8J97IsYeHAIl5pkWMU= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB99LJoI006077 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Dec 2019 03:21:19 -0600 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:21:18 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:21:18 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99Kcd9087697; Mon, 9 Dec 2019 03:21:15 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Arnd Bergmann , Andrew Murray CC: , , , , Kishon Vijay Abraham I Subject: [PATCH 11/13] PCI: j721e: Add TI J721E PCIe driver Date: Mon, 9 Dec 2019 14:51:45 +0530 Message-ID: <20191209092147.22901-12-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191209092147.22901-1-kishon@ti.com> References: <20191209092147.22901-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for PCIe controller in J721E SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller will work in both host mode and device mode. Some of the features of the controller are: *) Supports both RC mode and EP mode *) Supports MSI and MSI-X support *) Supports upto GEN3 speed mode *) Supports SR-IOV capability *) Ability to route all transactions via SMMU (support will be added in a later patch). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/Kconfig | 23 ++ drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pci-j721e.c | 430 +++++++++++++++++++++ 3 files changed, 454 insertions(+) create mode 100644 drivers/pci/controller/cadence/pci-j721e.c -- 2.17.1 diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig index b76b3cf55ce5..5d30564190e1 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -42,4 +42,27 @@ config PCIE_CADENCE_PLAT_EP endpoint mode. This PCIe controller may be embedded into many different vendors SoCs. +config PCI_J721E + bool + +config PCI_J721E_HOST + bool "TI J721E PCIe platform host controller" + depends on OF + select PCIE_CADENCE_HOST + select PCI_J721E + help + Say Y here if you want to support the TI J721E PCIe platform + controller in host mode. TI J721E PCIe controller uses Cadence PCIe + core. + +config PCI_J721E_EP + bool "TI J721E PCIe platform endpoint controller" + depends on OF + depends on PCI_ENDPOINT + select PCIE_CADENCE_EP + select PCI_J721E + help + Say Y here if you want to support the TI J721E PCIe platform + controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe + core. endmenu diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile index 232a3f20876a..9bac5fb2f13d 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o +obj-$(CONFIG_PCI_J721E) += pci-j721e.o diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c new file mode 100644 index 000000000000..9ffb7e88c739 --- /dev/null +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -0,0 +1,430 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * pci-j721e - PCIe controller driver for TI's J721E SoCs + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * Author: Kishon Vijay Abraham I + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../pci.h" +#include "pcie-cadence.h" + +#define J721E_PCIE_USER_CMD_STATUS 0x4 +#define LINK_TRAINING_ENABLE BIT(0) + +#define J721E_PCIE_USER_LINKSTATUS 0x14 +#define LINK_STATUS GENMASK(1, 0) + +enum link_status { + NO_RECIEVERS_DETECTED, + LINK_TRAINING_IN_PROGRESS, + LINK_UP_DL_IN_PROGRESS, + LINK_UP_DL_COMPLETED, +}; + +#define J721E_MODE_RC BIT(7) +#define LANE_COUNT_MASK BIT(8) +#define LANE_COUNT(n) ((n) << 8) + +#define GENERATION_SEL_MASK GENMASK(1, 0) + +#define MAX_LANES 2 + +struct j721e_pcie { + struct device *dev; + struct device_node *node; + u32 mode; + u32 num_lanes; + struct cdns_pcie *cdns_pcie; + void __iomem *user_cfg_base; +}; + +enum j721e_pcie_mode { + PCI_MODE_RC, + PCI_MODE_EP, +}; + +struct j721e_pcie_data { + enum j721e_pcie_mode mode; +}; + +static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) +{ + return readl(pcie->user_cfg_base + offset); +} + +static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, + u32 value) +{ + writel(value, pcie->user_cfg_base + offset); +} + +static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie, bool start) +{ + struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); + u32 reg; + + reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); + if (start) + reg |= LINK_TRAINING_ENABLE; + else + reg &= ~LINK_TRAINING_ENABLE; + j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); + + return 0; +} + +static bool j721e_pcie_is_link_up(struct cdns_pcie *cdns_pcie) +{ + struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); + u32 reg; + + reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS); + reg &= LINK_STATUS; + if (reg == LINK_UP_DL_COMPLETED) + return true; + + return false; +} + +static const struct cdns_pcie_ops j721e_ops_ops = { + .read = cdns_pcie_read32, + .write = cdns_pcie_write32, + .start_link = j721e_pcie_start_link, + .is_link_up = j721e_pcie_is_link_up, +}; + +static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon) +{ + struct device *dev = pcie->dev; + u32 mask = J721E_MODE_RC; + u32 mode = pcie->mode; + u32 val = 0; + int ret = 0; + + if (mode == PCI_MODE_RC) + val = J721E_MODE_RC; + + ret = regmap_update_bits(syscon, 0, mask, val); + if (ret) + dev_err(dev, "failed to set pcie mode\n"); + + return ret; +} + +static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, + struct regmap *syscon) +{ + struct device *dev = pcie->dev; + struct device_node *np = dev->of_node; + int link_speed; + u32 val = 0; + int ret; + + link_speed = of_pci_get_max_link_speed(np); + if (link_speed < 2) + link_speed = 2; + + val = link_speed - 1; + ret = regmap_update_bits(syscon, 0, GENERATION_SEL_MASK, val); + if (ret) + dev_err(dev, "failed to set link speed\n"); + + return ret; +} + +static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, + struct regmap *syscon) +{ + struct device *dev = pcie->dev; + u32 lanes = pcie->num_lanes; + u32 val = 0; + int ret; + + val = LANE_COUNT(lanes - 1); + ret = regmap_update_bits(syscon, 0, LANE_COUNT_MASK, val); + if (ret) + dev_err(dev, "failed to set link count\n"); + + return ret; +} + +static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) +{ + struct device *dev = pcie->dev; + struct device_node *node = dev->of_node; + struct regmap *syscon; + int ret; + + syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl"); + if (IS_ERR(syscon)) { + dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n"); + return PTR_ERR(syscon); + } + + ret = j721e_pcie_set_mode(pcie, syscon); + if (ret < 0) { + dev_err(dev, "Failed to set pci mode\n"); + return ret; + } + + ret = j721e_pcie_set_link_speed(pcie, syscon); + if (ret < 0) { + dev_err(dev, "Failed to set link speed\n"); + return ret; + } + + ret = j721e_pcie_set_lane_count(pcie, syscon); + if (ret < 0) { + dev_err(dev, "Failed to set num-lanes\n"); + return ret; + } + + return 0; +} + +static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *value) +{ + struct pci_host_bridge *bridge = pci_find_host_bridge(bus); + struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge); + unsigned int busn = bus->number; + + if (busn == rc->bus_range->start) + return pci_generic_config_read32(bus, devfn, where, size, + value); + + return pci_generic_config_read(bus, devfn, where, size, value); +} + +static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + struct pci_host_bridge *bridge = pci_find_host_bridge(bus); + struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge); + unsigned int busn = bus->number; + + if (busn == rc->bus_range->start) + return pci_generic_config_write32(bus, devfn, where, size, + value); + + return pci_generic_config_write(bus, devfn, where, size, value); +} + +static struct pci_ops cdns_ti_pcie_host_ops = { + .map_bus = cdns_pci_map_bus, + .read = cdns_ti_pcie_config_read, + .write = cdns_ti_pcie_config_write, +}; + +static const struct j721e_pcie_data j721e_pcie_rc_data = { + .mode = PCI_MODE_RC, +}; + +static const struct j721e_pcie_data j721e_pcie_ep_data = { + .mode = PCI_MODE_EP, +}; + +static const struct of_device_id of_j721e_pcie_match[] = { + { + .compatible = "ti,j721e-pcie-host", + .data = &j721e_pcie_rc_data, + }, + { + .compatible = "ti,j721e-pcie-ep", + .data = &j721e_pcie_ep_data, + }, + {}, +}; + +static int j721e_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + const struct of_device_id *match; + struct pci_host_bridge *bridge; + struct j721e_pcie_data *data; + struct cdns_pcie *cdns_pcie; + struct j721e_pcie *pcie; + struct cdns_pcie_rc *rc; + struct cdns_pcie_ep *ep; + struct gpio_desc *gpiod; + struct resource *res; + void __iomem *base; + u32 num_lanes; + u32 mode; + int ret; + + match = of_match_device(of_match_ptr(of_j721e_pcie_match), dev); + if (!match) + return -EINVAL; + + data = (struct j721e_pcie_data *)match->data; + mode = (u32)data->mode; + + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + pcie->dev = dev; + pcie->node = node; + pcie->mode = mode; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "user_cfg"); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + pcie->user_cfg_base = base; + + ret = of_property_read_u32(node, "num-lanes", &num_lanes); + if (ret || num_lanes > MAX_LANES) + num_lanes = 1; + pcie->num_lanes = num_lanes; + + dev_set_drvdata(dev, pcie); + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + goto err_get_sync; + } + + ret = j721e_pcie_ctrl_init(pcie); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + goto err_get_sync; + } + + switch (mode) { + case PCI_MODE_RC: + if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) { + ret = -ENODEV; + goto err_get_sync; + } + + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); + if (!bridge) { + ret = -ENOMEM; + goto err_get_sync; + } + + bridge->ops = &cdns_ti_pcie_host_ops; + rc = pci_host_bridge_priv(bridge); + + cdns_pcie = &rc->pcie; + cdns_pcie->dev = dev; + cdns_pcie->ops = &j721e_ops_ops; + pcie->cdns_pcie = cdns_pcie; + + gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(gpiod)) { + ret = PTR_ERR(gpiod); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get reset GPIO\n"); + goto err_get_sync; + } + + ret = cdns_pcie_init_phy(dev, cdns_pcie); + if (ret) { + dev_err(dev, "Failed to init phy\n"); + goto err_get_sync; + } + + /* + * "Power Sequencing and Reset Signal Timings" table in + * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 + * indicates PERST# should be deasserted after minimum of 100us + * once REFCLK is stable. The REFCLK to the connector in RC + * mode is selected while enabling the PHY. So deassert PERST# + * after 100 us. + */ + if (gpiod) { + usleep_range(100, 200); + gpiod_set_value_cansleep(gpiod, 1); + } + + ret = cdns_pcie_host_setup(rc); + if (ret < 0) + goto err_pcie_setup; + + break; + case PCI_MODE_EP: + if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP)) { + ret = -ENODEV; + goto err_get_sync; + } + + ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); + if (!ep) { + ret = -ENOMEM; + goto err_get_sync; + } + + cdns_pcie = &ep->pcie; + cdns_pcie->dev = dev; + cdns_pcie->ops = &j721e_ops_ops; + pcie->cdns_pcie = cdns_pcie; + + ret = cdns_pcie_init_phy(dev, cdns_pcie); + if (ret) { + dev_err(dev, "Failed to init phy\n"); + goto err_get_sync; + } + + ret = cdns_pcie_ep_setup(ep); + if (ret < 0) + goto err_pcie_setup; + + break; + default: + dev_err(dev, "INVALID device type %d\n", mode); + } + + return 0; + +err_pcie_setup: + cdns_pcie_disable_phy(cdns_pcie); + +err_get_sync: + pm_runtime_put(dev); + pm_runtime_disable(dev); + + return ret; +} + +static int j721e_pcie_remove(struct platform_device *pdev) +{ + struct j721e_pcie *pcie = platform_get_drvdata(pdev); + struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; + struct device *dev = &pdev->dev; + + cdns_pcie_disable_phy(cdns_pcie); + pm_runtime_put(dev); + pm_runtime_disable(dev); + of_platform_depopulate(dev); + + return 0; +} + +static struct platform_driver j721e_pcie_driver = { + .probe = j721e_pcie_probe, + .remove = j721e_pcie_remove, + .driver = { + .name = "j721e-pcie", + .of_match_table = of_j721e_pcie_match, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(j721e_pcie_driver); From patchwork Mon Dec 9 09:21:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181001 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4098274ile; Mon, 9 Dec 2019 01:21:34 -0800 (PST) X-Google-Smtp-Source: APXvYqxPkpZU0ryOsY/kknrOcJFKrQtNUqSARtgqDHrynxEV1Qh73eXmXCdiVBX8E1RntEIYbqj9 X-Received: by 2002:aca:72cd:: with SMTP id p196mr21736840oic.99.1575883294355; Mon, 09 Dec 2019 01:21:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575883294; cv=none; d=google.com; s=arc-20160816; b=JPZ3t6lliYqDVvbkf+6DnQHzb/G01vn1wnRqQlVYrFObvjkIX8zMw68621Wo8IWFCD nPvudNdnZwhWo4Y/4ssAwCLu1ZWWjNZMnt5EPmIe/6I+wOfdBzC/C4TMHSqsEewdHr98 HarBmER/CfYRaHcS4SeIcb7d5qCeJBOJLNGdKNR1dow6JWqx5eKB0EOtDPe5s8GCLMvB vcE8F6Ktyu+KigQUcjhlm1IipvNIJqy/CpS2aydz1x4HVm4N0xjLwqPBkPAE3rVDMFtc WAyoy6ihZ307+kExLJQw2mBIp3JMY0zSxdPZQrTHc/iDE0Jdb+28/vjUvd9z0vKWbBZJ ogRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=OE+CQaY8YINUAl14yThoqiQN60PdlpJALyII5dYryI0=; b=eKlka06w5A/ivHRHPsFqAdMVsLetqZzstoyfIeACIOp6poLAzfLAMZFT4YAx9FSm93 41ho/WGTjULBH6Z8q+ENWr+JTzQ4I3Q0zOr/hV7HyZ75CHh60Fi9sdq/oU36FNE+9gIm 38bXpHEo8KgSakcIjtZpmDDfdySFZqe9kXkqUKlmKdqbZySkXCRE1+6q2wolDpjwq70w VRedKKllWx/n50Xy4bes1lcS1VTqaU1XKq3aXCkIRdryeyGWe4ZYK8xmtF/tuHIbSJcH xWaqkv1uYaYs7iBoBK1OAE5JzuNH7dYn+3z9xr42J7eLKMle6hYpBYarvEP/CgzM7wq5 nL+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=pSdh0Hcw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n14si5634492otk.179.2019.12.09.01.21.34; Mon, 09 Dec 2019 01:21:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=pSdh0Hcw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727729AbfLIJVc (ORCPT + 27 others); Mon, 9 Dec 2019 04:21:32 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:49978 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727706AbfLIJVa (ORCPT ); Mon, 9 Dec 2019 04:21:30 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99LMCJ080999; Mon, 9 Dec 2019 03:21:22 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575883282; bh=OE+CQaY8YINUAl14yThoqiQN60PdlpJALyII5dYryI0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pSdh0HcwFe5UPzyR7XLR935NQiaefE9pxrgC7ov4I7AJP2++kvpTtY5jjClpvWc1z 1E05v/KVDYPevpFv4WEPkzBxfeuJO/dCL6Ugtm83IMPVemXMPod1wGrrizXRhUcTg1 0/ZlOmZsEZK+tRzZQs/iEbdkGWnPNfOVjRi2N+ic= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB99LM8E006138 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Dec 2019 03:21:22 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:21:22 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:21:22 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99KcdA087697; Mon, 9 Dec 2019 03:21:19 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Arnd Bergmann , Andrew Murray CC: , , , , Kishon Vijay Abraham I Subject: [PATCH 12/13] misc: pci_endpoint_test: Add J721E in pci_device_id table Date: Mon, 9 Dec 2019 14:51:46 +0530 Message-ID: <20191209092147.22901-13-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191209092147.22901-1-kishon@ti.com> References: <20191209092147.22901-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add J721E in pci_device_id table so that pci-epf-test can be used for testing PCIe EP in J721E. Signed-off-by: Kishon Vijay Abraham I --- drivers/misc/pci_endpoint_test.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.17.1 diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index a5e317073d95..215f9b8432a3 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -64,6 +64,7 @@ #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24 #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28 +#define PCI_DEVICE_ID_TI_J721E 0xb00d #define PCI_DEVICE_ID_TI_AM654 0xb00c #define is_am654_pci_dev(pdev) \ @@ -789,6 +790,11 @@ static const struct pci_endpoint_test_data am654_data = { .irq_type = IRQ_TYPE_MSI, }; +static const struct pci_endpoint_test_data j721e_data = { + .alignment = 256, + .irq_type = IRQ_TYPE_MSI, +}; + static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) }, { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) }, @@ -797,6 +803,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654), .driver_data = (kernel_ulong_t)&am654_data }, + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E), + .driver_data = (kernel_ulong_t)&j721e_data, + }, { } }; MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl); From patchwork Mon Dec 9 09:21:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181002 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4098340ile; Mon, 9 Dec 2019 01:21:39 -0800 (PST) X-Google-Smtp-Source: APXvYqxihz6L6Wr/qEhFK589tgiLkcHl8mIvv1c687GmZg34nlPwnvTwaQ24wvHxB3Mo9c2S9W0/ X-Received: by 2002:a9d:2073:: with SMTP id n106mr20727393ota.145.1575883298902; Mon, 09 Dec 2019 01:21:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575883298; cv=none; d=google.com; s=arc-20160816; b=ZNxYqm+xhvRCx+twy+5kf6b+fBtXzwSODhbgTbz3YmJgFKZsrAtTrtw/+boqfrz6xx +59iaBuYf+sucpcMNbBT2x0yux8Ggwm+hX6xirY62j/ZzjYfnuYAHLPmM4+d7RO1DbaW WvQkt/XtYvd22ScTqWaQ8bbwrn/oUU9il8XdSy2mXD8U/jVeC7gpFhxLGAtQYqoiF6+V 6Qcea66UfwpzZEuPVzpTJvCBVyJjxbBG1XouC6tJ3saWFeD3PFOXquNHoGYIUj4K24Ie yKELeWdw8zNaDh+dJoqR1pbHoEANM470LUPVMCbd13e8ivDd7pYcX7DIKPMkJh8+Cv5w Mhyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=cTJomjNQR0NW5SRIkkORWQfkiTKy/NfWuwZUGbbS3uA=; b=nAj41ub8pz2Uy4/+FchnDJTQswxfnB1eMMlcpZgJOA1xtWPJMdsIcEt043IAO7JWUv PMhn+yqiMVF89GzcfsaloRC9PiBUFvfhKlyyjrIBx/hM4iHA03dhQKLIiRJeFhKMRFO0 sySFU24V5tuplH0vyn5rYRDJyH68i0piEU5g024ffPFb62J4Qbi3rYtT/umwNqyA+FR0 vWMwMEI4lArVIjNZfSlcZij1tO1jaxZORgh2UeQqEu2E3zVYVkUmqTnc/n+xKa6ghEvQ Wto9Eg6CUNFceWLKuUY2akPZSZKKkWGAUwGJ383JDu0YY12aXDE05qTkeUwgpHnNMA1p KkgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=OAleDUDj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v21si10871264otj.282.2019.12.09.01.21.38; Mon, 09 Dec 2019 01:21:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=OAleDUDj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727740AbfLIJVh (ORCPT + 27 others); Mon, 9 Dec 2019 04:21:37 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:49524 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727718AbfLIJVc (ORCPT ); Mon, 9 Dec 2019 04:21:32 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99LPHq026154; Mon, 9 Dec 2019 03:21:25 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575883285; bh=cTJomjNQR0NW5SRIkkORWQfkiTKy/NfWuwZUGbbS3uA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OAleDUDjlZrmKYS+2pxGC/MILdtul2ndm1T8f/23r67hG0phlm7zivhm2j55WszWv r5oReC8nsFTwMKKWg7+GQHBpLAlNn9Cm/nMTKlYAZN5ylm4UEn2H59yF6fciiSnp/O 8ExJYRSQ1+x7NxBuefTLcudPpqVk55e4ojIwdYsk= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB99LPBZ064204 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Dec 2019 03:21:25 -0600 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:21:25 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:21:25 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99KcdB087697; Mon, 9 Dec 2019 03:21:22 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Arnd Bergmann , Andrew Murray CC: , , , , Kishon Vijay Abraham I Subject: [PATCH 13/13] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Date: Mon, 9 Dec 2019 14:51:47 +0530 Message-ID: <20191209092147.22901-14-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191209092147.22901-1-kishon@ti.com> References: <20191209092147.22901-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Kishon Vijay Abraham I as MAINTAINER for TI J721E SoC PCIe. Signed-off-by: Kishon Vijay Abraham I --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/MAINTAINERS b/MAINTAINERS index bd5847e802de..a9533d0752de 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12691,13 +12691,14 @@ S: Maintained F: Documentation/devicetree/bindings/pci/designware-pcie.txt F: drivers/pci/controller/dwc/*designware* -PCI DRIVER FOR TI DRA7XX +PCI DRIVER FOR TI DRA7XX/J721E M: Kishon Vijay Abraham I L: linux-omap@vger.kernel.org L: linux-pci@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/pci/ti-pci.txt F: drivers/pci/controller/dwc/pci-dra7xx.c +F: drivers/pci/controller/cadence/pci-j721e.c PCI DRIVER FOR TI KEYSTONE M: Murali Karicheri