From patchwork Mon Dec 9 09:43:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 181005 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4117418ile; Mon, 9 Dec 2019 01:43:51 -0800 (PST) X-Google-Smtp-Source: APXvYqyRbx0z+bYXX8GBVS5d9g4RkIuGPRKiTskcXNS5DknYvl0SR/UDhIXu6aBhBb8kULv1FVZk X-Received: by 2002:aca:b808:: with SMTP id i8mr12178021oif.66.1575884631187; Mon, 09 Dec 2019 01:43:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575884631; cv=none; d=google.com; s=arc-20160816; b=eGg4TbCf9RyellA7pryrryLpH7k/D35JnKV8BwD+dgX8/IHtAKMvwCx6Y4wgBGgFJB nRAh1YUZjOHQ2GnhbNsRTeSQetfTfbDwLfAvekvRF9FF4inh9Akw76/CFDJb47LIy4Ul Tzy3LmWQQP2M7UU+B7YfVLH3+xkGB/D+4K6qCVIzt5JnvCymINNwTEfd9JiT5v52Mlw7 YLkFcAfe4S+qJTTBZGzBHEkS0a1q52VPwz/GoQRcv4gAct2vIoqpLRXaCGPDvErKKbeM Yy5pcWtHJ3szQsWETSNWV5/518bFop3VmM0qiFwssCGQ/5WG1M/swR3t1yBS4DdmUqaa JaQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uSViP+QvJDzIv6c8dhx5jMKNUxJQ+VwAKiFTRE1e4co=; b=bqe7AyI/Xs5W8QD0nBDsvH42DiPNzCjXDT3CjUrc9p8laV4fIQ3wDcrDwXLq5LOVR6 kxZMhdDMzRwNMrnISqMb8wB54WraOr4EQ7WQn2hz1v8at+T0ud8o1wWsDi/RURmNs+7N DzLuOL9jDzAtY+ttwhMjT4JMtrhgVrr+HvuA4aXdbTBvXeXp9ByIm0DLDWAIGrHDI/4A ySu04Jn1x4hhgF4Rw4LyS9dtlDtx08nlu9MWfyJArOY2A/YvFYb/s0Lk+qkwFRI+L4uL 97J8BXI8zQnXd1BJmcdhXcWBA4S+40HhbOdblLMiuWzFVFqmb6yDaPON8IVnUNIKg6Nj eqZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=KPzgZ+xo; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h139si11805290oib.85.2019.12.09.01.43.50; Mon, 09 Dec 2019 01:43:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=KPzgZ+xo; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727666AbfLIJnt (ORCPT + 8 others); Mon, 9 Dec 2019 04:43:49 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:52216 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727649AbfLIJns (ORCPT ); Mon, 9 Dec 2019 04:43:48 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99hf2L033102; Mon, 9 Dec 2019 03:43:41 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575884621; bh=uSViP+QvJDzIv6c8dhx5jMKNUxJQ+VwAKiFTRE1e4co=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=KPzgZ+xorC/+hnSfVemPOyUjF4D9dyQ90O7xw1/As7IAZz3iXpYE4Eb2Ng+rpIhrR wN9eitL05T5RA61t3mDju6a3/7JwnQXzqyqZ8fLnjyiMM/vyzj7U7sjGwHmgIkmpqG YNnzoYbR3QRYrJgzLZ107PjjNvc8bqMeP0vlBxQI= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB99hfEp041537 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Dec 2019 03:43:41 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:43:41 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:43:41 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99hOWk080263; Mon, 9 Dec 2019 03:43:37 -0600 From: Peter Ujfalusi To: , , , CC: , , , , , , , , , , Subject: [PATCH v7 03/12] dmaengine: doc: Add sections for per descriptor metadata support Date: Mon, 9 Dec 2019 11:43:23 +0200 Message-ID: <20191209094332.4047-4-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191209094332.4047-1-peter.ujfalusi@ti.com> References: <20191209094332.4047-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update the provider and client documentation with details about the metadata support. Signed-off-by: Peter Ujfalusi Reviewed-by: Tero Kristo --- Documentation/driver-api/dmaengine/client.rst | 75 +++++++++++++++++++ .../driver-api/dmaengine/provider.rst | 46 ++++++++++++ 2 files changed, 121 insertions(+) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/driver-api/dmaengine/client.rst b/Documentation/driver-api/dmaengine/client.rst index 45953f171500..41309c176df4 100644 --- a/Documentation/driver-api/dmaengine/client.rst +++ b/Documentation/driver-api/dmaengine/client.rst @@ -151,6 +151,81 @@ The details of these operations are: Note that callbacks will always be invoked from the DMA engines tasklet, never from interrupt context. + Optional: per descriptor metadata + --------------------------------- + DMAengine provides two ways for metadata support. + + DESC_METADATA_CLIENT + + The metadata buffer is allocated/provided by the client driver and it is + attached to the descriptor. + + .. code-block:: c + + int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc, + void *data, size_t len); + + DESC_METADATA_ENGINE + + The metadata buffer is allocated/managed by the DMA driver. The client + driver can ask for the pointer, maximum size and the currently used size of + the metadata and can directly update or read it. + + .. code-block:: c + + void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc, + size_t *payload_len, size_t *max_len); + + int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc, + size_t payload_len); + + Client drivers can query if a given mode is supported with: + + .. code-block:: c + + bool dmaengine_is_metadata_mode_supported(struct dma_chan *chan, + enum dma_desc_metadata_mode mode); + + Depending on the used mode client drivers must follow different flow. + + DESC_METADATA_CLIENT + + - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM: + 1. prepare the descriptor (dmaengine_prep_*) + construct the metadata in the client's buffer + 2. use dmaengine_desc_attach_metadata() to attach the buffer to the + descriptor + 3. submit the transfer + - DMA_DEV_TO_MEM: + 1. prepare the descriptor (dmaengine_prep_*) + 2. use dmaengine_desc_attach_metadata() to attach the buffer to the + descriptor + 3. submit the transfer + 4. when the transfer is completed, the metadata should be available in the + attached buffer + + DESC_METADATA_ENGINE + + - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM: + 1. prepare the descriptor (dmaengine_prep_*) + 2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the + engine's metadata area + 3. update the metadata at the pointer + 4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the + amount of data the client has placed into the metadata buffer + 5. submit the transfer + - DMA_DEV_TO_MEM: + 1. prepare the descriptor (dmaengine_prep_*) + 2. submit the transfer + 3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get the + pointer to the engine's metadata area + 4. Read out the metadata from the pointer + + .. note:: + + Mixed use of DESC_METADATA_CLIENT / DESC_METADATA_ENGINE is not allowed, + client drivers must use either of the modes per descriptor. + 4. Submit the transaction Once the descriptor has been prepared and the callback information diff --git a/Documentation/driver-api/dmaengine/provider.rst b/Documentation/driver-api/dmaengine/provider.rst index dfc4486b5743..da557c21c619 100644 --- a/Documentation/driver-api/dmaengine/provider.rst +++ b/Documentation/driver-api/dmaengine/provider.rst @@ -247,6 +247,52 @@ after each transfer. In case of a ring buffer, they may loop (DMA_CYCLIC). Addresses pointing to a device's register (e.g. a FIFO) are typically fixed. +Per descriptor metadata support +------------------------------- +Some data movement architecture (DMA controller and peripherals) uses metadata +associated with a transaction. The DMA controller role is to transfer the +payload and the metadata alongside. +The metadata itself is not used by the DMA engine itself, but it contains +parameters, keys, vectors, etc for peripheral or from the peripheral. + +The DMAengine framework provides a generic ways to facilitate the metadata for +descriptors. Depending on the architecture the DMA driver can implement either +or both of the methods and it is up to the client driver to choose which one +to use. + +- DESC_METADATA_CLIENT + + The metadata buffer is allocated/provided by the client driver and it is + attached (via the dmaengine_desc_attach_metadata() helper to the descriptor. + + From the DMA driver the following is expected for this mode: + - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM + The data from the provided metadata buffer should be prepared for the DMA + controller to be sent alongside of the payload data. Either by copying to a + hardware descriptor, or highly coupled packet. + - DMA_DEV_TO_MEM + On transfer completion the DMA driver must copy the metadata to the client + provided metadata buffer. + +- DESC_METADATA_ENGINE + + The metadata buffer is allocated/managed by the DMA driver. The client driver + can ask for the pointer, maximum size and the currently used size of the + metadata and can directly update or read it. dmaengine_desc_get_metadata_ptr() + and dmaengine_desc_set_metadata_len() is provided as helper functions. + + From the DMA driver the following is expected for this mode: + - get_metadata_ptr + Should return a pointer for the metadata buffer, the maximum size of the + metadata buffer and the currently used / valid (if any) bytes in the buffer. + - set_metadata_len + It is called by the clients after it have placed the metadata to the buffer + to let the DMA driver know the number of valid bytes provided. + + Note: since the client will ask for the metadata pointer in the completion + callback (in DMA_DEV_TO_MEM case) the DMA driver must ensure that the + descriptor is not freed up prior the callback is called. + Device operations ----------------- From patchwork Mon Dec 9 09:43:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 181006 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4117496ile; Mon, 9 Dec 2019 01:43:58 -0800 (PST) X-Google-Smtp-Source: APXvYqz49trKADHN1rZMAdmH87A07VlY6OYxWqdoinBG5zBdudnzKgkkjw7xnVUOhljP6gGVj/wQ X-Received: by 2002:a05:6830:1d7a:: with SMTP id l26mr14298448oti.138.1575884638270; Mon, 09 Dec 2019 01:43:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575884638; cv=none; d=google.com; s=arc-20160816; b=DjJ4z6Dm+rumKUwYLjMenlVtHWiv0Y7SiNJcMysk3ak1RG+5FtdaPcktlgcCAhGiPq ubKtpida3PdEmSdBUB9xvg/efUBTDLUAvjZmGbAZokvPM8utjz4OWT5L17m7PzNYhBTJ xpfEVuZsFoM+gLF/Z7IsHgGQkjAQtX5bLK3zbuqCn3+ISadaV0mFXKHbSJYLop/STipM dcOczzP1Sx6eUBUS2qNpq27olaNCgC6LZjVwmOmKWecTOB5aY8g7Rbp4u06+yesFtQVw 8IwvhRWhtJp7OMnxheJFr218R9dDELUu/H+aLlS17uV93HToQuMy9abvWsHL/vZ4pGED viuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=1ejU+vd2T9/FB/A9l3rJiiNfVEy7pyhWG9mzxXGvrc8=; b=aX2esnEO0s0lqkWJIR5igYJ3aUuOET85/thRAKP5xiCZKyfYlmFIqkwqW0Vbqm1EEv Z4YApu1M4O4eUxaNOIkJyu3HX3DgLutEf7/zwN0Dk1qOIsw7xLBLaPNy+hXPcsYSb9tC iAhpFItmFxTNPpBmL5P7CBrqVmPAqxRo0bFC+Zh6eV8jikAfSqpKqBeCVQ7Kk3sq4229 wE5OBGx18joXs/kzaRojzTf3lcqH1aBFul8JB0Vim7c06NS3FgUoGOCLhy7UVsFeSrK5 ZjtPLKhwxyIq0WZrjVqp1X83F2PDAY77uWrRfZ6yGcqRS5/9urxH+EkA0L9CAlxCdtYG 2Org== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=t2MRX1bD; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q26si11566144oij.38.2019.12.09.01.43.58; Mon, 09 Dec 2019 01:43:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=t2MRX1bD; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727506AbfLIJn5 (ORCPT + 8 others); Mon, 9 Dec 2019 04:43:57 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:57546 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727682AbfLIJn5 (ORCPT ); Mon, 9 Dec 2019 04:43:57 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99hnEh108537; Mon, 9 Dec 2019 03:43:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575884629; bh=1ejU+vd2T9/FB/A9l3rJiiNfVEy7pyhWG9mzxXGvrc8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=t2MRX1bDhbmbg6nQZg6aKzoT6ERle44QR8OAMv57meO94t17L82jlT4de1YQXBHi/ gyMJ5C3jX8F6+R6m5GZwh3S6Nj/GfUbumde8kfY8aumE57kBwV7xt1M4CsNnOtMj8I l7jLXwCum9rap3Mbp+0CMFz7qVHXpH75ClVRvWYQ= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99hnPC032005; Mon, 9 Dec 2019 03:43:49 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:43:49 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:43:49 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99hOWm080263; Mon, 9 Dec 2019 03:43:45 -0600 From: Peter Ujfalusi To: , , , CC: , , , , , , , , , , Subject: [PATCH v7 05/12] dmaengine: Add support for reporting DMA cached data amount Date: Mon, 9 Dec 2019 11:43:25 +0200 Message-ID: <20191209094332.4047-6-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191209094332.4047-1-peter.ujfalusi@ti.com> References: <20191209094332.4047-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org A DMA hardware can have big cache or FIFO and the amount of data sitting in the DMA fabric can be an interest for the clients. For example in audio we want to know the delay in the data flow and in case the DMA have significantly large FIFO/cache, it can affect the latenc/delay Signed-off-by: Peter Ujfalusi Reviewed-by: Tero Kristo --- drivers/dma/dmaengine.h | 8 ++++++++ include/linux/dmaengine.h | 2 ++ 2 files changed, 10 insertions(+) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h index 501c0b063f85..b0b97475707a 100644 --- a/drivers/dma/dmaengine.h +++ b/drivers/dma/dmaengine.h @@ -77,6 +77,7 @@ static inline enum dma_status dma_cookie_status(struct dma_chan *chan, state->last = complete; state->used = used; state->residue = 0; + state->in_flight_bytes = 0; } return dma_async_is_complete(cookie, complete, used); } @@ -87,6 +88,13 @@ static inline void dma_set_residue(struct dma_tx_state *state, u32 residue) state->residue = residue; } +static inline void dma_set_in_flight_bytes(struct dma_tx_state *state, + u32 in_flight_bytes) +{ + if (state) + state->in_flight_bytes = in_flight_bytes; +} + struct dmaengine_desc_callback { dma_async_tx_callback callback; dma_async_tx_callback_result callback_result; diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 0e8b426bbde9..c4c5219030a6 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -682,11 +682,13 @@ static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descr * @residue: the remaining number of bytes left to transmit * on the selected transfer for states DMA_IN_PROGRESS and * DMA_PAUSED if this is implemented in the driver, else 0 + * @in_flight_bytes: amount of data in bytes cached by the DMA. */ struct dma_tx_state { dma_cookie_t last; dma_cookie_t used; u32 residue; + u32 in_flight_bytes; }; /** From patchwork Mon Dec 9 09:43:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 181012 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4117829ile; Mon, 9 Dec 2019 01:44:25 -0800 (PST) X-Google-Smtp-Source: APXvYqzCdgH/AFN3+O9AkTAD2dboDBO7yljsRYPsEWvUfGZdrki74/Gc+J6rwPkDDuKRuZ7lKJ98 X-Received: by 2002:a05:6808:14:: with SMTP id u20mr18119693oic.118.1575884664916; Mon, 09 Dec 2019 01:44:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575884664; cv=none; d=google.com; s=arc-20160816; b=v+OWW524WouKr47rN0StqQCicsRADwnDPA2nYmhbRo03x/gBNSbtojCGj83JAUCrpE pCxSFMHiIBSVYeSDGk7R106jk/gS8u6CpJg18/XECeSablZgZjx5vt2r/6Xwpg6IJn35 730nHm4P1r/T9UVm8REGF16Ymc5AzQBDxMqePKBDxTxs91IaSUajD1QOHWpZDQmF76rq 3YT/w9Um0sRVpPlkPSweSY2QQXXfCTOR5cWohuaoRWJdZWuaoEeciOCXq8luONOpTKI3 /v8NApuIECGA914wuZ59fiFzknwt7wrIUS2968dhlAlObDkAWDBwLPpXS7gzxwfGthND xjgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=k8zlie3vgjn4WO7EA2Hs+7MNYJ/pD0HQW1aRzR1mgkk=; b=eQWZBNFFWaQQ6xdC3+2G/XPLIQblP1CE4WP8u53ol1D2G1d94PlPm3RiAIKc1jXQkG II80ELhdJ+O/3KxeKaVB3sLZy8KNUuOTzX4t29CCE7/s/1MiNB1hEVOcQtEQS28PwXEL fXT/+hhxp2pzgyW2zgGFzOnSTkTdMlOfG4IaNzpbELY6mbxlZKQyjKARaINPWl41V4IH E5jLNuzGgWE/TZpELqq2EktuLCwYRp2ogD2l2jQjHO0j3UmZP8LXpTZo/hjyfimVVbC0 T+Yc8+0mc3JGCY/7OTJaVFa9yJlFtWr11jdY4jijVuMIMsV3vkP800l7lyHV7+zDZDkE CInQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Mtcy7Gap; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d4si10702026ote.135.2019.12.09.01.44.24; Mon, 09 Dec 2019 01:44:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Mtcy7Gap; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727200AbfLIJoX (ORCPT + 8 others); Mon, 9 Dec 2019 04:44:23 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:52300 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727225AbfLIJoX (ORCPT ); Mon, 9 Dec 2019 04:44:23 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99iEM1033284; Mon, 9 Dec 2019 03:44:14 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575884654; bh=k8zlie3vgjn4WO7EA2Hs+7MNYJ/pD0HQW1aRzR1mgkk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Mtcy7GappiVQy6Zw67leO3jv5qLpKTPsaJY5HY7DC/sHORpYrCvxCFgbdwOe+0HqF XhTj+HRAfRg9FdGXgil1aXi2+fPY2pm1uTH6ykCPBoBSWnsSb3TvZ0+/STZ36WnP2v /7WFm+aBhY6ZlIHBnWRWZ5RLCoWk0TDNPDbTuIHU= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB99iEIT077723 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Dec 2019 03:44:14 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:44:14 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:44:14 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99hOWs080263; Mon, 9 Dec 2019 03:44:10 -0600 From: Peter Ujfalusi To: , , , CC: , , , , , , , , , , Subject: [PATCH v7 11/12] firmware: ti_sci: rm: Add support for tx_tdtype parameter for tx channel Date: Mon, 9 Dec 2019 11:43:31 +0200 Message-ID: <20191209094332.4047-12-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191209094332.4047-1-peter.ujfalusi@ti.com> References: <20191209094332.4047-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The system controller's resource manager have support for configuring the TDTYPE of TCHAN_CFG register on j721e. With this parameter the teardown completion can be controlled: TDTYPE == 0: Return without waiting for peer to complete the teardown TDTYPE == 1: Wait for peer to complete the teardown Signed-off-by: Peter Ujfalusi --- drivers/firmware/ti_sci.c | 1 + drivers/firmware/ti_sci.h | 7 +++++++ include/linux/soc/ti/ti_sci_protocol.h | 2 ++ 3 files changed, 10 insertions(+) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 4126be9e3216..f13e4a96f3b7 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -2412,6 +2412,7 @@ static int ti_sci_cmd_rm_udmap_tx_ch_cfg(const struct ti_sci_handle *handle, req->fdepth = params->fdepth; req->tx_sched_priority = params->tx_sched_priority; req->tx_burst_size = params->tx_burst_size; + req->tx_tdtype = params->tx_tdtype; ret = ti_sci_do_xfer(info, xfer); if (ret) { diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h index f0d068c03944..255327171dae 100644 --- a/drivers/firmware/ti_sci.h +++ b/drivers/firmware/ti_sci.h @@ -910,6 +910,7 @@ struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg { * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size + * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype * * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located * @@ -973,6 +974,11 @@ struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg { * * @tx_burst_size: UDMAP transmit channel burst size configuration to be * programmed into the tx_burst_size field of the TCHAN_TCFG register. + * + * @tx_tdtype: UDMAP transmit channel teardown type configuration to be + * programmed into the tdtype field of the TCHAN_TCFG register: + * 0 - Return immediately + * 1 - Wait for completion message from remote peer */ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req { struct ti_sci_msg_hdr hdr; @@ -994,6 +1000,7 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req { u16 fdepth; u8 tx_sched_priority; u8 tx_burst_size; + u8 tx_tdtype; } __packed; /** diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index 9531ec823298..f3aed0b91564 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -342,6 +342,7 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg { #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID BIT(15) u16 nav_id; u16 index; u8 tx_pause_on_err; @@ -359,6 +360,7 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg { u16 fdepth; u8 tx_sched_priority; u8 tx_burst_size; + u8 tx_tdtype; }; /**