From patchwork Mon Dec 9 16:21:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 181060 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4565545ile; Mon, 9 Dec 2019 08:21:17 -0800 (PST) X-Google-Smtp-Source: APXvYqyLY5rbYQ+PkeAVRf7TFUO/Ej1YvAcG60uTgp7CNlIfaXDYEiIfMFg7Q5DNxu5xyJG4dYmF X-Received: by 2002:aca:530e:: with SMTP id h14mr23826848oib.105.1575908476944; Mon, 09 Dec 2019 08:21:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575908476; cv=none; d=google.com; s=arc-20160816; b=wBh8nYFyNYBD3gOiNfDW9eH+JuRuo20F9CkRvtu9yackXLM+VAMDpI2aZTvIoIk2W1 qpbEjZfwhnoARgK/KYfDDpoabHE1nMNdnwoeRWu1+4qooda+Jq56zLniaHzxr7Sf4OJF RPBdLXI+1dN7sXGg5M7mBHgQGrIiKqMiHx7Uo1OQr4B2pZLLzmkteLLbD8L0VTXTYdTf ZxzCQ2JtzQkzRfylHMCom6BpSYbBBbXZF46Y+ltYIPA5TDtKzQSVrEqPzg5BnmO57Lcb HFHuFQLMspPzZ5RlFkEzuGOhpfXkf9WDY1XyS2FoZGKlXx0smEnE8fnA5aKjBVlk+uEG Y9bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=vxhkMBsN2pPnCv5+ROibr/eTdfzg7Vv+kXmb+sy+smY=; b=HQ5eh6tg+PBxhHiPYKRRuAhE8EhZO05Y6tpljsTOPDhawFc/rdS40TlgyAqQ/h9Qd9 znK5h3DtChYL8RuAUxuqtBLSb6iNccvtmTVoOt29H61Eyxo+XilYzvUNvOgiPXMaoHQU tlfRNmO0U8G/qwg6nxFcTnMnm602QKT1hNx9DcVTEY9h/EUfbQPeYTF0z+lJ5ODPgH4O t5Etql3y5XdgA6BUqvlak+4w32iSzYKqAOHut3JvaNyaytMdAl1RQ2jVfVCrHEO5TEvT naPBq6taLvciAFhvmYUendP5USI0YwBvH2KGLpHGqh/t9TkmorTEaXBneMN1GEyC5WYj Qkzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="Jhg/fh6t"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m2si48184otk.122.2019.12.09.08.21.16; Mon, 09 Dec 2019 08:21:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="Jhg/fh6t"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726637AbfLIQVP (ORCPT + 8 others); Mon, 9 Dec 2019 11:21:15 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:43364 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725904AbfLIQVO (ORCPT ); Mon, 9 Dec 2019 11:21:14 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB9GLCa7083653; Mon, 9 Dec 2019 10:21:12 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575908472; bh=vxhkMBsN2pPnCv5+ROibr/eTdfzg7Vv+kXmb+sy+smY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Jhg/fh6tPZt5NHrdIWV3b4OzYQkx9+0SKW3RoR8zD73j1TTY0TkQ3e6NJMpV70bF5 ZBwj0jwy4X4Lpib+pwAoLsBrw2wAlbPs6xxZ6+r8Tc5JNQ22s62ZLztFD2N6vbSjyi aD0wrPWWLzkVuWz6pvbLa3kjGEpmyZYwWFKNoFHo= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB9GLC9B000606 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Dec 2019 10:21:12 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 10:21:12 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 10:21:12 -0600 Received: from jadmar.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB9GL9xX003945; Mon, 9 Dec 2019 10:21:10 -0600 From: Jyri Sarha To: , , CC: , , , , , Subject: [PATCH 1/3] dt-bindings: phy: Add PHY_TYPE_DP definition Date: Mon, 9 Dec 2019 18:21:09 +0200 Message-ID: <89dfcd484bad19cb954ee4f74305d1aa172ea292.1575906694.git.jsarha@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add definition for DisplayPort phy type. Signed-off-by: Jyri Sarha Reviewed-by: Roger Quadros Reviewed-by: Kishon Vijay Abraham I --- include/dt-bindings/phy/phy.h | 1 + 1 file changed, 1 insertion(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki Acked-by: Rob Herring diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h index b6a1eaf1b339..1f3f866fae7b 100644 --- a/include/dt-bindings/phy/phy.h +++ b/include/dt-bindings/phy/phy.h @@ -16,5 +16,6 @@ #define PHY_TYPE_USB2 3 #define PHY_TYPE_USB3 4 #define PHY_TYPE_UFS 5 +#define PHY_TYPE_DP 6 #endif /* _DT_BINDINGS_PHY */ From patchwork Mon Dec 9 16:22:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 181061 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4567047ile; Mon, 9 Dec 2019 08:22:26 -0800 (PST) X-Google-Smtp-Source: APXvYqzsGaq32b3/WAkFj1r+RNn3l+7bmsltYQHaTozslkWeuZkgCanrcHB+fO9bQbxuNffGYvDo X-Received: by 2002:a9d:470a:: with SMTP id a10mr22542434otf.370.1575908546311; Mon, 09 Dec 2019 08:22:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575908546; cv=none; d=google.com; s=arc-20160816; b=dWybgAMkgDix31ehunbl/B59SOcJKckvmoUSD+stsASGbs2FaWagX5x7arV4f93upc QSXHA/sj16ESD6YnYgdH/rchEsRMNFvLdCaH5bhHkj21W+AUeGkntpu/aUCGzhpuKu6p xFJMhPQK1EHow9VNq1r7axirH4TYLeB/MekqnZpUD/FPTy+OjZ7vlrD5k7I8FZEH9Did 23ztj0FdqR3FojJeUs63nCweIwwxC6hnEWcjFxJYNQjGcM2sUIDDE6+eAycDVxfuud8e IdoHDybJrD+avy1q0HSXUTZidiTMFysI9xumpniVnkO6Qar/T4gGs/4N22aQ+YWtCedP wG6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=11P/kNtBZr7To0mT7AsXhF9sB871Rf94OEck46/XMgI=; b=gqdMvPODG/aIsnUJxc57ylfdhW0JMs462zHue2ebPxQAh/YI8t3JcXnpqtjeP2+RZx l4R6KimUbnVHyRslIipYNNjbJ1FkeI7cgdHPJF38LLNe/04wb1Gbz5DFFfLqLQTpk5Jw +smrPVHbBJLFCusbP7PIuRIxZoD/oBewkFctYH0E+RNtePTVFgloHTs3FADkRWNlbXT7 Z9frhH2TDQsNtWPFMqG25BtDYWQVKEjncg0TVVbIFbn9jx8aFSWkDC+q0z27UJJVrMB7 ZkcZz2RNDdRd7frLgf9Fc4EIvg2+/GUqI2v/DTxkLi6+ikeuC3tZi+ULhZrHyUt80Njo ZxUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dbzFKeQE; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j20si55204otp.147.2019.12.09.08.22.26; Mon, 09 Dec 2019 08:22:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dbzFKeQE; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726843AbfLIQWX (ORCPT + 8 others); Mon, 9 Dec 2019 11:22:23 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:48286 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726265AbfLIQWV (ORCPT ); Mon, 9 Dec 2019 11:22:21 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB9GMI7Z104372; Mon, 9 Dec 2019 10:22:18 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575908538; bh=11P/kNtBZr7To0mT7AsXhF9sB871Rf94OEck46/XMgI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dbzFKeQEGsD5elBkX4hgBjCcgUo8rksyXW9Z82/Lri6FFb7XVyWg90B7i3sbPe0VC AyOsptONJDCvWAIhaIYpEjhVJ1fxiEL/EXJYfzZE4ip0bcj2q2anZ99d6FcpR/rDzx kjPXOw/WLkhgGkZ3Grddwjkt3R0FadHMkrrwjgk8= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB9GMINa093851 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Dec 2019 10:22:18 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 10:22:14 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 10:22:14 -0600 Received: from jadmar.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB9GMBdO002331; Mon, 9 Dec 2019 10:22:12 -0600 From: Jyri Sarha To: , , , CC: , , , , , Subject: [PATCH 2/3] dt-bindings: phy: Add lane-mode property to WIZ (SERDES wrapper) Date: Mon, 9 Dec 2019 18:22:11 +0200 Message-ID: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add property to indicate the usage of SERDES lane controlled by the WIZ wrapper. The wrapper configuration has some variation depending on how each lane is going to be used. Signed-off-by: Jyri Sarha --- .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index 94e3b4b5ed8e..399725f65278 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -97,6 +97,18 @@ patternProperties: Torrent SERDES should follow the bindings specified in Documentation/devicetree/bindings/phy/phy-cadence-dp.txt + "^lane[1-4]-mode$": + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3, 4, 5, 6] + description: | + Integer describing static lane usage for the lane indicated in + the property name. For Sierra there may be properties lane0 and + lane1, for Torrent all lane[1-4]-mode properties may be + there. The constants to indicate the lane usage are defined in + "include/dt-bindings/phy/phy.h". The lane is assumed to be unused + if its lane-use property does not exist. + required: - compatible - power-domains From patchwork Mon Dec 9 16:22:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 181062 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4567186ile; Mon, 9 Dec 2019 08:22:31 -0800 (PST) X-Google-Smtp-Source: APXvYqwBH7GSubnRdr4pC+5zmPpAe9KwLWgQFA6F1CSxY8W07jmmRXD3vfqSxR4qIqsjGA6Y1D6b X-Received: by 2002:a9d:7f12:: with SMTP id j18mr22976790otq.17.1575908551673; Mon, 09 Dec 2019 08:22:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575908551; cv=none; d=google.com; s=arc-20160816; b=VCE9FIqofCTPcaCA1tBCp/2I/y42nFgwFeKVsBE1BO8gsODD3cztNYm5ZT1F5ClBYc 2SiVJ3VHTtXtFKZVWdDryY7AsH/PIwULvvDhFVgZ0+D81sCdWid5jkUZscCmfUZFPl0w foctSrF+amdWFVQ1he/h0C37XMDLczRVB60yRVIcPN/ptaSFZy//uibS3aNQgQIBK3bE f/BcVTtiq43Bj/bVa3zeVr+LQwwlRWj2p7wF1ox4oxfR6ZDjcciFiFLqM0DrCYtvOUwy mGJnisSzUZUIT5fn0DVT23OJf8CQakb71O/CEsvze7OqroP/euWGDfsZqZIcgstIaQ4P puFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=6Vt9YLldmDuHyHf+Z5P+YTHosd/Hr2dv4ZyxDYP1aBI=; b=FprnYdRaB4vVwT4j2VoIqIOpWDrw8c0Ilm6cm8LLGPfRUgw9Hi7vfJr7gl409MJwIT L03CSE6q0NCLEY9TzhEDTQURnCv8/pHe8V0/6csxuHhIntyT6jLoUpw7s4zMD80x6Ktq vM30dVpD/rdtyeP3gfpZMOWDdQ5KQjXRD6gTimVnG2UwgaHWfgGWJjjdSVolzhmXx7J6 3KpQBzAsCafuiA8zt2m3MgnSedPAvFB3mBVrkAWVh7vRxUg8Yg5mq8QS4KDwQB8khrVE amD3oCvRCV45bDBBVYmEGheONvtdU7vxoYNuKGSkF1YLeZy9S4vMmiuvheBbcvbpTULh JZLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Ml3Tkf+t; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l5si39555otr.255.2019.12.09.08.22.31; Mon, 09 Dec 2019 08:22:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Ml3Tkf+t; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726888AbfLIQWa (ORCPT + 8 others); Mon, 9 Dec 2019 11:22:30 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:42436 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726265AbfLIQWa (ORCPT ); Mon, 9 Dec 2019 11:22:30 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB9GMS3S028131; Mon, 9 Dec 2019 10:22:28 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575908548; bh=6Vt9YLldmDuHyHf+Z5P+YTHosd/Hr2dv4ZyxDYP1aBI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Ml3Tkf+tJYBperMGP/GzZGMiBbo30uoEAg+E7a5EVLY5Sywv66GM6NGiKc3+nCVd7 G0rr3VeDrTwf9whc1+u/Fy1hSWoABpc4vETAAXOPmJNu4vR5+HBJK6+03tQz182HNj nxKVHJs9BJ/ir5W57UUPmDgBXxpkXaDtJJPGSuKg= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB9GMSU1128399; Mon, 9 Dec 2019 10:22:28 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 10:22:27 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 10:22:27 -0600 Received: from jadmar.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB9GMP0t050201; Mon, 9 Dec 2019 10:22:25 -0600 From: Jyri Sarha To: , , CC: , , , , , Subject: [PATCH 3/3] phy: ti: j721e-wiz: Implement DisplayPort mode to the wiz driver Date: Mon, 9 Dec 2019 18:22:25 +0200 Message-ID: <8a8d070e1d8550dd0adc3f233bab18c074046089.1575906694.git.jsarha@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For DisplayPort use we need to set WIZ_CONFIG_LANECTL register's P_STANDARD_MODE bits to "mode 3". In the DisplayPort use also the P_ENABLE bits of the same register are set to P_ENABLE instead of P_ENABLE_FORCE, so that the DisplayPort driver can enable and disable the lane as needed. The DisplayPort mode is selected according to lane-mode -property. All other values of lane-mode -property but PHY_TYPE_DP will set P_STANDARD_MODE bits to 0 and P_ENABLE bits to force enable. Signed-off-by: Jyri Sarha --- drivers/phy/ti/phy-j721e-wiz.c | 55 +++++++++++++++++++++++++++++++--- 1 file changed, 51 insertions(+), 4 deletions(-) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index c74979655654..d2a38ea6d881 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -20,6 +20,7 @@ #include #include #include +#include #define WIZ_SERDES_CTRL 0x404 #define WIZ_SERDES_TOP_CTRL 0x408 @@ -78,6 +79,8 @@ static const struct reg_field p_enable[WIZ_MAX_LANES] = { REG_FIELD(WIZ_LANECTL(3), 30, 31), }; +enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 }; + static const struct reg_field p_align[WIZ_MAX_LANES] = { REG_FIELD(WIZ_LANECTL(0), 29, 29), REG_FIELD(WIZ_LANECTL(1), 29, 29), @@ -220,6 +223,7 @@ struct wiz { struct reset_controller_dev wiz_phy_reset_dev; struct gpio_desc *gpio_typec_dir; int typec_dir_delay; + u32 lane_modes[WIZ_MAX_LANES]; }; static int wiz_reset(struct wiz *wiz) @@ -242,12 +246,17 @@ static int wiz_reset(struct wiz *wiz) static int wiz_mode_select(struct wiz *wiz) { u32 num_lanes = wiz->num_lanes; + enum wiz_lane_standard_mode mode; int ret; int i; for (i = 0; i < num_lanes; i++) { - ret = regmap_field_write(wiz->p_standard_mode[i], - LANE_MODE_GEN4); + if (wiz->lane_modes[i] == PHY_TYPE_DP) + mode = LANE_MODE_GEN1; + else + mode = LANE_MODE_GEN4; + + ret = regmap_field_write(wiz->p_standard_mode[i], mode); if (ret) return ret; } @@ -713,7 +722,7 @@ static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, return ret; } - ret = regmap_field_write(wiz->p_enable[id - 1], false); + ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE); return ret; } @@ -740,7 +749,11 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, return ret; } - ret = regmap_field_write(wiz->p_enable[id - 1], true); + if (wiz->lane_modes[id - 1] == PHY_TYPE_DP) + ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); + else + ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); + return ret; } @@ -767,6 +780,33 @@ static const struct of_device_id wiz_id_table[] = { }; MODULE_DEVICE_TABLE(of, wiz_id_table); +static int wiz_get_lane_mode(struct device *dev, int lane_number, + u32 *lane_mode) +{ + char property_name[11]; /* 11 is length of "lane0-mode\0" */ + int ret; + + ret = snprintf(property_name, sizeof(property_name), "lane%u-mode", + lane_number); + + if (ret != 10) { /* 10 is length of "lane0-mode" */ + dev_err(dev, "%s: bad lane number %d (ret = %d)\n", + __func__, lane_number, ret); + return -ENOTSUPP; + } + + ret = of_property_read_u32(dev->of_node, property_name, lane_mode); + if (ret == -EINVAL) { + *lane_mode = PHY_NONE; + return 0; + } else if (ret) { + dev_err(dev, "Getting \"%s\" property failed: %d\n", + property_name, ret); + } + + return ret; +} + static int wiz_probe(struct platform_device *pdev) { struct reset_controller_dev *phy_reset_dev; @@ -780,6 +820,7 @@ static int wiz_probe(struct platform_device *pdev) struct wiz *wiz; u32 num_lanes; int ret; + int i; wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL); if (!wiz) @@ -850,6 +891,12 @@ static int wiz_probe(struct platform_device *pdev) } } + for (i = 0; i < num_lanes; i++) { + ret = wiz_get_lane_mode(dev, i, &wiz->lane_modes[i]); + if (ret) + return ret; + } + wiz->dev = dev; wiz->regmap = regmap; wiz->num_lanes = num_lanes;