From patchwork Mon Dec 9 17:59:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 181068 Delivered-To: patch@linaro.org Received: by 2002:ac9:44c4:0:0:0:0:0 with SMTP id t4csp4457948och; Mon, 9 Dec 2019 10:02:04 -0800 (PST) X-Google-Smtp-Source: APXvYqy0gboPA1bnpVue18uxh9StswM0U1mFjGC/B83YTjlhfv1W9oMdkoOGMrHWGx/dGV+bt5Z1 X-Received: by 2002:a9d:674f:: with SMTP id w15mr12836346otm.243.1575914524648; Mon, 09 Dec 2019 10:02:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575914524; cv=none; d=google.com; s=arc-20160816; b=JjxMxUAcUTAEBlEkkeljrNlwKjia7ILNyYCed30rNzdQqCnO8EuPS1KiKf2TRYhaIV n3VxfbAOaqkolsZTOx2G76b7zcy08IlAC20SnCmrYHsjStfYXt/Pzowmkh3hPkMbpxOT Coan2JLd2/1xax740R2SO9C52yRiTsp/HMiTo9+mQfeTjQlaktv16Pc/tJk2Pvjb6BOa 75AkRQNQM53gVW7CH5aF6F+rJuO1MrEvvmekXlT4t0+cw4iPKyAov1L5A/4VnOhAYVnw OlIMl5/sGHtMHIfi9tuoYrSiGkVhdKDhleNdpMNFvPvRz74V9FUtJtbcvUBqPLegwIvK 6flQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OSPe/QWwbGv5rEkM1GTgw52VUOMrBBQsY+i7pQwIszU=; b=Emb+omDtBSKgNeD2EKTY+uun0LCsO1zTOE2y7qc5dWY2JXYiStgTJ8PjIV7WoTwH3m Hp9imI7ds7G5V1hJTcif+7kweo15M0YmRVJUtbNiA3ro3I6H21c/RrOuT5rm1ne/cn/o zKtR3JwrhKlsuudYfZ0z+SHFnXCWxG5nHgo4kkk/kIOpfXnDYuftAeYdH/KpR+5ZX2lo qh5xwxjJuRaOvAOqSjoGiH1UXowsGyWIHTekR1edSpVj18kfi8cKhm/r5pjVWk0/C3lC Szs11sdimO3rNqVSmyLtWd/Mj040NSA+X50ztiRCnAgwhQsJTjzJyP8w0CYUDNW49Thd jrLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=n1xWiFs1; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o128si332264oih.66.2019.12.09.10.02.04; Mon, 09 Dec 2019 10:02:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=n1xWiFs1; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726771AbfLISCC (ORCPT + 9 others); Mon, 9 Dec 2019 13:02:02 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58666 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726822AbfLISCA (ORCPT ); Mon, 9 Dec 2019 13:02:00 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB9I1sEs119818; Mon, 9 Dec 2019 12:01:54 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575914514; bh=OSPe/QWwbGv5rEkM1GTgw52VUOMrBBQsY+i7pQwIszU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=n1xWiFs1sdZ74KT4nPfL/PFm+m/RMiEUqcowWrWy+CEMVWgF5fIyA7OnTW/HVFemv EqDGNcUyCSbRe6Wo3JIZ+Vio2AwoHp9gCeCFdyV9I/qzNVS7ge5q+KWZP2SuruVUTL MY3PtssLCSxG5PzmpTbD7sv01SC0RdgE2bRoSmh8= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB9I1sld024438; Mon, 9 Dec 2019 12:01:54 -0600 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 12:01:52 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 12:01:52 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB9I1qN7053053; Mon, 9 Dec 2019 12:01:52 -0600 From: Dan Murphy To: , , , CC: , , , , Dan Murphy Subject: [PATCH net-next v2 2/2] net: phy: dp83867: Add rx-fifo-depth and tx-fifo-depth Date: Mon, 9 Dec 2019 11:59:43 -0600 Message-ID: <20191209175943.23110-3-dmurphy@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191209175943.23110-1-dmurphy@ti.com> References: <20191209175943.23110-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This code changes the TI specific ti,fifo-depth to the common tx-fifo-depth property. The tx depth is applicable for both RGMII and SGMII modes of operation. rx-fifo-depth was added as well but this is only applicable for SGMII mode. So in summary if RGMII mode write tx fifo depth only if SGMII mode write both rx and tx fifo depths If the property is not populated in the device tree then set the value to the default values. Signed-off-by: Dan Murphy Reported-by: Adrian Bunk --- drivers/net/phy/dp83867.c | 62 +++++++++++++++++++++++++++++++-------- 1 file changed, 49 insertions(+), 13 deletions(-) -- 2.23.0 diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 9cd9dcee4eb2..adda0d0eab80 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -93,9 +93,11 @@ #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2) /* PHY CTRL bits */ -#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 +#define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14 +#define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12 #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03 -#define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14) +#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14) +#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) #define DP83867_PHYCR_RESERVED_MASK BIT(11) /* RGMIIDCTL bits */ @@ -131,7 +133,8 @@ enum { struct dp83867_private { u32 rx_id_delay; u32 tx_id_delay; - u32 fifo_depth; + u32 tx_fifo_depth; + u32 rx_fifo_depth; int io_impedance; int port_mirroring; bool rxctrl_strap_quirk; @@ -408,18 +411,32 @@ static int dp83867_of_init(struct phy_device *phydev) dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; ret = of_property_read_u32(of_node, "ti,fifo-depth", - &dp83867->fifo_depth); + &dp83867->tx_fifo_depth); if (ret) { - phydev_err(phydev, - "ti,fifo-depth property is required\n"); - return ret; + ret = of_property_read_u32(of_node, "tx-fifo-depth", + &dp83867->tx_fifo_depth); + if (ret) + dp83867->tx_fifo_depth = + DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; } - if (dp83867->fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { - phydev_err(phydev, - "ti,fifo-depth value %u out of range\n", - dp83867->fifo_depth); + + if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { + phydev_err(phydev, "tx-fifo-depth value %u out of range\n", + dp83867->tx_fifo_depth); + return -EINVAL; + } + + ret = of_property_read_u32(of_node, "rx-fifo-depth", + &dp83867->rx_fifo_depth); + if (ret) + dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; + + if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { + phydev_err(phydev, "rx-fifo-depth value %u out of range\n", + dp83867->rx_fifo_depth); return -EINVAL; } + return 0; } #else @@ -458,12 +475,31 @@ static int dp83867_config_init(struct phy_device *phydev) phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, BIT(7)); + if (phy_interface_is_rgmii(phydev) || + phydev->interface == PHY_INTERFACE_MODE_SGMII) { + val = phy_read(phydev, MII_DP83867_PHYCTRL); + if (val < 0) + return val; + + val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK; + val |= (dp83867->tx_fifo_depth << + DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT); + + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK; + val |= (dp83867->rx_fifo_depth << + DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT); + } + + ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); + if (ret) + return ret; + } + if (phy_interface_is_rgmii(phydev)) { val = phy_read(phydev, MII_DP83867_PHYCTRL); if (val < 0) return val; - val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK; - val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT); /* The code below checks if "port mirroring" N/A MODE4 has been * enabled during power on bootstrap.