From patchwork Thu Dec 12 12:51:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 181465 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp844242ile; Thu, 12 Dec 2019 04:51:41 -0800 (PST) X-Google-Smtp-Source: APXvYqwVl6ReDZeiqAzT243b3QPg2yGUl0CVb+xVX8dbWgKpHplgaLnJqL/7acnTXiwHwU/UApkS X-Received: by 2002:a9d:480c:: with SMTP id c12mr8397709otf.255.1576155101790; Thu, 12 Dec 2019 04:51:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576155101; cv=none; d=google.com; s=arc-20160816; b=yF5YJGStPmcHjEVlUMfFyBovQK5BLn2Asd/6WBAvr5sW/y4YCTT2WVtFh8ru3u77C6 Dj8/Xl3mP9/6kHAMm/rKcdQXi7dN7wPWRa7Beli3l93VGEQLCFdxVB40sfFYelkm0wne xC1LCEPRl7S5JNxl+X+FUQtcpDFIn3LUM/A6bNIvpPIsmKTzrz5XyvL45rPOZyN9iIh+ GxbiVfhOnjvJUHmfeejmoznSc02t+mvYTIj49pG1bEvBkVvdYBtTArwVOKoTXAmupB5j q734Jo3maQE3Dc06pC+9s5TRI/b9B1AQ2mUlqewfjChTe3tmyibOk29M6+o4Zou+6zbf aaBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=1Zg+C9+mOLS4pU15/CRjCfOGBrSNNhZJr+fi9fi9PEc=; b=V4ZZzdwQmMM5KhWJ816KBy7syMuPzWJlireSgn/9g6neus9Rp6AAefvJr++VbiNyov 4+oMyUELmUW70q4CQr+gxxCqtVZ/+866DJ2gI2EIhxq9rK78QLHCQS4MS0qDOvbBc1j/ Dwt1jMLZYWATqzXbgDhElWWhKa3pwVJ+V9ZBKRWt/L+bn/PrkoCfQ1AHoLNWXy5UYquF YTSfwp68FbQZoS08SGJ5aD3IjLIUyVFcqAV+OgpHXKHeG7yYhUoKOiO+vBwUjrykbUS5 Spzan5pvC/A+69iNdsyVT5edsf1ytQbpcsT45WiDHD++jJXGBd3gEUPz+KS7VXFMvfM/ YkHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FEP+6UEG; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l9si2788631otn.301.2019.12.12.04.51.41; Thu, 12 Dec 2019 04:51:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FEP+6UEG; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729270AbfLLMvl (ORCPT + 4 others); Thu, 12 Dec 2019 07:51:41 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:41510 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729207AbfLLMvk (ORCPT ); Thu, 12 Dec 2019 07:51:40 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBCCpb4T101330; Thu, 12 Dec 2019 06:51:37 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576155097; bh=1Zg+C9+mOLS4pU15/CRjCfOGBrSNNhZJr+fi9fi9PEc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FEP+6UEGwPYoZTCypmeMrbK24la76LvHpq1hk2yqtXQ8VPt8W16DGBsTM11rrJ7tK 7KwKD7F/SRotWMdKGOSZltCo/sXA/E7bW7XnAlv4dMWqBSZ/gYIhmMB1ei/2djZvj6 FL07v5STE0f5gY3W3Nbb1a7g0qfdvjmJnHpcnsVs= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBCCpbJ3017598; Thu, 12 Dec 2019 06:51:37 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 12 Dec 2019 06:51:36 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 12 Dec 2019 06:51:36 -0600 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBCCpWNd045158; Thu, 12 Dec 2019 06:51:34 -0600 From: Tero Kristo To: , CC: , Subject: [PATCH 1/6] ARM: dts: dra7: convert IOMMUs to use ti-sysc Date: Thu, 12 Dec 2019 14:51:18 +0200 Message-ID: <20191212125123.3465-2-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191212125123.3465-1-t-kristo@ti.com> References: <20191212125123.3465-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Convert dra7 IOMMUs to use ti-sysc instead of legacy omap-hwmod based implementation. Enable the IOMMUs also while doing this. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/dra7.dtsi | 140 +++++++++++++++++++++++++++--------- 1 file changed, 108 insertions(+), 32 deletions(-) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 73e5011f531a..e7c9b81d929a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -377,44 +377,120 @@ ti,hwmods = "dmm"; }; - mmu0_dsp1: mmu@40d01000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x40d01000 0x100>; - interrupts = ; - ti,hwmods = "mmu0_dsp1"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp1_system 0x0>; - status = "disabled"; + target-module@40d01000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x40d01000 0x4>, + <0x40d01010 0x4>, + <0x40d01014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_dsp1 1>; + reset-names = "rstctrl"; + ranges = <0x0 0x40d01000 0x1000>; + #size-cells = <1>; + #address-cells = <1>; + + mmu0_dsp1: mmu@0 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp1_system 0x0>; + }; }; - mmu1_dsp1: mmu@40d02000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x40d02000 0x100>; - interrupts = ; - ti,hwmods = "mmu1_dsp1"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp1_system 0x1>; - status = "disabled"; + target-module@40d02000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x40d02000 0x4>, + <0x40d02010 0x4>, + <0x40d02014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_dsp1 1>; + reset-names = "rstctrl"; + ranges = <0x0 0x40d02000 0x1000>; + #size-cells = <1>; + #address-cells = <1>; + + mmu1_dsp1: mmu@0 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp1_system 0x1>; + }; }; - mmu_ipu1: mmu@58882000 { - compatible = "ti,dra7-iommu"; - reg = <0x58882000 0x100>; - interrupts = ; - ti,hwmods = "mmu_ipu1"; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - status = "disabled"; + target-module@58882000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x58882000 0x4>, + <0x58882010 0x4>, + <0x58882014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_ipu 2>; + reset-names = "rstctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x58882000 0x100>; + + mmu_ipu1: mmu@0 { + compatible = "ti,dra7-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,iommu-bus-err-back; + }; }; - mmu_ipu2: mmu@55082000 { - compatible = "ti,dra7-iommu"; - reg = <0x55082000 0x100>; - interrupts = ; - ti,hwmods = "mmu_ipu2"; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - status = "disabled"; + target-module@55082000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x55082000 0x4>, + <0x55082010 0x4>, + <0x55082014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_core 2>; + reset-names = "rstctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x55082000 0x100>; + + mmu_ipu2: mmu@0 { + compatible = "ti,dra7-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,iommu-bus-err-back; + }; }; abb_mpu: regulator-abb-mpu { From patchwork Thu Dec 12 12:51:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 181470 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp844367ile; 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[209.132.180.67]) by mx.google.com with ESMTP id h139si2970746oib.85.2019.12.12.04.51.49; Thu, 12 Dec 2019 04:51:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fKpFC6z2; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729312AbfLLMvr (ORCPT + 4 others); Thu, 12 Dec 2019 07:51:47 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:49192 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729277AbfLLMvq (ORCPT ); Thu, 12 Dec 2019 07:51:46 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBCCphKT109106; Thu, 12 Dec 2019 06:51:43 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576155103; bh=tHnACjGUpLKjDtCnkDo4UB7UZhykwsles7vVS+FHhIs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fKpFC6z2kDLV4o0FItSvuWBMim9vGXCFrXSwW2anxh+ktV1xIKivy7nWE3ILWgNHk DNg4YhlEWW7vGpXr9dP4hcyd+r8VTamAD/VXx4g4ofQJ694ojO+94Fu7lr7C2Rfa7i dRcLuZdeXBno13CUcoaVlGPV58LiHi0rX7FMSQ00= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBCCphFN054482 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 12 Dec 2019 06:51:43 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 12 Dec 2019 06:51:43 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 12 Dec 2019 06:51:43 -0600 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBCCpWNi045158; Thu, 12 Dec 2019 06:51:42 -0600 From: Tero Kristo To: , CC: , Subject: [PATCH 6/6] ARM: OMAP5: hwmod-data: remove OMAP5 IOMMU hwmod data Date: Thu, 12 Dec 2019 14:51:23 +0200 Message-ID: <20191212125123.3465-7-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191212125123.3465-1-t-kristo@ti.com> References: <20191212125123.3465-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org IOMMUs are now supported via ti-sysc, so the legacy hwmod data can be removed. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 83 ---------------------- 1 file changed, 83 deletions(-) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index cc5ad6acab1d..e48b09c18144 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -677,71 +677,6 @@ static struct omap_hwmod omap54xx_mcpdm_hwmod = { }; -/* - * 'mmu' class - * The memory management unit performs virtual to physical address translation - * for its requestors. - */ - -static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap54xx_mmu_hwmod_class = { - .name = "mmu", - .sysc = &omap54xx_mmu_sysc, -}; - -static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = { - { .name = "mmu_cache", .rst_shift = 1 }, -}; - -static struct omap_hwmod omap54xx_mmu_dsp_hwmod = { - .name = "mmu_dsp", - .class = &omap54xx_mmu_hwmod_class, - .clkdm_name = "dsp_clkdm", - .rst_lines = omap54xx_mmu_dsp_resets, - .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_dsp_resets), - .main_clk = "dpll_iva_h11x2_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET, - .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET, - .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* mmu ipu */ -static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = { - { .name = "mmu_cache", .rst_shift = 2 }, -}; - -static struct omap_hwmod omap54xx_mmu_ipu_hwmod = { - .name = "mmu_ipu", - .class = &omap54xx_mmu_hwmod_class, - .clkdm_name = "ipu_clkdm", - .rst_lines = omap54xx_mmu_ipu_resets, - .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_ipu_resets), - .main_clk = "dpll_core_h22x2_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET, - .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET, - .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - /* * 'mpu' class * mpu sub-system @@ -1303,14 +1238,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_cfg -> mmu_dsp */ -static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = { - .master = &omap54xx_l4_cfg_hwmod, - .slave = &omap54xx_mmu_dsp_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* mpu -> l3_main_1 */ static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = { .master = &omap54xx_mpu_hwmod, @@ -1335,14 +1262,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l3_main_2 -> mmu_ipu */ -static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = { - .master = &omap54xx_l3_main_2_hwmod, - .slave = &omap54xx_mmu_ipu_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_1 -> l3_main_3 */ static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = { .master = &omap54xx_l3_main_1_hwmod, @@ -1675,7 +1594,6 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l4_wkup__counter_32k, &omap54xx_l4_cfg__dma_system, &omap54xx_l4_abe__dmic, - &omap54xx_l4_cfg__mmu_dsp, &omap54xx_l3_main_2__dss, &omap54xx_l3_main_2__dss_dispc, &omap54xx_l3_main_2__dss_dsi1_a, @@ -1684,7 +1602,6 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l3_main_2__dss_rfbi, &omap54xx_mpu__emif1, &omap54xx_mpu__emif2, - &omap54xx_l3_main_2__mmu_ipu, &omap54xx_l4_wkup__kbd, &omap54xx_l4_abe__mcpdm, &omap54xx_l4_cfg__mpu,