From patchwork Mon Dec 16 09:56:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181646 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4091173ile; Mon, 16 Dec 2019 01:56:08 -0800 (PST) X-Google-Smtp-Source: APXvYqwJ6FLaejXK0eunqgDAghbmS8NgDBJ9oau1lSDzka1mbWpNrbT5kpb8CIvQeJ6XtRFANns3 X-Received: by 2002:a9d:7a4d:: with SMTP id z13mr30848102otm.148.1576490168232; Mon, 16 Dec 2019 01:56:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576490168; cv=none; d=google.com; s=arc-20160816; b=DLYwS8btemG96fPDqvj4fzSIkcm0KFOubdSQkOZRcoPnlSrByaGuK79E5l/COx5CVB 4BYJ8+W+OQ7ikC1GIUdyub2nj3dAGnx+C0fk6XWpqBC2mEVRrd0UdaVs3XGqoA8+9P+i 4ILc05mgenYFu/yupWdHzik5cy/wkHRHrr9Y+GKuuH04+5pbiI6tIjwvQHImWj3+DLEV ux7pD6UkyZtxqsMbSkyo9UmvIMAU+66VW7rPXcHOF8EC/ODcU0ZHMqyF9VvcitXPIUQ4 15lhT3LhIRMkvRkmbeXysSDI4q2+XQSHEKWh9QvsCH9PCneftz+n3lXm+2UVKjadQYjK 4G1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=6fpvrXJ83jkqpt127njJSVIBYoo3/59w/XSU+W0RtjE=; b=yzr5/JCtldRan5ty29cC3uiZvuj1PuGD5kkUo7EXYngoCK3eDGWLK6xuPCch1yjZ4d ma7jfmP1tQ1ty7ybtyKhs61Q/Qpoquk7gYqeNX5OtDuifBWzhYG5jp8I1eSL9tk9yheE cPsj+h2on0UJ7A9atr7GopGwhOhe78GsHt4V8WywSY4WHrTOrW4tjlTudvBIWJaWahdu wbUbuYiBoahLLby/OQqkwN7lrA7wgNaEjWYfZBoY2JiR5r6LZCER3LZcv/EB6ZkjFit+ 8s5CDdLMtq+C4UBbY10FvtVGIGcHcKNQPlXbkVJc39tWOPA1sx/9UrXhSspDd6TvIj1x tMQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=NKlrK6FA; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l62si10206706oif.20.2019.12.16.01.56.08; Mon, 16 Dec 2019 01:56:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=NKlrK6FA; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727137AbfLPJ4H (ORCPT + 8 others); Mon, 16 Dec 2019 04:56:07 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:58728 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727121AbfLPJ4H (ORCPT ); Mon, 16 Dec 2019 04:56:07 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBG9u0Yx105981; Mon, 16 Dec 2019 03:56:00 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576490160; bh=6fpvrXJ83jkqpt127njJSVIBYoo3/59w/XSU+W0RtjE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NKlrK6FAlZIywRYsmE4sw/16bzggCzHeGDwwldI39Hdp7S90tAciZ/h6bu4/1rxNa RAz6bnpPEBZX+XHfhoYUI8V2Cc2UUIx2O0W+bMmZVEwv7e1CWuLDIrtbj4wEkeoEfR y2qcPmhmzNzlUyTM4+aq2e3p7s/niGMY1vT8bBis= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBG9u0fu048706 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 16 Dec 2019 03:56:00 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 16 Dec 2019 03:55:59 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 16 Dec 2019 03:55:59 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9tsJK084408; Mon, 16 Dec 2019 03:55:57 -0600 From: Kishon Vijay Abraham I To: Rob Herring , Anil Varughese , Roger Quadros , Jyri Sarha CC: , Kishon Vijay Abraham I , , Subject: [PATCH v4 01/14] dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E Date: Mon, 16 Dec 2019 15:26:59 +0530 Message-ID: <20191216095712.13266-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216095712.13266-1-kishon@ti.com> References: <20191216095712.13266-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT binding documentation for Sierra PHY IP used in TI's J721E SoC. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../devicetree/bindings/phy/phy-cadence-sierra.txt | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt index 6e1b47bfce43..03f5939d3d19 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt +++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt @@ -2,21 +2,24 @@ Cadence Sierra PHY ----------------------- Required properties: -- compatible: cdns,sierra-phy-t0 -- clocks: Must contain an entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must be "phy_clk" +- compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform + Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC. - resets: Must contain an entry for each in reset-names. See ../reset/reset.txt for details. - reset-names: Must include "sierra_reset" and "sierra_apb". "sierra_reset" must control the reset line to the PHY. "sierra_apb" must control the reset line to the APB PHY - interface. + interface ("sierra_apb" is optional). - reg: register range for the PHY. - #address-cells: Must be 1 - #size-cells: Must be 0 Optional properties: +- clocks: Must contain an entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must contain "cmn_refclk_dig_div" and + "cmn_refclk1_dig_div" for configuring the frequency of + the clock to the lanes. "phy_clk" is deprecated. - cdns,autoconf: A boolean property whose presence indicates that the PHY registers will be configured by hardware. If not present, all sub-node optional properties must be From patchwork Mon Dec 16 09:57:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181649 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4091251ile; Mon, 16 Dec 2019 01:56:16 -0800 (PST) X-Google-Smtp-Source: APXvYqx6OwtX8ID4/CfOhcQTxPlQfQ1ta3ZrKkudZt0llEMwHpiTURRxjEi1C0pxCrlKMiVNwWgv X-Received: by 2002:a05:6830:1e30:: with SMTP id t16mr31675528otr.220.1576490176312; Mon, 16 Dec 2019 01:56:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576490176; cv=none; d=google.com; s=arc-20160816; b=Nf8VUoU67LV+sw0ETY48Mo9wW8+hdxNJeN3SlfR8xydBUY+sTuufc/3xHhFcRpzsis BVvZGfDjagke5YAFjbQ2JDXozJwqgK8DZJmNlChM/+VuZq/sMsWKQ8VYh5cp6aHPi5UK CcshNWfZFMxwP9vdDZGw+eP6zNd/CZ9hdVtwjwAsbg4ALa8C9TS14qPKHbchjdYmY0Np q0wk1JVgjgTEVWzo0GEjWihmSwvBgUEJyhMfI9jFjZbyCgOsMqbOuIeLElFwMEQSsW/z q6G8pYGsxAjzZ6d/GvYhAa5q3QgxtAzvD+vScsHifb16iVia5K+6LRYf3nAzws1tZrpr J4Rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=agcoWtKSTenRqtUlTyzEyGcBRm6Q0+Ai3WNO3BmnFjE=; b=DEm0bV3ksNIGSvzBK4BzSlhiyUUrG/T3et3hEjXQ3IooeHgcsm1kGawPJ6KsNwwkXG 85lkhejHIETo5LfLvwLebw1BpoS9vEFH0drAae36+pAVusCGa1bKZ+8NsJXBwppkDb3r WLWOAW4CWFxY7kAomF0E5mJgU+OMrwjvRkNz5Jz4ZV49DGutc0Ac1nGu7nTLviRzaJuE P6J6uKoQxcwLUWd0ajJWRhYNDcju83vKZRxHMyIwcD9UT4RzA8bhNGGCSXgdHxQ/mCPG puEw58aN3wWCwUySus8Yhd9vny8k8DDFLJINqKQdlEXsFt7xz2jhqqpwX4og6H/K13wi oi5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Uof0ysU5; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 5si10879687oih.274.2019.12.16.01.56.16; Mon, 16 Dec 2019 01:56:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Uof0ysU5; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727216AbfLPJ4O (ORCPT + 8 others); Mon, 16 Dec 2019 04:56:14 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:58770 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727208AbfLPJ4N (ORCPT ); Mon, 16 Dec 2019 04:56:13 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBG9u9pX106061; Mon, 16 Dec 2019 03:56:09 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576490169; bh=agcoWtKSTenRqtUlTyzEyGcBRm6Q0+Ai3WNO3BmnFjE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Uof0ysU5TPzwfKG40Uzfy3oOgkL88X8NpP/HLWEBW8eX5P6633G6i12APh6fQHAbd z8bBNFxt7voDHW3fQZ893V5LxSwYsnRtUzZ8iTJu9FHILnbXGBhjd4hUNrlIVdo7j3 FzgfYHEUMNEBDWOfX19YnikN12XYjkD8GoHPylEo= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBG9u8Qt049177 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 16 Dec 2019 03:56:08 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 16 Dec 2019 03:56:08 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 16 Dec 2019 03:56:08 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9tsJN084408; Mon, 16 Dec 2019 03:56:06 -0600 From: Kishon Vijay Abraham I To: Rob Herring , Anil Varughese , Roger Quadros , Jyri Sarha CC: , Kishon Vijay Abraham I , , Subject: [PATCH v4 04/14] phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC Date: Mon, 16 Dec 2019 15:27:02 +0530 Message-ID: <20191216095712.13266-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216095712.13266-1-kishon@ti.com> References: <20191216095712.13266-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SERDES_16G in TI's J721E SoC uses Cadence Sierra PHY. Add support to use Cadence Sierra driver in J721E SoC. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index c60809f615af..d3b0dac2db77 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -553,11 +553,25 @@ static const struct cdns_sierra_data cdns_map_sierra = { cdns_usb_regs }; +static const struct cdns_sierra_data cdns_ti_map_sierra = { + SIERRA_MACRO_ID, + 0x0, + 0x1, + ARRAY_SIZE(cdns_pcie_regs), + ARRAY_SIZE(cdns_usb_regs), + cdns_pcie_regs, + cdns_usb_regs +}; + static const struct of_device_id cdns_sierra_id_table[] = { { .compatible = "cdns,sierra-phy-t0", .data = &cdns_map_sierra, }, + { + .compatible = "ti,sierra-phy-t0", + .data = &cdns_ti_map_sierra, + }, {} }; MODULE_DEVICE_TABLE(of, cdns_sierra_id_table); From patchwork Mon Dec 16 09:57:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181652 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4091405ile; Mon, 16 Dec 2019 01:56:28 -0800 (PST) X-Google-Smtp-Source: APXvYqyrc2t97sdfcETdRP9uboUrTrlN0cAmLtSjtmSlI0+G22LxbyqsybNfPm44u7DRxS7ydBYn X-Received: by 2002:a9d:7f12:: with SMTP id j18mr32005189otq.17.1576490188094; Mon, 16 Dec 2019 01:56:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576490188; cv=none; d=google.com; s=arc-20160816; b=t51gQcmul+jmsUX3H4WR7t7WglSYwlMtv5eD9GbDF0JIpmOTzJ5eJl9QPDoH0und6n HG7bcDOA7P6cm5UV5QAEzVSKjpEroSlL90velDpqTpfHSY0FJiYd8PmMVXOJ+nnxmYhU MRUNzggX0nlvLtjsVJ1ErWkmab+92fgC2B7HGy+D25u7B4ZMePc8grO6DipnXCj4o1Rk L/ZDxBKY23hH2BUp3Ys9eeN08hriyrNEn37SBPYI/XTgTeNSMjxUsVUHS6tKTqsPuUVD vlYMLlmAkJ92B6JSax4J3CpkKdq/W2EA6r5UC/Fy1dkH3k29kVDoiHHhGlxQ1q9CLDuy k+GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=wFhMbK0aKwv2VfpsctsKUnFfelTtACNb0m2S+vpm1lw=; b=TwQsMJTAVL3b0ZS1FNqSg9We+rC1DfFSr3zDlKii1uXoY7PBnaoscdMhvQjTL4Vc2o lpc42X4aXLD+up5x15p7vyIDBeJVrPlfMgJwbx07itzk72yK6U9Fu34sk9NfeMp3D+if dzhlyAbbJL6tlX2hjqpwTmUrhQ+XSli1iiIWOvONk5fAyy4WIzdY2SdRV1w/He2Fir6D E3er3tvrwYmz9SG4eHWa+weebo1/saLH1D/NqHAs9PWVp3P5ZM1G1xfPN/dNPsG3Vpnb 55HBvqilZp+7RpZq65+PMb2osc5dWtfr1mp4WBYFldaD1DhSTsVDibMwBaSujjP8we6C sAUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Nk4InlhQ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q26si9734870oij.38.2019.12.16.01.56.27; Mon, 16 Dec 2019 01:56:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Nk4InlhQ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727261AbfLPJ40 (ORCPT + 8 others); Mon, 16 Dec 2019 04:56:26 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:55226 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727296AbfLPJ4Z (ORCPT ); Mon, 16 Dec 2019 04:56:25 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBG9uH2Z038082; Mon, 16 Dec 2019 03:56:17 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576490177; bh=wFhMbK0aKwv2VfpsctsKUnFfelTtACNb0m2S+vpm1lw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Nk4InlhQFltYTEoVZG3VpS+dhiwWFK5VNSV8fAp+eguzS492xr+bV0LrtyBw4Kt2J 5cllS0IyIP2Xp3M56hztFdo4Kf+UF7ivJfWbZs7gDuMGmA3lsGLpp7wUYU8hoFgisK VkIG8LEjYulgdmEVFkXI0oC2gXVXcR5BAGkrcGVA= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBG9uHdv094675 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 16 Dec 2019 03:56:17 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 16 Dec 2019 03:56:17 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 16 Dec 2019 03:56:17 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9tsJQ084408; Mon, 16 Dec 2019 03:56:14 -0600 From: Kishon Vijay Abraham I To: Rob Herring , Anil Varughese , Roger Quadros , Jyri Sarha CC: , Kishon Vijay Abraham I , , Subject: [PATCH v4 07/14] phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC Date: Mon, 16 Dec 2019 15:27:05 +0530 Message-ID: <20191216095712.13266-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216095712.13266-1-kishon@ti.com> References: <20191216095712.13266-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Anil Varughese The existing configuration done in Cadence Sierra driver is only for reference and is not used in any platforms. Remove them and configure both lane cdb and common cdb registers to be used with external SSC configuration. This is validated in TI J721E platform. Signed-off-by: Anil Varughese Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 350 ++++++++++++++++------- 1 file changed, 254 insertions(+), 96 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index d490e1641cf9..fdca3bd178c6 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -22,58 +22,125 @@ #include /* PHY register offsets */ -#define SIERRA_COMMON_CDB_OFFSET 0x0 -#define SIERRA_MACRO_ID_REG 0x0 +#define SIERRA_COMMON_CDB_OFFSET 0x0 +#define SIERRA_MACRO_ID_REG 0x0 +#define SIERRA_CMN_PLLLC_MODE_PREG 0x48 +#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 +#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A +#define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B +#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F +#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 +#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ ((0x4000 << (block_offset)) + \ (((ln) << 9) << (reg_offset))) -#define SIERRA_DET_STANDEC_A_PREG 0x000 -#define SIERRA_DET_STANDEC_B_PREG 0x001 -#define SIERRA_DET_STANDEC_C_PREG 0x002 -#define SIERRA_DET_STANDEC_D_PREG 0x003 -#define SIERRA_DET_STANDEC_E_PREG 0x004 -#define SIERRA_PSM_LANECAL_PREG 0x008 -#define SIERRA_PSM_DIAG_PREG 0x015 -#define SIERRA_PSC_TX_A0_PREG 0x028 -#define SIERRA_PSC_TX_A1_PREG 0x029 -#define SIERRA_PSC_TX_A2_PREG 0x02A -#define SIERRA_PSC_TX_A3_PREG 0x02B -#define SIERRA_PSC_RX_A0_PREG 0x030 -#define SIERRA_PSC_RX_A1_PREG 0x031 -#define SIERRA_PSC_RX_A2_PREG 0x032 -#define SIERRA_PSC_RX_A3_PREG 0x033 -#define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A -#define SIERRA_PLLCTRL_GEN_D_PREG 0x03E -#define SIERRA_DRVCTRL_ATTEN_PREG 0x06A -#define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 -#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 -#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 -#define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E -#define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 -#define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 -#define SIERRA_CTLELUT_CTRL_PREG 0x098 -#define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 -#define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 -#define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 -#define SIERRA_TMRVAL_MODE3_PREG 0x16E -#define SIERRA_TMRVAL_MODE2_PREG 0x16F -#define SIERRA_TMRVAL_MODE1_PREG 0x170 -#define SIERRA_TMRVAL_MODE0_PREG 0x171 -#define SIERRA_PICNT_MODE1_PREG 0x174 -#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C -#define SIERRA_LFPSFILT_NS_PREG 0x18A -#define SIERRA_LFPSFILT_RD_PREG 0x18B -#define SIERRA_LFPSFILT_MP_PREG 0x18C -#define SIERRA_SDFILT_H2L_A_PREG 0x191 +#define SIERRA_DET_STANDEC_A_PREG 0x000 +#define SIERRA_DET_STANDEC_B_PREG 0x001 +#define SIERRA_DET_STANDEC_C_PREG 0x002 +#define SIERRA_DET_STANDEC_D_PREG 0x003 +#define SIERRA_DET_STANDEC_E_PREG 0x004 +#define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008 +#define SIERRA_PSM_A0IN_TMR_PREG 0x009 +#define SIERRA_PSM_DIAG_PREG 0x015 +#define SIERRA_PSC_TX_A0_PREG 0x028 +#define SIERRA_PSC_TX_A1_PREG 0x029 +#define SIERRA_PSC_TX_A2_PREG 0x02A +#define SIERRA_PSC_TX_A3_PREG 0x02B +#define SIERRA_PSC_RX_A0_PREG 0x030 +#define SIERRA_PSC_RX_A1_PREG 0x031 +#define SIERRA_PSC_RX_A2_PREG 0x032 +#define SIERRA_PSC_RX_A3_PREG 0x033 +#define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A +#define SIERRA_PLLCTRL_GEN_D_PREG 0x03E +#define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F +#define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B +#define SIERRA_DFE_BIASTRIM_PREG 0x04C +#define SIERRA_DRVCTRL_ATTEN_PREG 0x06A +#define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 +#define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085 +#define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086 +#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 +#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 +#define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E +#define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 +#define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 +#define SIERRA_CREQ_EQ_CTRL_PREG 0x093 +#define SIERRA_CREQ_SPARE_PREG 0x096 +#define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097 +#define SIERRA_CTLELUT_CTRL_PREG 0x098 +#define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 +#define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 +#define SIERRA_DEQ_PHALIGN_CTRL 0x0C4 +#define SIERRA_DEQ_CONCUR_CTRL1_PREG 0x0C8 +#define SIERRA_DEQ_CONCUR_CTRL2_PREG 0x0C9 +#define SIERRA_DEQ_EPIPWR_CTRL2_PREG 0x0CD +#define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG 0x0CE +#define SIERRA_DEQ_ERRCMP_CTRL_PREG 0x0D0 +#define SIERRA_DEQ_OFFSET_CTRL_PREG 0x0D8 +#define SIERRA_DEQ_GAIN_CTRL_PREG 0x0E0 +#define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 +#define SIERRA_DEQ_GLUT0 0x0E8 +#define SIERRA_DEQ_GLUT1 0x0E9 +#define SIERRA_DEQ_GLUT2 0x0EA +#define SIERRA_DEQ_GLUT3 0x0EB +#define SIERRA_DEQ_GLUT4 0x0EC +#define SIERRA_DEQ_GLUT5 0x0ED +#define SIERRA_DEQ_GLUT6 0x0EE +#define SIERRA_DEQ_GLUT7 0x0EF +#define SIERRA_DEQ_GLUT8 0x0F0 +#define SIERRA_DEQ_GLUT9 0x0F1 +#define SIERRA_DEQ_GLUT10 0x0F2 +#define SIERRA_DEQ_GLUT11 0x0F3 +#define SIERRA_DEQ_GLUT12 0x0F4 +#define SIERRA_DEQ_GLUT13 0x0F5 +#define SIERRA_DEQ_GLUT14 0x0F6 +#define SIERRA_DEQ_GLUT15 0x0F7 +#define SIERRA_DEQ_GLUT16 0x0F8 +#define SIERRA_DEQ_ALUT0 0x108 +#define SIERRA_DEQ_ALUT1 0x109 +#define SIERRA_DEQ_ALUT2 0x10A +#define SIERRA_DEQ_ALUT3 0x10B +#define SIERRA_DEQ_ALUT4 0x10C +#define SIERRA_DEQ_ALUT5 0x10D +#define SIERRA_DEQ_ALUT6 0x10E +#define SIERRA_DEQ_ALUT7 0x10F +#define SIERRA_DEQ_ALUT8 0x110 +#define SIERRA_DEQ_ALUT9 0x111 +#define SIERRA_DEQ_ALUT10 0x112 +#define SIERRA_DEQ_ALUT11 0x113 +#define SIERRA_DEQ_ALUT12 0x114 +#define SIERRA_DEQ_ALUT13 0x115 +#define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128 +#define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134 +#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 +#define SIERRA_DEQ_TAU_CTRL2_PREG 0x151 +#define SIERRA_DEQ_PICTRL_PREG 0x161 +#define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170 +#define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171 +#define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174 +#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C +#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183 +#define SIERRA_LFPSDET_SUPPORT_PREG 0x188 +#define SIERRA_LFPSFILT_NS_PREG 0x18A +#define SIERRA_LFPSFILT_RD_PREG 0x18B +#define SIERRA_LFPSFILT_MP_PREG 0x18C +#define SIERRA_SIGDET_SUPPORT_PREG 0x190 +#define SIERRA_SDFILT_H2L_A_PREG 0x191 +#define SIERRA_SDFILT_L2H_PREG 0x193 +#define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E +#define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F +#define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0 +#define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F +#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 #define SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset) \ (0xc000 << (block_offset)) -#define SIERRA_PHY_PLL_CFG 0xe +#define SIERRA_PHY_PLL_CFG 0xe -#define SIERRA_MACRO_ID 0x00007364 -#define SIERRA_MAX_LANES 4 +#define SIERRA_MACRO_ID 0x00007364 +#define SIERRA_MAX_LANES 4 static const struct reg_field macro_id_type = REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); @@ -97,10 +164,14 @@ struct cdns_sierra_data { u32 id_value; u8 block_offset_shift; u8 reg_offset_shift; - u32 pcie_regs; - u32 usb_regs; - struct cdns_reg_pairs *pcie_vals; - struct cdns_reg_pairs *usb_vals; + u32 pcie_cmn_regs; + u32 pcie_ln_regs; + u32 usb_cmn_regs; + u32 usb_ln_regs; + struct cdns_reg_pairs *pcie_cmn_vals; + struct cdns_reg_pairs *pcie_ln_vals; + struct cdns_reg_pairs *usb_cmn_vals; + struct cdns_reg_pairs *usb_ln_vals; }; struct cdns_regmap_cdb_context { @@ -183,26 +254,35 @@ static int cdns_sierra_phy_init(struct phy *gphy) struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent); struct regmap *regmap = phy->regmap; int i, j; - struct cdns_reg_pairs *vals; - u32 num_regs; + struct cdns_reg_pairs *cmn_vals, *ln_vals; + u32 num_cmn_regs, num_ln_regs; /* Initialise the PHY registers, unless auto configured */ if (phy->autoconf) return 0; if (ins->phy_type == PHY_TYPE_PCIE) { - num_regs = phy->init_data->pcie_regs; - vals = phy->init_data->pcie_vals; + num_cmn_regs = phy->init_data->pcie_cmn_regs; + num_ln_regs = phy->init_data->pcie_ln_regs; + cmn_vals = phy->init_data->pcie_cmn_vals; + ln_vals = phy->init_data->pcie_ln_vals; } else if (ins->phy_type == PHY_TYPE_USB3) { - num_regs = phy->init_data->usb_regs; - vals = phy->init_data->usb_vals; + num_cmn_regs = phy->init_data->usb_cmn_regs; + num_ln_regs = phy->init_data->usb_ln_regs; + cmn_vals = phy->init_data->usb_cmn_vals; + ln_vals = phy->init_data->usb_ln_vals; } else { return -EINVAL; } + + regmap = phy->regmap_common_cdb; + for (j = 0; j < num_cmn_regs ; j++) + regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val); + for (i = 0; i < ins->num_lanes; i++) { - for (j = 0; j < num_regs ; j++) { + for (j = 0; j < num_ln_regs ; j++) { regmap = phy->regmap_lane_cdb[i + ins->mlane]; - regmap_write(regmap, vals[j].off, vals[j].val); + regmap_write(regmap, ln_vals[j].off, ln_vals[j].val); } } @@ -491,80 +571,158 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) return 0; } -static struct cdns_reg_pairs cdns_usb_regs[] = { - /* - * Write USB configuration parameters to the PHY. - * These values are specific to this specific hardware - * configuration. - */ +/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ +static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { + {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, + {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, + {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, + {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, + {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} +}; + +/* refclk100MHz_32b_PCIe_ln_ext_ssc */ +static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { + {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, + {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, + {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, + {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, + {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, + {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, + {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG} +}; + +/* refclk100MHz_20b_USB_cmn_pll_ext_ssc */ +static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { + {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, + {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, + {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, + {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} +}; + +/* refclk100MHz_20b_USB_ln_ext_ssc */ +static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = { {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, {0x000F, SIERRA_DET_STANDEC_B_PREG}, - {0x55A5, SIERRA_DET_STANDEC_C_PREG}, - {0x69AD, SIERRA_DET_STANDEC_D_PREG}, + {0x00A5, SIERRA_DET_STANDEC_C_PREG}, + {0x69ad, SIERRA_DET_STANDEC_D_PREG}, {0x0241, SIERRA_DET_STANDEC_E_PREG}, - {0x0110, SIERRA_PSM_LANECAL_PREG}, + {0x0010, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG}, + {0x0014, SIERRA_PSM_A0IN_TMR_PREG}, {0xCF00, SIERRA_PSM_DIAG_PREG}, {0x001F, SIERRA_PSC_TX_A0_PREG}, {0x0007, SIERRA_PSC_TX_A1_PREG}, {0x0003, SIERRA_PSC_TX_A2_PREG}, {0x0003, SIERRA_PSC_TX_A3_PREG}, {0x0FFF, SIERRA_PSC_RX_A0_PREG}, - {0x0003, SIERRA_PSC_RX_A1_PREG}, + {0x0619, SIERRA_PSC_RX_A1_PREG}, {0x0003, SIERRA_PSC_RX_A2_PREG}, {0x0001, SIERRA_PSC_RX_A3_PREG}, {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, + {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, + {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG}, + {0x2512, SIERRA_DFE_BIASTRIM_PREG}, {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, - {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG}, - {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, - {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, + {0x873E, SIERRA_CLKPATHCTRL_TMR_PREG}, + {0x03CF, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, + {0x01CE, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, - {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, + {0x033F, SIERRA_RX_CTLE_MAINTENANCE_PREG}, {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, - {0x8452, SIERRA_CTLELUT_CTRL_PREG}, - {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG}, - {0x4121, SIERRA_DFE_SMP_RATESEL_PREG}, - {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG}, - {0x0330, SIERRA_TMRVAL_MODE0_PREG}, - {0x01FF, SIERRA_PICNT_MODE1_PREG}, + {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, + {0x8000, SIERRA_CREQ_SPARE_PREG}, + {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, + {0x8453, SIERRA_CTLELUT_CTRL_PREG}, + {0x4110, SIERRA_DFE_ECMP_RATESEL_PREG}, + {0x4110, SIERRA_DFE_SMP_RATESEL_PREG}, + {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, + {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG}, + {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG}, + {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, + {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, + {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG}, + {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG}, + {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG}, + {0x9A8A, SIERRA_DEQ_VGATUNE_CTRL_PREG}, + {0x0014, SIERRA_DEQ_GLUT0}, + {0x0014, SIERRA_DEQ_GLUT1}, + {0x0014, SIERRA_DEQ_GLUT2}, + {0x0014, SIERRA_DEQ_GLUT3}, + {0x0014, SIERRA_DEQ_GLUT4}, + {0x0014, SIERRA_DEQ_GLUT5}, + {0x0014, SIERRA_DEQ_GLUT6}, + {0x0014, SIERRA_DEQ_GLUT7}, + {0x0014, SIERRA_DEQ_GLUT8}, + {0x0014, SIERRA_DEQ_GLUT9}, + {0x0014, SIERRA_DEQ_GLUT10}, + {0x0014, SIERRA_DEQ_GLUT11}, + {0x0014, SIERRA_DEQ_GLUT12}, + {0x0014, SIERRA_DEQ_GLUT13}, + {0x0014, SIERRA_DEQ_GLUT14}, + {0x0014, SIERRA_DEQ_GLUT15}, + {0x0014, SIERRA_DEQ_GLUT16}, + {0x0BAE, SIERRA_DEQ_ALUT0}, + {0x0AEB, SIERRA_DEQ_ALUT1}, + {0x0A28, SIERRA_DEQ_ALUT2}, + {0x0965, SIERRA_DEQ_ALUT3}, + {0x08A2, SIERRA_DEQ_ALUT4}, + {0x07DF, SIERRA_DEQ_ALUT5}, + {0x071C, SIERRA_DEQ_ALUT6}, + {0x0659, SIERRA_DEQ_ALUT7}, + {0x0596, SIERRA_DEQ_ALUT8}, + {0x0514, SIERRA_DEQ_ALUT9}, + {0x0492, SIERRA_DEQ_ALUT10}, + {0x0410, SIERRA_DEQ_ALUT11}, + {0x038E, SIERRA_DEQ_ALUT12}, + {0x030C, SIERRA_DEQ_ALUT13}, + {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG}, + {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG}, + {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, + {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, + {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG}, + {0x0033, SIERRA_DEQ_PICTRL_PREG}, + {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG}, + {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, + {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG}, {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, + {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, + {0x0005, SIERRA_LFPSDET_SUPPORT_PREG}, {0x000F, SIERRA_LFPSFILT_NS_PREG}, {0x0009, SIERRA_LFPSFILT_RD_PREG}, {0x0001, SIERRA_LFPSFILT_MP_PREG}, {0x8013, SIERRA_SDFILT_H2L_A_PREG}, - {0x0400, SIERRA_TMRVAL_MODE1_PREG}, -}; - -static struct cdns_reg_pairs cdns_pcie_regs[] = { - /* - * Write PCIe configuration parameters to the PHY. - * These values are specific to this specific hardware - * configuration. - */ - {0x891f, SIERRA_DET_STANDEC_D_PREG}, - {0x0053, SIERRA_DET_STANDEC_E_PREG}, - {0x0400, SIERRA_TMRVAL_MODE2_PREG}, - {0x0200, SIERRA_TMRVAL_MODE3_PREG}, + {0x8009, SIERRA_SDFILT_L2H_PREG}, + {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG}, + {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG}, + {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG} }; static const struct cdns_sierra_data cdns_map_sierra = { SIERRA_MACRO_ID, 0x2, 0x2, - ARRAY_SIZE(cdns_pcie_regs), - ARRAY_SIZE(cdns_usb_regs), - cdns_pcie_regs, - cdns_usb_regs + ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), + ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), + ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), + ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), + cdns_pcie_cmn_regs_ext_ssc, + cdns_pcie_ln_regs_ext_ssc, + cdns_usb_cmn_regs_ext_ssc, + cdns_usb_ln_regs_ext_ssc, }; static const struct cdns_sierra_data cdns_ti_map_sierra = { SIERRA_MACRO_ID, 0x0, 0x1, - ARRAY_SIZE(cdns_pcie_regs), - ARRAY_SIZE(cdns_usb_regs), - cdns_pcie_regs, - cdns_usb_regs + ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), + ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), + ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), + ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), + cdns_pcie_cmn_regs_ext_ssc, + cdns_pcie_ln_regs_ext_ssc, + cdns_usb_cmn_regs_ext_ssc, + cdns_usb_ln_regs_ext_ssc, }; static const struct of_device_id cdns_sierra_id_table[] = { From patchwork Mon Dec 16 09:57:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181653 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4091419ile; Mon, 16 Dec 2019 01:56:29 -0800 (PST) X-Google-Smtp-Source: APXvYqzrWRtmwOHFjqIH+YXXETFT8wh6VS25OQCFgrpDOtEDk7Ywp5Avq+3nIn0Rsakx65lbvuZN X-Received: by 2002:a05:6830:1582:: with SMTP id i2mr32096146otr.50.1576490189345; Mon, 16 Dec 2019 01:56:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576490189; cv=none; d=google.com; s=arc-20160816; b=psZZauenIJkyoBgGgBE3o+stSH6GW48NHjGRhyT+99wlPZZlUfbJB+WUADEZk+xrn6 KiAcYXPzzqj5c3A6eduzO/nUz31RVg0CwCH55Fs55hMvZKc+lzlyzERRz4f/6MEV1VTR PPmDsmhxwLiZMxm8FdY3uzGYQq9NXeEuZM5EBKMX7WxAsKUoAURqbOwIq9b5yOQdNPUD yrIay7dVwP7ElM4xRM1Cg5Jw8XbEqTfFZQuzH0iABa/JcgNUWAxqn6xZ/QP4kcLlJ9md KB1BNsoMgizpDl6GoNxxdCOQinI4nbR6t1rJHz82479mGatpgZWTsom9Y9D8Qs63zb8v yZ/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id q26si9734870oij.38.2019.12.16.01.56.29; Mon, 16 Dec 2019 01:56:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="rsjkF7M/"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727322AbfLPJ42 (ORCPT + 8 others); Mon, 16 Dec 2019 04:56:28 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:58798 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727315AbfLPJ41 (ORCPT ); Mon, 16 Dec 2019 04:56:27 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBG9uKJU106107; Mon, 16 Dec 2019 03:56:20 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576490180; bh=xsoCMaeYo5YfhzTn+vSlcz0XqN7p8MMRE1rbf+zv3po=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rsjkF7M/pzDNnWelB/P5Q1MKmcM3KGAZf5b8hrsLGRX4QfYrJrDFj5fBBymqnIMhT agdEQrDu6x0RAfqLxL1lizv1X5YqPDVeA/VuH4pbq5ByztbEe5qExDArj5uJH/U5r1 lrFktN5cmqmuE/m9cwF6Nfpg4vfz7mqbatyil4Po= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBG9uKbt049441 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 16 Dec 2019 03:56:20 -0600 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 16 Dec 2019 03:56:19 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 16 Dec 2019 03:56:19 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9tsJR084408; Mon, 16 Dec 2019 03:56:17 -0600 From: Kishon Vijay Abraham I To: Rob Herring , Anil Varughese , Roger Quadros , Jyri Sarha CC: , Kishon Vijay Abraham I , , Subject: [PATCH v4 08/14] phy: cadence: Sierra: Get reset control "array" for each link Date: Mon, 16 Dec 2019 15:27:06 +0530 Message-ID: <20191216095712.13266-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216095712.13266-1-kishon@ti.com> References: <20191216095712.13266-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org A link may have multiple lanes each with a separate reset. Get reset control "array" in order to reset all the lanes associated with the link. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index fdca3bd178c6..497c83827670 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -499,7 +499,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) struct phy *gphy; sp->phys[node].lnk_rst = - of_reset_control_get_exclusive_by_index(child, 0); + of_reset_control_array_get_exclusive(child); if (IS_ERR(sp->phys[node].lnk_rst)) { dev_err(dev, "failed to get reset %s\n", From patchwork Mon Dec 16 09:57:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181655 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4091546ile; Mon, 16 Dec 2019 01:56:39 -0800 (PST) X-Google-Smtp-Source: APXvYqybipmpZ7/XIE8cxtDiqnD63ZqltSUmJI1xwkYpQmSIxZeFA2SULF+H5I+OLgs80aa+Awfx X-Received: by 2002:a9d:74c4:: with SMTP id a4mr31820757otl.119.1576490198938; Mon, 16 Dec 2019 01:56:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576490198; cv=none; d=google.com; s=arc-20160816; b=z53sk3/KbjwH8Grh4zS2pWBp1ixFnAcNreMfK0yrvT6jWFRI1Vp00G8a0rmZF9gTVH ntpyhvY6I4Pds9LDPEMEJvw0y/JhNiu1vgoJIy2FEHGcpDWD1WFY6bjDfKoDz0FQSQQ/ L4s2BMZdl4z4SY2kwscr/7tPKpjmkgnCJllnQyLvjUTTM3x5rLdc2Q/R59og9da+/aSs fQWCjwY2PcW7V2YlSRrDMrlQAkhXWnWcH0FdsPRlpbbfb2263y0dn2djTP3JBO4sTr3+ SftnDIUsU/LydEl67xnySuIWMeSZ1EotY5RpJdHoDEzpxRx1JTNBgCxvdt/+yWNlsSbJ EC/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Zekc0AXiObZrPPvegTp4K5GUPS8IXJOxaEdMQ6wwWA0=; b=IgJ7/Hq7BXBcmxPBynasa5tgHvb90v507gY8mk6I3S2izsYM47p0UIElCF5vIdJCdn wPDhrKmxNa73eTKXYSArziEMQttuKgdUM+kr7XrUj5SpsQX3s5u02gxpb30/y4Vw6z29 EdMvBantS0h52FVNfmRUC3jXIlvDDkyxM3sQOKUs4lM4IXXIADJQHKmvhK8MQH7AhrP3 lP4PpjboiaOObtSPSt0WKHp6Osbc5bBzMKf99QxQw+ANWuiLiihPbrWa7hY2aILPNPyT 5V6sYyqtkWnfRgewHVqb+mnQF4Cvwi1KVEDLOfJbYFmHMyxb/HXQpI38ADYEy+3/AD/s qy4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=svry36Y9; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 16si182647ois.140.2019.12.16.01.56.38; Mon, 16 Dec 2019 01:56:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=svry36Y9; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727381AbfLPJ4h (ORCPT + 8 others); Mon, 16 Dec 2019 04:56:37 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:58806 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727333AbfLPJ43 (ORCPT ); Mon, 16 Dec 2019 04:56:29 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBG9uNvB106117; Mon, 16 Dec 2019 03:56:23 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576490183; bh=Zekc0AXiObZrPPvegTp4K5GUPS8IXJOxaEdMQ6wwWA0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=svry36Y9SEy5nqCBDS949P2MxIkwOQjKA3MD3JzF9M4taTFldpbTbhILGa09CT9sD u2TbCA8zg2rBfLuAys6/0p/HVhwqh/Pp9OCvfEnovIVd+gOSj7Gapwprait5EZY7aQ Z4MhrxKxE550fy7nOBCzMy53CA67gUtLgBNPT3JE= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBG9uN4V094791 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 16 Dec 2019 03:56:23 -0600 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 16 Dec 2019 03:56:22 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 16 Dec 2019 03:56:22 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9tsJS084408; Mon, 16 Dec 2019 03:56:20 -0600 From: Kishon Vijay Abraham I To: Rob Herring , Anil Varughese , Roger Quadros , Jyri Sarha CC: , Kishon Vijay Abraham I , , Subject: [PATCH v4 09/14] phy: cadence: Sierra: Check for PLL lock during PHY power on Date: Mon, 16 Dec 2019 15:27:07 +0530 Message-ID: <20191216095712.13266-10-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216095712.13266-1-kishon@ti.com> References: <20191216095712.13266-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Check for PLL lock during PHY power on. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 33 +++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 497c83827670..62bff4b043f0 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -55,6 +55,7 @@ #define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A #define SIERRA_PLLCTRL_GEN_D_PREG 0x03E #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F +#define SIERRA_PLLCTRL_STATUS_PREG 0x044 #define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B #define SIERRA_DFE_BIASTRIM_PREG 0x04C #define SIERRA_DRVCTRL_ATTEN_PREG 0x06A @@ -141,11 +142,14 @@ #define SIERRA_MACRO_ID 0x00007364 #define SIERRA_MAX_LANES 4 +#define PLL_LOCK_TIME 100000 static const struct reg_field macro_id_type = REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); static const struct reg_field phy_pll_cfg_1 = REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1); +static const struct reg_field pllctrl_lock = + REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); struct cdns_sierra_inst { struct phy *phy; @@ -192,6 +196,7 @@ struct cdns_sierra_phy { struct regmap *regmap_common_cdb; struct regmap_field *macro_id_type; struct regmap_field *phy_pll_cfg_1; + struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; struct clk *clk; int nsubnodes; bool autoconf; @@ -291,10 +296,25 @@ static int cdns_sierra_phy_init(struct phy *gphy) static int cdns_sierra_phy_on(struct phy *gphy) { + struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent); struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); + struct device *dev = sp->dev; + u32 val; + int ret; /* Take the PHY lane group out of reset */ - return reset_control_deassert(ins->lnk_rst); + ret = reset_control_deassert(ins->lnk_rst); + if (ret) { + dev_err(dev, "Failed to take the PHY lane out of reset\n"); + return ret; + } + + ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane], + val, val, 1000, PLL_LOCK_TIME); + if (ret < 0) + dev_err(dev, "PLL lock of lane failed\n"); + + return ret; } static int cdns_sierra_phy_off(struct phy *gphy) @@ -350,6 +370,7 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp) struct device *dev = sp->dev; struct regmap_field *field; struct regmap *regmap; + int i; regmap = sp->regmap_common_cdb; field = devm_regmap_field_alloc(dev, regmap, macro_id_type); @@ -367,6 +388,16 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp) } sp->phy_pll_cfg_1 = field; + for (i = 0; i < SIERRA_MAX_LANES; i++) { + regmap = sp->regmap_lane_cdb[i]; + field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock); + if (IS_ERR(field)) { + dev_err(dev, "P%d_ENABLE reg field init failed\n", i); + return PTR_ERR(field); + } + sp->pllctrl_lock[i] = field; + } + return 0; } From patchwork Mon Dec 16 09:57:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181654 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4091481ile; Mon, 16 Dec 2019 01:56:34 -0800 (PST) X-Google-Smtp-Source: APXvYqwD3CIAGdM1z8uLBPgkjozocbFs+btW3bjJmFCDTSFmcsFH7eftemjjxNSrYdtt2nQHGtzk X-Received: by 2002:a05:6830:1e5c:: with SMTP id e28mr31624994otj.293.1576490193984; Mon, 16 Dec 2019 01:56:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576490193; cv=none; d=google.com; s=arc-20160816; b=I88QgOqrs3HuMuLHN0g1TIV7wXsAQZvSyGtAvuv2EV024GZWa+R/T7TuvEOXbquQ0u Q1pP5YFnYVBO0ouSs6Y+L5eyhpN5KT/Jz+z3P3mAlzsmiY6AyuwjxKGPS9tYE2WaAlhL fi0ll8cgRsVXnblMqBtaTpaGv8PYSNgP4pHOXQasN9E/USOfH1Y+Cn+1T7tcEfUXa41Q dK/URbUPmPshX+9YU6vA+tyrVXi+ABFGFVJZkdPnRn99RzGwYeUs3PANflXktytxAUm+ kT3sB7TBv2OpI7/ew4boA/uopns23jikgr26TRB8z+6gbzR493te+dd0wOXT5Tvgd9WA ofew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=uk33OX2/IRV4qk5zeJOpsDKsk+aZEVFfOmbpkxiarpY=; b=v1Z6cY4RtiAlAg6UzK2Dal4IGL9BydP8lXxKT7XKifsFoGVmGzeZe0K4cXRqc9fX87 b0JSVQvuIIEeJwPh97UL9hKTVkNwkPkIXw+e3PiLLpVis/WC1sy9CNXEjEXkMvYSCgCs 3mnVW36cdfvO2JgtS2Jgfik4LCNi7Dsn/Gp3iokgnjS5MtDhBR+xhWAuUlYuUntc32hU gqowxFl7KKTjK8ELS8c0Vg1cSRdyQuBSL9j7fdpKZ3vQ/LPG0L6Lh+ZO2BRlXfZR7G/N vAzbZILRm5478K8593eMvddXJgHqNWq3TFU7vyhhHTQC9PrHYh69cw2PagUOVM++hZu/ 6jLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Uo5l031V; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l8si10062709oii.249.2019.12.16.01.56.33; Mon, 16 Dec 2019 01:56:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Uo5l031V; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727315AbfLPJ4c (ORCPT + 8 others); Mon, 16 Dec 2019 04:56:32 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:58812 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727354AbfLPJ4c (ORCPT ); Mon, 16 Dec 2019 04:56:32 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBG9uPeO106127; Mon, 16 Dec 2019 03:56:25 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576490185; bh=uk33OX2/IRV4qk5zeJOpsDKsk+aZEVFfOmbpkxiarpY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Uo5l031VytwY+htp3tFoNwtIhjoGVm6sIm2RQ0gPw4d9I2XSz4E0Z3X+p/I2Y6+Pj 7uldACES1kpYDGOWKsRUFPGzd/KAm7JEb25a99lCxKje7s/UTr0LW7YOYCaUCYwwb4 HR8uomFcwMpbpy8p0b2O1KLCOcPNSaFjLvW18JYw= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBG9uPQG049540 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 16 Dec 2019 03:56:25 -0600 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 16 Dec 2019 03:56:25 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 16 Dec 2019 03:56:25 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9tsJT084408; Mon, 16 Dec 2019 03:56:23 -0600 From: Kishon Vijay Abraham I To: Rob Herring , Anil Varughese , Roger Quadros , Jyri Sarha CC: , Kishon Vijay Abraham I , , Subject: [PATCH v4 10/14] phy: cadence: Sierra: Change MAX_LANES of Sierra to 16 Date: Mon, 16 Dec 2019 15:27:08 +0530 Message-ID: <20191216095712.13266-11-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216095712.13266-1-kishon@ti.com> References: <20191216095712.13266-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Sierra SERDES IP supports upto 16 lanes (though not all of it will be enabled in a platform). Allow Sierra driver to support a maximum of upto 16 lanes. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 62bff4b043f0..665a6dbc7816 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -141,7 +141,7 @@ #define SIERRA_PHY_PLL_CFG 0xe #define SIERRA_MACRO_ID 0x00007364 -#define SIERRA_MAX_LANES 4 +#define SIERRA_MAX_LANES 16 #define PLL_LOCK_TIME 100000 static const struct reg_field macro_id_type = @@ -199,6 +199,7 @@ struct cdns_sierra_phy { struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; struct clk *clk; int nsubnodes; + u32 num_lanes; bool autoconf; }; @@ -235,6 +236,18 @@ static struct regmap_config cdns_sierra_lane_cdb_config[] = { SIERRA_LANE_CDB_REGMAP_CONF("1"), SIERRA_LANE_CDB_REGMAP_CONF("2"), SIERRA_LANE_CDB_REGMAP_CONF("3"), + SIERRA_LANE_CDB_REGMAP_CONF("4"), + SIERRA_LANE_CDB_REGMAP_CONF("5"), + SIERRA_LANE_CDB_REGMAP_CONF("6"), + SIERRA_LANE_CDB_REGMAP_CONF("7"), + SIERRA_LANE_CDB_REGMAP_CONF("8"), + SIERRA_LANE_CDB_REGMAP_CONF("9"), + SIERRA_LANE_CDB_REGMAP_CONF("10"), + SIERRA_LANE_CDB_REGMAP_CONF("11"), + SIERRA_LANE_CDB_REGMAP_CONF("12"), + SIERRA_LANE_CDB_REGMAP_CONF("13"), + SIERRA_LANE_CDB_REGMAP_CONF("14"), + SIERRA_LANE_CDB_REGMAP_CONF("15"), }; static struct regmap_config cdns_sierra_common_cdb_config = { @@ -548,6 +561,8 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) } } + sp->num_lanes += sp->phys[node].num_lanes; + gphy = devm_phy_create(dev, child, &ops); if (IS_ERR(gphy)) { @@ -561,6 +576,11 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) } sp->nsubnodes = node; + if (sp->num_lanes > SIERRA_MAX_LANES) { + dev_err(dev, "Invalid lane configuration\n"); + goto put_child2; + } + /* If more than one subnode, configure the PHY as multilink */ if (!sp->autoconf && sp->nsubnodes > 1) regmap_field_write(sp->phy_pll_cfg_1, 0x1); From patchwork Mon Dec 16 09:57:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 181656 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4091609ile; Mon, 16 Dec 2019 01:56:43 -0800 (PST) X-Google-Smtp-Source: APXvYqwTXlA3qwzG5w4Ei8mKYm6dcE/GFKG8FkoMltmCuA2fN6xJlckIAg+s4xcrQDuQ6voIiP79 X-Received: by 2002:a05:6830:1d1:: with SMTP id r17mr32847940ota.151.1576490203761; Mon, 16 Dec 2019 01:56:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576490203; cv=none; d=google.com; s=arc-20160816; b=Y5lJhmN5lueo4/VDN/c7Wp2QFXA12cYnSyD8WcBiGw6flTDxTDZ9b7DhU7UvxXEHiM QZXQtqzCz6zWSEVYKXijlzSsvs4KUr8Y9hqnP0xY9vPuxltpetNP8ltl7XpzZNhXBbPJ wK1H4huJ9Oq67Zdaqe5ED9bHoj3wpztz+tidr3najKGXsg/wr+ZrbhP0LZgkX8Y3R/du +x8pvr4qOkujK56q/TMdwq9EoDCPoCqT1TTzXVGslMN7Tiz3HR+EAGUMxc2tw/p47u18 luwgYIyboT/VApa9W0zrnsJLdHW1R1IPwi9iA3/3mAu/zOIEtqD1wmsln4zFW5sCYnf1 MdYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Dp1c8McrlzT08m2GtipwVgtlhr0EKQPJGCmLbB+VZUs=; b=CoHjbadscxCbubMHChzkQLENs8gmpx1TYAJ/1y0XLbmfa+xZbYxTAJa8emcTQ9XZgc vtu21BstG0lFbIY6WiYh3GNuHiETRa+uBv/Knwjz6g3tWxbkBR4go5pm2zHswX3K+1UW Ucno1ZE3lTJztOQ7Z7J8JWvnx7Wrx1btuwaiIpdTxGxYLRYVE4h6CQTXj8m6FK8PJrHB JUw/yWVjN850ISj786rD29U//4eZyeOwPanGHiNprxt9rKXv+xEVLMjd/4mBh85c/u0J yj07S49PCAAw/BNj/7VPcVhzrWL/SdQP6rZ5XXVrNcTe6VPVyDj5RktwtRIcJih1w5j4 ME5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=izt5sIo4; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p2si13699008otc.62.2019.12.16.01.56.43; Mon, 16 Dec 2019 01:56:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=izt5sIo4; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727412AbfLPJ4n (ORCPT + 8 others); Mon, 16 Dec 2019 04:56:43 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:58836 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727394AbfLPJ4m (ORCPT ); Mon, 16 Dec 2019 04:56:42 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBG9uYET106184; Mon, 16 Dec 2019 03:56:34 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576490194; bh=Dp1c8McrlzT08m2GtipwVgtlhr0EKQPJGCmLbB+VZUs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=izt5sIo4Db19Ch1dgWxIFufgUzX/s6pc7OH4NeqV98ZkzBoTwXoG6clUSgkP3f51j lFahlCLoXIYzCDE/3HM6a4MRTr0Zj8mbiBdXUGAdalyIJ6YV0TszUSPh5BSy9UJNi5 7Qnl53AolZMnfzVIZDKtBdmLmKqz0LpkJXZdLopI= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBG9uYTh125520 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 16 Dec 2019 03:56:34 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 16 Dec 2019 03:56:34 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 16 Dec 2019 03:56:33 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBG9tsJW084408; Mon, 16 Dec 2019 03:56:31 -0600 From: Kishon Vijay Abraham I To: Rob Herring , Anil Varughese , Roger Quadros , Jyri Sarha CC: , Kishon Vijay Abraham I , , Subject: [PATCH v4 13/14] dt-bindings: phy: Document WIZ (SERDES wrapper) bindings Date: Mon, 16 Dec 2019 15:27:11 +0530 Message-ID: <20191216095712.13266-14-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191216095712.13266-1-kishon@ti.com> References: <20191216095712.13266-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT binding documentation for WIZ (SERDES wrapper). WIZ is *NOT* a PHY but a wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) serdes. Signed-off-by: Kishon Vijay Abraham I [jsarha@ti.com: Add separate compatible for Sierra(16G) and Torrent(10G) SERDES] Signed-off-by: Jyri Sarha --- .../bindings/phy/ti,phy-j721e-wiz.yaml | 204 ++++++++++++++++++ 1 file changed, 204 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml new file mode 100644 index 000000000000..fd4204a960a9 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -0,0 +1,204 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI J721E WIZ (SERDES Wrapper) + +maintainers: + - Kishon Vijay Abraham I + +properties: + compatible: + enum: + - ti,j721e-wiz-16g + - ti,j721e-wiz-10g + + power-domains: + maxItems: 1 + + clocks: + maxItems: 3 + description: clock-specifier to represent input to the WIZ + + clock-names: + items: + - const: fck + - const: core_ref_clk + - const: ext_ref_clk + + num-lanes: + minimum: 1 + maximum: 4 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + "#reset-cells": + const: 1 + + ranges: true + + assigned-clocks: + maxItems: 2 + + assigned-clock-parents: + maxItems: 2 + +patternProperties: + "^pll[0|1]-refclk$": + type: object + description: | + WIZ node should have subnodes for each of the PLLs present in + the SERDES. + properties: + clocks: + maxItems: 2 + description: Phandle to clock nodes representing the two inputs to PLL. + + "#clock-cells": + const: 0 + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + required: + - clocks + - "#clock-cells" + - assigned-clocks + - assigned-clock-parents + + "^cmn-refclk1?-dig-div$": + type: object + description: | + WIZ node should have subnodes for each of the PMA common refclock + provided by the SERDES. + properties: + clocks: + maxItems: 1 + description: Phandle to the clock node representing the input to the + divider clock. + + "#clock-cells": + const: 0 + + required: + - clocks + - "#clock-cells" + + "^refclk-dig$": + type: object + description: | + WIZ node should have subnode for refclk_dig to select the reference + clock source for the reference clock used in the PHY and PMA digital + logic. + properties: + clocks: + maxItems: 4 + description: Phandle to four clock nodes representing the inputs to + refclk_dig + + "#clock-cells": + const: 0 + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + required: + - clocks + - "#clock-cells" + - assigned-clocks + - assigned-clock-parents + + "^serdes@[0-9a-f]+$": + type: object + description: | + WIZ node should have '1' subnode for the SERDES. It could be either + Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the + bindings specified in + Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt + Torrent SERDES should follow the bindings specified in + Documentation/devicetree/bindings/phy/phy-cadence-dp.txt + +required: + - compatible + - power-domains + - clocks + - clock-names + - num-lanes + - "#address-cells" + - "#size-cells" + - "#reset-cells" + - ranges + +examples: + - | + #include + + wiz@5000000 { + compatible = "ti,j721e-wiz-16g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; + assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; + num-lanes = <2>; + #reset-cells = <1>; + ranges = <0x5000000 0x0 0x5000000 0x10000>; + + pll0-refclk { + clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; + #clock-cells = <0>; + assigned-clocks = <&wiz1_pll0_refclk>; + assigned-clock-parents = <&k3_clks 293 13>; + }; + + pll1-refclk { + clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz1_pll1_refclk>; + assigned-clock-parents = <&k3_clks 293 0>; + }; + + cmn-refclk-dig-div { + clocks = <&wiz1_refclk_dig>; + #clock-cells = <0>; + }; + + cmn-refclk1-dig-div { + clocks = <&wiz1_pll1_refclk>; + #clock-cells = <0>; + }; + + refclk-dig { + clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&k3_clks 292 11>; + }; + + serdes@5000000 { + compatible = "cdns,ti,sierra-phy-t0"; + reg-names = "serdes"; + reg = <0x5000000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&serdes_wiz0 0>; + reset-names = "sierra_reset"; + clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + }; + };