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[209.51.188.17]) by mx.google.com with ESMTPS id m18si9802234qki.357.2019.12.16.03.21.51 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Dec 2019 03:21:51 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hY+zSFho; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51548 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igoRi-0006Dr-3w for patch@linaro.org; Mon, 16 Dec 2019 06:21:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50737) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igoFW-0007RR-86 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 06:09:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igoFS-0007YC-63 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 06:09:12 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:35598) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igoFS-0007Xe-0C for qemu-devel@nongnu.org; Mon, 16 Dec 2019 06:09:10 -0500 Received: by mail-wr1-x444.google.com with SMTP id g17so6736382wro.2 for ; Mon, 16 Dec 2019 03:09:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YMTEMJh/emKVxwbHbtHlnAEduqLFBKcxuqgnspTaEPo=; b=hY+zSFhon4ZaEkZild+FK7ostL8Qbx+iMZpglJVYtq2zuCIjGuu5VyDD9fWONGXsQi dkbAdLGYjjQO5VeSPy40oORjyRLZZjhGgs7apCUv4TuhWqkKAPeI1+vbIR5K94yg3Be9 eUYb2qcZ6sF+ltSD+dWmOopZFcCoVb6ULsN/FbGhAPLB2eXz95OTMHmKxn2R0lTd4pnu uZOPSxD/MD9mtJD4dfuaG+jhnpxabztOWupemdkr6+rfAcs9SERu7KRpKD+cADdnti+t cPNY2JKh8pOtHYr/kySFtWtHn+/TvGnDtwBiicHxj6V+kvKpZopYf+L35oawIOm5XJLm Q6TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YMTEMJh/emKVxwbHbtHlnAEduqLFBKcxuqgnspTaEPo=; b=EFktFZuI8/P3Owp1iVmQGeV+IxCdoH5uzb4bINhbgXqKaCJOCWZdX9Dr/kRgMYCxWN iK8/7ccUX7e6cvlY2KCXNb2xnEzbgvBVKfi2DfeyYW301UL2yL6RajmW7DvcgCu42StW upbYtC97itq81KAyxeVZ1IQfDoFrj4jjv57KA0TW9Z4x5aLa2PStEVm5fLkXAYMlWmi4 shmui3704w/s7l4tHwCWlf2uO8sxyj2EsnWveWolf51GI5OvzGa1ZxuPjTEdzBzianK0 kOhNAKlGuhI2PJ1Wn1+jeuYajj8Kf/jSZLiGcCjG5WZ6Dsdb6Tm9JO7Dr9TOi2j9GauR p1nA== X-Gm-Message-State: APjAAAVGlRrt7yWJ/od+pJH0E3PqHWI8zwHSk0yvi26AfMNz2HqoXYTo VT7sr1r9elaJxbqo6Wnju7JWHLVIrPlWuA== X-Received: by 2002:a5d:65c5:: with SMTP id e5mr29450377wrw.311.1576494548852; Mon, 16 Dec 2019 03:09:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/34] target/arm: Add support for cortex-m7 CPU Date: Mon, 16 Dec 2019 11:08:31 +0000 Message-Id: <20191216110904.30815-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Christophe Lyon This is derived from cortex-m4 description, adding DP support and FPv5 instructions with the corresponding flags in isar and mvfr2. Checked that it could successfully execute vrinta.f32 s15, s15 while cortex-m4 emulation rejects it with "illegal instruction". Signed-off-by: Christophe Lyon Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Message-id: 20191025090841.10299-1-christophe.lyon@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) -- 2.20.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a4ac9339bf..dd51adac059 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1975,6 +1975,37 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.id_isar6 = 0x00000000; } +static void cortex_m7_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + cpu->midr = 0x411fc272; /* r1p2 */ + cpu->pmsav7_dregion = 8; + cpu->isar.mvfr0 = 0x10110221; + cpu->isar.mvfr1 = 0x12000011; + cpu->isar.mvfr2 = 0x00000040; + cpu->id_pfr0 = 0x00000030; + cpu->id_pfr1 = 0x00000200; + cpu->id_dfr0 = 0x00100000; + cpu->id_afr0 = 0x00000000; + cpu->id_mmfr0 = 0x00100030; + cpu->id_mmfr1 = 0x00000000; + cpu->id_mmfr2 = 0x01000000; + cpu->id_mmfr3 = 0x00000000; + cpu->isar.id_isar0 = 0x01101110; + cpu->isar.id_isar1 = 0x02112000; + cpu->isar.id_isar2 = 0x20232231; + cpu->isar.id_isar3 = 0x01111131; + cpu->isar.id_isar4 = 0x01310132; + cpu->isar.id_isar5 = 0x00000000; + cpu->isar.id_isar6 = 0x00000000; +} + static void cortex_m33_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -2559,6 +2590,8 @@ static const ARMCPUInfo arm_cpus[] = { .class_init = arm_v7m_class_init }, { .name = "cortex-m4", .initfn = cortex_m4_initfn, .class_init = arm_v7m_class_init }, + { .name = "cortex-m7", .initfn = cortex_m7_initfn, + .class_init = arm_v7m_class_init }, { .name = "cortex-m33", .initfn = cortex_m33_initfn, .class_init = arm_v7m_class_init }, { .name = "cortex-r5", .initfn = cortex_r5_initfn }, From patchwork Mon Dec 16 11:08:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181680 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4173104ile; Mon, 16 Dec 2019 03:22:19 -0800 (PST) X-Google-Smtp-Source: APXvYqz044O5ZHNqmU6CP4teyZ19dh/qFjmjGfLxcVYF2FVSWIMC4BfDTSSFwUXA/EAiwSs+EMdR X-Received: by 2002:ae9:ee0f:: with SMTP id i15mr25353109qkg.16.1576495339208; Mon, 16 Dec 2019 03:22:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576495339; cv=none; d=google.com; s=arc-20160816; b=cdC8kfyYUL91+EcwnRNBIPYA2jNtpN7fvyXWJmDETlYmeJS2hsDXton0naX2bUkUCc +V0EVA4R/AyKQSqT7/V9hDaGyWF8NheiRCCYC0HmBHa2my0rYhxbY1UtJlsR9dS5+++0 x5b0btK4Aa0pb9dn3vJUYsLmA54w+p0htajLKQSfjQ00oBTTuDzvGIcRQlsjMLOdmJqV s+jpXS+/uo/xzSMAdZ0sIarRtTulOY0kov6kHC8FM1IVjimiboElxmHEsfG747G30KiO ImKoKfpMA7Gr39xVxwgq+OkS5nQDnWvbFwB4vv8vtSXlBsJN3DZxTuQWua50CfsPipDD jXow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0cxUjenX4Zcy7AbEng8uMiqxruOg2URtl6WiQlwztWY=; b=lfSSDXCg5zCOzqehX+gbXuNHsEK4DTnFOa2rZ6bULjC5FHq0NWi617WRXNmHH4GamK X2tumPlOkOD+h46WixWk29Xh6XgZdkrlR/pfu3aTE7hr0aUpTNWlHuTU3xJbtjGQNff7 2Ggzybz0Jdw7xlis0s9fN1myhWzVbLStkYxLe7srUc7H5JyN/aL+s98E/dv++R+lJSnI 2HeIdiPjQC+U031hsigBSmm/auONlsKFCDH0T6sTBrMQbzdpM0QObtFIqD6LnfRckQdj P3Vuz40ed2V3RPTDoayVA/p9BZI5KbUMBtocft6bua+biovXVKqD3AUs2uJ5kIJh6sIk M/CQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OoxFesnG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/34] exynos4210_gic: Suppress gcc9 format-truncation warnings Date: Mon, 16 Dec 2019 11:08:32 +0000 Message-Id: <20191216110904.30815-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: David Gibson exynos4210_gic_realize() prints the number of cpus into some temporary buffers, but it only allows 3 bytes space for it. That's plenty: existing machines will only ever set this value to EXYNOS4210_NCPUS (2). But the compiler can't always figure that out, so some[*] gcc9 versions emit -Wformat-truncation warnings. We can fix that by hinting the constraint to the compiler with a suitably placed assert(). [*] The bizarre thing here, is that I've long gotten these warnings compiling in a 32-bit x86 container as host - Fedora 30 with gcc-9.2.1-1.fc30.i686 - but it compiles just fine on my normal x86_64 host - Fedora 30 with and gcc-9.2.1-1.fc30.x86_64. Signed-off-by: David Gibson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson [PMM: deleted stray blank line] Signed-off-by: Peter Maydell --- hw/intc/exynos4210_gic.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c index a1b699b6bab..9a84d8522e9 100644 --- a/hw/intc/exynos4210_gic.c +++ b/hw/intc/exynos4210_gic.c @@ -293,6 +293,7 @@ static void exynos4210_gic_realize(DeviceState *dev, Error **errp) char cpu_alias_name[sizeof(cpu_prefix) + 3]; char dist_alias_name[sizeof(cpu_prefix) + 3]; SysBusDevice *gicbusdev; + uint32_t n = s->num_cpu; uint32_t i; s->gic = qdev_create(NULL, "arm_gic"); @@ -313,7 +314,13 @@ static void exynos4210_gic_realize(DeviceState *dev, Error **errp) memory_region_init(&s->dist_container, obj, "exynos4210-dist-container", EXYNOS4210_EXT_GIC_DIST_REGION_SIZE); - for (i = 0; i < s->num_cpu; i++) { + /* + * This clues in gcc that our on-stack buffers do, in fact have + * enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86 + * doesn't figure this out, otherwise and gives spurious warnings. + */ + assert(n <= EXYNOS4210_NCPUS); + for (i = 0; i < n; i++) { /* Map CPU interface per SMP Core */ sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); memory_region_init_alias(&s->cpu_alias[i], obj, From patchwork Mon Dec 16 11:08:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181691 Delivered-To: patch@linaro.org Received: by 2002:ac9:44c4:0:0:0:0:0 with SMTP id t4csp4176662och; Mon, 16 Dec 2019 03:29:15 -0800 (PST) X-Google-Smtp-Source: APXvYqy0U8BFGkyMuTX/Xp45++/2chPPXzoKAb3ACskGYkqIvtRE8K23KbEeqPk+ZWmGrR7LbN5E X-Received: by 2002:ac8:53d1:: with SMTP id c17mr24722378qtq.350.1576495755150; Mon, 16 Dec 2019 03:29:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576495755; cv=none; d=google.com; s=arc-20160816; b=VW6tEIMV+G2PBzp0bpMbaDKB/Gvzp5u1RLrsvvj3XCeFVnWFxQewoL0QktBnds37X4 gRzda2aStNlXmTQRt+mO0xAk/UOT03VGrvOct74AKv+Yw8UZcHzRkwzv09ukthxWYucK Vt/V7EM9fYS0IF95LujDADHiUaw0U0f9K0gl4ZGJmdPOBBkHXSuucyzpLeJW2nroJgor XWNmW+jSpQ6Ge7/51E/jD3SexrfqKPfr1HSdMMCM3N8pcuOw8vRacOi8qgS+pu4AYzYa cXZQvm72t0ZUIUYRkWxATFfbOtXE7iybeGC+br0UiI/zMnRM0xyz7cvXv7afOIka4Qlz W15g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oNLgQ7/WJxX1ZKmY5Vt3oSTTDEYqnkdhsC8/NLTg2u4=; b=ozZ2VFbP9NjXd9vrL7+ZTdw0+zeZgx8pTYOxnJmoQ+oSMcDdWjI5+MVVich8WERXFn ubRVwFQQKtQvcRkWmW08cHotDCip15ZAS99jX8Ft/5SyH6iMheGqfhEIsjjgV7eBXGLf dXmA4lIi+uM4nt+3V3Z/dVs9qWzv4/bUOT2bbmYh5GJRacLNm57cOlHehZgz2A72RXFA KmkbMJNrS9BmP/2rtj67bMWuYXkLhbmT9WAOKex+Il/TAkEkUQFDxnctgOwLYxGOfI7v +aNsuLdF+Pgk0u2htxEIN65sDhupa1ZK2lbk6V+Uf8BHp0yGy1VQLTxcmU9+1CdMkBaA s9Tw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="nAvOZsW/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/34] aspeed/i2c: Add support for pool buffer transfers Date: Mon, 16 Dec 2019 11:08:33 +0000 Message-Id: <20191216110904.30815-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The Aspeed I2C controller can operate in different transfer modes : - Byte Buffer mode, using a dedicated register to transfer a byte. This is what the model supports today. - Pool Buffer mode, using an internal SRAM to transfer multiple bytes in the same command sequence. Each SoC has different SRAM characteristics. On the AST2400, 2048 bytes of SRAM are available at offset 0x800 of the controller AHB window. The pool buffer can be configured from 1 to 256 bytes per bus. On the AST2500, the SRAM is at offset 0x200 and the pool buffer is of 16 bytes per bus. On the AST2600, the SRAM is at offset 0xC00 and the pool buffer is of 32 bytes per bus. It can be splitted in two for TX and RX but the current model does not add support for it as it it unused by known drivers. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Tested-by: Jae Hyun Yoo Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-2-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/i2c/aspeed_i2c.h | 8 ++ hw/i2c/aspeed_i2c.c | 197 ++++++++++++++++++++++++++++++++---- 2 files changed, 186 insertions(+), 19 deletions(-) -- 2.20.1 diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index 13e01059189..5313d07aa72 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -32,6 +32,7 @@ OBJECT_CHECK(AspeedI2CState, (obj), TYPE_ASPEED_I2C) #define ASPEED_I2C_NR_BUSSES 16 +#define ASPEED_I2C_MAX_POOL_SIZE 0x800 struct AspeedI2CState; @@ -50,6 +51,7 @@ typedef struct AspeedI2CBus { uint32_t intr_status; uint32_t cmd; uint32_t buf; + uint32_t pool_ctrl; } AspeedI2CBus; typedef struct AspeedI2CState { @@ -59,6 +61,8 @@ typedef struct AspeedI2CState { qemu_irq irq; uint32_t intr_status; + MemoryRegion pool_iomem; + uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE]; AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES]; } AspeedI2CState; @@ -75,6 +79,10 @@ typedef struct AspeedI2CClass { uint8_t reg_size; uint8_t gap; qemu_irq (*bus_get_irq)(AspeedI2CBus *); + + uint64_t pool_size; + hwaddr pool_base; + uint8_t *(*bus_pool_base)(AspeedI2CBus *); } AspeedI2CClass; I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr); diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 06c119f385b..e21f45d9686 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -35,8 +35,7 @@ /* I2C Device (Bus) Register */ #define I2CD_FUN_CTRL_REG 0x00 /* I2CD Function Control */ -#define I2CD_BUFF_SEL_MASK (0x7 << 20) -#define I2CD_BUFF_SEL(x) (x << 20) +#define I2CD_POOL_PAGE_SEL(x) (((x) >> 20) & 0x7) /* AST2400 */ #define I2CD_M_SDA_LOCK_EN (0x1 << 16) #define I2CD_MULTI_MASTER_DIS (0x1 << 15) #define I2CD_M_SCL_DRIVE_EN (0x1 << 14) @@ -113,10 +112,12 @@ #define I2CD_SCL_O_OUT_DIR (0x1 << 12) #define I2CD_BUS_RECOVER_CMD_EN (0x1 << 11) #define I2CD_S_ALT_EN (0x1 << 10) -#define I2CD_RX_DMA_ENABLE (0x1 << 9) -#define I2CD_TX_DMA_ENABLE (0x1 << 8) /* Command Bit */ +#define I2CD_RX_DMA_ENABLE (0x1 << 9) +#define I2CD_TX_DMA_ENABLE (0x1 << 8) +#define I2CD_RX_BUFF_ENABLE (0x1 << 7) +#define I2CD_TX_BUFF_ENABLE (0x1 << 6) #define I2CD_M_STOP_CMD (0x1 << 5) #define I2CD_M_S_RX_CMD_LAST (0x1 << 4) #define I2CD_M_RX_CMD (0x1 << 3) @@ -125,7 +126,11 @@ #define I2CD_M_START_CMD (0x1) #define I2CD_DEV_ADDR_REG 0x18 /* Slave Device Address */ -#define I2CD_BUF_CTRL_REG 0x1c /* Pool Buffer Control */ +#define I2CD_POOL_CTRL_REG 0x1c /* Pool Buffer Control */ +#define I2CD_POOL_RX_COUNT(x) (((x) >> 24) & 0xff) +#define I2CD_POOL_RX_SIZE(x) ((((x) >> 16) & 0xff) + 1) +#define I2CD_POOL_TX_COUNT(x) ((((x) >> 8) & 0xff) + 1) +#define I2CD_POOL_OFFSET(x) (((x) & 0x3f) << 2) /* AST2400 */ #define I2CD_BYTE_BUF_REG 0x20 /* Transmit/Receive Byte Buffer */ #define I2CD_BYTE_BUF_TX_SHIFT 0 #define I2CD_BYTE_BUF_TX_MASK 0xff @@ -170,6 +175,8 @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset, return bus->intr_ctrl; case I2CD_INTR_STS_REG: return bus->intr_status; + case I2CD_POOL_CTRL_REG: + return bus->pool_ctrl; case I2CD_BYTE_BUF_REG: return bus->buf; case I2CD_CMD_REG: @@ -192,14 +199,58 @@ static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus) return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK; } +static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start) +{ + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); + int ret = -1; + int i; + + if (bus->cmd & I2CD_TX_BUFF_ENABLE) { + for (i = pool_start; i < I2CD_POOL_TX_COUNT(bus->pool_ctrl); i++) { + uint8_t *pool_base = aic->bus_pool_base(bus); + + ret = i2c_send(bus->bus, pool_base[i]); + if (ret) { + break; + } + } + bus->cmd &= ~I2CD_TX_BUFF_ENABLE; + } else { + ret = i2c_send(bus->bus, bus->buf); + } + + return ret; +} + +static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) +{ + AspeedI2CState *s = bus->controller; + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); + uint8_t data; + int i; + + if (bus->cmd & I2CD_RX_BUFF_ENABLE) { + uint8_t *pool_base = aic->bus_pool_base(bus); + + for (i = 0; i < I2CD_POOL_RX_SIZE(bus->pool_ctrl); i++) { + pool_base[i] = i2c_recv(bus->bus); + } + + /* Update RX count */ + bus->pool_ctrl &= ~(0xff << 24); + bus->pool_ctrl |= (i & 0xff) << 24; + bus->cmd &= ~I2CD_RX_BUFF_ENABLE; + } else { + data = i2c_recv(bus->bus); + bus->buf = (data & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT; + } +} + static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus) { - uint8_t ret; - aspeed_i2c_set_state(bus, I2CD_MRXD); - ret = i2c_recv(bus->bus); + aspeed_i2c_bus_recv(bus); bus->intr_status |= I2CD_INTR_RX_DONE; - bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT; if (bus->cmd & I2CD_M_S_RX_CMD_LAST) { i2c_nack(bus->bus); } @@ -207,31 +258,66 @@ static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus) aspeed_i2c_set_state(bus, I2CD_MACTIVE); } +static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus) +{ + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); + + if (bus->cmd & I2CD_TX_BUFF_ENABLE) { + uint8_t *pool_base = aic->bus_pool_base(bus); + + return pool_base[0]; + } else { + return bus->buf; + } +} + /* * The state machine needs some refinement. It is only used to track * invalid STOP commands for the moment. */ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) { + uint8_t pool_start = 0; + bus->cmd &= ~0xFFFF; bus->cmd |= value & 0xFFFF; if (bus->cmd & I2CD_M_START_CMD) { uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ? I2CD_MSTARTR : I2CD_MSTART; + uint8_t addr; aspeed_i2c_set_state(bus, state); - if (i2c_start_transfer(bus->bus, extract32(bus->buf, 1, 7), - extract32(bus->buf, 0, 1))) { + addr = aspeed_i2c_get_addr(bus); + + if (i2c_start_transfer(bus->bus, extract32(addr, 1, 7), + extract32(addr, 0, 1))) { bus->intr_status |= I2CD_INTR_TX_NAK; } else { bus->intr_status |= I2CD_INTR_TX_ACK; } - /* START command is also a TX command, as the slave address is - * sent on the bus */ - bus->cmd &= ~(I2CD_M_START_CMD | I2CD_M_TX_CMD); + bus->cmd &= ~I2CD_M_START_CMD; + + /* + * The START command is also a TX command, as the slave + * address is sent on the bus. Drop the TX flag if nothing + * else needs to be sent in this sequence. + */ + if (bus->cmd & I2CD_TX_BUFF_ENABLE) { + if (I2CD_POOL_TX_COUNT(bus->pool_ctrl) == 1) { + bus->cmd &= ~I2CD_M_TX_CMD; + } else { + /* + * Increase the start index in the TX pool buffer to + * skip the address byte. + */ + pool_start++; + } + } else { + bus->cmd &= ~I2CD_M_TX_CMD; + } /* No slave found */ if (!i2c_bus_busy(bus->bus)) { @@ -242,7 +328,7 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) if (bus->cmd & I2CD_M_TX_CMD) { aspeed_i2c_set_state(bus, I2CD_MTXD); - if (i2c_send(bus->bus, bus->buf)) { + if (aspeed_i2c_bus_send(bus, pool_start)) { bus->intr_status |= (I2CD_INTR_TX_NAK); i2c_end_transfer(bus->bus); } else { @@ -313,6 +399,11 @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", __func__); break; + case I2CD_POOL_CTRL_REG: + bus->pool_ctrl &= ~0xffffff; + bus->pool_ctrl |= (value & 0xffffff); + break; + case I2CD_BYTE_BUF_REG: bus->buf = (value & I2CD_BYTE_BUF_TX_MASK) << I2CD_BYTE_BUF_TX_SHIFT; break; @@ -378,10 +469,45 @@ static const MemoryRegionOps aspeed_i2c_ctrl_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; +static uint64_t aspeed_i2c_pool_read(void *opaque, hwaddr offset, + unsigned size) +{ + AspeedI2CState *s = opaque; + uint64_t ret = 0; + int i; + + for (i = 0; i < size; i++) { + ret |= (uint64_t) s->pool[offset + i] << (8 * i); + } + + return ret; +} + +static void aspeed_i2c_pool_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + AspeedI2CState *s = opaque; + int i; + + for (i = 0; i < size; i++) { + s->pool[offset + i] = (value >> (8 * i)) & 0xFF; + } +} + +static const MemoryRegionOps aspeed_i2c_pool_ops = { + .read = aspeed_i2c_pool_read, + .write = aspeed_i2c_pool_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + }, +}; + static const VMStateDescription aspeed_i2c_bus_vmstate = { .name = TYPE_ASPEED_I2C, - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_UINT8(id, AspeedI2CBus), VMSTATE_UINT32(ctrl, AspeedI2CBus), @@ -390,19 +516,21 @@ static const VMStateDescription aspeed_i2c_bus_vmstate = { VMSTATE_UINT32(intr_status, AspeedI2CBus), VMSTATE_UINT32(cmd, AspeedI2CBus), VMSTATE_UINT32(buf, AspeedI2CBus), + VMSTATE_UINT32(pool_ctrl, AspeedI2CBus), VMSTATE_END_OF_LIST() } }; static const VMStateDescription aspeed_i2c_vmstate = { .name = TYPE_ASPEED_I2C, - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_UINT32(intr_status, AspeedI2CState), VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState, ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate, AspeedI2CBus), + VMSTATE_UINT8_ARRAY(pool, AspeedI2CState, ASPEED_I2C_MAX_POOL_SIZE), VMSTATE_END_OF_LIST() } }; @@ -472,6 +600,10 @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(&s->iomem, aic->reg_size * (i + offset), &s->busses[i].mr); } + + memory_region_init_io(&s->pool_iomem, OBJECT(s), &aspeed_i2c_pool_ops, s, + "aspeed.i2c-pool", aic->pool_size); + memory_region_add_subregion(&s->iomem, aic->pool_base, &s->pool_iomem); } static void aspeed_i2c_class_init(ObjectClass *klass, void *data) @@ -498,6 +630,14 @@ static qemu_irq aspeed_2400_i2c_bus_get_irq(AspeedI2CBus *bus) return bus->controller->irq; } +static uint8_t *aspeed_2400_i2c_bus_pool_base(AspeedI2CBus *bus) +{ + uint8_t *pool_page = + &bus->controller->pool[I2CD_POOL_PAGE_SEL(bus->ctrl) * 0x100]; + + return &pool_page[I2CD_POOL_OFFSET(bus->pool_ctrl)]; +} + static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -509,6 +649,9 @@ static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data) aic->reg_size = 0x40; aic->gap = 7; aic->bus_get_irq = aspeed_2400_i2c_bus_get_irq; + aic->pool_size = 0x800; + aic->pool_base = 0x800; + aic->bus_pool_base = aspeed_2400_i2c_bus_pool_base; } static const TypeInfo aspeed_2400_i2c_info = { @@ -522,6 +665,11 @@ static qemu_irq aspeed_2500_i2c_bus_get_irq(AspeedI2CBus *bus) return bus->controller->irq; } +static uint8_t *aspeed_2500_i2c_bus_pool_base(AspeedI2CBus *bus) +{ + return &bus->controller->pool[bus->id * 0x10]; +} + static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -533,6 +681,9 @@ static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) aic->reg_size = 0x40; aic->gap = 7; aic->bus_get_irq = aspeed_2500_i2c_bus_get_irq; + aic->pool_size = 0x100; + aic->pool_base = 0x200; + aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; } static const TypeInfo aspeed_2500_i2c_info = { @@ -546,6 +697,11 @@ static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus) return bus->irq; } +static uint8_t *aspeed_2600_i2c_bus_pool_base(AspeedI2CBus *bus) +{ + return &bus->controller->pool[bus->id * 0x20]; +} + static void aspeed_2600_i2c_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -557,6 +713,9 @@ static void aspeed_2600_i2c_class_init(ObjectClass *klass, void *data) aic->reg_size = 0x80; aic->gap = -1; /* no gap */ aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; + aic->pool_size = 0x200; + aic->pool_base = 0xC00; + aic->bus_pool_base = aspeed_2600_i2c_bus_pool_base; } static const TypeInfo aspeed_2600_i2c_info = { From patchwork Mon Dec 16 11:08:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181673 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4167904ile; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/34] aspeed/i2c: Check SRAM enablement on AST2500 Date: Mon, 16 Dec 2019 11:08:34 +0000 Message-Id: <20191216110904.30815-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The SRAM must be enabled before using the Buffer Pool mode or the DMA mode. This is not required on other SoCs. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Tested-by: Jae Hyun Yoo Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-3-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/i2c/aspeed_i2c.h | 3 +++ hw/i2c/aspeed_i2c.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) -- 2.20.1 diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index 5313d07aa72..7a555072dfb 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -61,6 +61,7 @@ typedef struct AspeedI2CState { qemu_irq irq; uint32_t intr_status; + uint32_t ctrl_global; MemoryRegion pool_iomem; uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE]; @@ -83,6 +84,8 @@ typedef struct AspeedI2CClass { uint64_t pool_size; hwaddr pool_base; uint8_t *(*bus_pool_base)(AspeedI2CBus *); + bool check_sram; + } AspeedI2CClass; I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr); diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index e21f45d9686..c7929aa2850 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -31,6 +31,8 @@ #define I2C_CTRL_STATUS 0x00 /* Device Interrupt Status */ #define I2C_CTRL_ASSIGN 0x08 /* Device Interrupt Target Assignment */ +#define I2C_CTRL_GLOBAL 0x0C /* Global Control Register */ +#define I2C_CTRL_SRAM_EN BIT(0) /* I2C Device (Bus) Register */ @@ -271,6 +273,29 @@ static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus) } } +static bool aspeed_i2c_check_sram(AspeedI2CBus *bus) +{ + AspeedI2CState *s = bus->controller; + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); + + if (!aic->check_sram) { + return true; + } + + /* + * AST2500: SRAM must be enabled before using the Buffer Pool or + * DMA mode. + */ + if (!(s->ctrl_global & I2C_CTRL_SRAM_EN) && + (bus->cmd & (I2CD_RX_DMA_ENABLE | I2CD_TX_DMA_ENABLE | + I2CD_RX_BUFF_ENABLE | I2CD_TX_BUFF_ENABLE))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: SRAM is not enabled\n", __func__); + return false; + } + + return true; +} + /* * The state machine needs some refinement. It is only used to track * invalid STOP commands for the moment. @@ -282,6 +307,10 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) bus->cmd &= ~0xFFFF; bus->cmd |= value & 0xFFFF; + if (!aspeed_i2c_check_sram(bus)) { + return; + } + if (bus->cmd & I2CD_M_START_CMD) { uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ? I2CD_MSTARTR : I2CD_MSTART; @@ -436,6 +465,8 @@ static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset, switch (offset) { case I2C_CTRL_STATUS: return s->intr_status; + case I2C_CTRL_GLOBAL: + return s->ctrl_global; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); @@ -448,7 +479,12 @@ static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset, static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { + AspeedI2CState *s = opaque; + switch (offset) { + case I2C_CTRL_GLOBAL: + s->ctrl_global = value; + break; case I2C_CTRL_STATUS: default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", @@ -684,6 +720,7 @@ static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) aic->pool_size = 0x100; aic->pool_base = 0x200; aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; + aic->check_sram = true; } static const TypeInfo aspeed_2500_i2c_info = { From patchwork Mon Dec 16 11:08:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181689 Delivered-To: patch@linaro.org Received: by 2002:ac9:44c4:0:0:0:0:0 with SMTP id t4csp4174416och; Mon, 16 Dec 2019 03:26:38 -0800 (PST) X-Google-Smtp-Source: APXvYqysG42PUS2h08ecpZl45ES3q+gGk1IuY9qavFnPvlwWdd63ELEK0vWyv31AL1EYpKRwoPUI X-Received: by 2002:ac8:4a85:: with SMTP id l5mr8118758qtq.64.1576495598594; Mon, 16 Dec 2019 03:26:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576495598; cv=none; d=google.com; s=arc-20160816; b=Bpxh53oMk0xVMf6oMqqUzT8A+Jb82rOS3OXb0uYVqRFqziaGxtCeryiLr1lhtFytoD wwhtSlrw63QvD88hsCIUktFgiGQXzR3Xxm5aKS3K5FPeSHyzYVRAoqU0KMvOHJsrfo9i /RnASjdpdMVc+CC4AMFNmbX5kVXWdQ22mdBKzRsQelQsrbXKK72cLkxWV/S4lKJ55ux3 d+4wwIdByEx814tenKtkTBgdwYWmq6L+3nZOnNAljsxJgvUD8kBgMTeTMzhOQJhWIpEX l72SfST4k7f9IFkfQ+1ZHIHgoVmPNxXQW7jo+a5FPsUqHtGNQmEeMPMeidxvN7eJTnh1 UwIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zjLDEF6DNpTRDBT/Aj8pPr1zY4WR/x86sRDNZnQ+teI=; b=ehrIMMrM9ck4LBS/NpyqeJ2wmJXGF8QC9N16LkYuYQmgD277iZrWUKF+ZcigofhCvp ZJDvvOmihU9xpXE9z/ocEHBMn1JEy2nIN/mPxSswrRVUAy4WXksiWMh4+XA/lrOxUZs0 PtMu+/d1N42NL1o7lIiVleLDX6mjvG/cROZ8pwRaGDhk6dVC6HT1LYPk9SSLDlg+uIzu S0tPwaBPVUeeuh0HHDMeQlQFIVGHxdt/WadDqFhsKDO8IE7svVIAmQYK4Y18UbZmPlJN yRD0dcdm8+8eQzUlOxhe4xJA3QaNuKlVk/HmzocGJfay0mFP/TQu5fsbiucyq2jwSuv6 UoBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Pzpo0ZM3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/34] aspeed: Add a DRAM memory region at the SoC level Date: Mon, 16 Dec 2019 11:08:35 +0000 Message-Id: <20191216110904.30815-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Currently, we link the DRAM memory region to the FMC model (for DMAs) through a property alias at the SoC level. The I2C model will need a similar region for DMA support, add a DRAM region property at the SoC level for both model to use. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Tested-by: Jae Hyun Yoo Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-4-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_ast2600.c | 7 +++++-- hw/arm/aspeed_soc.c | 9 +++++++-- 3 files changed, 13 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 495c08be1b8..e84380984f7 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -40,6 +40,7 @@ typedef struct AspeedSoCState { ARMCPU cpu[ASPEED_CPUS_NUM]; uint32_t num_cpus; A15MPPrivState a7mpcore; + MemoryRegion *dram_mr; MemoryRegion sram; AspeedVICState vic; AspeedRtcState rtc; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 931887ac681..a403c2aae06 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -158,8 +158,6 @@ static void aspeed_soc_ast2600_init(Object *obj) typename); object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", &error_abort); - object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram", - &error_abort); for (i = 0; i < sc->spis_num; i++) { snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); @@ -362,6 +360,11 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) } /* FMC, The number of CS is set at the board level */ + object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err); + if (err) { + error_propagate(errp, err); + return; + } object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], "sdram-base", &err); if (err) { diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index f4fe243458f..dd1ee0e3336 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -175,8 +175,6 @@ static void aspeed_soc_init(Object *obj) typename); object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", &error_abort); - object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram", - &error_abort); for (i = 0; i < sc->spis_num; i++) { snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); @@ -323,6 +321,11 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) aspeed_soc_get_irq(s, ASPEED_I2C)); /* FMC, The number of CS is set at the board level */ + object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err); + if (err) { + error_propagate(errp, err); + return; + } object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], "sdram-base", &err); if (err) { @@ -429,6 +432,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) } static Property aspeed_soc_properties[] = { DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0), + DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, + MemoryRegion *), DEFINE_PROP_END_OF_LIST(), }; From patchwork Mon Dec 16 11:08:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181679 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4173079ile; Mon, 16 Dec 2019 03:22:17 -0800 (PST) X-Google-Smtp-Source: APXvYqxVnJZhddwHanrf9F4h0uJFKPz3C8uksMMmFhaPogxhKyQQ45r9E0Y3LGoOObhFIx/iYmZP X-Received: by 2002:a37:b842:: with SMTP id i63mr26339171qkf.451.1576495337473; Mon, 16 Dec 2019 03:22:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576495337; cv=none; d=google.com; s=arc-20160816; b=dNHpZgCpp3l4VNuH5Wgl7vwZJvC6lcMt6fbTLffmpHw8LDpohVqoAUgFeQS8aPXUyt 69M0ILibTpGR5eQQlbZehXvJPYOK2IEuwIAo59Wti5amEGBjtwLpKOlEvniamzi5C2nT ro2Vi7xsla0mcoQxT2dQlsIp8/UvTqY+thmRS7HSNykX6lMRUf8yZGd5xYhfih1wylPD c2bUSCoP+iNCCzlyKLGgZUJ5ARO5mUGV6hQpfXVBmjrL/D+8MvFm1yCrq9ikvbnrqBlr ViWMMm7UTxGaLRNhO4TtV7TsRm58ifcvdwo1k+B2ikC7QMXGAaD1UJ+LEHNUkz+4N649 j+Gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aPucyTu35BZg4N9KmO26YmX+t5sHuLkag3CqvOlVE04=; b=hgNL7dgloGuoWK87wvIcO9dCmMVIPvFjLGNEXIRO7zICNmrTINLaf8qePRU4PjPkNG /yFZqZYfIrpmOA35LAr3Qq5br/ebKjWzNY6cA9srZh0iQXgUW/X9T1iJDUbWsyTPSWTa kba925pW7s24pvb4sLM9FQFBnbUfVKgZhJK2L0oxR+pVX01CjTtZxtuv2zMdVKrI2aaw 0AvxVGWM5J8I5D/2cITSO3QlHCJhEZqt3kVErI4IKtsriWBOsR+X97Io6o8ciIxtifkp uTLr2+rP7USlzTNkr0nPro0dqvydWz1cMzGZ1hFuscbIlgJeJ5mKNuNvSUyUsJmpDpOD KEYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=axYov1R8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/34] aspeed/i2c: Add support for DMA transfers Date: Mon, 16 Dec 2019 11:08:36 +0000 Message-Id: <20191216110904.30815-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA transfers to and from DRAM. A pair of registers defines the buffer address and the length of the DMA transfer. The address should be aligned on 4 bytes and the maximum length should not exceed 4K. The receive or transmit DMA transfer can then be initiated with specific bits in the Command/Status register of the controller. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Tested-by: Jae Hyun Yoo Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-5-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/i2c/aspeed_i2c.h | 5 ++ hw/arm/aspeed_ast2600.c | 5 ++ hw/arm/aspeed_soc.c | 5 ++ hw/i2c/aspeed_i2c.c | 126 +++++++++++++++++++++++++++++++++++- 4 files changed, 138 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index 7a555072dfb..f1b9e5bf91e 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -52,6 +52,8 @@ typedef struct AspeedI2CBus { uint32_t cmd; uint32_t buf; uint32_t pool_ctrl; + uint32_t dma_addr; + uint32_t dma_len; } AspeedI2CBus; typedef struct AspeedI2CState { @@ -66,6 +68,8 @@ typedef struct AspeedI2CState { uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE]; AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES]; + MemoryRegion *dram_mr; + AddressSpace dram_as; } AspeedI2CState; #define ASPEED_I2C_CLASS(klass) \ @@ -85,6 +89,7 @@ typedef struct AspeedI2CClass { hwaddr pool_base; uint8_t *(*bus_pool_base)(AspeedI2CBus *); bool check_sram; + bool has_dma; } AspeedI2CClass; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index a403c2aae06..0881eb25983 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -343,6 +343,11 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) } /* I2C */ + object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err); + if (err) { + error_propagate(errp, err); + return; + } object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index dd1ee0e3336..b01c9774419 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -311,6 +311,11 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) } /* I2C */ + object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err); + if (err) { + error_propagate(errp, err); + return; + } object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index c7929aa2850..030d9c56be6 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -23,8 +23,11 @@ #include "migration/vmstate.h" #include "qemu/log.h" #include "qemu/module.h" +#include "qemu/error-report.h" +#include "qapi/error.h" #include "hw/i2c/aspeed_i2c.h" #include "hw/irq.h" +#include "hw/qdev-properties.h" /* I2C Global Register */ @@ -138,7 +141,8 @@ #define I2CD_BYTE_BUF_TX_MASK 0xff #define I2CD_BYTE_BUF_RX_SHIFT 8 #define I2CD_BYTE_BUF_RX_MASK 0xff - +#define I2CD_DMA_ADDR 0x24 /* DMA Buffer Address */ +#define I2CD_DMA_LEN 0x28 /* DMA Transfer Length < 4KB */ static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus) { @@ -165,6 +169,7 @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset, unsigned size) { AspeedI2CBus *bus = opaque; + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); switch (offset) { case I2CD_FUN_CTRL_REG: @@ -183,6 +188,18 @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset, return bus->buf; case I2CD_CMD_REG: return bus->cmd | (i2c_bus_busy(bus->bus) << 16); + case I2CD_DMA_ADDR: + if (!aic->has_dma) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); + return -1; + } + return bus->dma_addr; + case I2CD_DMA_LEN: + if (!aic->has_dma) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); + return -1; + } + return bus->dma_len; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); @@ -201,6 +218,24 @@ static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus) return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK; } +static int aspeed_i2c_dma_read(AspeedI2CBus *bus, uint8_t *data) +{ + MemTxResult result; + AspeedI2CState *s = bus->controller; + + result = address_space_read(&s->dram_as, bus->dma_addr, + MEMTXATTRS_UNSPECIFIED, data, 1); + if (result != MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM read failed @%08x\n", + __func__, bus->dma_addr); + return -1; + } + + bus->dma_addr++; + bus->dma_len--; + return 0; +} + static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start) { AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); @@ -217,6 +252,16 @@ static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start) } } bus->cmd &= ~I2CD_TX_BUFF_ENABLE; + } else if (bus->cmd & I2CD_TX_DMA_ENABLE) { + while (bus->dma_len) { + uint8_t data; + aspeed_i2c_dma_read(bus, &data); + ret = i2c_send(bus->bus, data); + if (ret) { + break; + } + } + bus->cmd &= ~I2CD_TX_DMA_ENABLE; } else { ret = i2c_send(bus->bus, bus->buf); } @@ -242,6 +287,24 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) bus->pool_ctrl &= ~(0xff << 24); bus->pool_ctrl |= (i & 0xff) << 24; bus->cmd &= ~I2CD_RX_BUFF_ENABLE; + } else if (bus->cmd & I2CD_RX_DMA_ENABLE) { + uint8_t data; + + while (bus->dma_len) { + MemTxResult result; + + data = i2c_recv(bus->bus); + result = address_space_write(&s->dram_as, bus->dma_addr, + MEMTXATTRS_UNSPECIFIED, &data, 1); + if (result != MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM write failed @%08x\n", + __func__, bus->dma_addr); + return; + } + bus->dma_addr++; + bus->dma_len--; + } + bus->cmd &= ~I2CD_RX_DMA_ENABLE; } else { data = i2c_recv(bus->bus); bus->buf = (data & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT; @@ -268,6 +331,11 @@ static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus) uint8_t *pool_base = aic->bus_pool_base(bus); return pool_base[0]; + } else if (bus->cmd & I2CD_TX_DMA_ENABLE) { + uint8_t data; + + aspeed_i2c_dma_read(bus, &data); + return data; } else { return bus->buf; } @@ -344,6 +412,10 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) */ pool_start++; } + } else if (bus->cmd & I2CD_TX_DMA_ENABLE) { + if (bus->dma_len == 0) { + bus->cmd &= ~I2CD_M_TX_CMD; + } } else { bus->cmd &= ~I2CD_M_TX_CMD; } @@ -447,9 +519,35 @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, break; } + if (!aic->has_dma && + value & (I2CD_RX_DMA_ENABLE | I2CD_TX_DMA_ENABLE)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); + break; + } + aspeed_i2c_bus_handle_cmd(bus, value); aspeed_i2c_bus_raise_interrupt(bus); break; + case I2CD_DMA_ADDR: + if (!aic->has_dma) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); + break; + } + + bus->dma_addr = value & 0xfffffffc; + break; + + case I2CD_DMA_LEN: + if (!aic->has_dma) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); + break; + } + + bus->dma_len = value & 0xfff; + if (!bus->dma_len) { + qemu_log_mask(LOG_UNIMP, "%s: invalid DMA length\n", __func__); + } + break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", @@ -542,8 +640,8 @@ static const MemoryRegionOps aspeed_i2c_pool_ops = { static const VMStateDescription aspeed_i2c_bus_vmstate = { .name = TYPE_ASPEED_I2C, - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .fields = (VMStateField[]) { VMSTATE_UINT8(id, AspeedI2CBus), VMSTATE_UINT32(ctrl, AspeedI2CBus), @@ -553,6 +651,8 @@ static const VMStateDescription aspeed_i2c_bus_vmstate = { VMSTATE_UINT32(cmd, AspeedI2CBus), VMSTATE_UINT32(buf, AspeedI2CBus), VMSTATE_UINT32(pool_ctrl, AspeedI2CBus), + VMSTATE_UINT32(dma_addr, AspeedI2CBus), + VMSTATE_UINT32(dma_len, AspeedI2CBus), VMSTATE_END_OF_LIST() } }; @@ -584,6 +684,8 @@ static void aspeed_i2c_reset(DeviceState *dev) s->busses[i].intr_status = 0; s->busses[i].cmd = 0; s->busses[i].buf = 0; + s->busses[i].dma_addr = 0; + s->busses[i].dma_len = 0; i2c_end_transfer(s->busses[i].bus); } } @@ -640,14 +742,30 @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp) memory_region_init_io(&s->pool_iomem, OBJECT(s), &aspeed_i2c_pool_ops, s, "aspeed.i2c-pool", aic->pool_size); memory_region_add_subregion(&s->iomem, aic->pool_base, &s->pool_iomem); + + if (aic->has_dma) { + if (!s->dram_mr) { + error_setg(errp, TYPE_ASPEED_I2C ": 'dram' link not set"); + return; + } + + address_space_init(&s->dram_as, s->dram_mr, "dma-dram"); + } } +static Property aspeed_i2c_properties[] = { + DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr, + TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_END_OF_LIST(), +}; + static void aspeed_i2c_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->vmsd = &aspeed_i2c_vmstate; dc->reset = aspeed_i2c_reset; + dc->props = aspeed_i2c_properties; dc->realize = aspeed_i2c_realize; dc->desc = "Aspeed I2C Controller"; } @@ -721,6 +839,7 @@ static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) aic->pool_base = 0x200; aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; aic->check_sram = true; + aic->has_dma = true; } static const TypeInfo aspeed_2500_i2c_info = { @@ -753,6 +872,7 @@ static void aspeed_2600_i2c_class_init(ObjectClass *klass, void *data) aic->pool_size = 0x200; aic->pool_base = 0xC00; aic->bus_pool_base = aspeed_2600_i2c_bus_pool_base; + aic->has_dma = true; } static const TypeInfo aspeed_2600_i2c_info = { From patchwork Mon Dec 16 11:08:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181678 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4172977ile; Mon, 16 Dec 2019 03:22:12 -0800 (PST) X-Google-Smtp-Source: APXvYqwagFEl194sRuQfuRfV8Af3MGq6K2SdNcTksO8tDVZB8etWKymDFF1eF8rkYM7omyG8/57D X-Received: by 2002:aed:3044:: with SMTP id 62mr17408988qte.61.1576495331956; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/34] aspeed/i2c: Add trace events Date: Mon, 16 Dec 2019 11:08:37 +0000 Message-Id: <20191216110904.30815-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32b X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Tested-by: Jae Hyun Yoo Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-6-clg@kaod.org Signed-off-by: Peter Maydell --- hw/i2c/aspeed_i2c.c | 93 ++++++++++++++++++++++++++++++++++++++------- hw/i2c/trace-events | 9 +++++ 2 files changed, 89 insertions(+), 13 deletions(-) -- 2.20.1 diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 030d9c56be6..2da04a4bff3 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -28,6 +28,7 @@ #include "hw/i2c/aspeed_i2c.h" #include "hw/irq.h" #include "hw/qdev-properties.h" +#include "trace.h" /* I2C Global Register */ @@ -158,6 +159,13 @@ static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus) { AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); + trace_aspeed_i2c_bus_raise_interrupt(bus->intr_status, + bus->intr_status & I2CD_INTR_TX_NAK ? "nak|" : "", + bus->intr_status & I2CD_INTR_TX_ACK ? "ack|" : "", + bus->intr_status & I2CD_INTR_RX_DONE ? "done|" : "", + bus->intr_status & I2CD_INTR_NORMAL_STOP ? "normal|" : "", + bus->intr_status & I2CD_INTR_ABNORMAL ? "abnormal" : ""); + bus->intr_status &= bus->intr_ctrl; if (bus->intr_status) { bus->controller->intr_status |= 1 << bus->id; @@ -170,41 +178,57 @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset, { AspeedI2CBus *bus = opaque; AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); + uint64_t value = -1; switch (offset) { case I2CD_FUN_CTRL_REG: - return bus->ctrl; + value = bus->ctrl; + break; case I2CD_AC_TIMING_REG1: - return bus->timing[0]; + value = bus->timing[0]; + break; case I2CD_AC_TIMING_REG2: - return bus->timing[1]; + value = bus->timing[1]; + break; case I2CD_INTR_CTRL_REG: - return bus->intr_ctrl; + value = bus->intr_ctrl; + break; case I2CD_INTR_STS_REG: - return bus->intr_status; + value = bus->intr_status; + break; case I2CD_POOL_CTRL_REG: - return bus->pool_ctrl; + value = bus->pool_ctrl; + break; case I2CD_BYTE_BUF_REG: - return bus->buf; + value = bus->buf; + break; case I2CD_CMD_REG: - return bus->cmd | (i2c_bus_busy(bus->bus) << 16); + value = bus->cmd | (i2c_bus_busy(bus->bus) << 16); + break; case I2CD_DMA_ADDR: if (!aic->has_dma) { qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); - return -1; + break; } - return bus->dma_addr; + value = bus->dma_addr; + break; case I2CD_DMA_LEN: if (!aic->has_dma) { qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); - return -1; + break; } - return bus->dma_len; + value = bus->dma_len; + break; + default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); - return -1; + value = -1; + break; } + + trace_aspeed_i2c_bus_read(bus->id, offset, size, value); + return value; } static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state) @@ -246,6 +270,9 @@ static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start) for (i = pool_start; i < I2CD_POOL_TX_COUNT(bus->pool_ctrl); i++) { uint8_t *pool_base = aic->bus_pool_base(bus); + trace_aspeed_i2c_bus_send("BUF", i + 1, + I2CD_POOL_TX_COUNT(bus->pool_ctrl), + pool_base[i]); ret = i2c_send(bus->bus, pool_base[i]); if (ret) { break; @@ -256,6 +283,7 @@ static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start) while (bus->dma_len) { uint8_t data; aspeed_i2c_dma_read(bus, &data); + trace_aspeed_i2c_bus_send("DMA", bus->dma_len, bus->dma_len, data); ret = i2c_send(bus->bus, data); if (ret) { break; @@ -263,6 +291,7 @@ static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start) } bus->cmd &= ~I2CD_TX_DMA_ENABLE; } else { + trace_aspeed_i2c_bus_send("BYTE", pool_start, 1, bus->buf); ret = i2c_send(bus->bus, bus->buf); } @@ -281,6 +310,9 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) for (i = 0; i < I2CD_POOL_RX_SIZE(bus->pool_ctrl); i++) { pool_base[i] = i2c_recv(bus->bus); + trace_aspeed_i2c_bus_recv("BUF", i + 1, + I2CD_POOL_RX_SIZE(bus->pool_ctrl), + pool_base[i]); } /* Update RX count */ @@ -294,6 +326,7 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) MemTxResult result; data = i2c_recv(bus->bus); + trace_aspeed_i2c_bus_recv("DMA", bus->dma_len, bus->dma_len, data); result = address_space_write(&s->dram_as, bus->dma_addr, MEMTXATTRS_UNSPECIFIED, &data, 1); if (result != MEMTX_OK) { @@ -307,6 +340,7 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) bus->cmd &= ~I2CD_RX_DMA_ENABLE; } else { data = i2c_recv(bus->bus); + trace_aspeed_i2c_bus_recv("BYTE", 1, 1, bus->buf); bus->buf = (data & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT; } } @@ -364,6 +398,33 @@ static bool aspeed_i2c_check_sram(AspeedI2CBus *bus) return true; } +static void aspeed_i2c_bus_cmd_dump(AspeedI2CBus *bus) +{ + g_autofree char *cmd_flags; + uint32_t count; + + if (bus->cmd & (I2CD_RX_BUFF_ENABLE | I2CD_RX_BUFF_ENABLE)) { + count = I2CD_POOL_TX_COUNT(bus->pool_ctrl); + } else if (bus->cmd & (I2CD_RX_DMA_ENABLE | I2CD_RX_DMA_ENABLE)) { + count = bus->dma_len; + } else { /* BYTE mode */ + count = 1; + } + + cmd_flags = g_strdup_printf("%s%s%s%s%s%s%s%s%s", + bus->cmd & I2CD_M_START_CMD ? "start|" : "", + bus->cmd & I2CD_RX_DMA_ENABLE ? "rxdma|" : "", + bus->cmd & I2CD_TX_DMA_ENABLE ? "txdma|" : "", + bus->cmd & I2CD_RX_BUFF_ENABLE ? "rxbuf|" : "", + bus->cmd & I2CD_TX_BUFF_ENABLE ? "txbuf|" : "", + bus->cmd & I2CD_M_TX_CMD ? "tx|" : "", + bus->cmd & I2CD_M_RX_CMD ? "rx|" : "", + bus->cmd & I2CD_M_S_RX_CMD_LAST ? "last|" : "", + bus->cmd & I2CD_M_STOP_CMD ? "stop" : ""); + + trace_aspeed_i2c_bus_cmd(bus->cmd, cmd_flags, count, bus->intr_status); +} + /* * The state machine needs some refinement. It is only used to track * invalid STOP commands for the moment. @@ -379,6 +440,10 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) return; } + if (trace_event_get_state_backends(TRACE_ASPEED_I2C_BUS_CMD)) { + aspeed_i2c_bus_cmd_dump(bus); + } + if (bus->cmd & I2CD_M_START_CMD) { uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ? I2CD_MSTARTR : I2CD_MSTART; @@ -465,6 +530,8 @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); bool handle_rx; + trace_aspeed_i2c_bus_write(bus->id, offset, size, value); + switch (offset) { case I2CD_FUN_CTRL_REG: if (value & I2CD_SLAVE_EN) { diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events index e1c810d5bd0..08db8fa6892 100644 --- a/hw/i2c/trace-events +++ b/hw/i2c/trace-events @@ -5,3 +5,12 @@ i2c_event(const char *event, uint8_t address) "%s(addr:0x%02x)" i2c_send(uint8_t address, uint8_t data) "send(addr:0x%02x) data:0x%02x" i2c_recv(uint8_t address, uint8_t data) "recv(addr:0x%02x) data:0x%02x" + +# aspeed_i2c.c + +aspeed_i2c_bus_cmd(uint32_t cmd, const char *cmd_flags, uint32_t count, uint32_t intr_status) "handling cmd=0x%x %s count=%d intr=0x%x" +aspeed_i2c_bus_raise_interrupt(uint32_t intr_status, const char *str1, const char *str2, const char *str3, const char *str4, const char *str5) "handled intr=0x%x %s%s%s%s%s" +aspeed_i2c_bus_read(uint32_t busid, uint64_t offset, unsigned size, uint64_t value) "bus[%d]: To 0x%" PRIx64 " of size %u: 0x%" PRIx64 +aspeed_i2c_bus_write(uint32_t busid, uint64_t offset, unsigned size, uint64_t value) "bus[%d]: To 0x%" PRIx64 " of size %u: 0x%" PRIx64 +aspeed_i2c_bus_send(const char *mode, int i, int count, uint8_t byte) "%s send %d/%d 0x%02x" +aspeed_i2c_bus_recv(const char *mode, int i, int count, uint8_t byte) "%s recv %d/%d 0x%02x" From patchwork Mon Dec 16 11:08:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181681 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4173362ile; Mon, 16 Dec 2019 03:22:37 -0800 (PST) X-Google-Smtp-Source: APXvYqyDfcONY1t579u+g60Wn5sluBzfnsonjRGRDMlbCjF3NQwuOG2wp871Ys6w963ekQT0Bhga X-Received: by 2002:a9d:150:: with SMTP id 74mr29288841otu.149.1576495357719; Mon, 16 Dec 2019 03:22:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576495357; cv=none; d=google.com; s=arc-20160816; b=F1WQjDb1O7m01ThRv6CB4joOZAP1FR0AcmUlfrbI5BOuxvKDpdxmwFmlI5S5oLdpfE UwBeceXtmQ6Br6AqR4FgA6ikmuUcKGjeCDGwL5GSjVs4T0Sm1EzxQ35++uMlNZ3vAYRK kzgdzjhylLhylA5iurNF2dFTdcSGIyJzSQ5hck3xzV3X/Mqqi2CiXSKRONMsFVpQZ+p2 8YdSy5rQkNLAqQU0+8+Oxi8cwKaQNHGFl+QE1vPuUWeAEDBSMtfF5rHKmKywW6E26AiC suJ9KJw1X4jDFqg9rTUKD0P+2yJlQLSFnABFKL+Oi/JR7sCyxUD5Pzc6Tln45QCrJ/sB 1edw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xjn8RJQ0vY8rUfMNnaKgorm1b3kbGVHvXOz31kMfCJA=; b=wa45vgExYNNs7PbwV/x/8EPYSqcQrpnKhaVT/yqKaKld5yeH50zucoQajq5+L1A6Ad fH/+TSl+07RQJvU4eQ6NytMnmqnh/+LWB2eVGvzKpDwAaC+XEXchzcANhIpkPW4GcbRB /gzsqZtXK9tKooaV4xQRa+aA9Ph176NlaBAElMHxRi0xzH47LVjiKWSYK804Fn9lOgc9 SGtciub8z0jsyreoLENnjIMqF+ZiKS/V2xnwENRxAivgK2tvgy++OxhzvxPFSxOCwhMc lWWqwb5gh35ZN4blg8ui0k1i5BOE909dQzgoiGL3IS8ZX0byvF+7EiwoHuWZqJmxSwQV ZTig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nIvVcVJ8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/34] aspeed/sdmc: Make ast2600 default 1G Date: Mon, 16 Dec 2019 11:08:38 +0000 Message-Id: <20191216110904.30815-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley Most boards have this much. Reviewed-by: Cédric Le Goater Reviewed-by: Alex Bennée Signed-off-by: Joel Stanley Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-7-clg@kaod.org Signed-off-by: Peter Maydell --- hw/misc/aspeed_sdmc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index f3a63a2e01d..2df3244b53c 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -208,10 +208,10 @@ static int ast2600_rambits(AspeedSDMCState *s) } /* use a common default */ - warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 512M", + warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 1024M", s->ram_size); - s->ram_size = 512 << 20; - return ASPEED_SDMC_AST2600_512MB; + s->ram_size = 1024 << 20; + return ASPEED_SDMC_AST2600_1024MB; } static void aspeed_sdmc_reset(DeviceState *dev) From patchwork Mon Dec 16 11:08:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181676 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4170986ile; Mon, 16 Dec 2019 03:20:09 -0800 (PST) X-Google-Smtp-Source: APXvYqxpFD68nQ/YXHTZTY+k6gOsbuU3bZ6kax8flIWXLk6LLWTZvntMh9ELP7szRfiaJJ8RgZ/6 X-Received: by 2002:ac8:7b9b:: with SMTP id p27mr24291920qtu.2.1576495209453; Mon, 16 Dec 2019 03:20:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576495209; cv=none; d=google.com; s=arc-20160816; b=l6GaCkmvXSRfwPonwG3wdsf/bQpYFv+Qel78rxeLdkYbvmiNOjJNsCf8dGo2+KXLPy l1LWleIUYuqlFA6fTnh+mgGzjMMhV49f6Cxia952aogzvtXQPrvYqUoXwI9k8TVBuDVh V8R6h6WJHv/UO/w8+mfqRA9gHgB+M1of9oE+HkUzpsP2YQ5vYLlcdu4E/cazGAUXyC/g pfNWYwSvWYKK7HAqerKNjOoZPpE1Z6OuagGF1l2oCrrpGkWGJ0JhCfgiOuFIdXAT0IFe tSYqRGAXYrqSlqzPNqwHmrjldLHaOiKQeChFsXFJ3YDlrtWYv5yai6ElC7a3Z9rHXV5l LwEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QD+79veTer7FPiPBdF+SAJ8aBHWDVP6IlE9SRsgpnIk=; b=ZdlKs3meSloyFAjKOsDrM3xEuTCHNsPj6kMkQ150H+QH0kDYY5ahW1XmHPPvTJGGMd gO/7QJfVg8NAHaeX720MCAgsvkcmLlU+RzBjsZqrFEWwLwhnL/Gyo1CHcMq963wMIMhW mKIDpzPUPQZJ3yg1kdMY+5GlUtV8FjXE5uF9dNuurLytw2yGsUCA36pL6rIBVrbNw1MS 3s2SzXi+2qESuhUFuH/I2KGMlwwvdLI/QitehLaC+HULG8A2m9Xyjfh4n0KhBvl0E3x4 bj6MzRWOdKJYWygu9L9r5YnWwF09vlsFZqcM7TOGEpt+ibFR7Qx2LdR2TJ4o48kERRs/ FrVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cDIr5UjB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/34] aspeed/scu: Fix W1C behavior Date: Mon, 16 Dec 2019 11:08:39 +0000 Message-Id: <20191216110904.30815-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley This models the clock write one to clear registers, and fixes up some incorrect behavior in all of the write to clear registers. There was also a typo in one of the register definitions. Reviewed-by: Cédric Le Goater Reviewed-by: Alex Bennée Signed-off-by: Joel Stanley Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-8-clg@kaod.org [clg: checkpatch.pl fixes ] Signed-off-by: Cédric Le Goater Signed-off-by: Peter Maydell --- hw/misc/aspeed_scu.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) -- 2.20.1 diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 717509bc546..f62fa25e347 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -98,7 +98,7 @@ #define AST2600_CLK_STOP_CTRL TO_REG(0x80) #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84) #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90) -#define AST2600_CLK_STOP_CTR2L_CLR TO_REG(0x94) +#define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94) #define AST2600_SDRAM_HANDSHAKE TO_REG(0x100) #define AST2600_HPLL_PARAM TO_REG(0x200) #define AST2600_HPLL_EXT TO_REG(0x204) @@ -532,11 +532,13 @@ static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset, return s->regs[reg]; } -static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, uint64_t data, - unsigned size) +static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, + uint64_t data64, unsigned size) { AspeedSCUState *s = ASPEED_SCU(opaque); int reg = TO_REG(offset); + /* Truncate here so bitwise operations below behave as expected */ + uint32_t data = data64; if (reg >= ASPEED_AST2600_SCU_NR_REGS) { qemu_log_mask(LOG_GUEST_ERROR, @@ -563,15 +565,22 @@ static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, uint64_t data, /* fall through */ case AST2600_SYS_RST_CTRL: case AST2600_SYS_RST_CTRL2: + case AST2600_CLK_STOP_CTRL: + case AST2600_CLK_STOP_CTRL2: /* W1S (Write 1 to set) registers */ s->regs[reg] |= data; return; case AST2600_SYS_RST_CTRL_CLR: case AST2600_SYS_RST_CTRL2_CLR: + case AST2600_CLK_STOP_CTRL_CLR: + case AST2600_CLK_STOP_CTRL2_CLR: case AST2600_HW_STRAP1_CLR: case AST2600_HW_STRAP2_CLR: - /* W1C (Write 1 to clear) registers */ - s->regs[reg] &= ~data; + /* + * W1C (Write 1 to clear) registers are offset by one address from + * the data register + */ + s->regs[reg - 1] &= ~data; return; case AST2600_RNG_DATA: From patchwork Mon Dec 16 11:08:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181684 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4175095ile; Mon, 16 Dec 2019 03:24:22 -0800 (PST) X-Google-Smtp-Source: APXvYqwJdXiQL1/QM5PQu7sVyFrLf1zOj5XsL/pNqUubGqGppx6zXlDnBJaOXW83O2fARKlq0jWg X-Received: by 2002:a9d:73c8:: with SMTP id m8mr32346172otk.34.1576495462291; Mon, 16 Dec 2019 03:24:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576495462; cv=none; d=google.com; s=arc-20160816; b=DI6VL/u4BhPEW0P725VIerO8wKTPL26wAyu5yYuXTKIeph8jouPkvGkOItybuer1q7 7IjTp0XUDIZXVoPvbGEhRiLj7huIf1UHvm0CWXhfc+S9ZlEZzv3EsxGrjAkq5lZQRmfg HAHkrQd5dgg6RREpT2B4J+ua2yIz5Cw5mvLj2IdjyuWxREyQtmLndXS2/S3ib8APlXvJ 90LwMxaWhvJ5wwnVZMJJkPlrvPz03Th4gCTKkSv/t4mTDSFhd+GWlf2FR0IdnF9PRFRU aydyI4JSY+JpyP5YBSmcYpMoUEm6qAzAk3a93SnOOyZ2y9u7WqfHDkpaEYR9en2Ik6+A IAlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=INEC+O3trc34/sQ9VXKjuFm8nPKS5N+4sZ+l5CuQdRo=; b=gIST+XFRzR9Qxu6YyHONsutaShW8jK9JVvA1yzkt4pSDwLyjB8tPCYHOMFcHdeMe52 RM8s9ssNo1IJpgBn6neWOLZ2sOH9UkvqaZZkMFfoFtXlvLD4hOF6BCtp1i+qxsFh4414 LgaKp9sFofgf0CtDukgVJ8kUK/ygp60zMQHZayW8vmzp/kEMkR/+kKqJ+DXXvLhxoazD py6ylXtTGVq3LLW6tDwEAs85NcHVuXv9BTVk+fKAb4LISYO11UAxiB3sj7mAaqQ4b0Fy 2AvxfnKDGPBDsDUT4gHPVIrrGBuP0tjP0nsQ43QScWRMNVvIsfBoP1ANbhFUWxS70sXp 97Uw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lh1e8t1V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/34] watchdog/aspeed: Improve watchdog timeout message Date: Mon, 16 Dec 2019 11:08:40 +0000 Message-Id: <20191216110904.30815-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley Users benefit from knowing which watchdog timer has expired. The address of the watchdog's registers unambiguously indicates which has expired, so log that. Reviewed-by: Cédric Le Goater Reviewed-by: Alex Bennée Signed-off-by: Joel Stanley Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-9-clg@kaod.org Signed-off-by: Peter Maydell --- hw/watchdog/wdt_aspeed.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index 145be6f99ce..d283d07d654 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -219,7 +219,8 @@ static void aspeed_wdt_timer_expired(void *dev) return; } - qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n"); + qemu_log_mask(CPU_LOG_RESET, "Watchdog timer %" HWADDR_PRIx " expired.\n", + s->iomem.addr); watchdog_perform_action(); timer_del(s->timer); } From patchwork Mon Dec 16 11:08:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181686 Delivered-To: patch@linaro.org Received: by 2002:ac9:44c4:0:0:0:0:0 with SMTP id t4csp4172647och; Mon, 16 Dec 2019 03:24:42 -0800 (PST) X-Google-Smtp-Source: APXvYqziVhGYSLcli2q/8RofOt9CTWrKcOUQVtv8dYHgA/UTyrVebyPD2QfNpI2nsuvmF0oZEqQu X-Received: by 2002:a9d:5c84:: with SMTP id a4mr28708094oti.305.1576495482656; Mon, 16 Dec 2019 03:24:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576495482; cv=none; d=google.com; s=arc-20160816; b=zL8FhXDeS7hJaEViaraWy5IQoJRtp7TX6GoKaFdRidUBt+pRa8BztGb58RzAc+JE+u HbZwvSfpRHhHuZelPu60hr0h0HS3HKVmTxWfYpbQ1yLVGs5LgaD0CB8o9PdNEch3S0Tn N/myY8SyPrA1NKJsC9pxc0ahYgkhuI3I4BPTyWyK5osznqtUW3sToFo+4gVLC/Hi4dT7 XSLYTFEbklpQWw2YyzBumlNN+tgEEltX7nOw8VpIL+n0bvnv6uiHDnzreE52BTYAvPje CI02wk5MZlsXqDyxNZPurOFce9KvJ8by3uzFMz0dGfSdFrxQfl45X8nIUbmScPgCyCrg lDdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=sAVMne6xljKCCSIVb7x6KZ8Mn9NcByWXcsU8hgdMM68=; b=C1yAP0mEDny6S7KF/69vkbmVrZ01Rh5S5/MGOiyOTtiUhiMQWU4d6gMEQ+t7D6vby5 1bbOmvRNg060NW9xglBj9Lsd36heKY6GIYn6SwgDRR0lpaDGdWycD6jDa0u/Gq7CzEcx 0Dr3G7MaIteTyXu1o/M+Drv8vhIqbPAtXqeV7ZlmMPZ+0yLjRzchVvyTt1aY2kQ5muNI uOfUfJ38fyplX0jIIp4Ou+m85t1xg220lDLn3cuC5Ck6XLwUrmmIaPxRE7orc/LKSZKN UaJcK2E35t/OzOwSidUY5svmiezlNH3P7dke4hkesWbxJlSVeRVqLj6P1ttlKMAJT1GP u4HA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WwfSYe0c; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/34] watchdog/aspeed: Fix AST2600 frequency behaviour Date: Mon, 16 Dec 2019 11:08:41 +0000 Message-Id: <20191216110904.30815-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::332 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley The AST2600 control register sneakily changed the meaning of bit 4 without anyone noticing. It no longer controls the 1MHz vs APB clock select, and instead always runs at 1MHz. The AST2500 was always 1MHz too, but it retained bit 4, making it read only. We can model both using the same fixed 1MHz calculation. Fixes: 6b2b2a703cad ("hw: wdt_aspeed: Add AST2600 support") Reviewed-by: Cédric Le Goater Reviewed-by: Alex Bennée Signed-off-by: Joel Stanley Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-10-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/watchdog/wdt_aspeed.h | 1 + hw/watchdog/wdt_aspeed.c | 21 +++++++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h index dfedd7662dd..819c22993a6 100644 --- a/include/hw/watchdog/wdt_aspeed.h +++ b/include/hw/watchdog/wdt_aspeed.h @@ -47,6 +47,7 @@ typedef struct AspeedWDTClass { uint32_t ext_pulse_width_mask; uint32_t reset_ctrl_reg; void (*reset_pulse)(AspeedWDTState *s, uint32_t property); + void (*wdt_reload)(AspeedWDTState *s); } AspeedWDTClass; #endif /* WDT_ASPEED_H */ diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index d283d07d654..122aa8daaad 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -93,11 +93,11 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) } -static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk) +static void aspeed_wdt_reload(AspeedWDTState *s) { uint64_t reload; - if (pclk) { + if (!(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)) { reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND, s->pclk_freq); } else { @@ -109,6 +109,16 @@ static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk) } } +static void aspeed_wdt_reload_1mhz(AspeedWDTState *s) +{ + uint64_t reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL; + + if (aspeed_wdt_is_enabled(s)) { + timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload); + } +} + + static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, unsigned size) { @@ -130,13 +140,13 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, case WDT_RESTART: if ((data & 0xFFFF) == WDT_RESTART_MAGIC) { s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE]; - aspeed_wdt_reload(s, !(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)); + awc->wdt_reload(s); } break; case WDT_CTRL: if (enable && !aspeed_wdt_is_enabled(s)) { s->regs[WDT_CTRL] = data; - aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK)); + awc->wdt_reload(s); } else if (!enable && aspeed_wdt_is_enabled(s)) { s->regs[WDT_CTRL] = data; timer_del(s->timer); @@ -283,6 +293,7 @@ static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data) awc->offset = 0x20; awc->ext_pulse_width_mask = 0xff; awc->reset_ctrl_reg = SCU_RESET_CONTROL1; + awc->wdt_reload = aspeed_wdt_reload; } static const TypeInfo aspeed_2400_wdt_info = { @@ -317,6 +328,7 @@ static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data) awc->ext_pulse_width_mask = 0xfffff; awc->reset_ctrl_reg = SCU_RESET_CONTROL1; awc->reset_pulse = aspeed_2500_wdt_reset_pulse; + awc->wdt_reload = aspeed_wdt_reload_1mhz; } static const TypeInfo aspeed_2500_wdt_info = { @@ -336,6 +348,7 @@ static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data) awc->ext_pulse_width_mask = 0xfffff; /* TODO */ awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1; awc->reset_pulse = aspeed_2500_wdt_reset_pulse; + awc->wdt_reload = aspeed_wdt_reload_1mhz; } static const TypeInfo aspeed_2600_wdt_info = { From patchwork Mon Dec 16 11:08:42 2019 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/34] aspeed/smc: Restore default AHB window mapping at reset Date: Mon, 16 Dec 2019 11:08:42 +0000 Message-Id: <20191216110904.30815-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The current model only restores the Segment Register values but leaves the previous CS mapping behind. Introduce a helper setting the register value and mapping the region at the requested address. Use this helper when a Segment register is set and at reset. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-11-clg@kaod.org Signed-off-by: Peter Maydell --- hw/ssi/aspeed_smc.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) -- 2.20.1 diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index f0c7bbbad30..955ec21852a 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -475,10 +475,26 @@ static bool aspeed_smc_flash_overlap(const AspeedSMCState *s, return false; } +static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs, + uint64_t regval) +{ + AspeedSMCFlash *fl = &s->flashes[cs]; + AspeedSegments seg; + + s->ctrl->reg_to_segment(s, regval, &seg); + + memory_region_transaction_begin(); + memory_region_set_size(&fl->mmio, seg.size); + memory_region_set_address(&fl->mmio, seg.addr - s->ctrl->flash_window_base); + memory_region_set_enabled(&fl->mmio, true); + memory_region_transaction_commit(); + + s->regs[R_SEG_ADDR0 + cs] = regval; +} + static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, uint64_t new) { - AspeedSMCFlash *fl = &s->flashes[cs]; AspeedSegments seg; s->ctrl->reg_to_segment(s, new, &seg); @@ -529,13 +545,7 @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, aspeed_smc_flash_overlap(s, &seg, cs); /* All should be fine now to move the region */ - memory_region_transaction_begin(); - memory_region_set_size(&fl->mmio, seg.size); - memory_region_set_address(&fl->mmio, seg.addr - s->ctrl->flash_window_base); - memory_region_set_enabled(&fl->mmio, true); - memory_region_transaction_commit(); - - s->regs[R_SEG_ADDR0 + cs] = new; + aspeed_smc_flash_set_segment_region(s, cs, new); } static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr, @@ -897,10 +907,10 @@ static void aspeed_smc_reset(DeviceState *d) qemu_set_irq(s->cs_lines[i], true); } - /* setup default segment register values for all */ + /* setup the default segment register values and regions for all */ for (i = 0; i < s->ctrl->max_slaves; ++i) { - s->regs[R_SEG_ADDR0 + i] = - s->ctrl->segment_to_reg(s, &s->ctrl->segments[i]); + aspeed_smc_flash_set_segment_region(s, i, + s->ctrl->segment_to_reg(s, &s->ctrl->segments[i])); } /* HW strapping flash type for the AST2600 controllers */ From patchwork Mon Dec 16 11:08:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181692 Delivered-To: patch@linaro.org Received: by 2002:ac9:44c4:0:0:0:0:0 with SMTP id t4csp4176870och; Mon, 16 Dec 2019 03:29:29 -0800 (PST) X-Google-Smtp-Source: APXvYqxie/v+U2bATgpLkHUL2DErhD2sV9MTMiomE6H4pETqGA8N+OoiLukV74Q40r1QBj6k6uQL X-Received: by 2002:a05:6830:145:: with SMTP id j5mr30143765otp.242.1576495769859; Mon, 16 Dec 2019 03:29:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576495769; cv=none; d=google.com; s=arc-20160816; b=zSSe95x62G+xpLoWUkij3vuEHg84jf81gfAeuOE7SnuirwuwVJUtJWpNVCUfacV7oL ZeNDkEhQHvvhPdcd20HWIhIOXy1XUSa0JGkutOl7xzHlQipt6xlQZHI32/qLaSACjlww YRs/YGtbb128pWwm41lcAVdY+DbK2w0lIlbdH4BXprhOl9J7t+ucHnM652yp2JW6DzLr isazXlpUChBM//DqaU+JAo7QihJzHjr+Vg6Qf97ohZwtOx/RhciwJGqAVvaIwx0yfKeF ghH6NH4ZBqIpkSRIAOTDk1+iIryd6bD2wI3hGfUxzFJFmqtyQ21LHqEz0yyZzGbXyKDL 4kIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8rDgs8l8yhYpP9GCvm5KtL7CxF0GTpM1OtN2KNG9tUw=; b=0qKlJdUE9VqRbE41uGUapYNvFzrf5Qfp++oaXVHvtxqyEkZgfEvC/7ypOmgh1xtp4O 1Hp4gY8hqfY5TOvvQ0MfA6SfUYVPEl41i7aGtNPtWpaBgh02wxA4zUZHbX1Vh3X7o/5J wKFI/8J/1m5VR5rIBoMaG71+1PoAMpgyJJNK7WohPxPSeXpYOv5kZeztc8Vxk0X40+i0 pSuFgEjjsb4LbHPPpDP1uJ+KxJOmOxPwPKLClrOUax/VWmXQyA4zxz5+BrxU/nDmdShe Ir3V19PWAIlhrEi3qw4i48yr8j26aV7xcoU0SUmJB69TjukygRqvcrdJ6FZPh6iBcxcD G1rA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qfBbRMXQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/34] aspeed/smc: Do not map disabled segment on the AST2600 Date: Mon, 16 Dec 2019 11:08:43 +0000 Message-Id: <20191216110904.30815-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The segments can be disabled on the AST2600 (zero register value). CS0 is open by default but not the other CS. This is closing the access to the flash device in user mode and forbids scanning. In the model, check the segment size and disable the associated region when the value is zero. Fixes: bcaa8ddd081c ("aspeed/smc: Add AST2600 support") Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-12-clg@kaod.org Signed-off-by: Peter Maydell --- hw/ssi/aspeed_smc.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) -- 2.20.1 diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 955ec21852a..86cadbe4cc0 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -444,8 +444,13 @@ static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s, uint32_t start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK; uint32_t end_offset = reg & AST2600_SEG_ADDR_MASK; - seg->addr = s->ctrl->flash_window_base + start_offset; - seg->size = end_offset + MiB - start_offset; + if (reg) { + seg->addr = s->ctrl->flash_window_base + start_offset; + seg->size = end_offset + MiB - start_offset; + } else { + seg->addr = s->ctrl->flash_window_base; + seg->size = 0; + } } static bool aspeed_smc_flash_overlap(const AspeedSMCState *s, @@ -486,7 +491,7 @@ static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs, memory_region_transaction_begin(); memory_region_set_size(&fl->mmio, seg.size); memory_region_set_address(&fl->mmio, seg.addr - s->ctrl->flash_window_base); - memory_region_set_enabled(&fl->mmio, true); + memory_region_set_enabled(&fl->mmio, !!seg.size); memory_region_transaction_commit(); s->regs[R_SEG_ADDR0 + cs] = regval; @@ -526,8 +531,9 @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, } /* Keep the segment in the overall flash window */ - if (seg.addr + seg.size <= s->ctrl->flash_window_base || - seg.addr > s->ctrl->flash_window_base + s->ctrl->flash_window_size) { + if (seg.size && + (seg.addr + seg.size <= s->ctrl->flash_window_base || + seg.addr > s->ctrl->flash_window_base + s->ctrl->flash_window_size)) { qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment for CS%d is invalid : " "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n", s->ctrl->name, cs, seg.addr, seg.addr + seg.size); From patchwork Mon Dec 16 11:08:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181697 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4182983ile; Mon, 16 Dec 2019 03:32:29 -0800 (PST) X-Google-Smtp-Source: APXvYqxvo3aRIK7xHkDrKmvaHyPGQyHnylG9bhKSr8+WF/y2Qq+cfbVoK5lGyD2zNpKAbsBginYM X-Received: by 2002:a05:6830:1bd5:: with SMTP id v21mr4262320ota.154.1576495948988; Mon, 16 Dec 2019 03:32:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576495948; cv=none; d=google.com; s=arc-20160816; b=OMEG36DOSFm820Uw9VZd6wBKowso4hRdpmAy2guBbPgQ0cEjNspIhUyJAMDAVD2P4R BHUAb+OMCfrP5B3EPvhZU/BWsjA5Q0rz4QrhX4k/HI5u23Ag3opeG3cbCFV+16WzuY7P e+9UEZWlYPmJk1cIJPyPYivngIOX9B+5LapBDr4YafJXm92h3WdzagPwWRqBjJ9bKkMZ jme2vS8ahzJIXTZhcPQdhghkjzmGlFeH3MqOAYB3j/fh/RcGOpd9gzkpZgwSQ/kOW2G+ BtEWL3/3PWoJx18DqSNgijtA2MOdAqzW8ZKesCEWwv4ITE3e4A0wMizNHFxTLnX4lVlA UdzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ibgl5PVRhP+gnfhMETg2bP2CZS3sDh+cN9nWx6vn2LY=; b=046Q8hJ73QVQqQMswTLV4gQi/AIpnB/Wq+fhDQaaWRZz0BbU1/mlEPJxednKv+Fcau gp7Y8s8+XAGiFLgYBlEc9XhCHmeAAuGpVuaxY6x3VXuFKSubCdFDWgNjf+BYdiP5zGZz BWjR/MzYTgbXJLyoZTjA7gWXIcwgqZ7d1qTlP3Zf2G4Ykxf0iiWW6OCOUuZM0BqARsSC cPRe1KI31uiaqO0Wx1RPH7T2r5BqfnyhRqj42W0hQVE9dpEJge2tcRqBXbUVmnSKWNwC eCLexBrKzoC5Ib9pOTBJmyYkT00nuO+RBjUdaX6nkUF34KRBFiy3P6OdmwYv/6QAKuII ML5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cL7s36FY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/34] aspeed/smc: Add AST2600 timings registers Date: Mon, 16 Dec 2019 11:08:44 +0000 Message-Id: <20191216110904.30815-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::432 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Each CS has its own Read Timing Compensation Register on newer SoCs. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-13-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/ssi/aspeed_smc.h | 1 + hw/ssi/aspeed_smc.c | 17 ++++++++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 684d16e3361..6fbbb238f15 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -40,6 +40,7 @@ typedef struct AspeedSMCController { uint8_t r_ce_ctrl; uint8_t r_ctrl0; uint8_t r_timings; + uint8_t nregs_timings; uint8_t conf_enable_w0; uint8_t max_slaves; const AspeedSegments *segments; diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 86cadbe4cc0..7755eca3497 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -137,7 +137,7 @@ /* Checksum Calculation Result */ #define R_DMA_CHECKSUM (0x90 / 4) -/* Misc Control Register #2 */ +/* Read Timing Compensation Register */ #define R_TIMINGS (0x94 / 4) /* SPI controller registers and bits (AST2400) */ @@ -256,6 +256,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, .r_timings = R_TIMINGS, + .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, .max_slaves = 5, .segments = aspeed_segments_legacy, @@ -271,6 +272,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, .r_timings = R_TIMINGS, + .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, .max_slaves = 5, .segments = aspeed_segments_fmc, @@ -288,6 +290,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = 0xff, .r_ctrl0 = R_SPI_CTRL0, .r_timings = R_SPI_TIMINGS, + .nregs_timings = 1, .conf_enable_w0 = SPI_CONF_ENABLE_W0, .max_slaves = 1, .segments = aspeed_segments_spi, @@ -303,6 +306,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, .r_timings = R_TIMINGS, + .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, .max_slaves = 3, .segments = aspeed_segments_ast2500_fmc, @@ -320,6 +324,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, .r_timings = R_TIMINGS, + .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, .max_slaves = 2, .segments = aspeed_segments_ast2500_spi1, @@ -335,6 +340,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, .r_timings = R_TIMINGS, + .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, .max_slaves = 2, .segments = aspeed_segments_ast2500_spi2, @@ -350,6 +356,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, .r_timings = R_TIMINGS, + .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, .max_slaves = 3, .segments = aspeed_segments_ast2600_fmc, @@ -365,6 +372,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, .r_timings = R_TIMINGS, + .nregs_timings = 2, .conf_enable_w0 = CONF_ENABLE_W0, .max_slaves = 2, .segments = aspeed_segments_ast2600_spi1, @@ -380,6 +388,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, .r_timings = R_TIMINGS, + .nregs_timings = 3, .conf_enable_w0 = CONF_ENABLE_W0, .max_slaves = 3, .segments = aspeed_segments_ast2600_spi2, @@ -951,7 +960,8 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) addr >>= 2; if (addr == s->r_conf || - addr == s->r_timings || + (addr >= s->r_timings && + addr < s->r_timings + s->ctrl->nregs_timings) || addr == s->r_ce_ctrl || addr == R_INTR_CTRL || addr == R_DUMMY_DATA || @@ -1216,7 +1226,8 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, addr >>= 2; if (addr == s->r_conf || - addr == s->r_timings || + (addr >= s->r_timings && + addr < s->r_timings + s->ctrl->nregs_timings) || addr == s->r_ce_ctrl) { s->regs[addr] = value; } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) { From patchwork Mon Dec 16 11:08:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181682 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4173639ile; Mon, 16 Dec 2019 03:22:56 -0800 (PST) X-Google-Smtp-Source: APXvYqxnT5yffuo7I8JzGK0OGq6W01F68MbVAUp8GbpXygRG3urHwvAbp4lN1lD25kg8Cem7a2DR X-Received: by 2002:a9d:4f0f:: with SMTP id d15mr32348241otl.179.1576495376872; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/34] aspeed: Remove AspeedBoardConfig array and use AspeedMachineClass Date: Mon, 16 Dec 2019 11:08:45 +0000 Message-Id: <20191216110904.30815-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater AspeedBoardConfig is a redundant way to define class attributes and it complexifies the machine definition and initialization. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-14-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/arm/aspeed.h | 24 ++-- hw/arm/aspeed.c | 243 ++++++++++++++++++++++------------------ 2 files changed, 143 insertions(+), 124 deletions(-) -- 2.20.1 diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index f49bc7081e4..4423cd0cda7 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -13,19 +13,6 @@ typedef struct AspeedBoardState AspeedBoardState; -typedef struct AspeedBoardConfig { - const char *name; - const char *desc; - const char *soc_name; - uint32_t hw_strap1; - uint32_t hw_strap2; - const char *fmc_model; - const char *spi_model; - uint32_t num_cs; - void (*i2c_init)(AspeedBoardState *bmc); - uint32_t ram; -} AspeedBoardConfig; - #define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed") #define ASPEED_MACHINE(obj) \ OBJECT_CHECK(AspeedMachine, (obj), TYPE_ASPEED_MACHINE) @@ -41,7 +28,16 @@ typedef struct AspeedMachine { typedef struct AspeedMachineClass { MachineClass parent_obj; - const AspeedBoardConfig *board; + + const char *name; + const char *desc; + const char *soc_name; + uint32_t hw_strap1; + uint32_t hw_strap2; + const char *fmc_model; + const char *spi_model; + uint32_t num_cs; + void (*i2c_init)(AspeedBoardState *bmc); } AspeedMachineClass; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 028191ff36f..e34e6787430 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -167,10 +167,10 @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, } } -static void aspeed_board_init(MachineState *machine, - const AspeedBoardConfig *cfg) +static void aspeed_machine_init(MachineState *machine) { AspeedBoardState *bmc; + AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); AspeedSoCClass *sc; DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); ram_addr_t max_ram_size; @@ -182,18 +182,18 @@ static void aspeed_board_init(MachineState *machine, UINT32_MAX); object_initialize_child(OBJECT(machine), "soc", &bmc->soc, - (sizeof(bmc->soc)), cfg->soc_name, &error_abort, + (sizeof(bmc->soc)), amc->soc_name, &error_abort, NULL); sc = ASPEED_SOC_GET_CLASS(&bmc->soc); object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size", &error_abort); - object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1", + object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap1, "hw-strap1", &error_abort); - object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap2, "hw-strap2", + object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap2, "hw-strap2", &error_abort); - object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs", + object_property_set_int(OBJECT(&bmc->soc), amc->num_cs, "num-cs", &error_abort); object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus", &error_abort); @@ -230,8 +230,8 @@ static void aspeed_board_init(MachineState *machine, "max_ram", max_ram_size - ram_size); memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram); - aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort); - aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort); + aspeed_board_init_flashes(&bmc->soc.fmc, amc->fmc_model, &error_abort); + aspeed_board_init_flashes(&bmc->soc.spi[0], amc->spi_model, &error_abort); /* Install first FMC flash content as a boot rom. */ if (drive0) { @@ -255,8 +255,8 @@ static void aspeed_board_init(MachineState *machine, aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM]; aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus; - if (cfg->i2c_init) { - cfg->i2c_init(bmc); + if (amc->i2c_init) { + amc->i2c_init(bmc); } for (i = 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) { @@ -383,118 +383,141 @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) 0x60); } -static void aspeed_machine_init(MachineState *machine) -{ - AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); - - aspeed_board_init(machine, amc->board); -} - static void aspeed_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); - AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); - const AspeedBoardConfig *board = data; - mc->desc = board->desc; mc->init = aspeed_machine_init; mc->max_cpus = ASPEED_CPUS_NUM; mc->no_floppy = 1; mc->no_cdrom = 1; mc->no_parallel = 1; - if (board->ram) { - mc->default_ram_size = board->ram; - } - amc->board = board; } -static const TypeInfo aspeed_machine_type = { - .name = TYPE_ASPEED_MACHINE, - .parent = TYPE_MACHINE, - .instance_size = sizeof(AspeedMachine), - .class_size = sizeof(AspeedMachineClass), - .abstract = true, -}; - -static const AspeedBoardConfig aspeed_boards[] = { - { - .name = MACHINE_TYPE_NAME("palmetto-bmc"), - .desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)", - .soc_name = "ast2400-a1", - .hw_strap1 = PALMETTO_BMC_HW_STRAP1, - .fmc_model = "n25q256a", - .spi_model = "mx25l25635e", - .num_cs = 1, - .i2c_init = palmetto_bmc_i2c_init, - .ram = 256 * MiB, - }, { - .name = MACHINE_TYPE_NAME("ast2500-evb"), - .desc = "Aspeed AST2500 EVB (ARM1176)", - .soc_name = "ast2500-a1", - .hw_strap1 = AST2500_EVB_HW_STRAP1, - .fmc_model = "w25q256", - .spi_model = "mx25l25635e", - .num_cs = 1, - .i2c_init = ast2500_evb_i2c_init, - .ram = 512 * MiB, - }, { - .name = MACHINE_TYPE_NAME("romulus-bmc"), - .desc = "OpenPOWER Romulus BMC (ARM1176)", - .soc_name = "ast2500-a1", - .hw_strap1 = ROMULUS_BMC_HW_STRAP1, - .fmc_model = "n25q256a", - .spi_model = "mx66l1g45g", - .num_cs = 2, - .i2c_init = romulus_bmc_i2c_init, - .ram = 512 * MiB, - }, { - .name = MACHINE_TYPE_NAME("swift-bmc"), - .desc = "OpenPOWER Swift BMC (ARM1176)", - .soc_name = "ast2500-a1", - .hw_strap1 = SWIFT_BMC_HW_STRAP1, - .fmc_model = "mx66l1g45g", - .spi_model = "mx66l1g45g", - .num_cs = 2, - .i2c_init = swift_bmc_i2c_init, - .ram = 512 * MiB, - }, { - .name = MACHINE_TYPE_NAME("witherspoon-bmc"), - .desc = "OpenPOWER Witherspoon BMC (ARM1176)", - .soc_name = "ast2500-a1", - .hw_strap1 = WITHERSPOON_BMC_HW_STRAP1, - .fmc_model = "mx25l25635e", - .spi_model = "mx66l1g45g", - .num_cs = 2, - .i2c_init = witherspoon_bmc_i2c_init, - .ram = 512 * MiB, - }, { - .name = MACHINE_TYPE_NAME("ast2600-evb"), - .desc = "Aspeed AST2600 EVB (Cortex A7)", - .soc_name = "ast2600-a0", - .hw_strap1 = AST2600_EVB_HW_STRAP1, - .hw_strap2 = AST2600_EVB_HW_STRAP2, - .fmc_model = "w25q512jv", - .spi_model = "mx66u51235f", - .num_cs = 1, - .i2c_init = ast2600_evb_i2c_init, - .ram = 1 * GiB, - }, -}; - -static void aspeed_machine_types(void) +static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) { - int i; + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); - type_register_static(&aspeed_machine_type); - for (i = 0; i < ARRAY_SIZE(aspeed_boards); ++i) { - TypeInfo ti = { - .name = aspeed_boards[i].name, - .parent = TYPE_ASPEED_MACHINE, - .class_init = aspeed_machine_class_init, - .class_data = (void *)&aspeed_boards[i], - }; - type_register(&ti); + mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; + amc->soc_name = "ast2400-a1"; + amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; + amc->fmc_model = "n25q256a"; + amc->spi_model = "mx25l25635e"; + amc->num_cs = 1; + amc->i2c_init = palmetto_bmc_i2c_init; + mc->default_ram_size = 256 * MiB; +}; + +static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "Aspeed AST2500 EVB (ARM1176)"; + amc->soc_name = "ast2500-a1"; + amc->hw_strap1 = AST2500_EVB_HW_STRAP1; + amc->fmc_model = "w25q256"; + amc->spi_model = "mx25l25635e"; + amc->num_cs = 1; + amc->i2c_init = ast2500_evb_i2c_init; + mc->default_ram_size = 512 * MiB; +}; + +static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; + amc->soc_name = "ast2500-a1"; + amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; + amc->fmc_model = "n25q256a"; + amc->spi_model = "mx66l1g45g"; + amc->num_cs = 2; + amc->i2c_init = romulus_bmc_i2c_init; + mc->default_ram_size = 512 * MiB; +}; + +static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "OpenPOWER Swift BMC (ARM1176)"; + amc->soc_name = "ast2500-a1"; + amc->hw_strap1 = SWIFT_BMC_HW_STRAP1; + amc->fmc_model = "mx66l1g45g"; + amc->spi_model = "mx66l1g45g"; + amc->num_cs = 2; + amc->i2c_init = swift_bmc_i2c_init; + mc->default_ram_size = 512 * MiB; +}; + +static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; + amc->soc_name = "ast2500-a1"; + amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; + amc->fmc_model = "mx25l25635e"; + amc->spi_model = "mx66l1g45g"; + amc->num_cs = 2; + amc->i2c_init = witherspoon_bmc_i2c_init; + mc->default_ram_size = 512 * MiB; +}; + +static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; + amc->soc_name = "ast2600-a0"; + amc->hw_strap1 = AST2600_EVB_HW_STRAP1; + amc->hw_strap2 = AST2600_EVB_HW_STRAP2; + amc->fmc_model = "w25q512jv"; + amc->spi_model = "mx66u51235f"; + amc->num_cs = 1; + amc->i2c_init = ast2600_evb_i2c_init; + mc->default_ram_size = 1 * GiB; +}; + +static const TypeInfo aspeed_machine_types[] = { + { + .name = MACHINE_TYPE_NAME("palmetto-bmc"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_palmetto_class_init, + }, { + .name = MACHINE_TYPE_NAME("ast2500-evb"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_ast2500_evb_class_init, + }, { + .name = MACHINE_TYPE_NAME("romulus-bmc"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_romulus_class_init, + }, { + .name = MACHINE_TYPE_NAME("swift-bmc"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_swift_class_init, + }, { + .name = MACHINE_TYPE_NAME("witherspoon-bmc"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_witherspoon_class_init, + }, { + .name = MACHINE_TYPE_NAME("ast2600-evb"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_ast2600_evb_class_init, + }, { + .name = TYPE_ASPEED_MACHINE, + .parent = TYPE_MACHINE, + .instance_size = sizeof(AspeedMachine), + .class_size = sizeof(AspeedMachineClass), + .class_init = aspeed_machine_class_init, + .abstract = true, } -} +}; -type_init(aspeed_machine_types) +DEFINE_TYPES(aspeed_machine_types) From patchwork Mon Dec 16 11:08:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181700 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4185964ile; Mon, 16 Dec 2019 03:35:11 -0800 (PST) X-Google-Smtp-Source: APXvYqzDWxmSnu+C9JysdUAeVj7U+WBotqP0ajl8ntbbKf1UHZvXIaA4V0KIR/5l4QO0mLam9KHf X-Received: by 2002:a05:620a:2010:: with SMTP id c16mr25468633qka.386.1576496111027; Mon, 16 Dec 2019 03:35:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576496111; cv=none; d=google.com; s=arc-20160816; b=ea778c1Td1zN9jHcuoL0dAcwsc+21oaVOt1nPofOHQ3chc/sI6I/ryTzB/khLU/bLC D7FzZBzaTUSAizMhyFMc40VxnpxAv3+SNdcP7F4wBZJqZ9ZTsRtjd4kbh4oUfxnBb1Cm BTrx1HoRUZ1+WtaX8yfkT02J4vLYmXnlAlGCem0r0JYea/lnYhhIZqc/0MyDtsrIwQCo +XpkoQYQs90oIEks/kx92usCCdGPrCCVh5aHR3hK5Ih19B8TslqXTQVMCA0IPbphH175 DJtYGivSgKcDKVQGMSX0xv+c4TojabKrIyXkhjyUOJljpH0PE04IFUKFHKy2Iil5F4Ns SnwQ== ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/34] aspeed: Add support for the tacoma-bmc board Date: Mon, 16 Dec 2019 11:08:46 +0000 Message-Id: <20191216110904.30815-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The Tacoma BMC board is replacement board for the BMC of the OpenPOWER Witherspoon system. It uses a AST2600 SoC instead of a AST2500 and the I2C layout is the same as it controls the same main board. Used for HW bringup. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-15-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) -- 2.20.1 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index e34e6787430..cc06af4fbb3 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -92,6 +92,10 @@ struct AspeedBoardState { #define AST2600_EVB_HW_STRAP1 0x000000C0 #define AST2600_EVB_HW_STRAP2 0x00000003 +/* Tacoma hardware value */ +#define TACOMA_BMC_HW_STRAP1 0x00000000 +#define TACOMA_BMC_HW_STRAP2 0x00000000 + /* * The max ram region is for firmwares that scan the address space * with load/store to guess how much RAM the SoC has. @@ -363,6 +367,9 @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) AspeedSoCState *soc = &bmc->soc; uint8_t *eeprom_buf = g_malloc0(8 * 1024); + /* Bus 3: TODO bmp280@77 */ + /* Bus 3: TODO max31785@52 */ + /* Bus 3: TODO dps310@76 */ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), TYPE_PCA9552, 0x60); @@ -381,6 +388,7 @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) eeprom_buf); i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), TYPE_PCA9552, 0x60); + /* Bus 11: TODO ucd90160@64 */ } static void aspeed_machine_class_init(ObjectClass *oc, void *data) @@ -485,6 +493,22 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) mc->default_ram_size = 1 * GiB; }; +static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; + amc->soc_name = "ast2600-a0"; + amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; + amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; + amc->fmc_model = "mx66l1g45g"; + amc->spi_model = "mx66l1g45g"; + amc->num_cs = 2; + amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ + mc->default_ram_size = 1 * GiB; +}; + static const TypeInfo aspeed_machine_types[] = { { .name = MACHINE_TYPE_NAME("palmetto-bmc"), @@ -510,6 +534,10 @@ static const TypeInfo aspeed_machine_types[] = { .name = MACHINE_TYPE_NAME("ast2600-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2600_evb_class_init, + }, { + .name = MACHINE_TYPE_NAME("tacoma-bmc"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_tacoma_class_init, }, { .name = TYPE_ASPEED_MACHINE, .parent = TYPE_MACHINE, From patchwork Mon Dec 16 11:08:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181693 Delivered-To: patch@linaro.org Received: by 2002:ac9:44c4:0:0:0:0:0 with SMTP id t4csp4176988och; Mon, 16 Dec 2019 03:29:35 -0800 (PST) X-Google-Smtp-Source: APXvYqxLmnLvDnfhA0kvtZyBByFFr+S66YUKBO9Hy6GHQauIArgIlvmYOSft3S+C7yNlCwz2zA3P X-Received: by 2002:a05:6830:60f:: with SMTP id w15mr31591465oti.225.1576495775941; Mon, 16 Dec 2019 03:29:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576495775; cv=none; d=google.com; s=arc-20160816; b=S91PdPba7ZTYN0cnB2lQjfMOmbW87zWpUFvMCUaracmJ1QKvHHZkb8XacUSa1PwHz3 6UXhuWApvVk0QjS9Rh/oszath2tJvM4H4KPulB0dVzlztojTEkqFQONmfmTCaWY3JVru PB3lsA9FV/DPlMe52uZHYSmlRoS8+hP7qT+mFZUmHJEQFVJgC9hSKsdUu1cNvk4x1doA otgfwk7oi4qfB3Qr9ii0IPlWsAb6s9XtJIq1D1AYNdy8Zhj/xcv4eoOKxevz+u2/eod+ snnpiMAJjArOIRNsogvFepmZAF+k08qxhHnZhZXOeaLWODSOuYaTpEyo/Wa5BH9Xr42F OclA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cLD2Kna7vySI7JTixY4DUbJiDAp4iUXD1298DaSCR8I=; b=JOjmCynL9Tvnx3dvFMxZpqG+kKlRGt14genOt+8YPw/Ik3xWlmJviPnEn72gEu9drq ZvAg2GJ6+J9YBxY56Wz2CXjYq0vm+czEuUK4V2IFvAxem2INHPGtBtpU222OTGB5f27m 1ZZ846lot8DW8QBXrsKD65VYBAv10FG8JLw3mUbtHYrEQal3e1B/og/YSSZ1g05xuzTS /J4DKQRHkZKZsF3OkPQIXKiibWAfypFA3i9etGNlNOKaRnEn8Xf6oS/jvdKqhFPmgeSB k1iQKupxIQ4OBpm4OuL4K6w+WMtJ+6PyXK1MeFTb/mFVmNfXWckUGxY1Y2wGZQ+vxM9m s7vw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rZ0hP8tz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/34] gpio: fix memory leak in aspeed_gpio_init() Date: Mon, 16 Dec 2019 11:08:47 +0000 Message-Id: <20191216110904.30815-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: PanNengyuan Address Sanitizer shows memory leak in hw/gpio/aspeed_gpio.c:875 Reported-by: Euler Robot Signed-off-by: PanNengyuan Reviewed-by: Cédric Le Goater Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-16-clg@kaod.org Signed-off-by: Peter Maydell --- hw/gpio/aspeed_gpio.c | 1 + 1 file changed, 1 insertion(+) -- 2.20.1 diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index 7acc5fa8e29..41e11ea9b04 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -876,6 +876,7 @@ static void aspeed_gpio_init(Object *obj) pin_idx % GPIOS_PER_GROUP); object_property_add(obj, name, "bool", aspeed_gpio_get_pin, aspeed_gpio_set_pin, NULL, NULL, NULL); + g_free(name); } } From patchwork Mon Dec 16 11:08:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181690 Delivered-To: patch@linaro.org Received: by 2002:ac9:44c4:0:0:0:0:0 with SMTP id t4csp4175090och; Mon, 16 Dec 2019 03:27:26 -0800 (PST) X-Google-Smtp-Source: APXvYqxUKf7ov+jpFkfeNekxyWYneY5NScl1irkA8XcpYe2PuAt5nQFJh03xD1/VowqCA8kvc+W8 X-Received: by 2002:a05:6830:13da:: with SMTP id e26mr31616082otq.302.1576495646272; Mon, 16 Dec 2019 03:27:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576495646; cv=none; d=google.com; s=arc-20160816; b=0durAaxvyPNUyzGpODEKt8TK6Q8rK6qMv+GlJiwEpVmVt0sRN3JLgtr4V+iQCC/Dbh jirNvP2G8MBRiR0qB0qbMigJIisLEQ/pwumTmFroqjDflr0a/6r9jMi/0snuUWREHu9o A06vTxciAGvUo+rtQ/+VjALZCAgsl54u/0Ud37cm+X67vu3+nNGdHxqNTrg+3bP3joJZ j8nGKpuAk0N58ljSb+a6cEErVQQX+Bx8S6OyrGq3pInHnKw0jSloCWJxKbYkhhkVqagE Fm1gds+MuSye5LuTBdMN9f06g9D+zcZjCiBN3lwaFm8u2grkJHS9NPNhs7LsqP8pRLDJ bKhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=biJgw9AmxEjt8OjXP6jfcEtE+uZVIiqydwwtIiuDGOc=; b=CfKolpM26XXGqzRYUCwmnouCdKu04a8qDH3Zy3HGY/bZxez9U1lo8vTQCsacB+JsUQ 92qa69a1eheoLmbygOPluJUPIBesfX3hdQ7CJ7Q5zU0amf64lhaGi35bxV1mE4QGu7Fm nL2GCMlY1LoCug4H/qQtz3dq118KidO4/mrScAEcgbp9EvMJhb9bS0lMQTmmE+MwI1as F7ZDILQt4YOkASGCtNSKOKABdRMF5WKnX0EIlxTtW5GHQ7xOCCK3fF3pJ8ANg9bA3GFF zcDUGpY+NdcAs6gnUK/Vq1RbY8EUiMJ7dVWEfaF8Og5AcU4zseInVPjE+jFOeWDvH9e9 ESaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cEGyIRJF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/34] aspeed: Change the "scu" property definition Date: Mon, 16 Dec 2019 11:08:48 +0000 Message-Id: <20191216110904.30815-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The Aspeed Watchdog and Timer models have a link pointing to the SCU controller model of the machine. Change the "scu" property definition so that it explicitly sets the pointer. The property isn't optional : not being able to set the link is a bug and QEMU should rather abort than exit in this case. Signed-off-by: Cédric Le Goater Reviewed-by: Greg Kurz Reviewed-by: Joel Stanley Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-17-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed_ast2600.c | 8 ++++---- hw/arm/aspeed_soc.c | 8 ++++---- hw/timer/aspeed_timer.c | 17 +++++++++-------- hw/watchdog/wdt_aspeed.c | 17 ++++++++--------- 4 files changed, 25 insertions(+), 25 deletions(-) -- 2.20.1 diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 0881eb25983..810fd7de0c0 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -146,8 +146,6 @@ static void aspeed_soc_ast2600_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl), sizeof(s->timerctrl), typename); - object_property_add_const_link(OBJECT(&s->timerctrl), "scu", - OBJECT(&s->scu), &error_abort); snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), @@ -177,8 +175,6 @@ static void aspeed_soc_ast2600_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), sizeof(s->wdt[i]), typename); - object_property_add_const_link(OBJECT(&s->wdt[i]), "scu", - OBJECT(&s->scu), &error_abort); } for (i = 0; i < sc->macs_num; i++) { @@ -323,6 +319,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) aspeed_soc_get_irq(s, ASPEED_RTC)); /* Timer */ + object_property_set_link(OBJECT(&s->timerctrl), + OBJECT(&s->scu), "scu", &error_abort); object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); if (err) { error_propagate(errp, err); @@ -415,6 +413,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) for (i = 0; i < sc->wdts_num; i++) { AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); + object_property_set_link(OBJECT(&s->wdt[i]), + OBJECT(&s->scu), "scu", &error_abort); object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index b01c9774419..a6237e59401 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -163,8 +163,6 @@ static void aspeed_soc_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl), sizeof(s->timerctrl), typename); - object_property_add_const_link(OBJECT(&s->timerctrl), "scu", - OBJECT(&s->scu), &error_abort); snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), @@ -194,8 +192,6 @@ static void aspeed_soc_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), sizeof(s->wdt[i]), typename); - object_property_add_const_link(OBJECT(&s->wdt[i]), "scu", - OBJECT(&s->scu), &error_abort); } for (i = 0; i < sc->macs_num; i++) { @@ -291,6 +287,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) aspeed_soc_get_irq(s, ASPEED_RTC)); /* Timer */ + object_property_set_link(OBJECT(&s->timerctrl), + OBJECT(&s->scu), "scu", &error_abort); object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); if (err) { error_propagate(errp, err); @@ -376,6 +374,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) for (i = 0; i < sc->wdts_num; i++) { AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); + object_property_set_link(OBJECT(&s->wdt[i]), + OBJECT(&s->scu), "scu", &error_abort); object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index bcce2192a92..a8c38cc1189 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -19,6 +19,7 @@ #include "qemu/timer.h" #include "qemu/log.h" #include "qemu/module.h" +#include "hw/qdev-properties.h" #include "trace.h" #define TIMER_NR_REGS 4 @@ -603,15 +604,8 @@ static void aspeed_timer_realize(DeviceState *dev, Error **errp) int i; SysBusDevice *sbd = SYS_BUS_DEVICE(dev); AspeedTimerCtrlState *s = ASPEED_TIMER(dev); - Object *obj; - Error *err = NULL; - obj = object_property_get_link(OBJECT(dev), "scu", &err); - if (!obj) { - error_propagate_prepend(errp, err, "required link 'scu' not found: "); - return; - } - s->scu = ASPEED_SCU(obj); + assert(s->scu); for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { aspeed_init_one_timer(s, i); @@ -677,6 +671,12 @@ static const VMStateDescription vmstate_aspeed_timer_state = { } }; +static Property aspeed_timer_properties[] = { + DEFINE_PROP_LINK("scu", AspeedTimerCtrlState, scu, TYPE_ASPEED_SCU, + AspeedSCUState *), + DEFINE_PROP_END_OF_LIST(), +}; + static void timer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -685,6 +685,7 @@ static void timer_class_init(ObjectClass *klass, void *data) dc->reset = aspeed_timer_reset; dc->desc = "ASPEED Timer"; dc->vmsd = &vmstate_aspeed_timer_state; + dc->props = aspeed_timer_properties; } static const TypeInfo aspeed_timer_info = { diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index 122aa8daaad..f50dab922e0 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -241,16 +241,8 @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp) { SysBusDevice *sbd = SYS_BUS_DEVICE(dev); AspeedWDTState *s = ASPEED_WDT(dev); - Error *err = NULL; - Object *obj; - obj = object_property_get_link(OBJECT(dev), "scu", &err); - if (!obj) { - error_propagate(errp, err); - error_prepend(errp, "required link 'scu' not found: "); - return; - } - s->scu = ASPEED_SCU(obj); + assert(s->scu); s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev); @@ -264,6 +256,12 @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(sbd, &s->iomem); } +static Property aspeed_wdt_properties[] = { + DEFINE_PROP_LINK("scu", AspeedWDTState, scu, TYPE_ASPEED_SCU, + AspeedSCUState *), + DEFINE_PROP_END_OF_LIST(), +}; + static void aspeed_wdt_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -273,6 +271,7 @@ static void aspeed_wdt_class_init(ObjectClass *klass, void *data) dc->reset = aspeed_wdt_reset; set_bit(DEVICE_CATEGORY_MISC, dc->categories); dc->vmsd = &vmstate_aspeed_wdt; + dc->props = aspeed_wdt_properties; } static const TypeInfo aspeed_wdt_info = { From patchwork Mon Dec 16 11:08:49 2019 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/34] aspeed: Change the "nic" property definition Date: Mon, 16 Dec 2019 11:08:49 +0000 Message-Id: <20191216110904.30815-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The Aspeed MII model has a link pointing to its associated FTGMAC100 NIC in the machine. Change the "nic" property definition so that it explicitly sets the pointer. The property isn't optional : not being able to set the link is a bug and QEMU should rather abort than exit in this case. Signed-off-by: Cédric Le Goater Reviewed-by: Greg Kurz Reviewed-by: Joel Stanley Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-18-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed_ast2600.c | 5 ++--- hw/net/ftgmac100.c | 19 +++++++++---------- 2 files changed, 11 insertions(+), 13 deletions(-) -- 2.20.1 diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 810fd7de0c0..be88005dab8 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -183,9 +183,6 @@ static void aspeed_soc_ast2600_init(Object *obj) sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]), TYPE_ASPEED_MII); - object_property_add_const_link(OBJECT(&s->mii[i]), "nic", - OBJECT(&s->ftgmac100[i]), - &error_abort); } sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), @@ -441,6 +438,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); + object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]), + "nic", &error_abort); object_property_set_bool(OBJECT(&s->mii[i]), true, "realized", &err); if (err) { diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c index eb8b441461a..86ac25894a8 100644 --- a/hw/net/ftgmac100.c +++ b/hw/net/ftgmac100.c @@ -1204,17 +1204,8 @@ static void aspeed_mii_realize(DeviceState *dev, Error **errp) { AspeedMiiState *s = ASPEED_MII(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - Object *obj; - Error *local_err = NULL; - obj = object_property_get_link(OBJECT(dev), "nic", &local_err); - if (!obj) { - error_propagate(errp, local_err); - error_prepend(errp, "required link 'nic' not found: "); - return; - } - - s->nic = FTGMAC100(obj); + assert(s->nic); memory_region_init_io(&s->iomem, OBJECT(dev), &aspeed_mii_ops, s, TYPE_ASPEED_MII, 0x8); @@ -1231,6 +1222,13 @@ static const VMStateDescription vmstate_aspeed_mii = { VMSTATE_END_OF_LIST() } }; + +static Property aspeed_mii_properties[] = { + DEFINE_PROP_LINK("nic", AspeedMiiState, nic, TYPE_FTGMAC100, + FTGMAC100State *), + DEFINE_PROP_END_OF_LIST(), +}; + static void aspeed_mii_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -1239,6 +1237,7 @@ static void aspeed_mii_class_init(ObjectClass *klass, void *data) dc->reset = aspeed_mii_reset; dc->realize = aspeed_mii_realize; dc->desc = "Aspeed MII controller"; + dc->props = aspeed_mii_properties; } static const TypeInfo aspeed_mii_info = { From patchwork Mon Dec 16 11:08:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181705 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4189823ile; Mon, 16 Dec 2019 03:39:10 -0800 (PST) X-Google-Smtp-Source: APXvYqxJpfVdDP9wWB3SwWHXpRpDPiazZv+/33aO5PHCxR3UsbRy36VmnWj1dr7tF/fGQjO1oZqe X-Received: by 2002:a9d:708a:: with SMTP id l10mr29744339otj.263.1576496350744; Mon, 16 Dec 2019 03:39:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576496350; cv=none; d=google.com; s=arc-20160816; b=XexcsbsAuMvC/GZpZrRsiYRjkeGtnDt6XlAaZhS5fQVJea6WWI7hVjDHAC7NM9DkCk HTmLBkIhqiGMeEKc7k5WdmWgmIoMu4gbA3BDwjrbLgAQFK/v29ZcGz1ffK+Yc1LRqfhn BqV6+LITWyw7PbpuvcrU+9gRvm2C+12L5gm7DK45tPyeCq+6DJK6X/vKGnzWC5G43joW SZi9sY6EqbKEUlztfK26MApxt+3MP12bGvnXMakjbttXSFuqE3gvC1ybu2SZRRixKRn3 7m1IfEJPC5OoE2jgF1tYOB7CG56a6EvuDDVSQscOUJII5sw83umzte+X5MQmdUqnFeGX L2AA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hppP2bCQOezxDFaY7+RUxIWUw1GUMX8Ov6ZmLeYdIro=; b=YTJ7rmvsGS5jmXYXVGL5VUkaTpT170SQek7F3jHHOCQeo/l484WLogWZQspdXGZaPp OhxI2zwE/w3K5x7KSogbOGR974AyKfT9IR7ZphoiWG4dgiTR8fmfmQ1VlzBK9USBVb59 7c0ODJUB2zGrabXl/jwJXgrjZP7jgFJA1xu2SRSAJo1Ewm3Pgge9w3xpXMSLu5u4AkGF 8MnjygBkpHBlOvEFp8iFpu9GaGEJiSFMAWNN7KJNqSiQYh81/w51K0QIR9f1h7uSORv5 5Wx2gz08dQx7vUUIZImT8RIjR+rnCo2FYyh3yV3Nf0NFOFbVRAi9zOWzaiK5UU8QlCkr YBxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="vpY+9M/S"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/34] target/arm: Honor HCR_EL2.TID2 trapping requirements Date: Mon, 16 Dec 2019 11:08:50 +0000 Message-Id: <20191216110904.30815-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Marc Zyngier HCR_EL2.TID2 mandates that access from EL1 to CTR_EL0, CCSIDR_EL1, CCSIDR2_EL1, CLIDR_EL1, CSSELR_EL1 are trapped to EL2, and QEMU completely ignores it, making it impossible for hypervisors to virtualize the cache hierarchy. Do the right thing by trapping to EL2 if HCR_EL2.TID2 is set. Signed-off-by: Marc Zyngier Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson Message-id: 20191201122018.25808-2-maz@kernel.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 0bf8f53d4b8..1e546096b82 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1910,6 +1910,17 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) raw_write(env, ri, value); } +static CPAccessResult access_aa64_tid2(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = env_archcpu(env); @@ -2110,10 +2121,14 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .writefn = pmintenclr_write }, { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, - .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, + .access = PL1_R, + .accessfn = access_aa64_tid2, + .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, - .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, + .access = PL1_RW, + .accessfn = access_aa64_tid2, + .writefn = csselr_write, .resetvalue = 0, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), offsetof(CPUARMState, cp15.csselr_ns) } }, /* Auxiliary ID register: this actually has an IMPDEF value but for now @@ -5204,6 +5219,11 @@ static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { return CP_ACCESS_TRAP; } + + if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; } @@ -6184,7 +6204,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo clidr = { .name = "CLIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, - .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr + .access = PL1_R, .type = ARM_CP_CONST, + .accessfn = access_aa64_tid2, + .resetvalue = cpu->clidr }; define_one_arm_cp_reg(cpu, &clidr); define_arm_cp_regs(cpu, v7_cp_reginfo); @@ -6717,7 +6739,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) /* These are common to v8 and pre-v8 */ { .name = "CTR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, - .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, + .access = PL1_R, .accessfn = ctr_el0_access, + .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, .access = PL0_R, .accessfn = ctr_el0_access, From patchwork Mon Dec 16 11:08:51 2019 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/34] target/arm: Honor HCR_EL2.TID1 trapping requirements Date: Mon, 16 Dec 2019 11:08:51 +0000 Message-Id: <20191216110904.30815-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Marc Zyngier HCR_EL2.TID1 mandates that access from EL1 to REVIDR_EL1, AIDR_EL1 (and their 32bit equivalents) as well as TCMTR, TLBTR are trapped to EL2. QEMU ignores it, making it harder for a hypervisor to virtualize the HW (though to be fair, no known hypervisor actually cares). Do the right thing by trapping to EL2 if HCR_EL2.TID1 is set. Reviewed-by: Edgar E. Iglesias Signed-off-by: Marc Zyngier Reviewed-by: Richard Henderson Message-id: 20191201122018.25808-3-maz@kernel.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 1e546096b82..93ecab27c0c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1973,6 +1973,26 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) return ret; } +static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID1)) { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + +static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_feature(env, ARM_FEATURE_V8)) { + return access_aa64_tid1(env, ri, isread); + } + + return CP_ACCESS_OK; +} + static const ARMCPRegInfo v7_cp_reginfo[] = { /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, @@ -2136,7 +2156,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { */ { .name = "AIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, - .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + .access = PL1_R, .type = ARM_CP_CONST, + .accessfn = access_aa64_tid1, + .resetvalue = 0 }, /* Auxiliary fault status registers: these also are IMPDEF, and we * choose to RAZ/WI for all cores. */ @@ -6732,7 +6754,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .resetvalue = cpu->midr }, { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, - .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, + .access = PL1_R, + .accessfn = access_aa64_tid1, + .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, REGINFO_SENTINEL }; ARMCPRegInfo id_cp_reginfo[] = { @@ -6748,14 +6772,18 @@ void register_cp_regs_for_features(ARMCPU *cpu) /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ { .name = "TCMTR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, - .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + .access = PL1_R, + .accessfn = access_aa32_tid1, + .type = ARM_CP_CONST, .resetvalue = 0 }, REGINFO_SENTINEL }; /* TLBTR is specific to VMSA */ ARMCPRegInfo id_tlbtr_reginfo = { .name = "TLBTR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, - .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0, + .access = PL1_R, + .accessfn = access_aa32_tid1, + .type = ARM_CP_CONST, .resetvalue = 0, }; /* MPUIR is specific to PMSA V6+ */ ARMCPRegInfo id_mpuir_reginfo = { From patchwork Mon Dec 16 11:08:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181687 Delivered-To: patch@linaro.org Received: by 2002:ac9:44c4:0:0:0:0:0 with SMTP id t4csp4173879och; Mon, 16 Dec 2019 03:26:03 -0800 (PST) X-Google-Smtp-Source: APXvYqwrhtI8slLmjhFBfc2isT2brBFXdEUKiMiSpp5s4hUPZVANL79p6RNC1WupX1e3Y19jdirj X-Received: by 2002:ac8:7516:: with SMTP id u22mr15972463qtq.229.1576495563894; Mon, 16 Dec 2019 03:26:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576495563; cv=none; d=google.com; s=arc-20160816; b=jkjdMWB0rWDaYDeNsx0QNLIoOJllh41yigMMia2Mkb2l7yVIXwnsW5zqjwtvdAcwfr j/LQRStStCPNpA9oO2OOf9regsAyO6/lwulQsJaZxNUlceAhmKaDaKBWrvsOhiOqfYGs 0o46Zvxqgwg8NSLAWB+1r+AOjF5WiA8fbJlkNkM+l2CHh+fgeAOmuzfoI1XeFzsAWNt0 JTYowaE19hnDIWvC7vlqUgfVHQgjniEjFNB39KjluXVAuu3nNrj9S4j2eRyJGsjQ4KWx JwTHVnEa+RF/RxNgXl+SeDIm475xaBcyEtK9FBrTisL219jwXHDAACRI357kmsnAOei2 2GLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cRpUuyaFQptJ3Uv0Xu4cqCnT035R8uR0+h+PEux3tSk=; b=LLU4Cic8ncpKG3WTVUsEncFLRQ7wmuj9ypX6nTkHlvlwWUeWe4vc2/edClRFCuxwBv /iZCLtOnvpDCslgPVIQ9UuPZTkEOt9r0O8yN4Fr1LcwTcNfQtDDd7I2zd7k28X3rv023 CgsQ5jCDonFUyV7OkAeZj8oz34GsDT6IDaKfYryZqingGGSVJb+MGQbJSentREDPGfGL oiIBRPNNILdkaug3O58Vu/12bqAYffdEa4Gt3DcLQZYceKpNcoph3SwFY0EamoayfT1B luedB6mMyIB+oMwaAaA+keLEDqT2lF0wv3aE97rQR1F1RvGzwTEhBq/s5y1LjDwmgaMo Zrqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kJxBi3eM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/34] target/arm: Handle trapping to EL2 of AArch32 VMRS instructions Date: Mon, 16 Dec 2019 11:08:52 +0000 Message-Id: <20191216110904.30815-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Marc Zyngier HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to EL2, and HCR_EL2.TID0 does the same for reads of FPSID. In order to handle this, introduce a new TCG helper function that checks for these control bits before executing the VMRC instruction. Tested with a hacked-up version of KVM/arm64 that sets the control bits for 32bit guests. Reviewed-by: Edgar E. Iglesias Signed-off-by: Marc Zyngier Reviewed-by: Richard Henderson Message-id: 20191201122018.25808-4-maz@kernel.org [PMM: move helper declaration to helper.h; make it TCG_CALL_NO_WG] Signed-off-by: Peter Maydell --- target/arm/helper.h | 2 ++ target/arm/translate-vfp.inc.c | 20 ++++++++++++++++---- target/arm/vfp_helper.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.h b/target/arm/helper.h index 3d4ec267a2c..7ce5169afb5 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -226,6 +226,8 @@ DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env) DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr) +DEF_HELPER_FLAGS_3(check_hcr_el2_trap, TCG_CALL_NO_WG, void, env, i32, i32) + /* neon_helper.c */ DEF_HELPER_FLAGS_3(neon_qadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32) DEF_HELPER_FLAGS_3(neon_qadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 85c5ef897be..bf90ac0e5b7 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -761,13 +761,25 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) if (a->l) { /* VMRS, move VFP special register to gp register */ switch (a->reg) { - case ARM_VFP_FPSID: - case ARM_VFP_FPEXC: - case ARM_VFP_FPINST: - case ARM_VFP_FPINST2: case ARM_VFP_MVFR0: case ARM_VFP_MVFR1: case ARM_VFP_MVFR2: + case ARM_VFP_FPSID: + if (s->current_el == 1) { + TCGv_i32 tcg_reg, tcg_rt; + + gen_set_condexec(s); + gen_set_pc_im(s, s->pc_curr); + tcg_reg = tcg_const_i32(a->reg); + tcg_rt = tcg_const_i32(a->rt); + gen_helper_check_hcr_el2_trap(cpu_env, tcg_rt, tcg_reg); + tcg_temp_free_i32(tcg_reg); + tcg_temp_free_i32(tcg_rt); + } + /* fall through */ + case ARM_VFP_FPEXC: + case ARM_VFP_FPINST: + case ARM_VFP_FPINST2: tmp = load_cpu_field(vfp.xregs[a->reg]); break; case ARM_VFP_FPSCR: diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 9710ef1c3e5..0ae7d4f34a9 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -1322,4 +1322,33 @@ float64 HELPER(frint64_d)(float64 f, void *fpst) return frint_d(f, fpst, 64); } +void HELPER(check_hcr_el2_trap)(CPUARMState *env, uint32_t rt, uint32_t reg) +{ + uint32_t syndrome; + + switch (reg) { + case ARM_VFP_MVFR0: + case ARM_VFP_MVFR1: + case ARM_VFP_MVFR2: + if (!(arm_hcr_el2_eff(env) & HCR_TID3)) { + return; + } + break; + case ARM_VFP_FPSID: + if (!(arm_hcr_el2_eff(env) & HCR_TID0)) { + return; + } + break; + default: + g_assert_not_reached(); + } + + syndrome = ((EC_FPIDTRAP << ARM_EL_EC_SHIFT) + | ARM_EL_IL + | (1 << 24) | (0xe << 20) | (7 << 14) + | (reg << 10) | (rt << 5) | 1); + + raise_exception(env, EXCP_HYP_TRAP, syndrome, 2); +} + #endif From patchwork Mon Dec 16 11:08:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181699 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4185603ile; Mon, 16 Dec 2019 03:34:53 -0800 (PST) X-Google-Smtp-Source: APXvYqzev8W5xRwM/Z8t9hFVaupJ3k6i8H+sCX89kWvgJjVjyVBE4zLffyaqDC5VFT2D1w+QzXvy X-Received: by 2002:ac8:3510:: with SMTP id y16mr5298022qtb.6.1576496092960; Mon, 16 Dec 2019 03:34:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576496092; cv=none; d=google.com; s=arc-20160816; b=xGfM0dlQ2Vp6QGkbqjItLRUtRm4YgNsJv3BHtAhW1Auvc3Qlk1YreePA/XguORfNME w6+mbuJRI7lZ261UpTwV+NxCHB2mMTTxD/ZZ1lf3ntlP11JrRiKtdm4Zd6qqiWVQpimk on3UHj8Awvthet39kpTwBiiQaghwQYwbf/SM/fSW/4xzvZ0TkKzF1ENEk5YlMkaxsRTS S78My26bv55HxWgTb+Y93CqCIVTLLQ3u0SizTZxwpGoy8fSLSR0BiUEsts8SOjPI68qF kLSe7Ui/ikd4jf0HUW2uR/4asOWFWF+bi3k4SMSonG2IdQx99EXb/EdlJZ7kYyQ5pttE v2YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9nM3iGNTG1qevbyU7U0Hu0NpGxKKU4DdwS7KMIMwwQ0=; b=pIHRd5EgIWdAYOAbyaBv20F7ZDHzAyKrHwL+Dz0LmHSAHkEB2XF7fjaYFJBUtsb0Yo nGtSh1ThZ5rzUSPFsAbZxHZPCWsDR0yHDLNPNW+C22mX37nEG+pHDCeyb5j3UZEQXUqv 9wkb+PjUZoNv62yXGxcKvquV3ImRWA4PbKK1MYMB3rXGovHiiJ62UqREmRbFimY0dmk/ jKoM8bPYQowIDC5QIDKLEFZfYy7SPyStvdJWiJ3f1PeXplk2Ckv12f2UEsaEWE8bfbih V0IU2J3Kj+0T5G4lBy/cB0R3Xdzb7doHqDBQ/w24QjfY48PvrWHV1e+3MSVniqoz79CO fmoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DX+LxUVl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o11si9119167qvs.79.2019.12.16.03.34.52 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Dec 2019 03:34:52 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DX+LxUVl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51848 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igoeJ-0007RZ-M3 for patch@linaro.org; Mon, 16 Dec 2019 06:34:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51142) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igoFr-000816-8W for qemu-devel@nongnu.org; Mon, 16 Dec 2019 06:09:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igoFp-0008Vc-PZ for qemu-devel@nongnu.org; Mon, 16 Dec 2019 06:09:35 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:35127) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igoFp-0008Sm-IY for qemu-devel@nongnu.org; Mon, 16 Dec 2019 06:09:33 -0500 Received: by mail-wm1-x32a.google.com with SMTP id p17so6238579wmb.0 for ; Mon, 16 Dec 2019 03:09:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9nM3iGNTG1qevbyU7U0Hu0NpGxKKU4DdwS7KMIMwwQ0=; b=DX+LxUVlsv/JRD8WKNvdcKZeYua0buyjqCjhmRjzvDhjfUXNa0f3a8NSdidPaO1V/1 dAKizpij9zECadcjWT7q6tVaRgaboThF33MGYYuwfOZFlrafIughggQ6epb7iCwdIdTo d5iUJdUr6Mbsf6SU1v2l1NYQzDFRk5XS8aKXg9iLKPX1yhfiQC/GYnQcR2phBOLmlF87 PLDuUnfr1/27mSMUFL0EgQb6OO4BMV1il6b5DewlQf9az88hTiliKuZLo+jCuSviCUCG iU4Dy/a3tXhs9sSSAXEHIcXkiLRHSddmpd4OxLZS9/huyTE4smoo1yJmrWbbxuetXsof 3TEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9nM3iGNTG1qevbyU7U0Hu0NpGxKKU4DdwS7KMIMwwQ0=; b=Suh+zES2rvU6F0SNqrS+KEM9ztRIhRHs923kF5XsGqQv5t+d5UbVNoKR5McCzOMUjO FrCck8kP3RFw2AoSq25VnPmVvHt6Fag7pRahin98vXO1tcR5oRXgW0hYM/znscDzGyl2 w6gyY3dcfmVy6SUU8b3zcb/mLyZCyaLHUYfqnLXtUvPWzlZHH5xrEnCmfkw8y/xE8kdp lLJvYUDF2JYY9DKE2Xs3ozhnYrtPgDzZAo1hfAhU5hNYR+bK/dzPIXVMPJ4D9tFGwvgS L6qpiSe6Gj0tgh5P8roYAQyCPcyw3mWl3Gz1QS4qHJaXD0O9Bb/C8naOhBv9DZGuVtA6 NGtA== X-Gm-Message-State: APjAAAVqRPK7+bTDVy83LFTTJM26ECVBJywXNhsq6A5o9JceahaF2lvD wQiUBFp6wyNF6xEXQb0/Jd6tz7mfUmnceQ== X-Received: by 2002:a1c:7e13:: with SMTP id z19mr29502082wmc.67.1576494572199; Mon, 16 Dec 2019 03:09:32 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/34] target/arm: Handle AArch32 CP15 trapping via HSTR_EL2 Date: Mon, 16 Dec 2019 11:08:53 +0000 Message-Id: <20191216110904.30815-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Marc Zyngier HSTR_EL2 offers a way to trap ranges of CP15 system register accesses to EL2, and it looks like this register is completely ignored by QEMU. To avoid adding extra .accessfn filters all over the place (which would have a direct performance impact), let's add a new TB flag that gets set whenever HSTR_EL2 is non-zero and that QEMU translates a context where this trap has a chance to apply, and only generate the extra access check if the hypervisor is actively using this feature. Tested with a hand-crafted KVM guest accessing CBAR. Signed-off-by: Marc Zyngier Reviewed-by: Richard Henderson Message-id: 20191201122018.25808-5-maz@kernel.org [PMM: use is_a64(); fix comment syntax] Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 2 ++ target/arm/helper.c | 6 ++++++ target/arm/op_helper.c | 22 ++++++++++++++++++++++ target/arm/translate.c | 3 ++- 5 files changed, 34 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 83a809d4bac..cebb3511a51 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3215,6 +3215,8 @@ FIELD(TBFLAG_A32, NS, 6, 1) FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) +FIELD(TBFLAG_A32, HSTR_ACTIVE, 17, 1) + /* For M profile only, set if FPCCR.LSPACT is set */ FIELD(TBFLAG_A32, LSPACT, 18, 1) /* Not cached. */ /* For M profile only, set if we must create a new FP context */ diff --git a/target/arm/translate.h b/target/arm/translate.h index dd24f91f265..b837b7fcbf1 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -77,6 +77,8 @@ typedef struct DisasContext { bool pauth_active; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ bool bt; + /* True if any CP15 access is trapped by HSTR_EL2 */ + bool hstr_active; /* * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/helper.c b/target/arm/helper.c index 93ecab27c0c..0ba08d550aa 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11283,6 +11283,12 @@ static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, if (arm_el_is_aa64(env, 1)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } + + if (arm_current_el(env) < 2 && env->cp15.hstr_el2 && + (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { + flags = FIELD_DP32(flags, TBFLAG_A32, HSTR_ACTIVE, 1); + } + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index b529d6c1bf7..e5a346cb87a 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -603,6 +603,27 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome, raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env)); } + /* + * Check for an EL2 trap due to HSTR_EL2. We expect EL0 accesses + * to sysregs non accessible at EL0 to have UNDEF-ed already. + */ + if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp == 15 && + (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { + uint32_t mask = 1 << ri->crn; + + if (ri->type & ARM_CP_64BIT) { + mask = 1 << ri->crm; + } + + /* T4 and T14 are RES0 */ + mask &= ~((1 << 4) | (1 << 14)); + + if (env->cp15.hstr_el2 & mask) { + target_el = 2; + goto exept; + } + } + if (!ri->accessfn) { return; } @@ -652,6 +673,7 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome, g_assert_not_reached(); } +exept: raise_exception(env, EXCP_UDEF, syndrome, target_el); } diff --git a/target/arm/translate.c b/target/arm/translate.c index 4d5d4bd8886..f162be8434f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6897,7 +6897,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) return 1; } - if (ri->accessfn || + if (s->hstr_active || ri->accessfn || (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) { /* Emit code to perform further access permissions checks at * runtime; this may result in an exception. @@ -10843,6 +10843,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) !arm_el_is_aa64(env, 3); dc->thumb = FIELD_EX32(tb_flags, TBFLAG_A32, THUMB); dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B); + dc->hstr_active = FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE); dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; condexec = FIELD_EX32(tb_flags, TBFLAG_A32, CONDEXEC); dc->condexec_mask = (condexec & 0xf) << 1; From patchwork Mon Dec 16 11:08:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181708 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4193032ile; Mon, 16 Dec 2019 03:42:28 -0800 (PST) X-Google-Smtp-Source: APXvYqyrEhxgLhfDhixoyFuJFW3fEWcOjSddpQ3qA4EVnw3KDpR+DOlpfGbjIWpa3FFXHa4yePfA X-Received: by 2002:a05:620a:13da:: with SMTP id g26mr27108604qkl.410.1576496548292; Mon, 16 Dec 2019 03:42:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576496548; cv=none; d=google.com; s=arc-20160816; b=oyNky67aJ9VhaHCBvvrcu0IEtMmFWUpUC1DTxZv9iJNE/HeIakp0/CzS+OtGROB1S/ OKBMfoWs6jZrv4Z0BWdh79MMsF4Opqq58JIO5qQwDVx8rmsVuIa8W84iPcekDGbNJRUc 9j5jGm8W9y0ugMu+ul3ufo7gFplPYqETLyBXEWtUkgVyS01NMZ8AOu/q7LVZielV+oqB rQouPsYtX810lFzAQiKOs+kL3xwOImBvj7Ek/3IkfICszzcwvRK/Z8D+BzYYLAAC2CYZ yEl3Y6XraAUfSRS0VnjxYpd1EQlwJreiNufKdPkZlox1n+X7jHVeGKftTCMVDX0aqF5N lGGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KOuvuhSQj8eVtemKGzERysHw3TTzF7KdECnJyVpBO44=; b=eqG5mgMVPNYz/aeWz2vO6Q5xcUl1eJT3uvR+6mfwCg+zntr5giDw4ZQdzSA1mSZ2IO TInvrAfxVNNK0Y+wrzT8OxJBIr0NmkYwTaGLkEb4QUG8v5xjLKmOScRJjgN0hpihTspN ymcDrN3k6ASi47F4eEwnIZ4za1Lguun9Dys1SijlmBFyseoyW1l4q3s1YYdcQw1ES7Y2 CbXfQxjFrTqRopf1NSb+FImU845OUvAd3VIumWvTjB7r7Z0tzbgdPnLMcCMLK45nLaPR TiqQFlrkmIh/KYcxIsOrwpg1Z8DwfmKAz/uhOmjoRKW79HAF04F2LyEUnrVQs4cRE9q5 KPeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L9Uomrsi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j9si9270570qtq.276.2019.12.16.03.42.28 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Dec 2019 03:42:28 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L9Uomrsi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52068 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igolf-00025u-NC for patch@linaro.org; Mon, 16 Dec 2019 06:42:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51151) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igoFr-00082A-RJ for qemu-devel@nongnu.org; Mon, 16 Dec 2019 06:09:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igoFq-000062-Jt for qemu-devel@nongnu.org; Mon, 16 Dec 2019 06:09:35 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:42717) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igoFq-0008Vn-Du for qemu-devel@nongnu.org; Mon, 16 Dec 2019 06:09:34 -0500 Received: by mail-wr1-x443.google.com with SMTP id q6so6697565wro.9 for ; Mon, 16 Dec 2019 03:09:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KOuvuhSQj8eVtemKGzERysHw3TTzF7KdECnJyVpBO44=; b=L9UomrsiCIUENvz8DMMGlb1kRhNSSAIyCIk9XqREeCcPypLv628qQ9gUDMFDBBS8d7 KZ28E9uSTcOwn9mJgXx3yRdCA7pKZw9z5CJEDHfX6CLb0NTm/jP7/z7tTHuai8q0mbwW 6vqJrN9kkQB4PxbZ7pkNODoQ1WfnmZ+geYlOTn553PCmjGz//RXh5+zeR/JM0s3uADEv PATZzkuQDImdJKqdBkj5x+8eSv8T/n6QLBjcWnghWNLJhRQ0yabESoiDeuhq62Cas0tY rEvdQ2p7maLkG8imKLYVmwreW2BkODmbDCm20u73Jf5syOqG5SZutn5WSn1X+AgikPYg GKsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KOuvuhSQj8eVtemKGzERysHw3TTzF7KdECnJyVpBO44=; b=OfJL0kxm6nie43FITB/Xtpnl/mxpkH9uB+CqNFsp4i9FBB/LScuV+VDP+T6fRjjPJA fsXYdsJBMwwGer0AW3I6qP+Aymi61X9nEETBi0+DZX3pb1uneXyy61rWLQ68jqMPtZAY SlxNjg6Ja9SHEskhg0gOiVgylxDJCM695ppkyjQ0wWhT4uQw90Y/l61iLm3ssxZIjZRk q63K0Cx7ozWqAmT0bMSlbyzcFtQ759GQPepptxPVtNBkS5qesfcp3tlCNBNmncVeetWQ 3BuiU8Fy2WQM0Z35cxzqs1Ev0DcSlfQaBGygLynlUFvh3NoQcSxciN884ly3sEqheSUF NDjw== X-Gm-Message-State: APjAAAUP2JDQOP/oOuRUR+vtMu3CZVP7fMSuE5L87GFE+qe/oirW+cUx ypG25S/hpq7Beb8Ts5DP53U8ceBFr69oyw== X-Received: by 2002:adf:f80c:: with SMTP id s12mr29310022wrp.1.1576494573226; Mon, 16 Dec 2019 03:09:33 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/34] target/arm: Add support for missing Jazelle system registers Date: Mon, 16 Dec 2019 11:08:54 +0000 Message-Id: <20191216110904.30815-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Marc Zyngier QEMU lacks the minimum Jazelle implementation that is required by the architecture (everything is RAZ or RAZ/WI). Add it together with the HCR_EL2.TID0 trapping that goes with it. Signed-off-by: Marc Zyngier Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson Message-id: 20191201122018.25808-6-maz@kernel.org [PMM: moved ARMCPRegInfo array to file scope, marked it 'static global', moved new condition down in register_cp_regs_for_features() to go with other feature things rather than up with the v6/v7/v8 stuff] Signed-off-by: Peter Maydell --- target/arm/helper.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ba08d550aa..a4f7b61b4e1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6040,6 +6040,30 @@ static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } +static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo jazelle_regs[] = { + { .name = "JIDR", + .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0, + .access = PL1_R, .accessfn = access_jazelle, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "JOSCR", + .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "JMCR", + .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -6699,6 +6723,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_LPAE)) { define_arm_cp_regs(cpu, lpae_cp_reginfo); } + if (cpu_isar_feature(jazelle, cpu)) { + define_arm_cp_regs(cpu, jazelle_regs); + } /* Slightly awkwardly, the OMAP and StrongARM cores need all of * cp15 crn=0 to be writes-ignored, whereas for other cores they should * be read-only (ie write causes UNDEF exception). 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[209.51.188.17]) by mx.google.com with ESMTPS id w1si9728855qvh.182.2019.12.16.03.26.24 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Dec 2019 03:26:24 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Qtv41et/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51662 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igoW7-0004Ha-EA for patch@linaro.org; Mon, 16 Dec 2019 06:26:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51172) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igoFs-00083y-UU for qemu-devel@nongnu.org; Mon, 16 Dec 2019 06:09:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igoFr-000083-Ip for qemu-devel@nongnu.org; Mon, 16 Dec 2019 06:09:36 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:43135) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igoFr-00006T-CA for qemu-devel@nongnu.org; Mon, 16 Dec 2019 06:09:35 -0500 Received: by mail-wr1-x441.google.com with SMTP id d16so6712516wre.10 for ; Mon, 16 Dec 2019 03:09:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ACmqU9kc4pH2AFemnhFozmUJPmfCe2y1E2GEg4ME7dE=; b=Qtv41et/cAnVAjr9sEMIwdJhL+pjKHlCpFIjd9AFEhnEGk2EGzeW9XHbpWNYBF0LBY uqdSCXdbsvLbL7QkrD3Zi24rB/cBwqBXbAwOo2Y214VmM7umK4UOWlALq7Fzixr/IQKG KqvG+hJwJOLFCXQek/jEgQAJECT6JbVJpklD9/D4IFKHUn0ocKq+noxv51U6Im2YxLm/ ua7qCqLqQRgGEwAtZTihcH8iSf3YZnEmvMXDwtL4pD2NjoBDDB3JAAVo8NVGMeOgiiMN 8p1GYjLpCAfHIejfMmsUtBVWQcxFFRLmZYw+ztiNFLoYIupAoQvHL/iV7kUQk8CCpPBK DfRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ACmqU9kc4pH2AFemnhFozmUJPmfCe2y1E2GEg4ME7dE=; b=W8cCMyqssVZmm35+26J7wXj8HVyfo2kT8uHqr4V5i81WDSN9HTi8MFeW2CnUuBBRuR q2J/TXOKJUuDAPuIeAJLtgFRam982XfjCSINJI5KqtgFzL7aZKXJCTvpbWc3lQ7EB90M XAeIbFuxVPfueOLsRt9Q3ul9Xis2ZLjp4Qb9vATWQ2dZHOLm4u7SCfN28lvsKmCLCL0/ j+fch9ksNAr9K5LbDlbgJcfc1xxrLT1B2OuZZbY1fl5XxhmqGIrG1D9g9lMBcib+xckf EXsVzHKtpYd3KogM1cVT1yOL9hEv17b/QGRJDnwuq71RHJpek/TeyozEEXVT83EF4yLJ D4DA== X-Gm-Message-State: APjAAAVxjhA2jRFF998rPFflRaDS/G5uhllMD4xwTAhqI74MiLO0zVWg scqVFEoBfsG8LXQS7hyjOWDLf2VREFt8/g== X-Received: by 2002:adf:f1d0:: with SMTP id z16mr28468734wro.209.1576494574226; Mon, 16 Dec 2019 03:09:34 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/34] arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on() Date: Mon, 16 Dec 2019 11:08:55 +0000 Message-Id: <20191216110904.30815-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Niek Linnenbank This change ensures that the FPU can be accessed in Non-Secure mode when the CPU core is reset using the arm_set_cpu_on() function call. The NSACR.{CP11,CP10} bits define the exception level required to access the FPU in Non-Secure mode. Without these bits set, the CPU will give an undefined exception trap on the first FPU access for the secondary cores under Linux. This is necessary because in this power-control codepath QEMU is effectively emulating a bit of EL3 firmware, and has to set the CPU up as the EL3 firmware would. Fixes: fc1120a7f5 Cc: qemu-stable@nongnu.org Signed-off-by: Niek Linnenbank [PMM: added clarifying para to commit message] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/arm-powerctl.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.20.1 diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index f77a950db67..b064513d44a 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -104,6 +104,9 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, /* Processor is not in secure mode */ target_cpu->env.cp15.scr_el3 |= SCR_NS; + /* Set NSACR.{CP11,CP10} so NS can access the FPU */ + target_cpu->env.cp15.nsacr |= 3 << 10; + /* * If QEMU is providing the equivalent of EL3 firmware, then we need * to make sure a CPU targeting EL2 comes out of reset with a From patchwork Mon Dec 16 11:08:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181701 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4185974ile; Mon, 16 Dec 2019 03:35:11 -0800 (PST) X-Google-Smtp-Source: APXvYqyFBTAfSV28zUUZMLba96hYdHogE3mGOJy/gjItaij3HYOAAX44Q06/rotXd8EM6Z59odgc X-Received: by 2002:ac8:330e:: with SMTP id t14mr24561304qta.232.1576496111512; Mon, 16 Dec 2019 03:35:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576496111; cv=none; d=google.com; s=arc-20160816; b=KoftA3wevGKtnRviMs958+qCKyVpzeLMB05yty1lQTBNl19YXuDVH/3xrhSL8JnyIR 4Hm6C6+ZzVzeaEoXTkq2t+D6yEYFpuWU0ynI1oCD1B/SaZ3+54yp9FfWtTO6Lu48cRIk pJm0CXub2mrrcg12zBq/DBoiLMxMP54BL+gBIfTfV8ykXWoW7bTUGawc4pNMIyR86KvL KkB8sk33DJpJ4LvyPgUuhH0CV9kuMoUAz1SCuKSYYCOE3HxthRMh+z6HslJzQ66O7GY5 /lWY4gd8Xxiz/BNbADiD8weKuNF6ks13eCFVOAPmy41iDjCk5JkIX9wtUmhtOmxZWdxr 6aAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UiJZOf8roQyIB6kTmOAd2zer7SLUCnDoCQmZEmstycM=; b=Im8ZGeovjUIBWasJ+oPKZ6adsBAHXXi7zF2Avx37rzT0htIkADe0e6eNhX4I2rv1gp FGjnAuHXsxhZhcCneIuchFY6NXVLea0JCkBymyN0H/J48cZ4IvKxc6eIPxs0G4cdrAqo /kkuEZLrLh/BRdy6odeqJQ2RuxqEoFudkal0R6jIJn+E0aOOuZb5eO92/9XBKu81YeuD qx8yoDEagyX8jUPz5EOcBGAW0r+8tAHye4Uon2Gth237aCps27B2gnt5+YzuY0ezef0b CYphGcLXlpIk6V9rMyE9u9gnVi8Wk5oSOMLijsy7sYzvTi0Frr4hPy3/Q+Jmq+Eu99Q0 1R8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LSMlUMSN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/34] tcg: cputlb: Add probe_read Date: Mon, 16 Dec 2019 11:08:56 +0000 Message-Id: <20191216110904.30815-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Beata Michalska Add probe_read alongside the write probing equivalent. Signed-off-by: Beata Michalska Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-id: 20191121000843.24844-2-beata.michalska@linaro.org Signed-off-by: Peter Maydell --- include/exec/exec-all.h | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.20.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index d85e610e85b..350c4b451be 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -339,6 +339,12 @@ static inline void *probe_write(CPUArchState *env, target_ulong addr, int size, return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); } +static inline void *probe_read(CPUArchState *env, target_ulong addr, int size, + int mmu_idx, uintptr_t retaddr) +{ + return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); +} + #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ /* Estimated block size for TB allocation. */ From patchwork Mon Dec 16 11:08:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181698 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4183500ile; Mon, 16 Dec 2019 03:32:56 -0800 (PST) X-Google-Smtp-Source: APXvYqzPzG52FUeuxJEKLbniaQDg+WaAU4rst5OCS7JyTmwr4dlFV4xiSuOpYIiRyAuVvUQbL7v5 X-Received: by 2002:a05:6830:1b6d:: with SMTP id d13mr31958013ote.258.1576495976621; Mon, 16 Dec 2019 03:32:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576495976; cv=none; d=google.com; s=arc-20160816; b=uczTv1mI4c9d7HbFHZcTr0QVcaW6+eiTdKJTMwn4LLhlILscS7wWyY2Zs4RF+9F+kM eMv0adA0GV8dM3a4lrhJREWuvsy2qvVF1LdPusQSB467T0eEeqeaK2TuUTgJfWZ65U+/ pWignFziZh8GrN/hgml85T/iCfZkrUccrU2JTyBYCmA9rtmUg9Do97MTLgDurwdpFrBQ ZfHVkXUzCTSoPx49L8MTnedbGvki3gaiVp0th+1WvnsLo6oGL61nw+TvuSIHdVD1rxr5 ZCHkkOLSHEhtvYnXwdkWCmKKI01vrFgaYBsp9rI9y9ouAor6hHAyaxtyx7rX4JjyJBtt 6ZBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/CNrVYrs9Xb73quEvVQlotZn9+L6OMMxXMmjH1TgHyY=; b=b44EfkXl6ILRUJliOvG9FgZbDuFHAhqhhvGl4mT17qwX2ZykNYts3ZAeDWJ1PbPwgr IR8sfbeVlDNZ3e53NTjcdXZS0/3roZoLLCHtzRPjVYJxjQ+GUqiq6g236HGEIjvUHMZM UffxEW2Xcj5flVnHkUbcap7imXf775EfFlD/f6USBjRMQC9AyfbjM2sL9uB+xPbzfM93 oVuIFQjx2Q2GbQT2+aAW+E+1DN1EHecUGTklCwbDh9Wf4QiLE8PP6ajTF8Mu9Yb6J/en RRi7TEBzvxfu1Ty76eNHDUvLDd9mXdns8yUOAf8LhiD7FVE6BC4xNTUUniS8Mo/yZ7vl 4/ag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eM1NDcBw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/34] Memory: Enable writeback for given memory region Date: Mon, 16 Dec 2019 11:08:57 +0000 Message-Id: <20191216110904.30815-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::329 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Beata Michalska Add an option to trigger memory writeback to sync given memory region with the corresponding backing store, case one is available. This extends the support for persistent memory, allowing syncing on-demand. Signed-off-by: Beata Michalska Reviewed-by: Richard Henderson Message-id: 20191121000843.24844-3-beata.michalska@linaro.org Signed-off-by: Peter Maydell --- include/exec/memory.h | 6 ++++++ include/exec/ram_addr.h | 8 ++++++++ include/qemu/cutils.h | 1 + exec.c | 36 ++++++++++++++++++++++++++++++++++++ memory.c | 12 ++++++++++++ util/cutils.c | 38 ++++++++++++++++++++++++++++++++++++++ 6 files changed, 101 insertions(+) -- 2.20.1 diff --git a/include/exec/memory.h b/include/exec/memory.h index e499dc215b3..27a84e0cc34 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1265,6 +1265,12 @@ void *memory_region_get_ram_ptr(MemoryRegion *mr); */ void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp); +/** + * memory_region_do_writeback: Trigger writeback for selected address range + * [addr, addr + size] + * + */ +void memory_region_do_writeback(MemoryRegion *mr, hwaddr addr, hwaddr size); /** * memory_region_set_log: Turn dirty logging on or off for a region. diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index bed0554f4d2..5adebb0bc7c 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -174,6 +174,14 @@ void qemu_ram_free(RAMBlock *block); int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp); +void qemu_ram_writeback(RAMBlock *block, ram_addr_t start, ram_addr_t length); + +/* Clear whole block of mem */ +static inline void qemu_ram_block_writeback(RAMBlock *block) +{ + qemu_ram_writeback(block, 0, block->used_length); +} + #define DIRTY_CLIENTS_ALL ((1 << DIRTY_MEMORY_NUM) - 1) #define DIRTY_CLIENTS_NOCODE (DIRTY_CLIENTS_ALL & ~(1 << DIRTY_MEMORY_CODE)) diff --git a/include/qemu/cutils.h b/include/qemu/cutils.h index b54c847e0fe..eb59852dfdf 100644 --- a/include/qemu/cutils.h +++ b/include/qemu/cutils.h @@ -130,6 +130,7 @@ const char *qemu_strchrnul(const char *s, int c); #endif time_t mktimegm(struct tm *tm); int qemu_fdatasync(int fd); +int qemu_msync(void *addr, size_t length, int fd); int fcntl_setfl(int fd, int flag); int qemu_parse_fd(const char *param); int qemu_strtoi(const char *nptr, const char **endptr, int base, diff --git a/exec.c b/exec.c index ffdb5185353..a34c3481840 100644 --- a/exec.c +++ b/exec.c @@ -65,6 +65,8 @@ #include "exec/ram_addr.h" #include "exec/log.h" +#include "qemu/pmem.h" + #include "migration/vmstate.h" #include "qemu/range.h" @@ -2156,6 +2158,40 @@ int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp) return 0; } +/* + * Trigger sync on the given ram block for range [start, start + length] + * with the backing store if one is available. + * Otherwise no-op. + * @Note: this is supposed to be a synchronous op. + */ +void qemu_ram_writeback(RAMBlock *block, ram_addr_t start, ram_addr_t length) +{ + void *addr = ramblock_ptr(block, start); + + /* The requested range should fit in within the block range */ + g_assert((start + length) <= block->used_length); + +#ifdef CONFIG_LIBPMEM + /* The lack of support for pmem should not block the sync */ + if (ramblock_is_pmem(block)) { + pmem_persist(addr, length); + return; + } +#endif + if (block->fd >= 0) { + /** + * Case there is no support for PMEM or the memory has not been + * specified as persistent (or is not one) - use the msync. + * Less optimal but still achieves the same goal + */ + if (qemu_msync(addr, length, block->fd)) { + warn_report("%s: failed to sync memory range: start: " + RAM_ADDR_FMT " length: " RAM_ADDR_FMT, + __func__, start, length); + } + } +} + /* Called with ram_list.mutex held */ static void dirty_memory_extend(ram_addr_t old_ram_size, ram_addr_t new_ram_size) diff --git a/memory.c b/memory.c index 06484c2bff2..0228cad38d0 100644 --- a/memory.c +++ b/memory.c @@ -2207,6 +2207,18 @@ void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp qemu_ram_resize(mr->ram_block, newsize, errp); } + +void memory_region_do_writeback(MemoryRegion *mr, hwaddr addr, hwaddr size) +{ + /* + * Might be extended case needed to cover + * different types of memory regions + */ + if (mr->ram_block && mr->dirty_log_mask) { + qemu_ram_writeback(mr->ram_block, addr, size); + } +} + /* * Call proper memory listeners about the change on the newly * added/removed CoalescedMemoryRange. diff --git a/util/cutils.c b/util/cutils.c index 77acadc70ac..23801652303 100644 --- a/util/cutils.c +++ b/util/cutils.c @@ -164,6 +164,44 @@ int qemu_fdatasync(int fd) #endif } +/** + * Sync changes made to the memory mapped file back to the backing + * storage. For POSIX compliant systems this will fallback + * to regular msync call. Otherwise it will trigger whole file sync + * (including the metadata case there is no support to skip that otherwise) + * + * @addr - start of the memory area to be synced + * @length - length of the are to be synced + * @fd - file descriptor for the file to be synced + * (mandatory only for POSIX non-compliant systems) + */ +int qemu_msync(void *addr, size_t length, int fd) +{ +#ifdef CONFIG_POSIX + size_t align_mask = ~(qemu_real_host_page_size - 1); + + /** + * There are no strict reqs as per the length of mapping + * to be synced. Still the length needs to follow the address + * alignment changes. Additionally - round the size to the multiple + * of PAGE_SIZE + */ + length += ((uintptr_t)addr & (qemu_real_host_page_size - 1)); + length = (length + ~align_mask) & align_mask; + + addr = (void *)((uintptr_t)addr & align_mask); + + return msync(addr, length, MS_SYNC); +#else /* CONFIG_POSIX */ + /** + * Perform the sync based on the file descriptor + * The sync range will most probably be wider than the one + * requested - but it will still get the job done + */ + return qemu_fdatasync(fd); +#endif /* CONFIG_POSIX */ +} + #ifndef _WIN32 /* Sets a specific flag */ int fcntl_setfl(int fd, int flag) From patchwork Mon Dec 16 11:08:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181694 Delivered-To: patch@linaro.org Received: by 2002:ac9:44c4:0:0:0:0:0 with SMTP id t4csp4177200och; Mon, 16 Dec 2019 03:29:51 -0800 (PST) X-Google-Smtp-Source: APXvYqzz2HB2WxkRDJLMjpKrbxtU54Srh+fsFgiPJ4gPA83QUSMy/gpir8BmAQaDchD9z6ZDH0NF X-Received: by 2002:a05:6830:1415:: with SMTP id v21mr32610117otp.188.1576495790982; Mon, 16 Dec 2019 03:29:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576495790; cv=none; d=google.com; s=arc-20160816; b=Pk9FqUVE6atgf1RHnKkapfZ14v03ZnSNG3YpNbZ821mRsY7e/ATALepV4xhQ5Bw1oY 3BzI+OWSd6JjDa0Fej/7WxT67dmCsgf3m0E3jHYfU0tEd9rOIf3Jh/nOvldJS0vi8jVb OrDnDRQ/Y1mAqxTOAqz+VeTQM4bLhD9mJNxP7gTW61SpUDLsSPsIjTpHLgzI/Gquuq9x 7As+02UjMZEV4yXtqtFPx8bkXZR2js/Yrh8x6R+qpKxNe50prRQBw9OyAriLVabsIXOP Udf1LmSEXYitw8i6/EWaGC0f8J78Em5kajodcXsbCG3mG7tEzolW8grr25pXDDKx7pd5 M8wA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kiznhuvKz4jfIKm/7fpiveKPXoY6Nj6u7zhRBMk1ww0=; b=UzbGbH0KMXsxFIpdtjSYRLMy4Yl58JHoivHMqpwXxBmyxIpISVa0rT240kay14Zv6i gtFilnbqsMehENEPI9PZd7Uuv2VaiigRueLEHzkhS6uv0uMVVhSXBYb92mfVk7u9xFVn LQZfIJl+MEPpIthg3RzEVrLnZ9hzvPGmoZn/uXczKh+Bdb/VlHf87Zg0nM/hF/8V/sqQ UTSSGIps7itu6YY68TcKEXCNhxQU6BlvhB9b1Nm9fE30hbjlYSHu9ezQXX43FZ1eBhf2 FLzfiG2mI9kV5enVYpHytK3shn808+e4diSgCXn1XxRK7n6wfMCmoknSAi8iZNamXkPV Ga3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jyhMQ+kX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/34] migration: ram: Switch to ram block writeback Date: Mon, 16 Dec 2019 11:08:58 +0000 Message-Id: <20191216110904.30815-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::433 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Beata Michalska Switch to ram block writeback for pmem migration. Signed-off-by: Beata Michalska Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Acked-by: Dr. David Alan Gilbert Message-id: 20191121000843.24844-4-beata.michalska@linaro.org Signed-off-by: Peter Maydell --- migration/ram.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) -- 2.20.1 diff --git a/migration/ram.c b/migration/ram.c index 5078f94490d..38070f1bb23 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -33,7 +33,6 @@ #include "qemu/bitops.h" #include "qemu/bitmap.h" #include "qemu/main-loop.h" -#include "qemu/pmem.h" #include "xbzrle.h" #include "ram.h" #include "migration.h" @@ -3981,9 +3980,7 @@ static int ram_load_cleanup(void *opaque) RAMBlock *rb; RAMBLOCK_FOREACH_NOT_IGNORED(rb) { - if (ramblock_is_pmem(rb)) { - pmem_persist(rb->host, rb->used_length); - } + qemu_ram_block_writeback(rb); } xbzrle_load_cleanup(); From patchwork Mon Dec 16 11:08:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181704 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4189523ile; Mon, 16 Dec 2019 03:38:52 -0800 (PST) X-Google-Smtp-Source: APXvYqxb7PLJgN2k/thpgxDMUONWTfP4fuOHOZ41dS1K5yYwOHITO5osWIIwFMz1cosULOGqga4V X-Received: by 2002:ac8:4693:: with SMTP id g19mr5636664qto.295.1576496332176; Mon, 16 Dec 2019 03:38:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576496332; cv=none; d=google.com; s=arc-20160816; b=zXgD5k3JDJqyGWZ4KVxmfZei0XqhDYTuhSKKAprMfgGqziPEt7yoTubMTYgNIRAD4O KJpkwjoAyvnyIpZ6OTHo2twJgC/GHxEMLFydf316GXE8QEIHnd0Qb9Ime/94rK0JDysd Gm1wqS6ErflVaxE2TsAooT0lieJKPZ3D9VTxNl3L/DgMv1t33utoQ5VgIX3bTftiQTaZ MZnmor25/P62N50wNct1BHaFSp74IFdma8LT0pBcmeC7/wGNJNSN5mmgjt6f2wJGlG1y VzIcKnmKU8T7jIW7gKoBk7SQXW6+mWNOx38RU09MAqQVw2dbJ+vPta9pGO5VHTtsBesx aEAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Bswh7/qVNoTMhX0s3zAgFkoXBHOrNaofcX0A6vxQIhI=; b=WyVOl6KUjYqu0e5bt6qc9JdZS7dE7vRDcqPXRNYGxQfl3/IzNgVtSdZY/zOj2dSdN4 zahmMig8SvmKHc0H0MEtangLracc/8zt8BqjyVXS9n1cO63KcMCUGc2qZM1pEK+Ffwty Ox829aZ606kZ4YeJecZ9ROEK+ktVLT4NXKNQUdnvwAocEEFn5qY1+nfEgfZybWEwJoql LV93S3OQ4/cvvOJc/ufEaR+ADBjJY9NA3lscQVe/MNrLEvuDUd6/+l5fTFKvUoZyBhhJ XBteBPglsoNqNE0OMhXSGaEy9IrENAMY6tYu+v2qHNjx0gOvxyEjQwG4vP4FHdXpLCpd fVug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=avq5xsVz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/34] target/arm: Add support for DC CVAP & DC CVADP ins Date: Mon, 16 Dec 2019 11:08:59 +0000 Message-Id: <20191216110904.30815-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Beata Michalska ARMv8.2 introduced support for Data Cache Clean instructions to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence) - DV CVADP. Both specify conceptual points in a memory system where all writes that are to reach them are considered persistent. The support provided considers both to be actually the same so there is no distinction between the two. If none is available (there is no backing store for given memory) both will result in Data Cache Clean up to the point of coherency. Otherwise sync for the specified range shall be performed. Signed-off-by: Beata Michalska Reviewed-by: Richard Henderson Message-id: 20191121000843.24844-5-beata.michalska@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 10 ++++++++ linux-user/elfload.c | 2 ++ target/arm/cpu64.c | 1 + target/arm/helper.c | 56 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 69 insertions(+) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cebb3511a51..4106e4ae590 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3618,6 +3618,16 @@ static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; } +static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; +} + +static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f6693e57609..07b16cc0f47 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -656,6 +656,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT); GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); + GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); return hwcaps; } @@ -665,6 +666,7 @@ static uint32_t get_elf_hwcap2(void) ARMCPU *cpu = ARM_CPU(thread_cpu); uint32_t hwcaps = 0; + GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a39d6fcea34..61fd0ade29a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -646,6 +646,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64isar0 = t; t = cpu->isar.id_aa64isar1; + t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */ diff --git a/target/arm/helper.c b/target/arm/helper.c index a4f7b61b4e1..3a93844a3bc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5974,6 +5974,52 @@ static const ARMCPRegInfo rndr_reginfo[] = { .access = PL0_R, .readfn = rndr_readfn }, REGINFO_SENTINEL }; + +#ifndef CONFIG_USER_ONLY +static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, + uint64_t value) +{ + ARMCPU *cpu = env_archcpu(env); + /* CTR_EL0 System register -> DminLine, bits [19:16] */ + uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); + uint64_t vaddr_in = (uint64_t) value; + uint64_t vaddr = vaddr_in & ~(dline_size - 1); + void *haddr; + int mem_idx = cpu_mmu_index(env, false); + + /* This won't be crossing page boundaries */ + haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC()); + if (haddr) { + + ram_addr_t offset; + MemoryRegion *mr; + + /* RCU lock is already being held */ + mr = memory_region_from_host(haddr, &offset); + + if (mr) { + memory_region_do_writeback(mr, offset, dline_size); + } + } +} + +static const ARMCPRegInfo dcpop_reg[] = { + { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1, + .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .accessfn = aa64_cacheop_access, .writefn = dccvap_writefn }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo dcpodp_reg[] = { + { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1, + .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .accessfn = aa64_cacheop_access, .writefn = dccvap_writefn }, + REGINFO_SENTINEL +}; +#endif /*CONFIG_USER_ONLY*/ + #endif static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, @@ -7046,6 +7092,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_rndr, cpu)) { define_arm_cp_regs(cpu, rndr_reginfo); } +#ifndef CONFIG_USER_ONLY + /* Data Cache clean instructions up to PoP */ + if (cpu_isar_feature(aa64_dcpop, cpu)) { + define_one_arm_cp_reg(cpu, dcpop_reg); + + if (cpu_isar_feature(aa64_dcpodp, cpu)) { + define_one_arm_cp_reg(cpu, dcpodp_reg); + } + } +#endif /*CONFIG_USER_ONLY*/ #endif /* From patchwork Mon Dec 16 11:09:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181696 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4182260ile; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/34] hw/arm/sbsa-ref: Simplify by moving the gic in the machine state Date: Mon, 16 Dec 2019 11:09:00 +0000 Message-Id: <20191216110904.30815-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42f X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Make the gic a field in the machine state, and instead of filling an array of qemu_irq and passing it around, directly call qdev_get_gpio_in() on the gic field. Signed-off-by: Philippe Mathieu-Daudé Message-id: 20191206162303.30338-1-philmd@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 86 +++++++++++++++++++++++------------------------ 1 file changed, 42 insertions(+), 44 deletions(-) -- 2.20.1 diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 27046cc284f..5853bdee5ce 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -89,6 +89,7 @@ typedef struct { void *fdt; int fdt_size; int psci_conduit; + DeviceState *gic; PFlashCFI01 *flash[2]; } SBSAMachineState; @@ -328,10 +329,9 @@ static void create_secure_ram(SBSAMachineState *sms, memory_region_add_subregion(secure_sysmem, base, secram); } -static void create_gic(SBSAMachineState *sms, qemu_irq *pic) +static void create_gic(SBSAMachineState *sms) { unsigned int smp_cpus = MACHINE(sms)->smp.cpus; - DeviceState *gicdev; SysBusDevice *gicbusdev; const char *gictype; uint32_t redist0_capacity, redist0_count; @@ -339,25 +339,25 @@ static void create_gic(SBSAMachineState *sms, qemu_irq *pic) gictype = gicv3_class_name(); - gicdev = qdev_create(NULL, gictype); - qdev_prop_set_uint32(gicdev, "revision", 3); - qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); + sms->gic = qdev_create(NULL, gictype); + qdev_prop_set_uint32(sms->gic, "revision", 3); + qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); /* * Note that the num-irq property counts both internal and external * interrupts; there are always 32 of the former (mandated by GIC spec). */ - qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); - qdev_prop_set_bit(gicdev, "has-security-extensions", true); + qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); + qdev_prop_set_bit(sms->gic, "has-security-extensions", true); redist0_capacity = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; redist0_count = MIN(smp_cpus, redist0_capacity); - qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1); - qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count); + qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); + qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); - qdev_init_nofail(gicdev); - gicbusdev = SYS_BUS_DEVICE(gicdev); + qdev_init_nofail(sms->gic); + gicbusdev = SYS_BUS_DEVICE(sms->gic); sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); @@ -383,15 +383,15 @@ static void create_gic(SBSAMachineState *sms, qemu_irq *pic) for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { qdev_connect_gpio_out(cpudev, irq, - qdev_get_gpio_in(gicdev, + qdev_get_gpio_in(sms->gic, ppibase + timer_irq[irq])); } qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, - qdev_get_gpio_in(gicdev, ppibase + qdev_get_gpio_in(sms->gic, ppibase + ARCH_GIC_MAINT_IRQ)); qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, - qdev_get_gpio_in(gicdev, ppibase + qdev_get_gpio_in(sms->gic, ppibase + VIRTUAL_PMU_IRQ)); sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); @@ -402,13 +402,9 @@ static void create_gic(SBSAMachineState *sms, qemu_irq *pic) sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); } - - for (i = 0; i < NUM_IRQS; i++) { - pic[i] = qdev_get_gpio_in(gicdev, i); - } } -static void create_uart(const SBSAMachineState *sms, qemu_irq *pic, int uart, +static void create_uart(const SBSAMachineState *sms, int uart, MemoryRegion *mem, Chardev *chr) { hwaddr base = sbsa_ref_memmap[uart].base; @@ -420,15 +416,15 @@ static void create_uart(const SBSAMachineState *sms, qemu_irq *pic, int uart, qdev_init_nofail(dev); memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); - sysbus_connect_irq(s, 0, pic[irq]); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); } -static void create_rtc(const SBSAMachineState *sms, qemu_irq *pic) +static void create_rtc(const SBSAMachineState *sms) { hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; int irq = sbsa_ref_irqmap[SBSA_RTC]; - sysbus_create_simple("pl031", base, pic[irq]); + sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); } static DeviceState *gpio_key_dev; @@ -442,13 +438,14 @@ static Notifier sbsa_ref_powerdown_notifier = { .notify = sbsa_ref_powerdown_req }; -static void create_gpio(const SBSAMachineState *sms, qemu_irq *pic) +static void create_gpio(const SBSAMachineState *sms) { DeviceState *pl061_dev; hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; int irq = sbsa_ref_irqmap[SBSA_GPIO]; - pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); + pl061_dev = sysbus_create_simple("pl061", base, + qdev_get_gpio_in(sms->gic, irq)); gpio_key_dev = sysbus_create_simple("gpio-key", -1, qdev_get_gpio_in(pl061_dev, 3)); @@ -457,7 +454,7 @@ static void create_gpio(const SBSAMachineState *sms, qemu_irq *pic) qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); } -static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic) +static void create_ahci(const SBSAMachineState *sms) { hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; int irq = sbsa_ref_irqmap[SBSA_AHCI]; @@ -471,7 +468,7 @@ static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic) qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); sysahci = SYSBUS_AHCI(dev); ahci = &sysahci->ahci; @@ -484,16 +481,16 @@ static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic) } } -static void create_ehci(const SBSAMachineState *sms, qemu_irq *pic) +static void create_ehci(const SBSAMachineState *sms) { hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; int irq = sbsa_ref_irqmap[SBSA_EHCI]; - sysbus_create_simple("platform-ehci-usb", base, pic[irq]); + sysbus_create_simple("platform-ehci-usb", base, + qdev_get_gpio_in(sms->gic, irq)); } -static void create_smmu(const SBSAMachineState *sms, qemu_irq *pic, - PCIBus *bus) +static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) { hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; int irq = sbsa_ref_irqmap[SBSA_SMMU]; @@ -507,11 +504,12 @@ static void create_smmu(const SBSAMachineState *sms, qemu_irq *pic, qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); for (i = 0; i < NUM_SMMU_IRQS; i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + qdev_get_gpio_in(sms->gic, irq + 1)); } } -static void create_pcie(SBSAMachineState *sms, qemu_irq *pic) +static void create_pcie(SBSAMachineState *sms) { hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; @@ -555,7 +553,8 @@ static void create_pcie(SBSAMachineState *sms, qemu_irq *pic) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); for (i = 0; i < GPEX_NUM_IRQS; i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + qdev_get_gpio_in(sms->gic, irq + 1)); gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); } @@ -574,7 +573,7 @@ static void create_pcie(SBSAMachineState *sms, qemu_irq *pic) pci_create_simple(pci->bus, -1, "VGA"); - create_smmu(sms, pic, pci->bus); + create_smmu(sms, pci->bus); } static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) @@ -598,7 +597,6 @@ static void sbsa_ref_init(MachineState *machine) bool firmware_loaded; const CPUArchIdList *possible_cpus; int n, sbsa_max_cpus; - qemu_irq pic[NUM_IRQS]; if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { error_report("sbsa-ref: CPU type other than the built-in " @@ -695,22 +693,22 @@ static void sbsa_ref_init(MachineState *machine) create_secure_ram(sms, secure_sysmem); - create_gic(sms, pic); + create_gic(sms); - create_uart(sms, pic, SBSA_UART, sysmem, serial_hd(0)); - create_uart(sms, pic, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); + create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); + create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); /* Second secure UART for RAS and MM from EL0 */ - create_uart(sms, pic, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); + create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); - create_rtc(sms, pic); + create_rtc(sms); - create_gpio(sms, pic); + create_gpio(sms); - create_ahci(sms, pic); + create_ahci(sms); - create_ehci(sms, pic); + create_ehci(sms); - create_pcie(sms, pic); + create_pcie(sms); sms->bootinfo.ram_size = machine->ram_size; sms->bootinfo.nb_cpus = smp_cpus; From patchwork Mon Dec 16 11:09:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181710 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4194269ile; Mon, 16 Dec 2019 03:43:41 -0800 (PST) X-Google-Smtp-Source: APXvYqzsiUHS12EY8k0dvfrhrZQi2q21g8+C7sXu9RDv7cGN2wImDzjnFGN7MZxUZXvilBL+k8m1 X-Received: by 2002:a05:6830:13d3:: with SMTP id e19mr31691774otq.135.1576496621728; Mon, 16 Dec 2019 03:43:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576496621; cv=none; d=google.com; s=arc-20160816; b=NQss990ixK4dsVVW3UlZ3kwz9eBZ4GsGNVhMhGLkDADRnQ/0ZkLNE+guWlNZPzGBh9 rmXXxikawpvTv9+WT2UsNr1COpTBxO966hAkk9VUjRy6TEAklAOQwLml/T5Q9Wx3qAe1 8vJf9gbbuaJNbPDHZsowTq/VbCTcoegL3q0jpjvwDSmnUgG9xrqAFG4Zou+VxnjDkejI HorhP/wYSEM+ASpHO5zjkbCq701tENQ93dZ6yDjXKAol5rNbw4LazcUgj9X9mRJBzS3W 9yhXVkJp5bK70DPBzJDvf3D26zhHNo/8S9KG/uDwcNQ8WBFYzaW6cH/jGf2a8pvMxlNx riEg== ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/34] hw/arm/acpi: simplify AML bit and/or statement Date: Mon, 16 Dec 2019 11:09:01 +0000 Message-Id: <20191216110904.30815-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Heyi Guo The last argument of AML bit and/or statement is the target variable, so we don't need to use a NULL target and then an additional store operation; using just aml_and() or aml_or() statement is enough. Also update tests/data/acpi/virt/DSDT* to pass "make check". Cc: Shannon Zhao Cc: Peter Maydell Cc: "Michael S. Tsirkin" Cc: Igor Mammedov Suggested-by: Igor Mammedov Reviewed-by: Igor Mammedov Signed-off-by: Heyi Guo Message-id: 20191209063719.23086-2-guoheyi@huawei.com Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 16 ++++++++-------- tests/data/acpi/virt/DSDT | Bin 18470 -> 18462 bytes tests/data/acpi/virt/DSDT.memhp | Bin 19807 -> 19799 bytes tests/data/acpi/virt/DSDT.numamem | Bin 18470 -> 18462 bytes 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT index bce76e3d23e99e6c5ef64c94c770282dd30ecdd0..05bcfc8a912f58f266aa906563ea01c24906717e 100644 GIT binary patch delta 133 zcmZ2BfpOjhMlP3Nmk>D*1_q|2iCof5o%I{lJ2{y;?{412x!p#mARjJS5V=5L(&S9WT970c2Uv;Nq{%?q7$gZ1761tsfcPNsCD{x4 MAmS{W8QoPG0j8@bzW@LL delta 141 zcmbO?fpOUcMlP3Nmk>1%1_q`n6S<_B8XGpMcXBc{-rKy1bGwazA7{LOuro_nHiNTE zxZwi7$(3%F{sq;}AwfP|vJ4<! diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.memhp index b4b153fcdc30d211237fced6be1e99d3500bd276..c041a910fdf272cb89263bb636239ae3a5e1708d 100644 GIT binary patch delta 132 zcmcaVi}Cs_MlP3NmymE@1_ma@iCof*O&is^IGH-{Zr;SX-A2HTGu}VgnWZb6!PzC; zaDm6_#p8m*$ep~ L;w+mP-Q(B*s{AMU delta 140 zcmcaUi}C&}MlP3Nmymd01_maViCof*T^rT9IGGynZQjJW-A2HVGu}VgnWZb6!PzC; zaDm_CN;gaYf@D*1_q|2iCof5o%I{lJ2{y;?{412x!p#mARjJS5V=5L(&S9WT970c2Uv;Nq{%?q7$gZ1761tsfcPNsCD{x4 MAmS{W8QoPG0j8@bzW@LL delta 141 zcmbO?fpOUcMlP3Nmk>1%1_q`n6S<_B8XGpMcXBc{-rKy1bGwazA7{LOuro_nHiNTE zxZwi7$(3%F{sq;}AwfP|vJ4<! -- 2.20.1 diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 4cd50175e04..51b293e0a1e 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -267,17 +267,17 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); - aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL), - aml_name("CTRL"))); + aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1D), + aml_name("CTRL"))); ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); - aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL), - aml_name("CDW1"))); + aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08), + aml_name("CDW1"))); aml_append(ifctx, ifctx1); ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); - aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL), - aml_name("CDW1"))); + aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10), + aml_name("CDW1"))); aml_append(ifctx, ifctx1); aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); @@ -285,8 +285,8 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, aml_append(method, ifctx); elsectx = aml_else(); - aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL), - aml_name("CDW1"))); + aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4), + aml_name("CDW1"))); aml_append(elsectx, aml_return(aml_arg(3))); aml_append(method, elsectx); aml_append(dev, method); From patchwork Mon Dec 16 11:09:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181695 Delivered-To: patch@linaro.org Received: by 2002:ac9:44c4:0:0:0:0:0 with SMTP id t4csp4178509och; Mon, 16 Dec 2019 03:31:11 -0800 (PST) X-Google-Smtp-Source: APXvYqw54LIYDezyqEn1iorZIfIly+K23Thx+36K8amQGnBop6Q5o/eNIIynNubhf7bGgRNY7+aG X-Received: by 2002:a05:6830:1e69:: with SMTP id m9mr6097077otr.335.1576495871367; Mon, 16 Dec 2019 03:31:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576495871; cv=none; d=google.com; s=arc-20160816; b=UhDssjRHoJFIpfLEt7NLZ00dtRQt2z1A/hzaQglpkEYD7qIYJ+kEsEQ1mp7RZg/Zv2 UzbtlhJfbIl+yKN1+Ol4NtRuffucGBeOD0WOkexWQamaFTXL1IZzQFZxWu8CaA21md86 u8lUvodwGt2wjLfE0kEOj+GZrcaBrHT8OALY3RG7xfTTmWQRGDZnFboKqoKufdU/5K3m /XmTsQNlPOUkCwhs67PAFLiVl3Q/QrKWo9y76UfeZSEEvzMVwTf5u7IATalUL1jV+EYU 0OTEbcR2ca26Fr+gqQSUIirLHs3aNAPJuiLhYPq7kByv0F/1akxd7F+vpYjXMbCzvtwd R5Hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wi/6WNBxanhHv1N5BExE4AXQCOcHHg7jTThmTTrFuxQ=; b=Fkd2uYrdDwFUwi1R6gKMMbm0t/+v91jKAYUFMCWDzxggVwGtbmPrvyEN6faB8HYPcP IlPf+pGooLOcHJvjaavd/9zijgqO72FSGIP5aYI2s+tA5wgJnD5DfDZ7ytoFcKwO017V FFgW8i8pMGV7ioYJc+dbPd43Z1KTz70mbqtWvtrAhAbOMX9yXGabnugx9DfxQJMe7dw5 rgYKlyxZGBUk/W8IrbtFrHfXpEuLLpt8l3OVVB5cWZntEgB6DLwOz9GBHkc4ThwCw/MI FWzJykt6QYneb9nnIlKE9pwwt/H3JT6oR0wlGPShwGKV/tTA0xCOr/dUk8h7G2OVBqaO l/Zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E3fAQ5rM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/34] hw/arm/acpi: enable SHPC native hot plug Date: Mon, 16 Dec 2019 11:09:02 +0000 Message-Id: <20191216110904.30815-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Heyi Guo After the introduction of generic PCIe root port and PCIe-PCI bridge, we will also have SHPC controller on ARM, so just enable SHPC native hot plug. Also update tests/data/acpi/virt/DSDT* to pass "make check". Cc: Shannon Zhao Cc: Peter Maydell Cc: "Michael S. Tsirkin" Cc: Igor Mammedov Reviewed-by: Michael S. Tsirkin Reviewed-by: Igor Mammedov Signed-off-by: Heyi Guo Message-id: 20191209063719.23086-3-guoheyi@huawei.com Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 7 ++++++- tests/data/acpi/virt/DSDT | Bin 18462 -> 18462 bytes tests/data/acpi/virt/DSDT.memhp | Bin 19799 -> 19799 bytes tests/data/acpi/virt/DSDT.numamem | Bin 18462 -> 18462 bytes 4 files changed, 6 insertions(+), 1 deletion(-) diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT index 05bcfc8a912f58f266aa906563ea01c24906717e..d0f3afeb134fdf1c11f64cd06dbcdd30be603b80 100644 GIT binary patch delta 28 kcmbO?fpOjhMlP3Nmk>D*1_q{tja=*8809zbbW3Ff0C~9xM*si- delta 28 kcmbO?fpOjhMlP3Nmk>D*1_q|2ja=*87-cu_bW3Ff0C~j-M*si- diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.memhp index c041a910fdf272cb89263bb636239ae3a5e1708d..41ccc6431b917252bcbaac86c33b340c796be5ce 100644 GIT binary patch delta 28 kcmcaUi}Cs_MlP3NmymE@1_mbija=*8809zbbeqQp0Eq|*2mk;8 delta 28 kcmcaUi}Cs_MlP3NmymE@1_ma@ja=*87-cu_beqQp0ErX{2mk;8 diff --git a/tests/data/acpi/virt/DSDT.numamem b/tests/data/acpi/virt/DSDT.numamem index 05bcfc8a912f58f266aa906563ea01c24906717e..d0f3afeb134fdf1c11f64cd06dbcdd30be603b80 100644 GIT binary patch delta 28 kcmbO?fpOjhMlP3Nmk>D*1_q{tja=*8809zbbW3Ff0C~9xM*si- delta 28 kcmbO?fpOjhMlP3Nmk>D*1_q|2ja=*87-cu_bW3Ff0C~j-M*si- -- 2.20.1 diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 51b293e0a1e..bd5f771e9be 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -267,7 +267,12 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); - aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1D), + + /* + * Allow OS control for all 5 features: + * PCIeHotplug SHPCHotplug PME AER PCIeCapability. + */ + aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F), aml_name("CTRL"))); ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); From patchwork Mon Dec 16 11:09:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181713 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4196218ile; Mon, 16 Dec 2019 03:45:44 -0800 (PST) X-Google-Smtp-Source: APXvYqzCcnfkM69TiynC+n6g0uIWIAs++jTl2zGDd7BPVRNrYvIChXRTE8oXzUYKW+xlS1V+qsGW X-Received: by 2002:a37:6851:: with SMTP id d78mr5255865qkc.246.1576496744751; Mon, 16 Dec 2019 03:45:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576496744; cv=none; d=google.com; s=arc-20160816; b=fVDvur5qN8nEJqNn7lvejzXDChWCMCMbHj8oBZ8llWPLmyMdWVhSBkZ7De++ctBpaE ALs8a4IyqgHcLoOPjMO0DKJP0zlwJDeZVvf3NGNwxB8jfd3hlTT+kmeWmsxoiIEk276e XF4fwRMNxny4X4j1PYRuJPeish+BMztLpk7qdecPh5XxGIcBKHG2my013bFJKFSrO7wR hKmvy2AUoqsxhncKtekrXP+1jiyfugsP5BJ6WLG4FNac81mDk4ZxoL/uGzoFXnCTlUPv xZS7bdPkyNGFCqGIgU5O35to5e+pjFN3+MeUtgFVTTSzWnaPDP9ej0Spb+1XueGzD20w W56g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7nY5MqSyOV50wVoDXR+NSInZ+hJVrBD1WXiJuwo9v6M=; b=D2zHBLa1Hq/ZPfPon9B1Re5XuFP8qwgkXtt257DNiQx56B21u8xVzlFzaM5VETrfGv dYwLRyqOJejtQUor5KEhKJ9+svTAB+jXyCtihWuYawavh55m+5d2M6MRnbFVYfKfXbkF Eg5betvR8n+FDpaZ1keZ714IFWDPSiohJMqFjeS8JyQzwjHvRCJN+84P1BFtateSJJWS +Y0/5zgPXDyPR5B0aAqASQ+gppFlSAv7v5vxuyjmokZclnWyOjNMvnhrvuWNzEPdcAV6 OlCL+iO6EiRLOUTdw8AFvtgn+K2OKYSCtNqbEt0pJk9+pfyG+DJas8imB097RCwwxdwf Ahnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DaTHXOzJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/34] hw/arm/virt: Simplify by moving the gic in the machine state Date: Mon, 16 Dec 2019 11:09:03 +0000 Message-Id: <20191216110904.30815-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::330 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Make the gic a field in the machine state, and instead of filling an array of qemu_irq and passing it around, directly call qdev_get_gpio_in() on the gic field. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20191209090306.20433-1-philmd@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/virt.h | 1 + hw/arm/virt.c | 109 +++++++++++++++++++++--------------------- 2 files changed, 55 insertions(+), 55 deletions(-) -- 2.20.1 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 0b41083e9d5..38f0c33c77c 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -136,6 +136,7 @@ typedef struct { uint32_t iommu_phandle; int psci_conduit; hwaddr highest_gpa; + DeviceState *gic; DeviceState *acpi_dev; Notifier powerdown_notifier; } VirtMachineState; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index bf4b1cbfb86..6f2a45d1b4c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -531,7 +531,7 @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms) } } -static inline DeviceState *create_acpi_ged(VirtMachineState *vms, qemu_irq *pic) +static inline DeviceState *create_acpi_ged(VirtMachineState *vms) { DeviceState *dev; MachineState *ms = MACHINE(vms); @@ -547,14 +547,14 @@ static inline DeviceState *create_acpi_ged(VirtMachineState *vms, qemu_irq *pic) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); qdev_init_nofail(dev); return dev; } -static void create_its(VirtMachineState *vms, DeviceState *gicdev) +static void create_its(VirtMachineState *vms) { const char *itsclass = its_class_name(); DeviceState *dev; @@ -566,7 +566,7 @@ static void create_its(VirtMachineState *vms, DeviceState *gicdev) dev = qdev_create(NULL, itsclass); - object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", + object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3", &error_abort); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); @@ -574,7 +574,7 @@ static void create_its(VirtMachineState *vms, DeviceState *gicdev) fdt_add_its_gic_node(vms); } -static void create_v2m(VirtMachineState *vms, qemu_irq *pic) +static void create_v2m(VirtMachineState *vms) { int i; int irq = vms->irqmap[VIRT_GIC_V2M]; @@ -587,17 +587,17 @@ static void create_v2m(VirtMachineState *vms, qemu_irq *pic) qdev_init_nofail(dev); for (i = 0; i < NUM_GICV2M_SPIS; i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + qdev_get_gpio_in(vms->gic, irq + i)); } fdt_add_v2m_gic_node(vms); } -static void create_gic(VirtMachineState *vms, qemu_irq *pic) +static void create_gic(VirtMachineState *vms) { MachineState *ms = MACHINE(vms); /* We create a standalone GIC */ - DeviceState *gicdev; SysBusDevice *gicbusdev; const char *gictype; int type = vms->gic_version, i; @@ -606,15 +606,15 @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic) gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); - gicdev = qdev_create(NULL, gictype); - qdev_prop_set_uint32(gicdev, "revision", type); - qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); + vms->gic = qdev_create(NULL, gictype); + qdev_prop_set_uint32(vms->gic, "revision", type); + qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); /* Note that the num-irq property counts both internal and external * interrupts; there are always 32 of the former (mandated by GIC spec). */ - qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); + qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); if (!kvm_irqchip_in_kernel()) { - qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); + qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); } if (type == 3) { @@ -624,25 +624,25 @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic) nb_redist_regions = virt_gicv3_redist_region_count(vms); - qdev_prop_set_uint32(gicdev, "len-redist-region-count", + qdev_prop_set_uint32(vms->gic, "len-redist-region-count", nb_redist_regions); - qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count); + qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); if (nb_redist_regions == 2) { uint32_t redist1_capacity = vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; - qdev_prop_set_uint32(gicdev, "redist-region-count[1]", + qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", MIN(smp_cpus - redist0_count, redist1_capacity)); } } else { if (!kvm_irqchip_in_kernel()) { - qdev_prop_set_bit(gicdev, "has-virtualization-extensions", + qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", vms->virt); } } - qdev_init_nofail(gicdev); - gicbusdev = SYS_BUS_DEVICE(gicdev); + qdev_init_nofail(vms->gic); + gicbusdev = SYS_BUS_DEVICE(vms->gic); sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); if (type == 3) { sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); @@ -678,23 +678,23 @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic) for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { qdev_connect_gpio_out(cpudev, irq, - qdev_get_gpio_in(gicdev, + qdev_get_gpio_in(vms->gic, ppibase + timer_irq[irq])); } if (type == 3) { - qemu_irq irq = qdev_get_gpio_in(gicdev, + qemu_irq irq = qdev_get_gpio_in(vms->gic, ppibase + ARCH_GIC_MAINT_IRQ); qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, irq); } else if (vms->virt) { - qemu_irq irq = qdev_get_gpio_in(gicdev, + qemu_irq irq = qdev_get_gpio_in(vms->gic, ppibase + ARCH_GIC_MAINT_IRQ); sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); } qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, - qdev_get_gpio_in(gicdev, ppibase + qdev_get_gpio_in(vms->gic, ppibase + VIRTUAL_PMU_IRQ)); sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); @@ -706,20 +706,16 @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic) qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); } - for (i = 0; i < NUM_IRQS; i++) { - pic[i] = qdev_get_gpio_in(gicdev, i); - } - fdt_add_gic_node(vms); if (type == 3 && vms->its) { - create_its(vms, gicdev); + create_its(vms); } else if (type == 2) { - create_v2m(vms, pic); + create_v2m(vms); } } -static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, +static void create_uart(const VirtMachineState *vms, int uart, MemoryRegion *mem, Chardev *chr) { char *nodename; @@ -735,7 +731,7 @@ static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, qdev_init_nofail(dev); memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); - sysbus_connect_irq(s, 0, pic[irq]); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); nodename = g_strdup_printf("/pl011@%" PRIx64, base); qemu_fdt_add_subnode(vms->fdt, nodename); @@ -767,7 +763,7 @@ static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, g_free(nodename); } -static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) +static void create_rtc(const VirtMachineState *vms) { char *nodename; hwaddr base = vms->memmap[VIRT_RTC].base; @@ -775,7 +771,7 @@ static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) int irq = vms->irqmap[VIRT_RTC]; const char compat[] = "arm,pl031\0arm,primecell"; - sysbus_create_simple("pl031", base, pic[irq]); + sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); nodename = g_strdup_printf("/pl031@%" PRIx64, base); qemu_fdt_add_subnode(vms->fdt, nodename); @@ -803,7 +799,7 @@ static void virt_powerdown_req(Notifier *n, void *opaque) } } -static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) +static void create_gpio(const VirtMachineState *vms) { char *nodename; DeviceState *pl061_dev; @@ -812,7 +808,8 @@ static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) int irq = vms->irqmap[VIRT_GPIO]; const char compat[] = "arm,pl061\0arm,primecell"; - pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); + pl061_dev = sysbus_create_simple("pl061", base, + qdev_get_gpio_in(vms->gic, irq)); uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); nodename = g_strdup_printf("/pl061@%" PRIx64, base); @@ -846,7 +843,7 @@ static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) g_free(nodename); } -static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) +static void create_virtio_devices(const VirtMachineState *vms) { int i; hwaddr size = vms->memmap[VIRT_MMIO].size; @@ -882,7 +879,8 @@ static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) int irq = vms->irqmap[VIRT_MMIO] + i; hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; - sysbus_create_simple("virtio-mmio", base, pic[irq]); + sysbus_create_simple("virtio-mmio", base, + qdev_get_gpio_in(vms->gic, irq)); } /* We add dtb nodes in reverse order so that they appear in the finished @@ -1131,7 +1129,7 @@ static void create_pcie_irq_map(const VirtMachineState *vms, 0x7 /* PCI irq */); } -static void create_smmu(const VirtMachineState *vms, qemu_irq *pic, +static void create_smmu(const VirtMachineState *vms, PCIBus *bus) { char *node; @@ -1154,7 +1152,8 @@ static void create_smmu(const VirtMachineState *vms, qemu_irq *pic, qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); for (i = 0; i < NUM_SMMU_IRQS; i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + qdev_get_gpio_in(vms->gic, irq + i)); } node = g_strdup_printf("/smmuv3@%" PRIx64, base); @@ -1181,7 +1180,7 @@ static void create_smmu(const VirtMachineState *vms, qemu_irq *pic, g_free(node); } -static void create_pcie(VirtMachineState *vms, qemu_irq *pic) +static void create_pcie(VirtMachineState *vms) { hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; @@ -1241,7 +1240,8 @@ static void create_pcie(VirtMachineState *vms, qemu_irq *pic) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); for (i = 0; i < GPEX_NUM_IRQS; i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + qdev_get_gpio_in(vms->gic, irq + i)); gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); } @@ -1301,7 +1301,7 @@ static void create_pcie(VirtMachineState *vms, qemu_irq *pic) if (vms->iommu) { vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); - create_smmu(vms, pic, pci->bus); + create_smmu(vms, pci->bus); qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", 0x0, vms->iommu_phandle, 0x0, 0x10000); @@ -1310,7 +1310,7 @@ static void create_pcie(VirtMachineState *vms, qemu_irq *pic) g_free(nodename); } -static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) +static void create_platform_bus(VirtMachineState *vms) { DeviceState *dev; SysBusDevice *s; @@ -1326,8 +1326,8 @@ static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) s = SYS_BUS_DEVICE(dev); for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { - int irqn = vms->irqmap[VIRT_PLATFORM_BUS] + i; - sysbus_connect_irq(s, i, pic[irqn]); + int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; + sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); } memory_region_add_subregion(sysmem, @@ -1509,7 +1509,6 @@ static void machvirt_init(MachineState *machine) VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); MachineClass *mc = MACHINE_GET_CLASS(machine); const CPUArchIdList *possible_cpus; - qemu_irq pic[NUM_IRQS]; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *secure_sysmem = NULL; int n, virt_max_cpus; @@ -1712,27 +1711,27 @@ static void machvirt_init(MachineState *machine) virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); - create_gic(vms, pic); + create_gic(vms); fdt_add_pmu_nodes(vms); - create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0)); + create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); if (vms->secure) { create_secure_ram(vms, secure_sysmem); - create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); + create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); } vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); - create_rtc(vms, pic); + create_rtc(vms); - create_pcie(vms, pic); + create_pcie(vms); if (has_ged && aarch64 && firmware_loaded && acpi_enabled) { - vms->acpi_dev = create_acpi_ged(vms, pic); + vms->acpi_dev = create_acpi_ged(vms); } else { - create_gpio(vms, pic); + create_gpio(vms); } /* connect powerdown request */ @@ -1743,12 +1742,12 @@ static void machvirt_init(MachineState *machine) * (which will be automatically plugged in to the transports). If * no backend is created the transport will just sit harmlessly idle. */ - create_virtio_devices(vms, pic); + create_virtio_devices(vms); vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); rom_set_fw(vms->fw_cfg); - create_platform_bus(vms, pic); + create_platform_bus(vms); vms->bootinfo.ram_size = machine->ram_size; vms->bootinfo.nb_cpus = smp_cpus; From patchwork Mon Dec 16 11:09:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 181706 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4189845ile; Mon, 16 Dec 2019 03:39:11 -0800 (PST) X-Google-Smtp-Source: APXvYqxQWAzmn42ttJdneKAzAFxrIeeHO01kmXRxSMrfHsBAeO6RjUIYceS1oQbxhDhrBEFru/a1 X-Received: by 2002:a9d:6005:: with SMTP id h5mr32693456otj.153.1576496351938; Mon, 16 Dec 2019 03:39:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576496351; cv=none; d=google.com; s=arc-20160816; b=ZIDg+1bqBTRrUXgTatbnxOPO6rXXedyOgKUUDj2U2vB1FCX8FjHgBDaPgJfYsyscs7 6JFkPUB+1yeBSEmnWVDBFfVKaS2HHzZgjuf5NFXJpea4ptgBC8SCuKLlPA16S6fkQgW+ KRChwICdfTsBQiaAddaGda8zwxmOzolexqkFgQaF+K0sfkkeXO0uWLnyntGJUSj1B8qw aF5gLG5GFYcZ+zWbhIV+TZbRo0o6lm6ugGD6EFO6rU0FmlEpvTU7f/IC+Ff0lkvHuKPx T7y0ERcahEomQ2WJgTS6geZsYJnZn6nhDJBS0E3m01vScSosaDL+ISoQ+TtFP7ZlNfrw fbBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DIuLYiQq5xzu9Y0KMgE74Fd5M3uLmxz+SEXsEQw/Wpg=; b=rAw6w+POmFywv81Nf5HA4UVeJKxDKlzxZvE3gA/daEMvgezB7RYoZfM/bdwnIeFsOY 7H3KJgd9t7QMtq8VoBNX9OmOEG//kzkdj/u0ekRFx/GLXPHcOXkS5bbTAXBDS66h+CCl Qx6Wqa0IWb2VNswdReghv8gWrrzrTUTUdQoLNK0JhLvSFdKKrcckLTPFUFeYGCZdKOeS aTwPFSly3u4x1CnIXc/c8ckiiCo5l5/inQEQFW7p3Pe7pVRgrUpfIZXKAdcy4ZN6UxyU ehhNpbYFsm2vprgxBwhDSLim0rYku5H5QtPLTqiBVt/xtFs5kmkuJNcEL2hwwKc5LxLe XIGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xOFCkSjQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x10sm20976131wrp.58.2019.12.16.03.09.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 03:09:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/34] target/arm: ensure we use current exception state after SCR update Date: Mon, 16 Dec 2019 11:09:04 +0000 Message-Id: <20191216110904.30815-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191216110904.30815-1-peter.maydell@linaro.org> References: <20191216110904.30815-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée A write to the SCR can change the effective EL by droppping the system from secure to non-secure mode. However if we use a cached current_el from before the change we'll rebuild the flags incorrectly. To fix this we introduce the ARM_CP_NEWEL CP flag to indicate the new EL should be used when recomputing the flags. Signed-off-by: Alex Bennée Tested-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20191212114734.6962-1-alex.bennee@linaro.org Cc: Richard Henderson Message-Id: <20191209143723.6368-1-alex.bennee@linaro.org> Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 8 ++++++-- target/arm/helper.h | 1 + target/arm/helper.c | 14 +++++++++++++- target/arm/translate.c | 6 +++++- 4 files changed, 25 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4106e4ae590..5f70e9e0438 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2238,6 +2238,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) * RAISES_EXC is for when the read or write hook might raise an exception; * the generated code will synchronize the CPU state before calling the hook * so that it is safe for the hook to call raise_exception(). + * NEWEL is for writes to registers that might change the exception + * level - typically on older ARM chips. For those cases we need to + * re-read the new el when recomputing the translation flags. */ #define ARM_CP_SPECIAL 0x0001 #define ARM_CP_CONST 0x0002 @@ -2257,10 +2260,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) #define ARM_CP_SVE 0x2000 #define ARM_CP_NO_GDB 0x4000 #define ARM_CP_RAISES_EXC 0x8000 +#define ARM_CP_NEWEL 0x10000 /* Used only as a terminator for ARMCPRegInfo lists */ -#define ARM_CP_SENTINEL 0xffff +#define ARM_CP_SENTINEL 0xfffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0xf0ff +#define ARM_CP_FLAG_MASK 0x1f0ff /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/target/arm/helper.h b/target/arm/helper.h index 7ce5169afb5..aa3d8cd08fa 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -91,6 +91,7 @@ DEF_HELPER_2(get_user_reg, i32, env, i32) DEF_HELPER_3(set_user_reg, void, env, i32, i32) DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3a93844a3bc..5074b5f69ca 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5133,7 +5133,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), .resetvalue = 0, .writefn = scr_write }, - { .name = "SCR", .type = ARM_CP_ALIAS, + { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL, .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, .access = PL1_RW, .accessfn = access_trap_aa32s_el1, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), @@ -11472,6 +11472,18 @@ void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); } +/* + * If we have triggered a EL state change we can't rely on the + * translator having passed it too us, we need to recompute. + */ +void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) +{ + int el = arm_current_el(env); + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); +} + void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) { int fp_el = fp_exception_el(env, el); diff --git a/target/arm/translate.c b/target/arm/translate.c index f162be8434f..2b6c1f91bf9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7083,7 +7083,11 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) if (arm_dc_feature(s, ARM_FEATURE_M)) { gen_helper_rebuild_hflags_m32(cpu_env, tcg_el); } else { - gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + if (ri->type & ARM_CP_NEWEL) { + gen_helper_rebuild_hflags_a32_newel(cpu_env); + } else { + gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + } } tcg_temp_free_i32(tcg_el); /*