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Mon, 16 Dec 2019 13:14:23 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20191216131423eusmtrp152303804333bee9a2cfadb08336547a2~g3EYat_bW3045930459eusmtrp1r; Mon, 16 Dec 2019 13:14:23 +0000 (GMT) X-AuditID: cbfec7f2-f0bff7000001ef66-e5-5df7832f19b3 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 14.44.08375.F2387FD5; Mon, 16 Dec 2019 13:14:23 +0000 (GMT) Received: from AMDC2765.digital.local (unknown [106.120.51.73]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20191216131422eusmtip175022561335d172149a30b2ef56af16b~g3EX6sSFY1012910129eusmtip1d; Mon, 16 Dec 2019 13:14:22 +0000 (GMT) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Marian Mihailescu , Stephen Boyd Subject: [PATCH v2] clk: samsung: exynos5420: Keep top G3D clocks enabled Date: Mon, 16 Dec 2019 14:14:07 +0100 Message-Id: <20191216131407.17225-1-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrKIsWRmVeSWpSXmKPExsWy7djPc7r6zd9jDX69VbbYOGM9q8X1L89Z Lc6f38Bu8bHnHqvFjPP7mCzWHrnLbrF+2k9Wi3/XNrJYtD99yezA6bFz1l12j02rOtk8+ras YvT4vEkugCWKyyYlNSezLLVI3y6BK6Nl1W2WgikqFX9/LWdpYPwu18XIySEhYCLx7/sxli5G Lg4hgRWMEk+evWGGcL4wStxd0QSV+cwosfDmDyaYlrUrpjNCJJYzSizecg2hZesJkH5ODjYB Q4mut11sILaIgIPE50+vwTqYBTYxSVxZswWsSFjAU2JTyzqwsSwCqhKPpnWwgti8ArYSkxes g1onL7F6wwGwDRIC99kkmvdvYIdIuEjc6f7CCmELS7w6vgUqLiNxenIPC0RDM6PEw3Nr2SGc HkaJy00zGCGqrCUOH78I1M0BdJOmxPpd+iCmhICjxINFDhAmn8SNt4IgxcxA5qRt05khwrwS HW1CEDPUJGYdXwe39eCFS8wQtofE7A3/wWwhgViJ1Wu7mScwys1CWLWAkXEVo3hqaXFuemqx YV5quV5xYm5xaV66XnJ+7iZGYGI4/e/4px2MXy8lHWIU4GBU4uGVKPkeK8SaWFZcmXuIUYKD WUmEd4cCUIg3JbGyKrUoP76oNCe1+BCjNAeLkjiv8aKXsUIC6YklqdmpqQWpRTBZJg5OqQbG 8O+prUKrPZan3+qfppLtZh0YzLaIZ9HTCCVzc/MvTS8OFNnKvfAxEXA/qKJs8lNpsfG8b54i XE+YpPXvPJD/77c27Mnltwmsd7KuKNR1Vd35Mdu2brdXzd+sidqvTqVu4zGTVfHpkL0y5wlP YzizyOP9B2o2SzFfUdH6OqneNXa21LHUjUFKLMUZiYZazEXFiQC8Z91XCAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrNLMWRmVeSWpSXmKPExsVy+t/xu7r6zd9jDV6v4LHYOGM9q8X1L89Z Lc6f38Bu8bHnHqvFjPP7mCzWHrnLbrF+2k9Wi3/XNrJYtD99yezA6bFz1l12j02rOtk8+ras YvT4vEkugCVKz6Yov7QkVSEjv7jEVina0MJIz9DSQs/IxFLP0Ng81srIVEnfziYlNSezLLVI 3y5BL6Nl1W2WgikqFX9/LWdpYPwu18XIySEhYCKxdsV0xi5GLg4hgaWMEiuObWeBSMhInJzW wAphC0v8udbFBlH0iVHiyNw5jCAJNgFDia63IAlODhEBJ4kH696wgxQxC2xjkti5/T5Yt7CA p8SmlnVMIDaLgKrEo2kdYHFeAVuJyQsg4hIC8hKrNxxgnsDIs4CRYRWjSGppcW56brGhXnFi bnFpXrpecn7uJkZgQG479nPzDsZLG4MPMQpwMCrx8EqUfI8VYk0sK67MPcQowcGsJMK7QwEo xJuSWFmVWpQfX1Sak1p8iNEUaPlEZinR5HxgtOSVxBuaGppbWBqaG5sbm1koifN2CByMERJI TyxJzU5NLUgtgulj4uCUamBM5E9pSZa5EKHttWL2sdmrsvyTbCYUv8hRejIpZotQmP530cs9 q4SlJyZf5nrw790JoUni54LXFb9qWL/7rNoBN49tooLXA2uan7Asi7E+Yz1lz1n/CK+NtY8l zr7ZE7DtnV9w4JzZ2QHvj6/SDPpcGhGn2tM06XKy1rMpIQElxQ/idsmnNVkrsRRnJBpqMRcV JwIAidcuoF4CAAA= X-CMS-MailID: 20191216131423eucas1p2162d6bf0a870357be9f0ab308641015b X-Msg-Generator: CA X-RootMTR: 20191216131423eucas1p2162d6bf0a870357be9f0ab308641015b X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20191216131423eucas1p2162d6bf0a870357be9f0ab308641015b References: Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org In Exynos542x/5800 SoCs, the G3D leaf clocks are located in the G3D power domain. This is similar to the other hardware modules and their power domains. However there is one thing specific to G3D clocks hierarchy. Unlike other hardware modules, the G3D clocks hierarchy doesn't have any gate clock between the TOP part of the hierarchy and the part located in the power domain and some SoC internal busses are sourced directly from the TOP muxes. The consequence of this design if the fact that the TOP part of the hierarchy has to be enabled permanently to ensure proper operation of the SoC power related components (G3D power domain and Exynos Power Management Unit for system suspend/resume). This patch adds an explicit call to clk_prepare_enable() on the last MUX in the TOP part of G3D clock hierarchy to keep it enabled permanently to ensure that the internal busses get their clock regardless of the main G3D clock enablement status. This fixes following imprecise abort issue observed on Odroid XU3/XU4 after enabling Panfrost driver by commit 1a5a85c56402 "ARM: dts: exynos: Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4"): panfrost 11800000.gpu: clock rate = 400000000 panfrost 11800000.gpu: failed to get regulator: -517 panfrost 11800000.gpu: regulator init failed -517 Power domain G3D disable failed ... panfrost 11800000.gpu: clock rate = 400000000 8<--- cut here --- Unhandled fault: imprecise external abort (0x1406) at 0x00000000 pgd = (ptrval) [00000000] *pgd=00000000 Internal error: : 1406 [#1] PREEMPT SMP ARM Modules linked in: CPU: 7 PID: 53 Comm: kworker/7:1 Not tainted 5.4.0-rc8-next-20191119-00032-g56f1001191a6 #6923 Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) Workqueue: events deferred_probe_work_func PC is at panfrost_gpu_soft_reset+0x94/0x110 LR is at ___might_sleep+0x128/0x2dc ... [] (panfrost_gpu_soft_reset) from [] (panfrost_gpu_init+0x10/0x67c) [] (panfrost_gpu_init) from [] (panfrost_device_init+0x158/0x2cc) [] (panfrost_device_init) from [] (panfrost_probe+0x80/0x178) [] (panfrost_probe) from [] (platform_drv_probe+0x48/0x9c) [] (platform_drv_probe) from [] (really_probe+0x1c4/0x474) [] (really_probe) from [] (driver_probe_device+0x78/0x1bc) [] (driver_probe_device) from [] (bus_for_each_drv+0x74/0xb8) [] (bus_for_each_drv) from [] (__device_attach+0xd4/0x16c) [] (__device_attach) from [] (bus_probe_device+0x88/0x90) [] (bus_probe_device) from [] (deferred_probe_work_func+0x4c/0xd0) [] (deferred_probe_work_func) from [] (process_one_work+0x300/0x864) [] (process_one_work) from [] (worker_thread+0x58/0x5a0) [] (worker_thread) from [] (kthread+0x12c/0x160) [] (kthread) from [] (ret_from_fork+0x14/0x20) Exception stack(0xee03dfb0 to 0xee03dff8) ... Code: e594300c e5933020 e3130c01 1a00000f (ebefff50). ---[ end trace badde2b74a65a540 ]--- In the above case, the Panfrost driver disables G3D clocks after failure of getting the needed regulator and return with -EPROVE_DEFER code. This causes G3D power domain disable failure and then, during second probe an imprecise abort is triggered due to undefined power domain state. Fixes: 45f10dabb56b ("clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path") Fixes: c9f7567aff31 ("clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU") Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos5420.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.17.1 Acked-by: Krzysztof Kozlowski Acked-by: Chanwoo Choi Acked-by: Sylwester Nawrocki diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 3a991ca1ee36..c9e5a1fb6653 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "clk.h" #include "clk-cpu.h" @@ -1646,6 +1647,13 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_subcmus); } + /* + * Keep top part of G3D clock path enabled permanently to ensure + * that the internal busses get their clock regardless of the + * main G3D clock enablement status. + */ + clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d")); + samsung_clk_of_add_provider(np, ctx); }