From patchwork Fri Jun 23 14:58:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 106267 Delivered-To: patch@linaro.org Received: by 10.140.91.2 with SMTP id y2csp251864qgd; Fri, 23 Jun 2017 07:59:09 -0700 (PDT) X-Received: by 10.98.30.65 with SMTP id e62mr8682993pfe.127.1498229949045; Fri, 23 Jun 2017 07:59:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498229949; cv=none; d=google.com; s=arc-20160816; b=B8uSLCjCu8zLDspsEqY7SIE5BCcS2Hoc/7uLrY6xZ1DmuRGA4bXmU3WpgfxROCUupH v95k5QKqufsn4rp5iW4e73Tp9jd+saT+M2AOH0S2Ku4hKGzprauCBWZ0Y5FUqFVOLcxm zw0cUe1N2Zk+LtPRDlBFCMyf/vganj5bC3OaiHf/AC2VhAPBZjcUSjRxKth4TVBgMlOV OjWr9+WT5IGktckRWBpWP4CqjGJPkXGXcHh95zgTVrFjqsqPkw2jS/cpLP5VQO5oUNX/ M3rD1Azqm6OSKOXrXcZWNEQXUcXGhkqI1DvhKT3hAZ06lAVwjJgPUKzPOjYxtARe3mKH wsgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=rOSAkZlcEZCmSsCQOXPTe1/UpPNUJV2Y0/eGIMjr5UI=; b=XCZjZPrT7YfMmS43hfBn+1KXyaLDZ/e3kHr6zRCb5uWs8RVRCGbfjaCKnY3URmP/1x ACun1csG9w0epy5MDrq4nODE8kyjuVJOY1m0CssTOjaq45ngwFUNVJfrhmlVOEYYz1gs 8KpbgcFjqbggbwp9zaER3cxUKy6gn0GLLxn46/gxXMBPdbgA5MOztK0PqmheXjCx1pm8 eZTRK/MF6/aA9c8om9dY1ZAXUS06z7eCiPIRL/UP24QLMThPL7hg5zKROfEvtBGMVtNh 2GI4t4zTk1zOuObyLsrhUJXmd6pKIiB1icrP/rfMvDaSXOVp28p7ZR6dqyKcFkTtMrZR 3eXw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p11si3597830pgn.190.2017.06.23.07.59.08; Fri, 23 Jun 2017 07:59:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754412AbdFWO7I (ORCPT + 8 others); Fri, 23 Jun 2017 10:59:08 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:7932 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754048AbdFWO7H (ORCPT ); Fri, 23 Jun 2017 10:59:07 -0400 Received: from 172.30.72.54 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.54]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APX86085; Fri, 23 Jun 2017 22:59:03 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Fri, 23 Jun 2017 22:58:53 +0800 From: shameer To: , , , , , CC: , , , , , , , , , shameer Subject: [PATCH v3 1/2] acpi:iort: Add an IORT helper function to reserve HW ITS address regions for IOMMU drivers Date: Fri, 23 Jun 2017 15:58:00 +0100 Message-ID: <20170623145801.325244-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170623145801.325244-1-shameerali.kolothum.thodi@huawei.com> References: <20170623145801.325244-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.594D2CB8.0010, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 8a5128e3e00207e71d2f276805dad689 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The helper function retrieves ITS address regions through IORT device <-> ITS mappings and reserves it so that these regions will not be translated by IOMMU and will be excluded from IOVA allocations. IOMMU drivers can use this to implement their .get_resv_regions callback. Signed-off-by: shameer --- drivers/acpi/arm64/iort.c | 91 ++++++++++++++++++++++++++++++++++++++-- drivers/irqchip/irq-gic-v3-its.c | 3 +- include/linux/acpi_iort.h | 7 +++- 3 files changed, 96 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index c5fecf9..cf0a6b8 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -34,6 +34,7 @@ struct iort_its_msi_chip { struct list_head list; struct fwnode_handle *fw_node; + phys_addr_t base_addr; u32 translation_id; }; @@ -131,14 +132,16 @@ typedef acpi_status (*iort_find_node_callback) static DEFINE_SPINLOCK(iort_msi_chip_lock); /** - * iort_register_domain_token() - register domain token and related ITS ID - * to the list from where we can get it back later on. + * iort_register_domain_token() - register domain token along with related + * ITS ID and base address to the list from where we can get it back later on. * @trans_id: ITS ID. + * @base: ITS base address. * @fw_node: Domain token. * * Returns: 0 on success, -ENOMEM if no memory when allocating list element */ -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) +int iort_register_domain_token(int trans_id, phys_addr_t base, + struct fwnode_handle *fw_node) { struct iort_its_msi_chip *its_msi_chip; @@ -148,6 +151,7 @@ int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) its_msi_chip->fw_node = fw_node; its_msi_chip->translation_id = trans_id; + its_msi_chip->base_addr = base; spin_lock(&iort_msi_chip_lock); list_add(&its_msi_chip->list, &iort_msi_chip_list); @@ -491,6 +495,24 @@ int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id) return -ENODEV; } +static int iort_find_its_base(u32 its_id, phys_addr_t *base) +{ + struct iort_its_msi_chip *its_msi_chip; + bool match = false; + + spin_lock(&iort_msi_chip_lock); + list_for_each_entry(its_msi_chip, &iort_msi_chip_list, list) { + if (its_msi_chip->translation_id == its_id) { + *base = its_msi_chip->base_addr; + match = true; + break; + } + } + spin_unlock(&iort_msi_chip_lock); + + return match ? 0 : -ENODEV; +} + /** * iort_dev_find_its_id() - Find the ITS identifier for a device * @dev: The device. @@ -649,6 +671,67 @@ int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev) return err; } + +/** + * iort_iommu_its_get_resv_regions - Reserved region driver helper + * @dev: Device from iommu_get_resv_regions() + * @list: Reserved region list from iommu_get_resv_regions() + * + * Returns: Number of reserved regions on success(0 if no associated ITS), + * appropriate error value otherwise. + * + * IOMMU drivers can use this to implement their .get_resv_regions callback + * for reserving the HW ITS address regions. + */ +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head) +{ + int i; + struct acpi_iort_its_group *its; + struct acpi_iort_node *node, *its_node = NULL; + int resv = 0; + + node = iort_find_dev_node(dev); + if (!node) + return -ENODEV; + + if (dev_is_pci(dev)) { + u32 rid; + + pci_for_each_dma_alias(to_pci_dev(dev), __get_pci_rid, &rid); + its_node = iort_node_map_id(node, rid, NULL, IORT_MSI_TYPE); + } else { + for (i = 0; i < node->mapping_count; i++) { + its_node = iort_node_map_platform_id(node, NULL, + IORT_MSI_TYPE, i); + if (its_node) + break; + } + } + + if (!its_node) + return 0; + + /* Move to ITS specific data */ + its = (struct acpi_iort_its_group *)its_node->node_data; + + for (i = 0; i < its->its_count; i++) { + phys_addr_t base; + + if (!iort_find_its_base(its->identifiers[i], &base)) { + int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + struct iommu_resv_region *region; + + region = iommu_alloc_resv_region(base, SZ_128K, prot, + IOMMU_RESV_MSI); + if (region) { + list_add_tail(®ion->list, head); + resv++; + } + } + } + + return resv ? : -ENODEV; +} #else static inline const struct iommu_ops *iort_fwspec_iommu_ops(struct iommu_fwspec *fwspec) @@ -656,6 +739,8 @@ const struct iommu_ops *iort_fwspec_iommu_ops(struct iommu_fwspec *fwspec) static inline int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev) { return 0; } +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head) +{ return -ENODEV; } #endif static const struct iommu_ops *iort_iommu_xlate(struct device *dev, diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 45ea1933..c45a2ad 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1854,7 +1854,8 @@ static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, return -ENOMEM; } - err = iort_register_domain_token(its_entry->translation_id, dom_handle); + err = iort_register_domain_token(its_entry->translation_id, res.start, + dom_handle); if (err) { pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", &res.start, its_entry->translation_id); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 3ff9ace..35cf45c 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -26,7 +26,8 @@ #define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL) #define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL) -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node); +int iort_register_domain_token(int trans_id, phys_addr_t base, + struct fwnode_handle *fw_node); void iort_deregister_domain_token(int trans_id); struct fwnode_handle *iort_find_domain_token(int trans_id); #ifdef CONFIG_ACPI_IORT @@ -39,6 +40,7 @@ /* IOMMU interface */ void iort_set_dma_mask(struct device *dev); const struct iommu_ops *iort_iommu_configure(struct device *dev); +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head); #else static inline void acpi_iort_init(void) { } static inline bool iort_node_match(u8 type) { return false; } @@ -53,6 +55,9 @@ static inline void iort_set_dma_mask(struct device *dev) { } static inline const struct iommu_ops *iort_iommu_configure(struct device *dev) { return NULL; } +static inline +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head) +{ return -ENODEV; } #endif #endif /* __ACPI_IORT_H__ */ From patchwork Fri Jun 23 14:58:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 106268 Delivered-To: patch@linaro.org Received: by 10.140.91.2 with SMTP id y2csp251883qgd; Fri, 23 Jun 2017 07:59:12 -0700 (PDT) X-Received: by 10.98.72.201 with SMTP id q70mr1535395pfi.23.1498229952340; Fri, 23 Jun 2017 07:59:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498229952; cv=none; d=google.com; s=arc-20160816; b=W/OsIvELFT3WG0+PyJyf9060ZzsOofhNiIlO09Rp+BduTpVi1jb7CXW3rNUqZ8SmcR 05Jjzn0S2nR1aXO+FK2I8ZeB2eZPpXSRMooLf+zrhcP+CyyqcACka/qkPkoR2V08WbT4 /Kt/MHk/hmUmGfRvAzrAaRCK2YCY3X2508j/bjaURjVH8xYNTVZ9aU2P1nQCcv+gSVWP 32EotIxdrLn+trmxkPFf7i1WpNZKxdMGLLe6a2eVR4HerAjE8aH/008DpEXL64bA5gMR 8m9uYRvrsJkJ2+Orkjv1xlofxzVPYjzHK3lbfNiOD6uRsLk0liu1VQ2jPgOTxsXNmcYV eRBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=W31SLF1wlS2fIynPt7++0iKaFtDhWb9dQtVwjm8M19U=; b=DbReZOlij/jVilAxquxuIDjHKlDT9tY3IcY7APlilMsSwg81FUPH0yk6VTbFmMm3c0 JOHXjcZzOmER2RUsiAKCrgLCQCPn/cxlrvwkFbYzZGplVbPWm7Bjbf8pm6TLSRRe33Yj 0l9OnIXIVq1onyQsAGeG86b7gn0CGj4f9aoNy60HhqME6wewlYekoM7AsUWCDfMoBeRU 1DQZdMdUv4RG6S1jBoF5Svt5kyjz+pNgADmZU0w3S6lkQ37uVPbQbOjnJ6bOZREMn0m+ fFBJJiYVBL5e17ZVx7xn7U+jr+zfbWhwQNZtMHeyqHNgQ9uYw9gFhA9WWz99tCs1EGU5 p83w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p11si3597830pgn.190.2017.06.23.07.59.12; Fri, 23 Jun 2017 07:59:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754421AbdFWO7L (ORCPT + 8 others); Fri, 23 Jun 2017 10:59:11 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:8787 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754418AbdFWO7L (ORCPT ); Fri, 23 Jun 2017 10:59:11 -0400 Received: from 172.30.72.55 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AQV92878; Fri, 23 Jun 2017 22:59:08 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Fri, 23 Jun 2017 22:59:00 +0800 From: shameer To: , , , , , CC: , , , , , , , , , shameer Subject: [PATCH v3 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Date: Fri, 23 Jun 2017 15:58:01 +0100 Message-ID: <20170623145801.325244-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170623145801.325244-1-shameerali.kolothum.thodi@huawei.com> References: <20170623145801.325244-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.594D2CBD.0014, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: f9c2803f2005d7378305baa35f391a70 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a ACPI table based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. Signed-off-by: shameer --- drivers/iommu/arm-smmu-v3.c | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index abe4b88..c9346f2 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -597,6 +597,7 @@ struct arm_smmu_device { u32 features; #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) +#define ARM_SMMU_OPT_RESV_HW_MSI (1 << 1) u32 options; struct arm_smmu_cmdq cmdq; @@ -1904,14 +1905,34 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { struct iommu_resv_region *region; + struct arm_smmu_device *smmu; + struct iommu_fwspec *fwspec = dev->iommu_fwspec; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + int resv = 0; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); - if (!region) + smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); + if (WARN_ON(!smmu)) return; - list_add_tail(®ion->list, head); + if ((smmu->options & ARM_SMMU_OPT_RESV_HW_MSI)) { + + if (!is_of_node(smmu->dev->fwnode)) + resv = iort_iommu_its_get_resv_regions(dev, head); + + if (resv < 0) { + dev_warn(dev, "HW MSI region resv failed: %d\n", resv); + return; + } + } + + if (!resv) { + region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, + prot, IOMMU_RESV_SW_MSI); + if (!region) + return; + + list_add_tail(®ion->list, head); + } iommu_dma_get_resv_regions(dev, head); } @@ -2611,6 +2632,7 @@ static void parse_driver_acpi_options(struct acpi_iort_smmu_v3 *iort_smmu, switch (iort_smmu->model) { case ACPI_IORT_SMMU_HISILICON_HI161X: smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; break; default: break;