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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm6109675wrq.16.2020.02.11.09.37.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2020 09:37:30 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/13] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers Date: Tue, 11 Feb 2020 17:37:14 +0000 Message-Id: <20200211173726.22541-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211173726.22541-1-peter.maydell@linaro.org> References: <20200211173726.22541-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Enforce a convention that an isar_feature function that tests a 32-bit ID register always has _aa32_ in its name, and one that tests a 64-bit ID register always has _aa64_ in its name. We already follow this except for three cases: thumb_div, arm_div and jazelle, which all need _aa32_ adding. (As noted in the comment, isar_feature_aa32_fp16_arith() is an exception in that it currently tests ID_AA64PFR0_EL1, but will switch to MVFR1 once we've properly implemented FP16 for AArch32.) Signed-off-by: Peter Maydell --- target/arm/cpu.h | 13 ++++++++++--- linux-user/elfload.c | 4 ++-- target/arm/cpu.c | 6 ++++-- target/arm/helper.c | 2 +- target/arm/translate.c | 6 +++--- 5 files changed, 20 insertions(+), 11 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 608fcbd0b75..ad2f0e172a7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3396,20 +3396,27 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) /* Shared between translate-sve.c and sve_helper.c. */ extern const uint64_t pred_esz_masks[4]; +/* + * Naming convention for isar_feature functions: + * Functions which test 32-bit ID registers should have _aa32_ in + * their name. Functions which test 64-bit ID registers should have + * _aa64_ in their name. + */ + /* * 32-bit feature tests via id registers. */ -static inline bool isar_feature_thumb_div(const ARMISARegisters *id) +static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; } -static inline bool isar_feature_arm_div(const ARMISARegisters *id) +static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; } -static inline bool isar_feature_jazelle(const ARMISARegisters *id) +static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; } diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f3080a16358..b1a895f24ce 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -475,8 +475,8 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); - GET_FEATURE_ID(arm_div, ARM_HWCAP_ARM_IDIVA); - GET_FEATURE_ID(thumb_div, ARM_HWCAP_ARM_IDIVT); + GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA); + GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT); /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.c. * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f86e71a260d..5712082c0b9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1470,7 +1470,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) * Presence of EL2 itself is ARM_FEATURE_EL2, and of the * Security Extensions is ARM_FEATURE_EL3. */ - assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu)); + assert(!tcg_enabled() || no_aa32 || + cpu_isar_feature(aa32_arm_div, cpu)); set_feature(env, ARM_FEATURE_LPAE); set_feature(env, ARM_FEATURE_V7); } @@ -1496,7 +1497,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); if (!arm_feature(env, ARM_FEATURE_M)) { - assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu)); + assert(!tcg_enabled() || no_aa32 || + cpu_isar_feature(aa32_jazelle, cpu)); set_feature(env, ARM_FEATURE_AUXCR); } } diff --git a/target/arm/helper.c b/target/arm/helper.c index 19a57a17da5..ddfd0183d98 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6781,7 +6781,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_LPAE)) { define_arm_cp_regs(cpu, lpae_cp_reginfo); } - if (cpu_isar_feature(jazelle, cpu)) { + if (cpu_isar_feature(aa32_jazelle, cpu)) { define_arm_cp_regs(cpu, jazelle_regs); } /* Slightly awkwardly, the OMAP and StrongARM cores need all of diff --git a/target/arm/translate.c b/target/arm/translate.c index 2f4aea927f1..052992037cc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -42,7 +42,7 @@ #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) /* currently all emulated v5 cores are also v5TE, so don't bother */ #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) -#define ENABLE_ARCH_5J dc_isar_feature(jazelle, s) +#define ENABLE_ARCH_5J dc_isar_feature(aa32_jazelle, s) #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2) @@ -9850,8 +9850,8 @@ static bool op_div(DisasContext *s, arg_rrr *a, bool u) TCGv_i32 t1, t2; if (s->thumb - ? !dc_isar_feature(thumb_div, s) - : !dc_isar_feature(arm_div, s)) { + ? !dc_isar_feature(aa32_thumb_div, s) + : !dc_isar_feature(aa32_arm_div, s)) { return false; } From patchwork Tue Feb 11 17:37:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 183285 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp5580325ile; Tue, 11 Feb 2020 09:39:40 -0800 (PST) X-Google-Smtp-Source: APXvYqxU1ZNTTVqqdQGo5alKDHWncUz/866QCtymPvjYHj67BDmM6Y5DicPLhUcQq8A53s9JR5aE X-Received: by 2002:a37:bd85:: with SMTP id n127mr7335657qkf.113.1581442780814; Tue, 11 Feb 2020 09:39:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581442780; cv=none; d=google.com; s=arc-20160816; b=M6eyq0QN03fvjDRy6V4N24LG5UWnB7jxV2a/VR0SrQMJ0aEhskHWYNZrgwV4Cv2Mcy +ToepvzO2N3YUuuDVMyue2YPXu66TUebS25HM1LvFpfrCSsAlDKTlP45Pcotztcqu4dl 5FId4xImwHA8+pvxgkM8mGzgPgw6od0e6hL/8HaKvrBKYSRFyXVCqtGFcM9c6FnLuVOa Z/H5RRoeyY7utIK7matejcYQ1QvqTQ0UDqWKADtilVm3f/g23yD1q7aUnHRejGFNWLAm 72GH2txOuPNbjJdBE7KZZzCjSqbiz6wPvwKQ9/9sg6jS+gm8cBQ6x1tvIxPzaf4V5/YG G53Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UvzHW7FwqyjZQe8719x2kLtn+42I2f2TvPE23s84PqM=; b=cVdPg2KXY7Jx0RKVgHGHlYWsel1b928APa961TdRYA3PEIHrxXnFqzeqhbsNf8YzyR zl0LFVAjZb7K+lKCrG6OssYb+R0Zp2s4nb4aqIxI2EgHp249pmb7NliPpfC4pTd5DKKr NFTuZSxV8YBQX9MJWkJHocWd3HNe87Gf6cJdmucohFllppj0pC4/5nCAMsnvqY5V6VB+ tuGtQnH8Zaw+kOoHtJ31d1rRkwWVEIayq4JsizrI2tCC3D3gMxbtVjxtdoQmvQ3hrdya guFL7APcLB55kx2g/uMvoGw1lkrC06tMVBdpdRZxzyOZWmqzwriG7mtoaJPUk/0ntqwb AQAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=tX+E3GiG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm6109675wrq.16.2020.02.11.09.37.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2020 09:37:31 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/13] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions Date: Tue, 11 Feb 2020 17:37:15 +0000 Message-Id: <20200211173726.22541-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211173726.22541-1-peter.maydell@linaro.org> References: <20200211173726.22541-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Our current usage of the isar_feature feature tests almost always uses an _aa32_ test when the code path is known to be AArch32 specific and an _aa64_ test when the code path is known to be AArch64 specific. There is just one exception: in the vfp_set_fpscr helper we check aa64_fp16 to determine whether the FZ16 bit in the FP(S)CR exists, but this code is also used for AArch32. There are other places in future where we're likely to want a general "does this feature exist for either AArch32 or AArch64" check (typically where architecturally the feature exists for both CPU states if it exists at all, but the CPU might be AArch32-only or AArch64-only, and so only have one set of ID registers). Introduce a new category of isar_feature_* functions: isar_feature_any_foo() should be tested when what we want to know is "does this feature exist for either AArch32 or AArch64", and always returns the logical OR of isar_feature_aa32_foo() and isar_feature_aa64_foo(). Signed-off-by: Peter Maydell --- target/arm/cpu.h | 19 ++++++++++++++++++- target/arm/vfp_helper.c | 2 +- 2 files changed, 19 insertions(+), 2 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ad2f0e172a7..ac4b7950166 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3400,7 +3400,16 @@ extern const uint64_t pred_esz_masks[4]; * Naming convention for isar_feature functions: * Functions which test 32-bit ID registers should have _aa32_ in * their name. Functions which test 64-bit ID registers should have - * _aa64_ in their name. + * _aa64_ in their name. These must only be used in code where we + * know for certain that the CPU has AArch32 or AArch64 respectively + * or where the correct answer for a CPU which doesn't implement that + * CPU state is "false" (eg when generating A32 or A64 code, if adding + * system registers that are specific to that CPU state, for "should + * we let this system register bit be set" tests where the 32-bit + * flavour of the register doesn't have the bit, and so on). + * Functions which simply ask "does this feature exist at all" have + * _any_ in their name, and always return the logical OR of the _aa64_ + * and the _aa32_ function. */ /* @@ -3702,6 +3711,14 @@ static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; } +/* + * Feature tests for "does this exist in either 32-bit or 64-bit?" + */ +static inline bool isar_feature_any_fp16(const ARMISARegisters *id) +{ + return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 0ae7d4f34a9..930d6e747f6 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -185,7 +185,7 @@ uint32_t vfp_get_fpscr(CPUARMState *env) void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ - if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) { + if (!cpu_isar_feature(any_fp16, env_archcpu(env))) { val &= ~FPCR_FZ16; } From patchwork Tue Feb 11 17:37:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 183286 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp5580359ile; Tue, 11 Feb 2020 09:39:43 -0800 (PST) X-Google-Smtp-Source: APXvYqy+5bLXGrCelZtizjQDmVy7wVHsJfsHu/NPFpwBMfivpSZwJcK4yXfGPkXq8BtQAT73TWnL X-Received: by 2002:a05:620a:662:: with SMTP id a2mr3873840qkh.329.1581442783006; Tue, 11 Feb 2020 09:39:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581442783; cv=none; d=google.com; s=arc-20160816; b=09z49wkCKD8bxS0rZ0XRR659aTXqGS1i1Vy3MOkpKV5RUgB4CMjybcxVRFG2m+C1jN vLyvFeftZ9U7M6XvPvU1KoI4Bf/bmi23zepEZJApHQ6ZrasYGWlLFhGs6b0KnyqgzcEj pDh+d8FPeCoJ6BJMpyIds434iQnluefsi2sRIE/6bf8ooyL62T4W8N+sAjjUGfGA57xy f7S2Z0dRMOGbbgi83Iuln7uKZnLuLAaX/XTMHj4eIUXAYQM0i47S/IDT+vw4hDIPAZgT OEt0wVWlxgiv3iDZChCJl03vT0hvJellhx0AqVHoTKZXZBvRu8OemPNLRCwOuPfsUJXm OyzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Gu4Ok/18d9t4bS+gGDbkd/ibAEuGshhJuDPzFWbBLFg=; b=nAiXxQVn7lppHFlhmH1ShGYla4HIsgc1nRYlUMRxJb9nZXnmM4MO1wPg6tFib2aHaV MYJcd4BJlBs1jvS03zulaJ0/WQRPa5jN6mKfleTSdyf/roL04vyoFCjjlQQ78Yz3CAIC +WptXJqaQMXCIVhPo4VGSsmuhSPIEIxFY+s5UNiM1aQd3y7MnjJqsfYqMe6VCDH3aPRc K/oEcpxFwpUVjvt2rXl3APzBLCfCu6mg5c5M32Eme1EmIablDvlQYjltOI0/9abK1/Wk MNYzzjgV9supEGfh1XAjKJDsRc2eh3TMyszEuFe7g/Z0a0BzXPXyjVGrDlrCvHoZETf0 o/Ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QeptztjY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm6109675wrq.16.2020.02.11.09.37.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2020 09:37:32 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/13] target/arm: Define and use any_predinv isar_feature test Date: Tue, 11 Feb 2020 17:37:16 +0000 Message-Id: <20200211173726.22541-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211173726.22541-1-peter.maydell@linaro.org> References: <20200211173726.22541-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Instead of open-coding "ARM_FEATURE_AARCH64 ? aa64_predinv: aa32_predinv", define and use an any_predinv isar_feature test function. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 +++++ target/arm/helper.c | 9 +-------- 2 files changed, 6 insertions(+), 8 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ac4b7950166..b1f3ecfd942 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3719,6 +3719,11 @@ static inline bool isar_feature_any_fp16(const ARMISARegisters *id) return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); } +static inline bool isar_feature_any_predinv(const ARMISARegisters *id) +{ + return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index ddfd0183d98..bf083c369fc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7116,14 +7116,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) #endif /*CONFIG_USER_ONLY*/ #endif - /* - * While all v8.0 cpus support aarch64, QEMU does have configurations - * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max, - * which will set ID_ISAR6. - */ - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) - ? cpu_isar_feature(aa64_predinv, cpu) - : cpu_isar_feature(aa32_predinv, cpu)) { + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } } From patchwork Tue Feb 11 17:37:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 183291 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp5582653ile; Tue, 11 Feb 2020 09:42:30 -0800 (PST) X-Google-Smtp-Source: APXvYqzQKrQJCD9sNaViMFqxRYQqjKup0DhSMdD66ocDlFOuZ1leAt2eH1lIxMBR6d1ZC1Eiryd6 X-Received: by 2002:a05:620a:146a:: with SMTP id j10mr6946448qkl.19.1581442950452; Tue, 11 Feb 2020 09:42:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581442950; cv=none; d=google.com; s=arc-20160816; b=ckj6o1fCUJ8QVNy4FjJT4jkq7qMnUcgiDXPE4wsZwngaYOAFx7brj/7dnShTCHkQAg B6hOGrPNOYkDW0RhY2N/GOzq5SFO92qV7qJjbqg1serX1q7uL283nUNjq0AEM3LMKsjO y1CZuGz7NWElJ9six0JezdeQ+uCP2CAbxDvV1Ddg36rRkLLeB5ncZWLK8DKvOXd210rl XqiWH0DDT/nRbPWlYaTI/gBBZjpdTAlvhg6riWFbNHPPluW5pj2vdhgEx/dM3aiWtney 1PJb/5EajXkLlrPPaJY2Ui/MmvxAV+YOxcojbJjsHzZtsdaEqcBZLyY1GLD+j0CsbKtG z0Xg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/e1L4KBHqvWrooUDR5lzsFsfvdP9rosN0/X6B5pxbVQ=; b=CoceEPGXrPbCAH09j7aq5ilceP1SPKsCkzE5mIscVak48cydy3cOhd3IG3wpNhhe70 17oGb4xFHA3BiFpPBdcEzFS3/ATTednRD5I4ydsq3vZcn7rlC8xpnwadNeSwVDAJRix8 6aS0Ry0uOjvVnsb83fjyYpJEaXs7bVvcKJkAhOHF2cJVZbKQRcqLDyrnGhRKeoKUC1w1 lYHsiCohFswZX0xX53Zv08nqwTEDhXXf2bERgtki+VgRkz88DJtKgZSvMlgYMUXpkmTm xA0xdUuCLkxo4TMuqn/02jrGfnORyBr0iyYNO/9/Wp9R6/3xXFxRsOD3PXFj9ZAlT4Oh Nukw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=znBIwIhD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a17si2206717qkl.66.2020.02.11.09.42.30 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 11 Feb 2020 09:42:30 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=znBIwIhD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54404 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j1ZYL-0005GF-SY for patch@linaro.org; Tue, 11 Feb 2020 12:42:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48505) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j1ZTj-0005k6-FZ for qemu-devel@nongnu.org; Tue, 11 Feb 2020 12:37:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j1ZTg-00044R-SW for qemu-devel@nongnu.org; Tue, 11 Feb 2020 12:37:43 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:35036) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j1ZTc-0003zB-FU for qemu-devel@nongnu.org; Tue, 11 Feb 2020 12:37:36 -0500 Received: by mail-wr1-x442.google.com with SMTP id w12so13502869wrt.2 for ; Tue, 11 Feb 2020 09:37:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/e1L4KBHqvWrooUDR5lzsFsfvdP9rosN0/X6B5pxbVQ=; b=znBIwIhDmIxmIoTItLT0q7uzwiIA1KqsWbNUs92C22Qac89yVzNPSPcsdULHf6dxia QS7P3j70Mga4qlgBM6wKNwkPjfeOVBNGf93pJOpuLFvq87RFvp/0O8hXInydbaVpEdjH Veorn/QTTAqMcJ40itejTs0+6n5+2Z8ukBhYyRpZKrj9O51vKtRgzi5vGZKwO/BI2kHN RzG32HLjiwJD3hCKkaJY1wqYx3K0d3hhpOdSB/0pVQ44nz/dgnvFMpsohquApZ2kKE16 +f4GrpAl5mIaHDDQuwVdQhk8/r7gWvaDRold5DFmxnGtGUaA5NohEtzhAR46i1Q+jQyi GZJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/e1L4KBHqvWrooUDR5lzsFsfvdP9rosN0/X6B5pxbVQ=; b=rKSRnlmBV3oNqLv9WBz5k1NsqrDICfmRN3bKrL6z1lpx0QwWlv4jYumWeuFom7vDhD pwl7grNztEmZnfPQuYgPS+soZDQWPDvLzVE82nntZWFlvxdbqSv3N6vBRhX8EpaV4NNz AEZrYW9d6GmeBBuHV9pTS9W6j3lFBX/zYwlKSCOAY+gg8Dad1KecMYJ98ZpQzGfDtTn+ GKDwfcLl0CqRIUI3/GEi12iuwjZKVFGpImnS5exSkxb7iOYl6+dgrC2NLrsnbaCKwGNo bCOj3e8HZmLrPvMYH6TTDr2EP2VXNqH3YOkO3De+s6RYe2vmDHOwUs7LdTkbed+Eqqv8 U5NQ== X-Gm-Message-State: APjAAAXCffMlQqTEO3i5Sf5ADBiGWQE1div+HqCOc4hpJMmOPo5KYbCS IPpN5GMHwr2gBLv5TCOdsCNf6RPl8Nw= X-Received: by 2002:a5d:6789:: with SMTP id v9mr10154631wru.55.1581442655275; Tue, 11 Feb 2020 09:37:35 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm6109675wrq.16.2020.02.11.09.37.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2020 09:37:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/13] target/arm: Factor out PMU register definitions Date: Tue, 11 Feb 2020 17:37:17 +0000 Message-Id: <20200211173726.22541-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211173726.22541-1-peter.maydell@linaro.org> References: <20200211173726.22541-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Pull the code that defines the various PMU registers out into its own function, matching the pattern we have already for the debug registers. Apart from one style fix to a multi-line comment, this is purely movement of code with no changes to it. Signed-off-by: Peter Maydell --- target/arm/helper.c | 158 +++++++++++++++++++++++--------------------- 1 file changed, 82 insertions(+), 76 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/helper.c b/target/arm/helper.c index bf083c369fc..0011a22f42d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5822,6 +5822,87 @@ static void define_debug_regs(ARMCPU *cpu) } } +static void define_pmu_regs(ARMCPU *cpu) +{ + /* + * v7 performance monitor control register: same implementor + * field as main ID register, and we implement four counters in + * addition to the cycle count register. + */ + unsigned int i, pmcrn = 4; + ARMCPRegInfo pmcr = { + .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, + .access = PL0_RW, + .type = ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), + .accessfn = pmreg_access, .writefn = pmcr_write, + .raw_writefn = raw_write, + }; + ARMCPRegInfo pmcr64 = { + .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, + .access = PL0_RW, .accessfn = pmreg_access, + .type = ARM_CP_IO, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), + .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT), + .writefn = pmcr_write, .raw_writefn = raw_write, + }; + define_one_arm_cp_reg(cpu, &pmcr); + define_one_arm_cp_reg(cpu, &pmcr64); + for (i = 0; i < pmcrn; i++) { + char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i); + char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i); + char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i); + char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i); + ARMCPRegInfo pmev_regs[] = { + { .name = pmevcntr_name, .cp = 15, .crn = 14, + .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, + .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, + .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, + .accessfn = pmreg_access }, + { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), + .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, + .type = ARM_CP_IO, + .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, + .raw_readfn = pmevcntr_rawread, + .raw_writefn = pmevcntr_rawwrite }, + { .name = pmevtyper_name, .cp = 15, .crn = 14, + .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, + .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, + .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, + .accessfn = pmreg_access }, + { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)), + .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, + .type = ARM_CP_IO, + .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, + .raw_writefn = pmevtyper_rawwrite }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, pmev_regs); + g_free(pmevcntr_name); + g_free(pmevcntr_el0_name); + g_free(pmevtyper_name); + g_free(pmevtyper_el0_name); + } + if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 && + FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) { + ARMCPRegInfo v81_pmu_regs[] = { + { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, + .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, + .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, + .resetvalue = extract64(cpu->pmceid0, 32, 32) }, + { .name = "PMCEID3", .state = ARM_CP_STATE_AA32, + .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, + .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, + .resetvalue = extract64(cpu->pmceid1, 32, 32) }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, v81_pmu_regs); + } +} + /* We don't know until after realize whether there's a GICv3 * attached, and that is what registers the gicv3 sysregs. * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1 @@ -6244,67 +6325,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, pmovsset_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_V7)) { - /* v7 performance monitor control register: same implementor - * field as main ID register, and we implement four counters in - * addition to the cycle count register. - */ - unsigned int i, pmcrn = 4; - ARMCPRegInfo pmcr = { - .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, - .access = PL0_RW, - .type = ARM_CP_IO | ARM_CP_ALIAS, - .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), - .accessfn = pmreg_access, .writefn = pmcr_write, - .raw_writefn = raw_write, - }; - ARMCPRegInfo pmcr64 = { - .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, - .access = PL0_RW, .accessfn = pmreg_access, - .type = ARM_CP_IO, - .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT), - .writefn = pmcr_write, .raw_writefn = raw_write, - }; - define_one_arm_cp_reg(cpu, &pmcr); - define_one_arm_cp_reg(cpu, &pmcr64); - for (i = 0; i < pmcrn; i++) { - char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i); - char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i); - char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i); - char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i); - ARMCPRegInfo pmev_regs[] = { - { .name = pmevcntr_name, .cp = 15, .crn = 14, - .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, - .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, - .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, - .accessfn = pmreg_access }, - { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), - .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, - .type = ARM_CP_IO, - .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, - .raw_readfn = pmevcntr_rawread, - .raw_writefn = pmevcntr_rawwrite }, - { .name = pmevtyper_name, .cp = 15, .crn = 14, - .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, - .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, - .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, - .accessfn = pmreg_access }, - { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)), - .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, - .type = ARM_CP_IO, - .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, - .raw_writefn = pmevtyper_rawwrite }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, pmev_regs); - g_free(pmevcntr_name); - g_free(pmevcntr_el0_name); - g_free(pmevtyper_name); - g_free(pmevtyper_el0_name); - } ARMCPRegInfo clidr = { .name = "CLIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, @@ -6315,24 +6335,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &clidr); define_arm_cp_regs(cpu, v7_cp_reginfo); define_debug_regs(cpu); + define_pmu_regs(cpu); } else { define_arm_cp_regs(cpu, not_v7_cp_reginfo); } - if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 && - FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) { - ARMCPRegInfo v81_pmu_regs[] = { - { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, - .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, - .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, - .resetvalue = extract64(cpu->pmceid0, 32, 32) }, - { .name = "PMCEID3", .state = ARM_CP_STATE_AA32, - .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, - .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, - .resetvalue = extract64(cpu->pmceid1, 32, 32) }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, v81_pmu_regs); - } if (arm_feature(env, ARM_FEATURE_V8)) { /* AArch64 ID registers, which all have impdef reset values. * Note that within the ID register ranges the unused slots From patchwork Tue Feb 11 17:37:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 183292 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp5582802ile; Tue, 11 Feb 2020 09:42:42 -0800 (PST) X-Google-Smtp-Source: APXvYqxAmct76u49AuihAkC7aD2KX/DW2tmN8WKcVX29LJzr0sA0ooZ5ONGwdmBbXVLqs6EKrLzy X-Received: by 2002:ac8:740c:: with SMTP id p12mr3465409qtq.286.1581442961958; Tue, 11 Feb 2020 09:42:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581442961; cv=none; d=google.com; s=arc-20160816; b=PKSEy2cOik69fnXPQ93Vz0fM8R80XRXOVp8e9bIj+xuc7DOb9qCmQW4zQWoPcRtCMK tjhoJgvbMRYOOEKUwJeqvbT90H9V+2n1EpyyCtwft1bKeJhBgXLSbKM7t3OmEdIONPeN GheCnHJTABUSjGXyk/bUiEiNLtXpm2LmUlKPUwuiDnb2gNCiQGA/9Wfi+wVhLIMc4Fzy Tk216rUb/DDzyXPUX85OeBinPf2k6bZ6BV732qnkmcWVLxGRxNeGjl+romuY2CPKKACn 6m1g1lNwSfSzx/sqbuFncLUFbsYtIhyR3/xRl/+6EwbHh/y4EwX1D+HS6HXt0eWvkNH+ A6lA== ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm6109675wrq.16.2020.02.11.09.37.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2020 09:37:35 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/13] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1 Date: Tue, 11 Feb 2020 17:37:18 +0000 Message-Id: <20200211173726.22541-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211173726.22541-1-peter.maydell@linaro.org> References: <20200211173726.22541-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add FIELD() definitions for the ID_AA64DFR0_EL1 and use them where we currently have hard-coded bit values. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 10 ++++++++++ target/arm/cpu.c | 2 +- target/arm/helper.c | 6 +++--- 3 files changed, 14 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b1f3ecfd942..f2194b27ba3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1806,6 +1806,16 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4) FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) FIELD(ID_AA64MMFR1, XNX, 28, 4) +FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) +FIELD(ID_AA64DFR0, TRACEVER, 4, 4) +FIELD(ID_AA64DFR0, PMUVER, 8, 4) +FIELD(ID_AA64DFR0, BRPS, 12, 4) +FIELD(ID_AA64DFR0, WRPS, 20, 4) +FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) +FIELD(ID_AA64DFR0, PMSVER, 32, 4) +FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) +FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5712082c0b9..dc582da8fa4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1602,7 +1602,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu); #endif } else { - cpu->id_aa64dfr0 &= ~0xf00; + cpu->id_aa64dfr0 = FIELD_DP32(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); cpu->id_dfr0 &= ~(0xf << 24); cpu->pmceid0 = 0; cpu->pmceid1 = 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 0011a22f42d..2a57bfd9e86 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5771,9 +5771,9 @@ static void define_debug_regs(ARMCPU *cpu) * check that if they both exist then they agree. */ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); - assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); - assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); + assert(FIELD_EX32(cpu->id_aa64dfr0, ID_AA64DFR0, BRPS) == brps); + assert(FIELD_EX32(cpu->id_aa64dfr0, ID_AA64DFR0, WRPS) == wrps); + assert(FIELD_EX32(cpu->id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) == ctx_cmps); } define_one_arm_cp_reg(cpu, &dbgdidr); From patchwork Tue Feb 11 17:37:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 183289 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp5582344ile; Tue, 11 Feb 2020 09:42:08 -0800 (PST) X-Google-Smtp-Source: APXvYqzSy4iTPDz5VBW7f5Tpcu+3420l6TyYF6e/crGoFIDCm21NT6hvSqsUSRdNy5g75Ivmhc0F X-Received: by 2002:a05:620a:1422:: with SMTP id k2mr3368574qkj.407.1581442927861; Tue, 11 Feb 2020 09:42:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581442927; cv=none; d=google.com; s=arc-20160816; b=DJlGIyJYusG0/t5RMKhYxO7kd3AJdFu80+/26ByT/LDbhcI1emx1vBfTG2sc0iOA04 SEwnNMyV2hMe897alaP0Bz15whknGemuSJyqOFJD74PslYJcd8r4aGgZ3SSLtGEDrIFo qkXMHccVtSujyeuFKyE3tfHXjlxDJtcaJiwdIiLJREN7mnSpgq9dZJ+ldLIdOwu7dQTj Ta0s14NKobMu3SYzGaznwIHu20gWQkt/L3E14xzN3jNjIv27ErQuSajDUsfZe1LxSI3L gVrCvsXrEe4LDJSC7BG7Z2Q1ozchO0gRSHP1X4HsPE3Br8V73Ko/CI6e0rfAcJE5ZSXS O3nQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qxQxsH3Nx8XV7gIhtppy/YXx/6TNRZKK5/Th8LAFzrk=; b=b9llh6EQObvwRsB+sYuqzh79sBJUnSQzCvmifgZW4wGVuCyUzcXtrVS+92EsyvqQNI LANSIcDKntWILOOufTWlPerS3ftzosLysew8Ffyn5EEn3s9ssSXbynbNZEK0ZrNfpUxU oRGTYfSCe6N6v7FjzKNu+pOl3kgBtH5RJsQ0pafwAVYl9rbnvUKBHjZcairL0S7j5AzE VWKbeIJL5IZXaVAs/QmdvVqfUO+jZ9sw6oHd7Uy7oDP1rhW1HLtcxeoAypZ1wtse5G1M /1SwuzGZHZi3w2sa8Egu7kuYRaNahi86G2xsaUOvYKUVvC4YdIIxdx0tgYu9sSupZype ffqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Or+uJnxK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm6109675wrq.16.2020.02.11.09.37.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2020 09:37:36 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/13] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field Date: Tue, 11 Feb 2020 17:37:19 +0000 Message-Id: <20200211173726.22541-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211173726.22541-1-peter.maydell@linaro.org> References: <20200211173726.22541-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We already define FIELD macros for ID_DFR0, so use them in the one place where we're doing direct bit value manipulation. Signed-off-by: Peter Maydell --- We have lots of this non-FIELD style in the code, of course; I change this one purely because it otherwise looks a bit odd sat next to the ID_AA64DFR0 line that was changed in the previous patch... --- target/arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu.c b/target/arm/cpu.c index dc582da8fa4..e7858b073b5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1603,7 +1603,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) #endif } else { cpu->id_aa64dfr0 = FIELD_DP32(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); - cpu->id_dfr0 &= ~(0xf << 24); + cpu->id_dfr0 = FIELD_DP32(cpu->id_dfr0, ID_DFR0, PERFMON, 0); cpu->pmceid0 = 0; cpu->pmceid1 = 0; } From patchwork Tue Feb 11 17:37:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 183293 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp5582993ile; Tue, 11 Feb 2020 09:42:57 -0800 (PST) X-Google-Smtp-Source: APXvYqw3hPG6hJoiFyafktkPmHF+qk6fjdUIzfh5C5+srNIVrbckis5yHVD7xEEwa3nNWPGoQAiS X-Received: by 2002:ac8:36dd:: with SMTP id b29mr3439365qtc.285.1581442977479; Tue, 11 Feb 2020 09:42:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581442977; cv=none; d=google.com; s=arc-20160816; b=xID0fBmiQIeut/Ex6A2JCsNKomVgJ/Vv6FA8dO/7acSt6DQP2+lliAj3KfB8u7toTb oWYi0+AI6yz05BqZrrznmoNbD5IboA6b5HwBUN/GK9SPUQe/WNequlOoJR9040V5AsAd w8bMaNdTuHx9lsdiUIHB38krE/g78uXGqrAc7x63eTBXYDKTP/TjF+tWo3bgOPcpHmxT ThILrpXGD80Iqna/JTP4boQ0PlN0LC9mXMBQPw3Tv6vzHcQ6iwuXBpLZ3bOEMHAly2ub vYR1qg3C5YsdMTRjv2PK5x6bDb/Ed+Wra1mRJXmswjT32l1Ndc/AYPQtVEk4bGhAmyUA uZjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=s9e+ltOlG4dXdl+NQ5FqVOuFr/RSUn1sJqHbtQBlPsQ=; b=gIKWUCI4abAgxNAc2RUmNr0IbT2cfpize+2UB32pSYjJFhyPmo1XGx9UkEYnaGcu4J 7csl+khxl9wWw3gag+TNolshkoXZ04xgErdMi/cRHUsWJN/xZDreJ0QARLHCkf5x6t2e PMQ3rNiYukIojd6NR1jJkW8BkyN5MN3kmOVG9GOPAwgJXxCcYP9KmMmDO94T63T4UYd6 gVazTZCgKNCuwB7NZDpngTdE+LJ6WhVS/av2u0Et/yl7ud3HAY4BmlFtLUgsR2NPbxbS o9uHD5k6pGAXiYXY7rAG8uzD1A8dOklW0qPisWmw7OcWsMyB5gxcHq3lyRbH6UtYoIPd lAxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="PYpvg/Zn"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm6109675wrq.16.2020.02.11.09.37.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2020 09:37:38 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 07/13] target/arm: Define an aa32_pmu_8_1 isar feature test function Date: Tue, 11 Feb 2020 17:37:20 +0000 Message-Id: <20200211173726.22541-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211173726.22541-1-peter.maydell@linaro.org> References: <20200211173726.22541-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Instead of open-coding a check on the ID_DFR0 PerfMon ID register field, create a standardly-named isar_feature for "does AArch32 have a v8.1 PMUv3" and use it. This entails moving the id_dfr0 field into the ARMISARegisters struct. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 9 ++++++++- hw/intc/armv7m_nvic.c | 2 +- target/arm/cpu.c | 28 ++++++++++++++-------------- target/arm/cpu64.c | 6 +++--- target/arm/helper.c | 5 ++--- 5 files changed, 28 insertions(+), 22 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f2194b27ba3..b55f6c8b7d3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -864,6 +864,7 @@ struct ARMCPU { uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; + uint32_t id_dfr0; uint64_t id_aa64isar0; uint64_t id_aa64isar1; uint64_t id_aa64pfr0; @@ -878,7 +879,6 @@ struct ARMCPU { uint32_t reset_sctlr; uint32_t id_pfr0; uint32_t id_pfr1; - uint32_t id_dfr0; uint64_t pmceid0; uint64_t pmceid1; uint32_t id_afr0; @@ -3562,6 +3562,13 @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4; } +static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) +{ + /* 0xf means "non-standard IMPDEF PMU" */ + return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && + FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; +} + /* * 64-bit feature tests via id registers. */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index f9e0eeaace6..5a403fc9704 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1227,7 +1227,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) case 0xd44: /* PFR1. */ return cpu->id_pfr1; case 0xd48: /* DFR0. */ - return cpu->id_dfr0; + return cpu->isar.id_dfr0; case 0xd4c: /* AFR0. */ return cpu->id_afr0; case 0xd50: /* MMFR0. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e7858b073b5..ac0c96322d1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1603,7 +1603,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) #endif } else { cpu->id_aa64dfr0 = FIELD_DP32(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); - cpu->id_dfr0 = FIELD_DP32(cpu->id_dfr0, ID_DFR0, PERFMON, 0); + cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); cpu->pmceid0 = 0; cpu->pmceid1 = 0; } @@ -1841,7 +1841,7 @@ static void arm1136_r2_initfn(Object *obj) cpu->reset_sctlr = 0x00050078; cpu->id_pfr0 = 0x111; cpu->id_pfr1 = 0x1; - cpu->id_dfr0 = 0x2; + cpu->isar.id_dfr0 = 0x2; cpu->id_afr0 = 0x3; cpu->id_mmfr0 = 0x01130003; cpu->id_mmfr1 = 0x10030302; @@ -1873,7 +1873,7 @@ static void arm1136_initfn(Object *obj) cpu->reset_sctlr = 0x00050078; cpu->id_pfr0 = 0x111; cpu->id_pfr1 = 0x1; - cpu->id_dfr0 = 0x2; + cpu->isar.id_dfr0 = 0x2; cpu->id_afr0 = 0x3; cpu->id_mmfr0 = 0x01130003; cpu->id_mmfr1 = 0x10030302; @@ -1906,7 +1906,7 @@ static void arm1176_initfn(Object *obj) cpu->reset_sctlr = 0x00050078; cpu->id_pfr0 = 0x111; cpu->id_pfr1 = 0x11; - cpu->id_dfr0 = 0x33; + cpu->isar.id_dfr0 = 0x33; cpu->id_afr0 = 0; cpu->id_mmfr0 = 0x01130003; cpu->id_mmfr1 = 0x10030302; @@ -1936,7 +1936,7 @@ static void arm11mpcore_initfn(Object *obj) cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ cpu->id_pfr0 = 0x111; cpu->id_pfr1 = 0x1; - cpu->id_dfr0 = 0; + cpu->isar.id_dfr0 = 0; cpu->id_afr0 = 0x2; cpu->id_mmfr0 = 0x01100103; cpu->id_mmfr1 = 0x10020302; @@ -1968,7 +1968,7 @@ static void cortex_m3_initfn(Object *obj) cpu->pmsav7_dregion = 8; cpu->id_pfr0 = 0x00000030; cpu->id_pfr1 = 0x00000200; - cpu->id_dfr0 = 0x00100000; + cpu->isar.id_dfr0 = 0x00100000; cpu->id_afr0 = 0x00000000; cpu->id_mmfr0 = 0x00000030; cpu->id_mmfr1 = 0x00000000; @@ -1999,7 +1999,7 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.mvfr2 = 0x00000000; cpu->id_pfr0 = 0x00000030; cpu->id_pfr1 = 0x00000200; - cpu->id_dfr0 = 0x00100000; + cpu->isar.id_dfr0 = 0x00100000; cpu->id_afr0 = 0x00000000; cpu->id_mmfr0 = 0x00000030; cpu->id_mmfr1 = 0x00000000; @@ -2030,7 +2030,7 @@ static void cortex_m7_initfn(Object *obj) cpu->isar.mvfr2 = 0x00000040; cpu->id_pfr0 = 0x00000030; cpu->id_pfr1 = 0x00000200; - cpu->id_dfr0 = 0x00100000; + cpu->isar.id_dfr0 = 0x00100000; cpu->id_afr0 = 0x00000000; cpu->id_mmfr0 = 0x00100030; cpu->id_mmfr1 = 0x00000000; @@ -2063,7 +2063,7 @@ static void cortex_m33_initfn(Object *obj) cpu->isar.mvfr2 = 0x00000040; cpu->id_pfr0 = 0x00000030; cpu->id_pfr1 = 0x00000210; - cpu->id_dfr0 = 0x00200000; + cpu->isar.id_dfr0 = 0x00200000; cpu->id_afr0 = 0x00000000; cpu->id_mmfr0 = 0x00101F40; cpu->id_mmfr1 = 0x00000000; @@ -2115,7 +2115,7 @@ static void cortex_r5_initfn(Object *obj) cpu->midr = 0x411fc153; /* r1p3 */ cpu->id_pfr0 = 0x0131; cpu->id_pfr1 = 0x001; - cpu->id_dfr0 = 0x010400; + cpu->isar.id_dfr0 = 0x010400; cpu->id_afr0 = 0x0; cpu->id_mmfr0 = 0x0210030; cpu->id_mmfr1 = 0x00000000; @@ -2170,7 +2170,7 @@ static void cortex_a8_initfn(Object *obj) cpu->reset_sctlr = 0x00c50078; cpu->id_pfr0 = 0x1031; cpu->id_pfr1 = 0x11; - cpu->id_dfr0 = 0x400; + cpu->isar.id_dfr0 = 0x400; cpu->id_afr0 = 0; cpu->id_mmfr0 = 0x31100003; cpu->id_mmfr1 = 0x20000000; @@ -2243,7 +2243,7 @@ static void cortex_a9_initfn(Object *obj) cpu->reset_sctlr = 0x00c50078; cpu->id_pfr0 = 0x1031; cpu->id_pfr1 = 0x11; - cpu->id_dfr0 = 0x000; + cpu->isar.id_dfr0 = 0x000; cpu->id_afr0 = 0; cpu->id_mmfr0 = 0x00100103; cpu->id_mmfr1 = 0x20000000; @@ -2308,7 +2308,7 @@ static void cortex_a7_initfn(Object *obj) cpu->reset_sctlr = 0x00c50078; cpu->id_pfr0 = 0x00001131; cpu->id_pfr1 = 0x00011011; - cpu->id_dfr0 = 0x02010555; + cpu->isar.id_dfr0 = 0x02010555; cpu->id_afr0 = 0x00000000; cpu->id_mmfr0 = 0x10101105; cpu->id_mmfr1 = 0x40000000; @@ -2354,7 +2354,7 @@ static void cortex_a15_initfn(Object *obj) cpu->reset_sctlr = 0x00c50078; cpu->id_pfr0 = 0x00001131; cpu->id_pfr1 = 0x00011011; - cpu->id_dfr0 = 0x02010555; + cpu->isar.id_dfr0 = 0x02010555; cpu->id_afr0 = 0x00000000; cpu->id_mmfr0 = 0x10201105; cpu->id_mmfr1 = 0x20000000; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index bf2cf278c03..f8fda7e0988 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -121,7 +121,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->reset_sctlr = 0x00c50838; cpu->id_pfr0 = 0x00000131; cpu->id_pfr1 = 0x00011011; - cpu->id_dfr0 = 0x03010066; + cpu->isar.id_dfr0 = 0x03010066; cpu->id_afr0 = 0x00000000; cpu->id_mmfr0 = 0x10101105; cpu->id_mmfr1 = 0x40000000; @@ -175,7 +175,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->reset_sctlr = 0x00c50838; cpu->id_pfr0 = 0x00000131; cpu->id_pfr1 = 0x00011011; - cpu->id_dfr0 = 0x03010066; + cpu->isar.id_dfr0 = 0x03010066; cpu->id_afr0 = 0x00000000; cpu->id_mmfr0 = 0x10101105; cpu->id_mmfr1 = 0x40000000; @@ -228,7 +228,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->reset_sctlr = 0x00c50838; cpu->id_pfr0 = 0x00000131; cpu->id_pfr1 = 0x00011011; - cpu->id_dfr0 = 0x03010066; + cpu->isar.id_dfr0 = 0x03010066; cpu->id_afr0 = 0x00000000; cpu->id_mmfr0 = 0x10201105; cpu->id_mmfr1 = 0x40000000; diff --git a/target/arm/helper.c b/target/arm/helper.c index 2a57bfd9e86..ca0bf3402ca 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5886,8 +5886,7 @@ static void define_pmu_regs(ARMCPU *cpu) g_free(pmevtyper_name); g_free(pmevtyper_el0_name); } - if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 && - FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) { + if (cpu_isar_feature(aa32_pmu_8_1, cpu)) { ARMCPRegInfo v81_pmu_regs[] = { { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, @@ -6241,7 +6240,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa32_tid3, - .resetvalue = cpu->id_dfr0 }, + .resetvalue = cpu->isar.id_dfr0 }, { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, From patchwork Tue Feb 11 17:37:21 2020 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm6109675wrq.16.2020.02.11.09.37.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2020 09:37:39 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/13] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks Date: Tue, 11 Feb 2020 17:37:21 +0000 Message-Id: <20200211173726.22541-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211173726.22541-1-peter.maydell@linaro.org> References: <20200211173726.22541-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add the 64-bit version of the "is this a v8.1 PMUv3?" ID register check function, and the _any_ version that checks for either AArch32 or AArch64 support. We'll use this in a later commit. We don't (yet) do any isar_feature checks on ID_AA64DFR1_EL1, but we move id_aa64dfr1 into the ARMISARegisters struct with id_aa64dfr0, for consistency. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 15 +++++++++++++-- target/arm/cpu.c | 3 ++- target/arm/cpu64.c | 6 +++--- target/arm/helper.c | 12 +++++++----- 4 files changed, 25 insertions(+), 11 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b55f6c8b7d3..2b3124fd76b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -871,6 +871,8 @@ struct ARMCPU { uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; + uint64_t id_aa64dfr0; + uint64_t id_aa64dfr1; } isar; uint32_t midr; uint32_t revidr; @@ -887,8 +889,6 @@ struct ARMCPU { uint32_t id_mmfr2; uint32_t id_mmfr3; uint32_t id_mmfr4; - uint64_t id_aa64dfr0; - uint64_t id_aa64dfr1; uint64_t id_aa64afr0; uint64_t id_aa64afr1; uint32_t dbgdidr; @@ -3728,6 +3728,12 @@ static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; } +static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && + FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ @@ -3741,6 +3747,11 @@ static inline bool isar_feature_any_predinv(const ARMISARegisters *id) return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); } +static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) +{ + return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ac0c96322d1..df44df1a43a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1602,7 +1602,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu); #endif } else { - cpu->id_aa64dfr0 = FIELD_DP32(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); + cpu->isar.id_aa64dfr0 = + FIELD_DP32(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); cpu->pmceid0 = 0; cpu->pmceid1 = 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f8fda7e0988..4b4b134ef84 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -135,7 +135,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar5 = 0x00011121; cpu->isar.id_isar6 = 0; cpu->isar.id_aa64pfr0 = 0x00002222; - cpu->id_aa64dfr0 = 0x10305106; + cpu->isar.id_aa64dfr0 = 0x10305106; cpu->isar.id_aa64isar0 = 0x00011120; cpu->isar.id_aa64mmfr0 = 0x00001124; cpu->dbgdidr = 0x3516d000; @@ -189,7 +189,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_isar5 = 0x00011121; cpu->isar.id_isar6 = 0; cpu->isar.id_aa64pfr0 = 0x00002222; - cpu->id_aa64dfr0 = 0x10305106; + cpu->isar.id_aa64dfr0 = 0x10305106; cpu->isar.id_aa64isar0 = 0x00011120; cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ cpu->dbgdidr = 0x3516d000; @@ -241,7 +241,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar4 = 0x00011142; cpu->isar.id_isar5 = 0x00011121; cpu->isar.id_aa64pfr0 = 0x00002222; - cpu->id_aa64dfr0 = 0x10305106; + cpu->isar.id_aa64dfr0 = 0x10305106; cpu->isar.id_aa64isar0 = 0x00011120; cpu->isar.id_aa64mmfr0 = 0x00001124; cpu->dbgdidr = 0x3516d000; diff --git a/target/arm/helper.c b/target/arm/helper.c index ca0bf3402ca..9537785104e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -25,6 +25,7 @@ #include "hw/semihosting/semihost.h" #include "sysemu/cpus.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "qemu/range.h" #include "qapi/qapi-commands-machine-target.h" #include "qapi/error.h" @@ -5771,9 +5772,10 @@ static void define_debug_regs(ARMCPU *cpu) * check that if they both exist then they agree. */ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - assert(FIELD_EX32(cpu->id_aa64dfr0, ID_AA64DFR0, BRPS) == brps); - assert(FIELD_EX32(cpu->id_aa64dfr0, ID_AA64DFR0, WRPS) == wrps); - assert(FIELD_EX32(cpu->id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) == ctx_cmps); + assert(FIELD_EX32(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) == brps); + assert(FIELD_EX32(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) == wrps); + assert(FIELD_EX32(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + == ctx_cmps); } define_one_arm_cp_reg(cpu, &dbgdidr); @@ -6395,12 +6397,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = cpu->id_aa64dfr0 }, + .resetvalue = cpu->isar.id_aa64dfr0 }, { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = cpu->id_aa64dfr1 }, + .resetvalue = cpu->isar.id_aa64dfr1 }, { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, From patchwork Tue Feb 11 17:37:22 2020 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id k23si2227199qtf.397.2020.02.11.09.40.47 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 11 Feb 2020 09:40:47 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HH1sWJ4s; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54344 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j1ZWg-0002di-U7 for patch@linaro.org; Tue, 11 Feb 2020 12:40:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48627) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j1ZTl-0005mr-2v for qemu-devel@nongnu.org; Tue, 11 Feb 2020 12:37:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j1ZTi-00049L-11 for qemu-devel@nongnu.org; Tue, 11 Feb 2020 12:37:44 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:35038) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j1ZTh-00045q-Oi for qemu-devel@nongnu.org; Tue, 11 Feb 2020 12:37:41 -0500 Received: by mail-wr1-x442.google.com with SMTP id w12so13503215wrt.2 for ; Tue, 11 Feb 2020 09:37:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YAolMHbVRc4z4JgtOBFldRu9cUtp/1u8OxuIdSNhw1w=; b=HH1sWJ4sQ+0T8BkfjmGLV4oOGm+e01IArqCqdQcoh9FCju7AAyVpVXJdoxsXxVZNcJ NUjpADGCP9igs4hUmzM+5W387e//3UA8NKpFuJNYKM/IixnyEoUrGxjI23/1ImToOFY+ BmZRl+cCugFMS7osvgoGohXXV+2Asf+OoryznAwSeUvtHSlwP1iV5XAdd1RAokIvF52A 0LXN0Wx8lVO0p98TYhxEfIbDjVvSHags2Tmac7BJYYUFUHXeWE3rcxRXfQ5XIWbFNfRb RdhNFo6Bzxp07MucbBylAc/37YTUon+XTxyRpJ2a44rFnhd1Zi1j6XBCEGpnIwemrxAT /j7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YAolMHbVRc4z4JgtOBFldRu9cUtp/1u8OxuIdSNhw1w=; b=UJd6lrgxIbOj6/os9KYOMjBFmqgFV4C+CLAMeMRdfV0HyZeM7nUzLtMyKQMKKb1B+I 2Sr3bREdDRvykiyDL+NeGpUbzqpDdvFybM+oLPdOtNzHOIMVAJzHymtOE1ipBgJ6bWhs IpUTkLL5fiMZg0IDmNekCSEfqVCN0Hrk1VUJOTgw0TtjO2sfS0G3Plnl7wHhQatQT5S5 htwsXqFGM6YQ+ScUOhTmdDAvvWmHJ9T9eV3wmQHl4nHOmSiZ73ACYNWT3eNcfV0UGCLy uYn+qedownD5cKu7knW++bN5PW5ajyZII/Ag7rPW3B4PgeyFEptoksBcTh4lthWVcCgq yFtg== X-Gm-Message-State: APjAAAUj1zhdLPP8hUQUjCy8hAICyFCRjq/kwgLANOYvJ4S5kxnYlGLG Cp24VHFjF336PxTjPVlsabImzw== X-Received: by 2002:adf:d0c1:: with SMTP id z1mr10209600wrh.371.1581442660645; Tue, 11 Feb 2020 09:37:40 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm6109675wrq.16.2020.02.11.09.37.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2020 09:37:40 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/13] target/arm: Implement ARMv8.1-PMU extension Date: Tue, 11 Feb 2020 17:37:22 +0000 Message-Id: <20200211173726.22541-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211173726.22541-1-peter.maydell@linaro.org> References: <20200211173726.22541-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The ARMv8.1-PMU extension requires: * the evtCount field in PMETYPER_EL0 is 16 bits, not 10 * MDCR_EL2.HPMD allows event counting to be disabled at EL2 * two new required events, STALL_FRONTEND and STALL_BACKEND * ID register bits in ID_AA64DFR0_EL1 and ID_DFR0 We already implement the 16-bit evtCount field and the HPMD bit, so all that is missing is the two new events: STALL_FRONTEND "counts every cycle counted by the CPU_CYCLES event on which no operation was issued because there are no operations available to issue to this PE from the frontend" STALL_BACKEND "counts every cycle counted by the CPU_CYCLES event on which no operation was issued because the backend is unable to accept any available operations from the frontend" QEMU never stalls in this sense, so our implementation is trivial: always return a zero count. Signed-off-by: Peter Maydell --- target/arm/helper.c | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 9537785104e..c896ad0b7ee 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1124,6 +1124,24 @@ static int64_t instructions_ns_per(uint64_t icount) } #endif +static bool pmu_8_1_events_supported(CPUARMState *env) +{ + /* For events which are supported in any v8.1 PMU */ + return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); +} + +static uint64_t zero_event_get_count(CPUARMState *env) +{ + /* For events which on QEMU never fire, so their count is always zero */ + return 0; +} + +static int64_t zero_event_ns_per(uint64_t cycles) +{ + /* An event which never fires can never overflow */ + return -1; +} + static const pm_event pm_events[] = { { .number = 0x000, /* SW_INCR */ .supported = event_always_supported, @@ -1140,8 +1158,18 @@ static const pm_event pm_events[] = { .supported = event_always_supported, .get_count = cycles_get_count, .ns_per_count = cycles_ns_per, - } + }, #endif + { .number = 0x023, /* STALL_FRONTEND */ + .supported = pmu_8_1_events_supported, + .get_count = zero_event_get_count, + .ns_per_count = zero_event_ns_per, + }, + { .number = 0x024, /* STALL_BACKEND */ + .supported = pmu_8_1_events_supported, + .get_count = zero_event_get_count, + .ns_per_count = zero_event_ns_per, + }, }; /* @@ -1150,7 +1178,7 @@ static const pm_event pm_events[] = { * should first be updated to something sparse instead of the current * supported_event_map[] array. */ -#define MAX_EVENT_ID 0x11 +#define MAX_EVENT_ID 0x24 #define UNSUPPORTED_EVENT UINT16_MAX static uint16_t supported_event_map[MAX_EVENT_ID + 1]; From patchwork Tue Feb 11 17:37:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 183294 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp5583045ile; Tue, 11 Feb 2020 09:43:00 -0800 (PST) X-Google-Smtp-Source: APXvYqxT3fCxlSapDHVS4iEytDI3QE2z7t4kjGPGJxJIvZkiFQxaxNmcgUkn6XFQKonErvfab/RV X-Received: by 2002:a0c:fac1:: with SMTP id p1mr3916676qvo.231.1581442980309; Tue, 11 Feb 2020 09:43:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581442980; cv=none; d=google.com; s=arc-20160816; b=ca/mXroXrKvWa3uDKzPB9hbpmfvKq0Ru12mibpWToTm59wS0U3UFOd+L7AKMSzM3hy j2ydcxrajkLc2mJ4KUrh1l0d/UsA8di65o9FAzmSQNdyw+AdkUtY2dfao4SuEYmCsIU2 frspFeCkcRrYRwq4wOVUPWC9tj8du2xiAABxomntS6ZNFsxVp+u9dDDrDDGwKKpBzrqw tQ3F2PRhFaNHQtPJZqvFmJ6Ih7lWxzLfGU1kYlWudQahFLfVB7ZULBNRYI4ilPXEvuOX jpAeiXeDlLJ4EGTZv6B/9D2RkhtnwaEWauSaCjsjFlhoaLDsorx8c9HcocC2wKIBhJ/i omQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Jy3CpiCNUfrp1JLIEXg9qAR4jJdj8q8ZZ8kelkkxy8w=; b=bbG3vuGOItpkYG5Q+iE3gkfpKygDdlab27QukQeePop/j4hG6L4FRRo2yF1tpwi36M IWBuu+C0DdcNBXE3WS0QRDlvG/3RrfK8MOUn5EwTqQg4f04hukwxk7yGoRR+MJuCEe1P yqfxea7Fv7qBxmEPtBZADa8qBCEIkp2emVl1XEKSIZ4BSN/O1mY9CPPvOl8AR+4i2sQK aUmmk7Y8IrciU7mvsMrv2tmkNDcnpvPBN95XQH6Me0dpz5iiy+qNqeQMKUOQlMnS8IbS swBdK1i1/xIQE/r3SJFNdjxGcRgEfx1iaeYyAaNOO8F2hm0ehf0i566QX5Xu9dOHM7Q+ 4dQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SpKaS64m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm6109675wrq.16.2020.02.11.09.37.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2020 09:37:41 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/13] target/arm: Implement ARMv8.4-PMU extension Date: Tue, 11 Feb 2020 17:37:23 +0000 Message-Id: <20200211173726.22541-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211173726.22541-1-peter.maydell@linaro.org> References: <20200211173726.22541-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The ARMv8.4-PMU extension adds: * one new required event, STALL * one new system register PMMIR_EL1 (There are also some more L1-cache related events, but since we don't implement any cache we don't provide these, in the same way we don't provide the base-PMUv3 cache events.) The STALL event "counts every attributable cycle on which no attributable instruction or operation was sent for execution on this PE". QEMU doesn't stall in this sense, so this is another always-reads-zero event. The PMMIR_EL1 register is a read-only register providing implementation-specific information about the PMU; currently it has only one field, SLOTS, which defines behaviour of the STALL_SLOT PMU event. Since QEMU doesn't implement the STALL_SLOT event, we can validly make the register read zero. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 18 ++++++++++++++++++ target/arm/helper.c | 22 +++++++++++++++++++++- 2 files changed, 39 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2b3124fd76b..cfe7cfd1a4d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3569,6 +3569,13 @@ static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; } +static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) +{ + /* 0xf means "non-standard IMPDEF PMU" */ + return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && + FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; +} + /* * 64-bit feature tests via id registers. */ @@ -3734,6 +3741,12 @@ static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; } +static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && + FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ @@ -3752,6 +3765,11 @@ static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); } +static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) +{ + return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index c896ad0b7ee..cb3c30f1725 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1130,6 +1130,12 @@ static bool pmu_8_1_events_supported(CPUARMState *env) return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); } +static bool pmu_8_4_events_supported(CPUARMState *env) +{ + /* For events which are supported in any v8.1 PMU */ + return cpu_isar_feature(any_pmu_8_4, env_archcpu(env)); +} + static uint64_t zero_event_get_count(CPUARMState *env) { /* For events which on QEMU never fire, so their count is always zero */ @@ -1170,6 +1176,11 @@ static const pm_event pm_events[] = { .get_count = zero_event_get_count, .ns_per_count = zero_event_ns_per, }, + { .number = 0x03c, /* STALL */ + .supported = pmu_8_4_events_supported, + .get_count = zero_event_get_count, + .ns_per_count = zero_event_ns_per, + }, }; /* @@ -1178,7 +1189,7 @@ static const pm_event pm_events[] = { * should first be updated to something sparse instead of the current * supported_event_map[] array. */ -#define MAX_EVENT_ID 0x24 +#define MAX_EVENT_ID 0x3c #define UNSUPPORTED_EVENT UINT16_MAX static uint16_t supported_event_map[MAX_EVENT_ID + 1]; @@ -5930,6 +5941,15 @@ static void define_pmu_regs(ARMCPU *cpu) }; define_arm_cp_regs(cpu, v81_pmu_regs); } + if (cpu_isar_feature(any_pmu_8_4, cpu)) { + static const ARMCPRegInfo v84_pmmir = { + .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6, + .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, + .resetvalue = 0 + }; + define_one_arm_cp_reg(cpu, &v84_pmmir); + } } /* We don't know until after realize whether there's a GICv3 From patchwork Tue Feb 11 17:37:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 183295 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp5583675ile; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm6109675wrq.16.2020.02.11.09.37.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2020 09:37:42 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/13] target/arm: Provide ARMv8.4-PMU in '-cpu max' Date: Tue, 11 Feb 2020 17:37:24 +0000 Message-Id: <20200211173726.22541-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211173726.22541-1-peter.maydell@linaro.org> References: <20200211173726.22541-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Set the ID register bits to provide ARMv8.4-PMU (and implicitly also ARMv8.1-PMU) in the 'max' CPU. Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4b4b134ef84..5b8b7a9d4b8 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -693,6 +693,14 @@ static void aarch64_max_initfn(Object *obj) u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 = u; + u = cpu->isar.id_aa64dfr0; + u = FIELD_DP32(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ + cpu->isar.id_aa64dfr0 = u; + + u = cpu->isar.id_dfr0; + u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 = u; + /* * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet, * so do not set MVFR1.FPHP. Strictly speaking this is not legal, From patchwork Tue Feb 11 17:37:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 183297 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp5587162ile; Tue, 11 Feb 2020 09:47:37 -0800 (PST) X-Google-Smtp-Source: APXvYqwT1YzOPaffX1RMMhcX6CDQT291xdq2Az0vgA29L47M8cPiqHJyrCUZ7ISXFsomVf/vfurN X-Received: by 2002:ac8:584:: with SMTP id a4mr3546093qth.240.1581443257781; Tue, 11 Feb 2020 09:47:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581443257; cv=none; d=google.com; s=arc-20160816; b=NqBsEkQuBlWGMEPcMB9goGcoSNuNJNHz83JknqJqCnPoUki40PEHhmLlR/LTQKelLN p2H4ylyyXK7PuZZpSvnCvsGEh25RZB6+DHrCcvKLTCRyDJUZypW8L+Iwl5Jc0qFmQ63F NWdisjpf5wLlSNfXcmjJnniMdLVyzmlMNMJqxk6arGTzdfvP8wtqDbNOVDzCUepWelyw mjlTP74xHQ92uZRIe9HIQyX/59A9NnMG+3qNOpQfvFIXg+3sY8rznxHz4Tg3rk8lt+zX jC0NfMIT/4OEUH9Ui5ixt8+cNZwoxWRWwMuwWhg79rOH2qT4DUSJM9G1hwJ6wOGlKwfk XKAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QC2sj7hRnULzZHQ/M270NTSzgdnZq80bFajxC6Weuc8=; b=0joyte7YsXr42f5GrkkAp6QTXcdGXqsxcqq0jaexUmmtywWrzK/Q4QRSQBS1uXb2FJ 8ITUWqlRb5lEMkUmSjFX2Nf4X2eR/0+iHnuOiI1QKpAfDSXVoqI9UlQxhpxM9MFL06jp eMqTTFTeO5PHnJAOlqZRCyBDjZVknPpX3C67C6Z3ovTA0tfbiuI6lODBxrfC0IXUMjMg O9Ght1Ue5+2nTDOrbeDxYtD+2NNE3U0Bt3BJPoEIN1ulycrCa5P4Dr0mN3+rlvvysXUz 4WjLG3qtmAAx1V5yZD0kRd7Yu2UBxq7i5JmK84cm2rcGlF3yYgPhu9mLKmEnbEBsa6pq LAiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=o+leqigJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q2si2318250qvv.198.2020.02.11.09.47.37 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 11 Feb 2020 09:47:37 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=o+leqigJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54558 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j1ZdJ-0004Id-BJ for patch@linaro.org; Tue, 11 Feb 2020 12:47:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49254) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j1ZTw-0006CP-5g for qemu-devel@nongnu.org; Tue, 11 Feb 2020 12:37:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j1ZTv-0004cH-8S for qemu-devel@nongnu.org; Tue, 11 Feb 2020 12:37:56 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:37311) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j1ZTv-0004FX-2G for qemu-devel@nongnu.org; Tue, 11 Feb 2020 12:37:55 -0500 Received: by mail-wr1-x444.google.com with SMTP id w15so13493860wru.4 for ; Tue, 11 Feb 2020 09:37:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QC2sj7hRnULzZHQ/M270NTSzgdnZq80bFajxC6Weuc8=; b=o+leqigJNWcFqwtsJhWALp7Y5vmlcJFbosiZSHof164p8ZMOLigeyVPjCKtYGEtQzM a5OqoFFz4+HmGrmMZCsCINSWcob29qU/P6x/yJEg/vQztpBBmjPPaAQOe4fmDtqN0TL2 0TI7h0nTrFVkKCtlv4zSBhGjI4VlY9ZD7yOg1DV6Yq/Y+NlON53bmKFeQtW67krmq/3h rKJAMm/5reOI7gpLqCVwKj5S+2q2gjI6rFG+MBYIhYLa0lvjmiAagTXbpVwpd88v6qcj shHvU+Pqa+pGQcWD2+aqKZkq1s1g/EOldp6ykIrsz17Tbr+9HGlk59S7oHs/jWfu6CQa Y9oA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QC2sj7hRnULzZHQ/M270NTSzgdnZq80bFajxC6Weuc8=; b=V7Qy0R0TOY+w1SobzbGBEDSQNOApr5vZAXSeMFm06kLFrr9TytGzglDgqOk3ZKH3DR Pr3FunCDkWXyPHps0DWg5LYGzTwlZ16+JR65rFHFpff9DpVqxZQI5TCR0Q2HC5I4Ql64 SfaVG62ICqURapHtFBCe3VT1YEkWkgmaM47F+Uh79nCt9fnXTGc67JealB7jcVYOil8j NRRV6185QeS90nwPaVnBMrwmYuG4rcIozelQrtUHA/Ahta7gVlg1r8FMVY/Vj42n+wPG lmFeickZv+2Q5ibzeTDZtrFFFhokz+Y+CLQUpndBYP4d3A3U21ZxlotlQrK+wtl1+cCQ atOQ== X-Gm-Message-State: APjAAAVRvdVQHfbLNysgBWikjZq4u6tEGJa9Sg0e/eHdBf/CjovWchgH gJAIcryP/B7SYyW2z+wcyG73VQ== X-Received: by 2002:adf:f302:: with SMTP id i2mr9605140wro.21.1581442664016; Tue, 11 Feb 2020 09:37:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm6109675wrq.16.2020.02.11.09.37.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2020 09:37:43 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 12/13] target/arm: Correct definition of PMCRDP Date: Tue, 11 Feb 2020 17:37:25 +0000 Message-Id: <20200211173726.22541-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211173726.22541-1-peter.maydell@linaro.org> References: <20200211173726.22541-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The PMCR_EL0.DP bit is bit 5, which is 0x20, not 0x10. 0x10 is 'X'. Correct our #define of PMCRDP and add the missing PMCRX. We do have the correct behaviour for handling the DP bit being set, so this fixes a guest-visible bug. Signed-off-by: Peter Maydell --- target/arm/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/helper.c b/target/arm/helper.c index cb3c30f1725..c6758bfbeb5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1017,7 +1017,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { #define PMCRN_MASK 0xf800 #define PMCRN_SHIFT 11 #define PMCRLC 0x40 -#define PMCRDP 0x10 +#define PMCRDP 0x20 +#define PMCRX 0x10 #define PMCRD 0x8 #define PMCRC 0x4 #define PMCRP 0x2 From patchwork Tue Feb 11 17:37:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 183296 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp5586657ile; Tue, 11 Feb 2020 09:47:03 -0800 (PST) X-Google-Smtp-Source: APXvYqyUfRZvlA6U0QypBr1qeZy0mH6mQ7KBelD3hykua6vGarsEJZ7h6mGnzWSt8yifXYqt3ozD X-Received: by 2002:aed:2a05:: with SMTP id c5mr3481487qtd.361.1581443222308; Tue, 11 Feb 2020 09:47:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581443222; cv=none; d=google.com; s=arc-20160816; b=LBrFDcdO7yjEc8hSdYg5uwKGAfQkbjU/6HfVWVHyhylOWrNI99uMSQ4di6fOGI5s8E 09+zivWt2B1DuvFlxPWCbBClSPPc9ht2Pgv9MhP29Y9yj1m0brOW+H+J1hZZvnD+2ycZ AMkhZwh+ZChksdluXVj5/UCwuJ/CMc9IoaiKlrRjgkcT5d56yQqVkXOmQEv+zJEusIfp HLOEdsPSNXRc9B+g5OcHIwjf/f3/W+HfQ80rr+c6iMv88wQUqNfQbobm6aBkfV5IJN7J Pgx+TG7WUCCx0pNhcXO48F4DxiTZ2cEsxBf8hMQYNejLDsHtJUnqaajL357OoupkYXdT EqsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=e9WDJDdjLb6cBOzgUb2FHyNTKjKf7aBhEJaTRctl1CQ=; b=akC49WF3pI586YVqcuetwOutwqLpkV7B9WOzK71t+qdurN99Ie5fi3Vw7Ekr/OrgVB gu5Mp2HtnYSbvbPU/KP6ALR2ouNqCNHXV2FI1UJS+armwMID/TEWuXR7D7ihk9NV6Pjt MSjBoTT3r7BjMSxriTJujhsEU1PZdbNJyMQuYflnG+IUyVxvi3WKnhxK8iWQKfZcWxq1 QiGJPw8J9yF2fnKXEg1O8xYua8RQ5r+Z/TZSkRbST64cJprG3++SIVRFyWEZap+2wkep asDSS5GUA+7R3oUPYtos+4+i778ZF8lKmj18qNQWlRb0R4/ZgvNPVW/3GSrKayp3mOMB P+yg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JdxnJb19; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y1sm6109675wrq.16.2020.02.11.09.37.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2020 09:37:44 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 13/13] target/arm: Correct handling of PMCR_EL0.LC bit Date: Tue, 11 Feb 2020 17:37:26 +0000 Message-Id: <20200211173726.22541-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211173726.22541-1-peter.maydell@linaro.org> References: <20200211173726.22541-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The LC bit in the PMCR_EL0 register is supposed to be: * read/write * RES1 on an AArch64-only implementation * an architecturally UNKNOWN value on reset (and use of LC==0 by software is deprecated). We were implementing it incorrectly as read-only always zero, though we do have all the code needed to test it and behave accordingly. Instead make it a read-write bit which resets to 1 always, which satisfies all the architectural requirements above. Signed-off-by: Peter Maydell --- target/arm/helper.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/helper.c b/target/arm/helper.c index c6758bfbeb5..1d8eafceda8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1023,6 +1023,11 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { #define PMCRC 0x4 #define PMCRP 0x2 #define PMCRE 0x1 +/* + * Mask of PMCR bits writeable by guest (not including WO bits like C, P, + * which can be written as 1 to trigger behaviour but which stay RAZ). + */ +#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) #define PMXEVTYPER_P 0x80000000 #define PMXEVTYPER_U 0x40000000 @@ -1577,9 +1582,8 @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, } } - /* only the DP, X, D and E bits are writable */ - env->cp15.c9_pmcr &= ~0x39; - env->cp15.c9_pmcr |= (value & 0x39); + env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK; + env->cp15.c9_pmcr |= (value & PMCR_WRITEABLE_MASK); pmu_op_finish(env); } @@ -5886,7 +5890,8 @@ static void define_pmu_regs(ARMCPU *cpu) .access = PL0_RW, .accessfn = pmreg_access, .type = ARM_CP_IO, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT), + .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) | + PMCRLC, .writefn = pmcr_write, .raw_writefn = raw_write, }; define_one_arm_cp_reg(cpu, &pmcr);