From patchwork Sun Feb 16 19:43:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183561 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp4180027ile; Sun, 16 Feb 2020 11:46:29 -0800 (PST) X-Google-Smtp-Source: APXvYqyekZ3QyRuIBjgzDuW7EL8BgG2zxXuZssftPUG//4Soa50HyjxMYSu1UPmGw26Uh2YnZQ6P X-Received: by 2002:ac8:60d5:: with SMTP id i21mr10779088qtm.341.1581882389305; Sun, 16 Feb 2020 11:46:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581882389; cv=none; d=google.com; s=arc-20160816; b=L+LbS5irjB+gfcPtcsKaY3BwhC12aFPMRijLlOklDkGdwzeYjZEFzPIEXmloJ8E/1g pBvbKsajEhPgGJ5EU41TvANqF89cIY91HD/xRam/vOSJpBfqs6L660/oMgHrgCGDIIJw +yKyA4o755qALBJe8t8wz6k+odCNiZHG+miHO30WyMpkNYS39MRSVgXDnZRhAxbDP1Sr L6ezMdicKlNmTF0eRtcy3ML8n8Mk2axMtYTc890qxAHRTZgRl4ET4LmzWvkXtQPkwqxr DfdaXhofluXq+Dw1xPkbAkR4meMOVmJsnOO1rFAD9FBpzTf7g1VjSZsupyEdqGaeXME8 8EbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=o5rb+tTqydiafB3qvUsAq8/vvIee2NCXymu3BNnsCeA=; b=oEA41+HhyhsieMTC/CX/d4Tx73+C5yOszKHKEHoKCb+L3R42a83F5g+AYRdCDGSfOV ix/n1uL48UwYYrwB7edclHifZmRG2F5Qlnx/3TfRVrkGBx/DCDKb8GSxtA0HCObEErX1 LNfoW2WktO/R6cqGrty61oxajyoDTkCU8MGKIw6PG/u0+brQbUj5YyQzWOMnNGwwGxMK dzAxzf4d3YpgobOg6tt7RPWK7jzgTePvTwN1k4oJ7WIjwqO0fVBnSgF1KdUYvJff1oFz 4EbgFJXVrXgNMNXAkbHJMIC1hqtDGYo05xbwJ36HHM0pDnDnDTB9wbVVFf69tXcjj4jx vPPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cxe7iddO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id y127sm13945188pfg.22.2020.02.16.11.43.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Feb 2020 11:43:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 1/4] target/arm: Use bit 55 explicitly for pauth Date: Sun, 16 Feb 2020 11:43:40 -0800 Message-Id: <20200216194343.21331-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200216194343.21331-1-richard.henderson@linaro.org> References: <20200216194343.21331-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The psuedocode in aarch64/functions/pac/auth/Auth and aarch64/functions/pac/strip/Strip always uses bit 55 for extfield and do not consider if the current regime has 2 ranges. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/pauth_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index 9746e32bf8..b909630317 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -320,7 +320,8 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) { - uint64_t extfield = -param.select; + /* Note that bit 55 is used whether or not the regime has 2 ranges. */ + uint64_t extfield = sextract64(ptr, 55, 1); int bot_pac_bit = 64 - param.tsz; int top_pac_bit = 64 - 8 * param.tbi; From patchwork Sun Feb 16 19:43:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183564 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp4181450ile; Sun, 16 Feb 2020 11:49:19 -0800 (PST) X-Google-Smtp-Source: APXvYqyOsrqD6IuKxUhyo8jnQAljFoZ6ruHzBMeapjYitzyD7IOIWMy2Os3KaS5ivROgvcYhoK0I X-Received: by 2002:ae9:e841:: with SMTP id a62mr8828538qkg.384.1581882559121; Sun, 16 Feb 2020 11:49:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581882559; cv=none; d=google.com; s=arc-20160816; b=LUite6IKq6+ZM3lwAOYdfsVHzf2jOlydF8qBk+RM64m8J7qSzkgyiv0MkqHCKMCL/4 P5ZepeeJ5yNpyKXW087XmlXtCL78bTqHSpioK3Z3yPEfSddQTLtZHFce+Hnh/1SpZLAF bQnpGd91hke+QIaUUiVBthI32lYaDA77qLxVBU/s9WZzRm733Qun/rKHXkd7EsKf+vDF T5sLila2lmSR3bDLDEqFcaLsJ6hDqRXmEgVx7riHbRwuL6NzTHWRsBNENMn5kyoQu+Di Df846ZrA4p4DlBvR2Wanmm1hZDltyBtp1Eo7T4b2VDIp73NC+qr7aFISjbfo7RAIIbuA 3mIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Qe8zug4Z0mtaHwBh2av/LIOpMaLY4DsO8Azuq2pRmxw=; b=Hi0FUSltqBMUJ40RGDBTkrQt5pCaRWa+WBu+bBJEuF2aK8vtIIuXf6AdNIsXCiUcVI Le9BTuxY35hgffC3ah5oK8PyPx2s6lejASwGnoZLo6XRhOJUUmmkO9z/DXz+2g4Y7TzC 7/rIBY/CGpWNQxjkWYg7yFH/a6w22jN/c07L0dXPv2VMMPMVdiMnHVZmio6yys11zr7L bClGZAhb8pUPKJKyZPfybfYop26Y98s/1kwkA6IwQpPlfRiGO6sYgAQqOUdVGuMWSaWC uxFhOkuNAmKNMKSX9HsfIFFNQbKmn4pNXGdm5DZ/QhbqMV0aYY2rFcwY7gAxgYn9JpT6 IDfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qcYh2Upb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id y127sm13945188pfg.22.2020.02.16.11.43.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Feb 2020 11:43:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 2/4] target/arm: Fix select for aa64_va_parameters_both Date: Sun, 16 Feb 2020 11:43:41 -0800 Message-Id: <20200216194343.21331-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200216194343.21331-1-richard.henderson@linaro.org> References: <20200216194343.21331-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Select should always be 0 for a regime with one range. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 46 +++++++++++++++++++++++---------------------- 1 file changed, 24 insertions(+), 22 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 366dbcf460..b09a501284 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10241,13 +10241,8 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, bool tbi, tbid, epd, hpd, using16k, using64k; int select, tsz; - /* - * Bit 55 is always between the two regions, and is canonical for - * determining if address tagging is enabled. - */ - select = extract64(va, 55, 1); - if (!regime_has_2_ranges(mmu_idx)) { + select = 0; tsz = extract32(tcr, 0, 6); using64k = extract32(tcr, 14, 1); using16k = extract32(tcr, 15, 1); @@ -10260,23 +10255,30 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, tbid = extract32(tcr, 29, 1); } epd = false; - } else if (!select) { - tsz = extract32(tcr, 0, 6); - epd = extract32(tcr, 7, 1); - using64k = extract32(tcr, 14, 1); - using16k = extract32(tcr, 15, 1); - tbi = extract64(tcr, 37, 1); - hpd = extract64(tcr, 41, 1); - tbid = extract64(tcr, 51, 1); } else { - int tg = extract32(tcr, 30, 2); - using16k = tg == 1; - using64k = tg == 3; - tsz = extract32(tcr, 16, 6); - epd = extract32(tcr, 23, 1); - tbi = extract64(tcr, 38, 1); - hpd = extract64(tcr, 42, 1); - tbid = extract64(tcr, 52, 1); + /* + * Bit 55 is always between the two regions, and is canonical for + * determining if address tagging is enabled. + */ + select = extract64(va, 55, 1); + if (!select) { + tsz = extract32(tcr, 0, 6); + epd = extract32(tcr, 7, 1); + using64k = extract32(tcr, 14, 1); + using16k = extract32(tcr, 15, 1); + tbi = extract64(tcr, 37, 1); + hpd = extract64(tcr, 41, 1); + tbid = extract64(tcr, 51, 1); + } else { + int tg = extract32(tcr, 30, 2); + using16k = tg == 1; + using64k = tg == 3; + tsz = extract32(tcr, 16, 6); + epd = extract32(tcr, 23, 1); + tbi = extract64(tcr, 38, 1); + hpd = extract64(tcr, 42, 1); + tbid = extract64(tcr, 52, 1); + } } tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ From patchwork Sun Feb 16 19:43:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183562 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp4180149ile; Sun, 16 Feb 2020 11:46:41 -0800 (PST) X-Google-Smtp-Source: APXvYqzGtB9PC9OgfvJnMuiCGvhOr2PB/g7qa4IuGXvV994dGEZK5BlP1insFlyZBFGCJl7utWne X-Received: by 2002:ac8:1b18:: with SMTP id y24mr10559890qtj.158.1581882401784; Sun, 16 Feb 2020 11:46:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581882401; cv=none; d=google.com; s=arc-20160816; b=QWozNPBNkgif6LjPfYJzNSLcKfbl/dcneIbuYl5IkHSDBUXTl+fj5AQE2TrBxUeENO utSMALmaTNxTpODfhjX5G1DWcit8JkA7q7+Jq7YXypoN4AoRODmwhCXc1ww2CSByOWU0 2JO5WjNganS6iNW32dk7Z+mWC1+53COxIRjNUoUAW9ii8w18t9Nr1/+RKyJC1Tigbk01 1ZpJ0dZ+wYPC/z846I3DhPr4TLMEncQgSSQJy06OStbrSsU8943oFyjkzYXSGFcuAnTp LT8hdlHkUGjmkjkCUfYv61oF9YERjyCZVvqu9WjlTSFCAXVuVWmAa27DatwAoy6dG7N9 AylA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kTU4kvjUvlD0h7Jj4NNpawxNwnsR3vNHE9107ezVFjs=; b=N7sXLyGe0FBc0OZtdn5ViHfkNaOQf/J2N07eKvW4+GEBHlKz5IKw88RfV9C7MaZDxv caNmFwiKyeNXZDRDlNXV+KAq/xJ6F9Qu0wadMB0O96XWema407jFCPFEV/5Xw8CoNxN0 0v7rWSGaXfrxBPMq7u58qF6S/hP/r4JruUzIf01HZguxM+663VJvDALwehlVXo/cDwLr n7oYEC2u9BbSWcyd7Mre4RQ5rtCfQUR68DJDHFEaPDKbt90GJVI36u8lUYO3SVy8q1Eg ShIcUJuB15twd98BERd+Ym9IGRmB/5SAmVXzv7fqgOsgIEv1U6qhKffOWEs0TBcusVzO s5rA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cmtxOL5k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id y127sm13945188pfg.22.2020.02.16.11.43.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Feb 2020 11:43:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 3/4] target/arm: Remove ttbr1_valid check from get_phys_addr_lpae Date: Sun, 16 Feb 2020 11:43:42 -0800 Message-Id: <20200216194343.21331-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200216194343.21331-1-richard.henderson@linaro.org> References: <20200216194343.21331-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1042 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that aa64_va_parameters_both sets select based on the number of ranges in the regime, the ttbr1_valid check is redundant. Signed-off-by: Richard Henderson --- target/arm/helper.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index b09a501284..eec7b01ab3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10390,7 +10390,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, TCR *tcr = regime_tcr(env, mmu_idx); int ap, ns, xn, pxn; uint32_t el = regime_el(env, mmu_idx); - bool ttbr1_valid; uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); bool guarded = false; @@ -10405,14 +10404,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, param = aa64_va_parameters(env, address, mmu_idx, access_type != MMU_INST_FETCH); level = 0; - ttbr1_valid = regime_has_2_ranges(mmu_idx); addrsize = 64 - 8 * param.tbi; inputsize = 64 - param.tsz; } else { param = aa32_va_parameters(env, address, mmu_idx); level = 1; - /* There is no TTBR1 for EL2 */ - ttbr1_valid = (el != 2); addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32); inputsize = addrsize - param.tsz; } @@ -10429,7 +10425,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, if (inputsize < addrsize) { target_ulong top_bits = sextract64(address, inputsize, addrsize - inputsize); - if (-top_bits != param.select || (param.select && !ttbr1_valid)) { + if (-top_bits != param.select) { /* The gap between the two regions is a Translation fault */ fault_type = ARMFault_Translation; goto do_fault; From patchwork Sun Feb 16 19:43:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183560 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp4178799ile; Sun, 16 Feb 2020 11:44:23 -0800 (PST) X-Google-Smtp-Source: APXvYqzMjgrUHaEqXH3qzWETu/HHg6KMr20yrcFooEGgdjC4bBjovTwe575Y+TIcQP5fqAZkXjoL X-Received: by 2002:a37:a717:: with SMTP id q23mr11765134qke.169.1581882263639; Sun, 16 Feb 2020 11:44:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581882263; cv=none; d=google.com; s=arc-20160816; b=ueuCfX8GXrNPd5ohL1fhMKKbeQpy4+4pixfd9Lj1zTzXgAJWtz1u1l9XPUuOpi4fSS 51DZ03Em/mlKoYoOhKaECTn/wOspg/MCY6VxMgiN+F6Dn2X2AQMjvVoFaL8awwkZmx6q 39XQzRYtIXRv0bZyo6cx896Owh1CREQtLZ2zns8beuY/5g7awDYF2CO4fn9yWobiWIRy 1h3wGwikr6AurEFwPVe+VqHmxN++FYCsyeT83bIgRGAI5+YJSAF485LsLCdkhdQEXHMN UN2g75060t32NNXZmlaIFzwUdyGzhPj7wW8CfRikVYb9SWiAPaPoR3Ea7/qXiOBXzRXI c6Zw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jKe60JzIR9wTTCupClDTcPlRGkah6P8mFmzkvCXt/nU=; b=LO+vOMNCapEkB8BWi0aisZkXDvLW34BHEha2o3hqP2vzq1aExwOUZ/qRboz99QPjMG M2qEz8TKU0OvA8Dfg8h8ane0pa3IdlfKsS05hepqO2XotwwTLsV6egCbHKINQCzyuUbH OETeh4IEb4dOmSeMcB76pA/83NtSZY8i/2CrjJqBfoNQp0NVgiiHk+kVB1WY8/r7Smcl ctlpI0+3hD9H5SKjtQOIpYBEkAnAjHRSKCBwEMRVRfnFo30xp37vPK3jxsTRkL4vfoDj zOBmMp9UbUIPf9TEc02HnZRY/Zxyn7R+E8zivyOAS3H1668eeUBz1cNAfoKhfx7RzrjI pFiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MFJ51olg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id y127sm13945188pfg.22.2020.02.16.11.43.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Feb 2020 11:43:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 4/4] target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid Date: Sun, 16 Feb 2020 11:43:43 -0800 Message-Id: <20200216194343.21331-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200216194343.21331-1-richard.henderson@linaro.org> References: <20200216194343.21331-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For the purpose of rebuild_hflags_a64, we do not need to compute all of the va parameters, only tbi. Moreover, we can compute them in a form that is more useful to storing in hflags. This eliminates the need for aa64_va_parameter_both, so fold that in to aa64_va_parameter. The remaining calls to aa64_va_parameter are in get_phys_addr_lpae and in pauth_helper.c. This reduces the total cpu consumption of aa64_va_parameter in a kernel boot plus a kvm guest kernel boot from 3% to 0.5%. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 -- target/arm/helper.c | 68 +++++++++++++++++++++++------------------- 2 files changed, 37 insertions(+), 34 deletions(-) -- 2.20.1 diff --git a/target/arm/internals.h b/target/arm/internals.h index 58c4d707c5..14328e3f7d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1127,15 +1127,12 @@ typedef struct ARMVAParameters { unsigned tsz : 8; unsigned select : 1; bool tbi : 1; - bool tbid : 1; bool epd : 1; bool hpd : 1; bool using16k : 1; bool using64k : 1; } ARMVAParameters; -ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx); ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); diff --git a/target/arm/helper.c b/target/arm/helper.c index eec7b01ab3..8d0f6eca27 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10234,12 +10234,34 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) } #endif /* !CONFIG_USER_ONLY */ -ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx) +static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) +{ + if (regime_has_2_ranges(mmu_idx)) { + return extract64(tcr, 37, 2); + } else if (mmu_idx == ARMMMUIdx_Stage2) { + return 0; /* VTCR_EL2 */ + } else { + return extract32(tcr, 20, 1); + } +} + +static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) +{ + if (regime_has_2_ranges(mmu_idx)) { + return extract64(tcr, 51, 2); + } else if (mmu_idx == ARMMMUIdx_Stage2) { + return 0; /* VTCR_EL2 */ + } else { + return extract32(tcr, 29, 1); + } +} + +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data) { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; - bool tbi, tbid, epd, hpd, using16k, using64k; - int select, tsz; + bool epd, hpd, using16k, using64k; + int select, tsz, tbi; if (!regime_has_2_ranges(mmu_idx)) { select = 0; @@ -10248,11 +10270,9 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, using16k = extract32(tcr, 15, 1); if (mmu_idx == ARMMMUIdx_Stage2) { /* VTCR_EL2 */ - tbi = tbid = hpd = false; + hpd = false; } else { - tbi = extract32(tcr, 20, 1); hpd = extract32(tcr, 24, 1); - tbid = extract32(tcr, 29, 1); } epd = false; } else { @@ -10266,28 +10286,30 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, epd = extract32(tcr, 7, 1); using64k = extract32(tcr, 14, 1); using16k = extract32(tcr, 15, 1); - tbi = extract64(tcr, 37, 1); hpd = extract64(tcr, 41, 1); - tbid = extract64(tcr, 51, 1); } else { int tg = extract32(tcr, 30, 2); using16k = tg == 1; using64k = tg == 3; tsz = extract32(tcr, 16, 6); epd = extract32(tcr, 23, 1); - tbi = extract64(tcr, 38, 1); hpd = extract64(tcr, 42, 1); - tbid = extract64(tcr, 52, 1); } } tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ + /* Present TBI as a composite with TBID. */ + tbi = aa64_va_parameter_tbi(tcr, mmu_idx); + if (!data) { + tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi = (tbi >> select) & 1; + return (ARMVAParameters) { .tsz = tsz, .select = select, .tbi = tbi, - .tbid = tbid, .epd = epd, .hpd = hpd, .using16k = using16k, @@ -10295,16 +10317,6 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, }; } -ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data) -{ - ARMVAParameters ret = aa64_va_parameters_both(env, va, mmu_idx); - - /* Present TBI as a composite with TBID. */ - ret.tbi &= (data || !ret.tbid); - return ret; -} - #ifndef CONFIG_USER_ONLY static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) @@ -12134,21 +12146,15 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, { uint32_t flags = rebuild_hflags_aprofile(env); ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); - ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); + uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint64_t sctlr; int tbii, tbid; flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); /* Get control bits for tagged addresses. */ - if (regime_has_2_ranges(mmu_idx)) { - ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); - tbid = (p1.tbi << 1) | p0.tbi; - tbii = tbid & ~((p1.tbid << 1) | p0.tbid); - } else { - tbid = p0.tbi; - tbii = tbid & !p0.tbid; - } + tbid = aa64_va_parameter_tbi(tcr, mmu_idx); + tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid);