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[209.51.188.17]) by mx.google.com with ESMTPS id y32si1324439qta.311.2020.02.26.07.27.37 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 26 Feb 2020 07:27:37 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UJ07rjUF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45836 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6yb2-0005VP-Pi for patch@linaro.org; Wed, 26 Feb 2020 10:27:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48446) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6yaq-0005Tv-03 for qemu-devel@nongnu.org; Wed, 26 Feb 2020 10:27:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6yao-0001Om-Hv for qemu-devel@nongnu.org; Wed, 26 Feb 2020 10:27:23 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:38194) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j6yao-0001L6-9V for qemu-devel@nongnu.org; Wed, 26 Feb 2020 10:27:22 -0500 Received: by mail-wr1-x443.google.com with SMTP id e8so3555224wrm.5 for ; Wed, 26 Feb 2020 07:27:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=dv7Dxwk2EOL91ONyIJ37RrEIbEVFccpjybkrT6dJ72Y=; b=UJ07rjUFRGvGcyMu9AQxaPZ1BnIJpc2ZfcjNIZ0pHVPxQbfD9tLLi1XbZ6lUahctkl TFlEdUmrQ9TYpqfgHYO8Z8LJitQE/+M8PrNJO3t1W8oZnPq/AQRIBHSgWoFXbUc5p18R bLIyQlrr7IHVkyTKjiuNwIyCwGJ1FM7Ve8g/0EQk9MS35KxeIJBDTRX9mlv9iq4qcDgO KYtX1hl2fwmvzbYdHb/TdEgnIlSGhbjMS0Mt0h+9Q41Rg0zUsVBT7rYIB2j11l4vMPfA fVD3aZOGM68WvCxe28xCzH776XkC2gvh4tqxPmKHAhESOw/Q4LQLv/IXvrHmjCInPUmG v7Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=dv7Dxwk2EOL91ONyIJ37RrEIbEVFccpjybkrT6dJ72Y=; b=QBdw+YQLeh6ZE64X6g6c2wh1BXPPFpDsII8oUS41NCCwrB7G2SZ0G64Kv2SQHlbFkM oE6+wVQHwBgn0fVRPTuF+qv9kvfIJL/A3CkLoHNGutNIq6Qgyql809WiREIW7eaqIEaS VWEKXpoWAw0qab+SD1jzJ4jlX+giYrqdwDRkLO718Xfxa76qLDBLQuAMyOpb+6dlJ1hk NBDoAJzgM94VzlPHmFET1qT3TpE9GDmt1uNU2dsYUSCz17rzott74zC87VKTn3s4FSAT rLlsCiLTQWr5am1XdG2fvKPbIZb2SRvx/PQ2MR2NfqGS1ukHC2b6sf0rYAuUH38VKyyo sawg== X-Gm-Message-State: APjAAAVQlM9YWxrQl9vAaoGNB+G0pIH2Uada7Kn5BocW1pYdVfrbCTdd sies7ZEnpwroFOi80N18p1VslQ== X-Received: by 2002:adf:b19e:: with SMTP id q30mr325777wra.163.1582730840869; Wed, 26 Feb 2020 07:27:20 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id j12sm3697753wrt.35.2020.02.26.07.27.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Feb 2020 07:27:19 -0800 (PST) Received: from zen.home.arpa (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id ACD9C1FF87; Wed, 26 Feb 2020 15:27:18 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH] accel/tcg: remove link between guest ram and TCG cache size Date: Wed, 26 Feb 2020 15:27:10 +0000 Message-Id: <20200226152710.31751-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, Niek Linnenbank , qemu-arm@nongnu.org, Paolo Bonzini , Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Basing the TB cache size on the ram_size was always a little heuristic and was broken by a1b18df9a4 which caused ram_size not to be fully realised at the time we initialise the TCG translation cache. At the same time the default code generation size seems mainly set to deal with the fact we use a static code buffer for CONFIG_USER to avoid mmap allocation problems on constrained systems. So we: - only use a static code buffer on 32 bit systems - up the default buffer size for bigger systems - ignore the ram_size and just go with the default - document the fact tb-size is ignored for 32 bit linux-user The could potentially slow down softmmu emulation on 32 bit systems with lots (3gb?) of spare memory. Those users can still manually up the tb-size via the command line if they do in fact exist. Fixes: a1b18df9a4 Signed-off-by: Alex Bennée Cc: Niek Linnenbank Cc: Igor Mammedov --- accel/tcg/translate-all.c | 23 ++++++++++------------- qemu-options.hx | 3 ++- 2 files changed, 12 insertions(+), 14 deletions(-) -- 2.20.1 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index a08ab11f657..cdfa2db7c56 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -891,11 +891,12 @@ static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1, } } -#if defined(CONFIG_USER_ONLY) -/* Currently it is not recommended to allocate big chunks of data in - user mode. It will change when a dedicated libc will be used. */ -/* ??? 64-bit hosts ought to have no problem mmaping data outside the - region in which the guest needs to run. Revisit this. */ +#if defined(CONFIG_USER_ONLY) && TCG_TARGET_REG_BITS == 32 +/* + * For user mode on smaller 32 bit systems we may run into trouble + * allocating big chunks of data in the right place. On these systems + * we utilise a static code generation buffer directly in the binary. + */ #define USE_STATIC_CODE_GEN_BUFFER #endif @@ -927,7 +928,11 @@ static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1, # define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) #endif +#if TCG_TARGET_REG_BITS == 32 #define DEFAULT_CODE_GEN_BUFFER_SIZE_1 (32u * 1024 * 1024) +#else +#define DEFAULT_CODE_GEN_BUFFER_SIZE_1 (2ul * 1024 * 1024 * 1024) +#endif #define DEFAULT_CODE_GEN_BUFFER_SIZE \ (DEFAULT_CODE_GEN_BUFFER_SIZE_1 < MAX_CODE_GEN_BUFFER_SIZE \ @@ -937,15 +942,7 @@ static inline size_t size_code_gen_buffer(size_t tb_size) { /* Size the buffer. */ if (tb_size == 0) { -#ifdef USE_STATIC_CODE_GEN_BUFFER tb_size = DEFAULT_CODE_GEN_BUFFER_SIZE; -#else - /* ??? Needs adjustments. */ - /* ??? If we relax the requirement that CONFIG_USER_ONLY use the - static buffer, we could size this on RESERVED_VA, on the text - segment size of the executable, or continue to use the default. */ - tb_size = (unsigned long)(ram_size / 4); -#endif } if (tb_size < MIN_CODE_GEN_BUFFER_SIZE) { tb_size = MIN_CODE_GEN_BUFFER_SIZE; diff --git a/qemu-options.hx b/qemu-options.hx index ac315c1ac45..0a4bbdb8eb9 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -139,7 +139,8 @@ irqchip completely is not recommended except for debugging purposes. @item kvm-shadow-mem=size Defines the size of the KVM shadow MMU. @item tb-size=@var{n} -Controls the size (in MiB) of the TCG translation block cache. +Controls the size (in MiB) of the TCG translation block cache. It has no effect on +32 bit linux-user binaries. @item thread=single|multi Controls number of TCG threads. When the TCG is multi-threaded there will be one thread per vCPU therefor taking advantage of additional host cores. The default