From patchwork Wed Mar 5 21:03:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shree Ramamoorthy X-Patchwork-Id: 871045 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E5152580C6; Wed, 5 Mar 2025 21:04:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741208660; cv=none; b=eZ5f/OcTzT+u+qcZF3bJh2MVwnQUq3OfC6D9PkhvIUSxPhuOZgkmj82vQxpoRaLVSEt2RuQWEqrU+qtPzxTzL2Nw2Jy9yHN88HkpXzgLGjAVA69MgZcjfFNdFXSJrH0Y9enl7Db0gLnNd/GOUK5Uo3bHexV9yJTVuNlAtm26Igs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741208660; c=relaxed/simple; bh=Pov7nJtkOZ5HfHS1cXKZ7b9hFVEZJfFxkCeGliJPvJc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=C/ZG2aBTywWT2VT4WktOLLc6w63W7DZEgo+wE9BQnXJGy9U7yNeqZNrXncGsvC9IibKPGN78fybBXYq2c56ilPFo9YGLvC9xknLmJEy+RPVx9AHvLzXimFMQpJxutbUnXFYgMu2hBOROgiU4vGXVTROZj5p8o7kKiywyv5ElMo4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=nmA3DdSu; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="nmA3DdSu" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 525L3qHa3414929 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 5 Mar 2025 15:03:52 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1741208632; bh=dD1VwGrNpd2NkN9mIIECzz6+iWCpvrOQszaRP4ix5i4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nmA3DdSuqISPeQEJFnkyXj2DfLuozmJbZsfdXcv9z/PYdvkebV/EwWNU9BR/6KQXW BqytjuY1OZNTihYWD4OyYYyjsTEfKgF+1GOd6RFxf+1aTxerwH+K8kAAfQJ06pxuaR 8kATPMXJtAWAI2XzbDkwogSjxWcg4fio85qf77Bk= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTP id 525L3q3Z114081; Wed, 5 Mar 2025 15:03:52 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 5 Mar 2025 15:03:51 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 5 Mar 2025 15:03:51 -0600 Received: from DMZ007XYY.dhcp.ti.com (dmz007xyy.dhcp.ti.com [128.247.29.251]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 525L3peB125160; Wed, 5 Mar 2025 15:03:51 -0600 From: Shree Ramamoorthy To: , , , , , , , , , , , , , CC: , Subject: [PATCH v6 1/9] regulator: dt-bindings: Add TI TPS65215 PMIC bindings Date: Wed, 5 Mar 2025 15:03:43 -0600 Message-ID: <20250305210351.249811-2-s-ramamoorthy@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250305210351.249811-1-s-ramamoorthy@ti.com> References: <20250305210351.249811-1-s-ramamoorthy@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea TPS65215 is a Power Management IC with 3 Buck regulators and 2 LDOs. TPS65215 has 2 LDOS and 1 GPO, whereas TPS65219 has 4 LDOs and 2 GPOs. The remaining features for both devices are the same. Signed-off-by: Shree Ramamoorthy Acked-by: Conor Dooley --- .../bindings/regulator/ti,tps65219.yaml | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml b/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml index 78e64521d401..b0d47415bf83 100644 --- a/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml +++ b/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/regulator/ti,tps65219.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: TI tps65219 Power Management Integrated Circuit regulators +title: TI TPS65215/TPS65219 Power Management Integrated Circuits maintainers: - Jerome Neanne @@ -12,9 +12,16 @@ maintainers: description: | Regulator nodes should be named to buck and ldo. + TI TPS65219 is a Power Management IC with 3 Buck regulators, 4 Low + Drop-out Regulators (LDOs), 1 GPIO, 2 GPOs, and power-button. + + TI TPS65215 is a derivative of TPS65219 with 3 Buck regulators, 2 Low + Drop-out Regulators (LDOs), 1 GPIO, 1 GPO, and power-button. + properties: compatible: enum: + - ti,tps65215 - ti,tps65219 reg: @@ -90,6 +97,18 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: ti,tps65215 + then: + properties: + regulators: + patternProperties: + "^ldo[3-4]$": false + examples: - | #include From patchwork Wed Mar 5 21:03:44 2025 Content-Type: text/plain; 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Wed, 5 Mar 2025 15:03:51 -0600 From: Shree Ramamoorthy To: , , , , , , , , , , , , , CC: , Subject: [PATCH v6 2/9] regulator: dt-bindings: Add TI TPS65214 PMIC bindings Date: Wed, 5 Mar 2025 15:03:44 -0600 Message-ID: <20250305210351.249811-3-s-ramamoorthy@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250305210351.249811-1-s-ramamoorthy@ti.com> References: <20250305210351.249811-1-s-ramamoorthy@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea - TPS65214 is a Power Management IC with 3 Buck regulators and 2 LDOs. - TPS65214 has 2 LDOS and 1 GPO, whereas TPS65219 has 4 LDOs and 2 GPOs. - TPS65214's LDO1 maps to TPS65219's LDO3. - A key difference between TPS65215 & TPS65214 are the LDO current and voltage output ranges and the configurable options available. - The remaining features for both devices are the same. Signed-off-by: Shree Ramamoorthy Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/regulator/ti,tps65219.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml b/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml index b0d47415bf83..7c64e588a8b5 100644 --- a/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml +++ b/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/regulator/ti,tps65219.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: TI TPS65215/TPS65219 Power Management Integrated Circuits +title: TI TPS65214/TPS65215/TPS65219 Power Management Integrated Circuit maintainers: - Jerome Neanne @@ -18,9 +18,13 @@ description: | TI TPS65215 is a derivative of TPS65219 with 3 Buck regulators, 2 Low Drop-out Regulators (LDOs), 1 GPIO, 1 GPO, and power-button. + TI TPS65214 is a derivative of TPS65219 with 3 Buck regulators, 2 Low + Drop-out Regulators (LDOs), 1 GPIO, 1 GPO, and power-button. + properties: compatible: enum: + - ti,tps65214 - ti,tps65215 - ti,tps65219 @@ -102,7 +106,9 @@ allOf: properties: compatible: contains: - const: ti,tps65215 + enum: + - ti,tps65214 + - ti,tps65215 then: properties: regulators: From patchwork Wed Mar 5 21:03:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shree Ramamoorthy X-Patchwork-Id: 871046 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2FC42571B3; Wed, 5 Mar 2025 21:04:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741208655; cv=none; b=CNnenC9jEa+o+vrqNOgwh1XRU4ZbGM67VyH6O/8RjnW/mlQ2KF+rfLZrxuq6O0/JsApC0S6DnBJ/gWib4ijAfmvCccDmJnUIVJpKfZYD6vOfKg1q9jVaQRuxWWgbHI56MSbDWK2fxX9c4cmtL3C/yP7KDWLf/lojLn28l3VygCE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741208655; c=relaxed/simple; bh=zt/mnfcWoNqNLuBEU24kRzrEBrIJBtEPoY2gFPHU8vw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Wed, 5 Mar 2025 15:03:52 -0600 Received: from DMZ007XYY.dhcp.ti.com (dmz007xyy.dhcp.ti.com [128.247.29.251]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 525L3peD125160; Wed, 5 Mar 2025 15:03:51 -0600 From: Shree Ramamoorthy To: , , , , , , , , , , , , , CC: , Subject: [PATCH v6 3/9] mfd: tps65219: Remove regmap_read check Date: Wed, 5 Mar 2025 15:03:45 -0600 Message-ID: <20250305210351.249811-4-s-ramamoorthy@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250305210351.249811-1-s-ramamoorthy@ti.com> References: <20250305210351.249811-1-s-ramamoorthy@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea The chipid macro/variable and regmap_read function call is not needed because the TPS65219_REG_TI_DEV_ID register value is not a consistent value across TPS65219 PMIC config versions. Reading from the DEV_ID register without a consistent value to compare it to isn't useful. There isn't a way to verify the match data ID is the same ID read from the DEV_ID device register. 0xF0 isn't a DEV_ID value consistent across TPS65219 NVM configurations. For TPS65215, there is a consistent value in bits 5-0 of the DEV_ID register. However, there are other error checks in place within probe() that apply to both PMICs rather than keeping this isolated check for one PMIC. Signed-off-by: Shree Ramamoorthy --- drivers/mfd/tps65219.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/mfd/tps65219.c b/drivers/mfd/tps65219.c index 081c5a30b04a..4aca922658e3 100644 --- a/drivers/mfd/tps65219.c +++ b/drivers/mfd/tps65219.c @@ -221,7 +221,6 @@ static const struct regmap_irq_chip tps65219_irq_chip = { static int tps65219_probe(struct i2c_client *client) { struct tps65219 *tps; - unsigned int chipid; bool pwr_button; int ret; @@ -246,12 +245,6 @@ static int tps65219_probe(struct i2c_client *client) if (ret) return ret; - ret = regmap_read(tps->regmap, TPS65219_REG_TI_DEV_ID, &chipid); - if (ret) { - dev_err(tps->dev, "Failed to read device ID: %d\n", ret); - return ret; - } - ret = devm_mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO, tps65219_cells, ARRAY_SIZE(tps65219_cells), NULL, 0, regmap_irq_get_domain(tps->irq_data)); From patchwork Wed Mar 5 21:03:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shree Ramamoorthy X-Patchwork-Id: 871044 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63E8B2586EB; Wed, 5 Mar 2025 21:04:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741208664; cv=none; b=g18TV8mQ6vXNRbag9kfibeM+cbdZfKko7VvqNQZh8Cyf5V3H/EuDZDZ3EHSxFSegIkqO0ozIIil3xMXYzCougx4CkD+B/DdnIOy4xUgg/PqY/DYV87X/tntp/a/NwTVmoekgi6sn6rpGfEVzQtDl7gR3KCrehTbKGsGjAoMzuF0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741208664; c=relaxed/simple; bh=VYBhLXwBJtgYYnddABcUpttFcdPZnBK2iXoErIu9xWY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OxNdR0MM37eYYzCSvg3Ft8263RyhRKyxgyFTBX5tXsTsrACRFpTTOBj1Fp90lKujieVGzq/CxLoEBGjrzsDErbyvFLWWbgDSRCHKSgwtLZ7gOur+4I9QqYq++gPmSrpxypgeQEewTY99fZ6GaM+F9hcAKKDUznyq+GBvtvOQFgU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=hv49tSEQ; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="hv49tSEQ" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 525L3qeI3513449 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 5 Mar 2025 15:03:52 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1741208632; bh=FH8+u45IFg7clQTneCie7pPyIWNKJ/iwpmiKdg3Wtdk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hv49tSEQUw/Ar7xKnSPNADePovMB+SEE2tv9KLcWOzS8lJ97exepYtgbe7shNesok 2sH5qZFm10h25tW6gUQq22pZau0CJNI5gyxuXTARJpjg2PqIdOcfcbC1HH/D+j0SB9 A47IORhJxy16arGc3Q+genl/4blVv56yg4ESLU9k= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 525L3qvC034784 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 5 Mar 2025 15:03:52 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 5 Mar 2025 15:03:52 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 5 Mar 2025 15:03:52 -0600 Received: from DMZ007XYY.dhcp.ti.com (dmz007xyy.dhcp.ti.com [128.247.29.251]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 525L3peE125160; Wed, 5 Mar 2025 15:03:51 -0600 From: Shree Ramamoorthy To: , , , , , , , , , , , , , CC: , Subject: [PATCH v6 4/9] mfd: tps65219: Add support for TI TPS65215 PMIC Date: Wed, 5 Mar 2025 15:03:46 -0600 Message-ID: <20250305210351.249811-5-s-ramamoorthy@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250305210351.249811-1-s-ramamoorthy@ti.com> References: <20250305210351.249811-1-s-ramamoorthy@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Use chip ID and chip_data struct to differentiate between devices in probe(). Add TPS65215 resource information. Update descriptions and copyright information to reflect the driver supports 2 PMIC devices. Signed-off-by: Shree Ramamoorthy --- drivers/mfd/tps65219.c | 150 +++++++++++++++++++++++++++++++++-- include/linux/mfd/tps65219.h | 71 +++++++++++++++-- 2 files changed, 209 insertions(+), 12 deletions(-) diff --git a/drivers/mfd/tps65219.c b/drivers/mfd/tps65219.c index 4aca922658e3..d4788ebcb5c4 100644 --- a/drivers/mfd/tps65219.c +++ b/drivers/mfd/tps65219.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 // -// Driver for TPS65219 Integrated Power Management Integrated Chips (PMIC) +// Driver for TPS65215/TPS65219 Power Management Integrated Chips (PMIC) // // Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/ +// Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ #include #include @@ -59,6 +60,46 @@ static const struct resource tps65219_pwrbutton_resources[] = { DEFINE_RES_IRQ_NAMED(TPS65219_INT_PB_RISING_EDGE_DETECT, "rising"), }; +static const struct resource tps65215_regulator_resources[] = { + DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO1_SCG, "LDO1_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO1_OC, "LDO1_OC"), + DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO1_UV, "LDO1_UV"), + DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO2_SCG, "LDO2_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO2_OC, "LDO2_OC"), + DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO2_UV, "LDO2_UV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_SCG, "BUCK3_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_OC, "BUCK3_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_NEG_OC, "BUCK3_NEG_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_UV, "BUCK3_UV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_SCG, "BUCK1_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_OC, "BUCK1_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_NEG_OC, "BUCK1_NEG_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_UV, "BUCK1_UV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_SCG, "BUCK2_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_OC, "BUCK2_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_NEG_OC, "BUCK2_NEG_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_UV, "BUCK2_UV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV, "BUCK1_RV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV, "BUCK2_RV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV, "BUCK3_RV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_RV, "LDO1_RV"), + DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO2_RV, "LDO2_RV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV_SD, "BUCK1_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV_SD, "BUCK2_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV_SD, "BUCK3_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_RV_SD, "LDO1_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO2_RV_SD, "LDO2_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_TIMEOUT, "TIMEOUT"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_3_WARM, "SENSOR_3_WARM"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_WARM, "SENSOR_2_WARM"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_WARM, "SENSOR_1_WARM"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_WARM, "SENSOR_0_WARM"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_3_HOT, "SENSOR_3_HOT"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_HOT, "SENSOR_2_HOT"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_HOT, "SENSOR_1_HOT"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_HOT, "SENSOR_0_HOT"), +}; + static const struct resource tps65219_regulator_resources[] = { DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_SCG, "LDO3_SCG"), DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_OC, "LDO3_OC"), @@ -109,6 +150,11 @@ static const struct resource tps65219_regulator_resources[] = { DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_HOT, "SENSOR_0_HOT"), }; +static const struct mfd_cell tps65215_cells[] = { + MFD_CELL_RES("tps65215-regulator", tps65215_regulator_resources), + MFD_CELL_NAME("tps65215-gpio"), +}; + static const struct mfd_cell tps65219_cells[] = { MFD_CELL_RES("tps65219-regulator", tps65219_regulator_resources), MFD_CELL_NAME("tps65219-gpio"), @@ -136,6 +182,8 @@ static unsigned int bit3_offsets[] = { TPS65219_REG_INT_BUCK_1_2_POS }; /* Buck static unsigned int bit4_offsets[] = { TPS65219_REG_INT_BUCK_3_POS }; /* Buck 3 */ static unsigned int bit5_offsets[] = { TPS65219_REG_INT_LDO_1_2_POS }; /* LDO 1-2 */ static unsigned int bit6_offsets[] = { TPS65219_REG_INT_LDO_3_4_POS }; /* LDO 3-4 */ +static unsigned int tps65215_bit5_offsets[] = { TPS65215_REG_INT_LDO_1_POS }; +static unsigned int tps65215_bit6_offsets[] = { TPS65215_REG_INT_LDO_2_POS }; static unsigned int bit7_offsets[] = { TPS65219_REG_INT_PB_POS }; /* Power Button */ static struct regmap_irq_sub_irq_map tps65219_sub_irq_offsets[] = { @@ -149,9 +197,62 @@ static struct regmap_irq_sub_irq_map tps65219_sub_irq_offsets[] = { REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), }; +static struct regmap_irq_sub_irq_map tps65215_sub_irq_offsets[] = { + REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(tps65215_bit5_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(tps65215_bit6_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), +}; + #define TPS65219_REGMAP_IRQ_REG(int_name, register_position) \ REGMAP_IRQ_REG(int_name, register_position, int_name##_MASK) +static const struct regmap_irq tps65215_irqs[] = { + TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO1_SCG, TPS65215_REG_INT_LDO_1_POS), + TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO1_OC, TPS65215_REG_INT_LDO_1_POS), + TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO1_UV, TPS65215_REG_INT_LDO_1_POS), + TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO2_SCG, TPS65215_REG_INT_LDO_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO2_OC, TPS65215_REG_INT_LDO_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO2_UV, TPS65215_REG_INT_LDO_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_SCG, TPS65219_REG_INT_BUCK_3_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_OC, TPS65219_REG_INT_BUCK_3_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_NEG_OC, TPS65219_REG_INT_BUCK_3_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_UV, TPS65219_REG_INT_BUCK_3_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_SCG, TPS65219_REG_INT_BUCK_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_OC, TPS65219_REG_INT_BUCK_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_NEG_OC, TPS65219_REG_INT_BUCK_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_UV, TPS65219_REG_INT_BUCK_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_SCG, TPS65219_REG_INT_BUCK_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_OC, TPS65219_REG_INT_BUCK_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_NEG_OC, TPS65219_REG_INT_BUCK_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_UV, TPS65219_REG_INT_BUCK_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_3_WARM, TPS65219_REG_INT_SYS_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_WARM, TPS65219_REG_INT_SYS_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_WARM, TPS65219_REG_INT_SYS_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_WARM, TPS65219_REG_INT_SYS_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_3_HOT, TPS65219_REG_INT_SYS_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_HOT, TPS65219_REG_INT_SYS_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_HOT, TPS65219_REG_INT_SYS_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_HOT, TPS65219_REG_INT_SYS_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV, TPS65219_REG_INT_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV, TPS65219_REG_INT_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV, TPS65219_REG_INT_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_RV, TPS65219_REG_INT_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO2_RV, TPS65219_REG_INT_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV_SD, TPS65219_REG_INT_TO_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV_SD, TPS65219_REG_INT_TO_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV_SD, TPS65219_REG_INT_TO_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_RV_SD, TPS65219_REG_INT_TO_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO2_RV_SD, TPS65219_REG_INT_TO_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_TIMEOUT, TPS65219_REG_INT_TO_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_FALLING_EDGE_DETECT, TPS65219_REG_INT_PB_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_RISING_EDGE_DETECT, TPS65219_REG_INT_PB_POS), +}; + static const struct regmap_irq tps65219_irqs[] = { TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO3_SCG, TPS65219_REG_INT_LDO_3_4_POS), TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO3_OC, TPS65219_REG_INT_LDO_3_4_POS), @@ -204,6 +305,20 @@ static const struct regmap_irq tps65219_irqs[] = { TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_RISING_EDGE_DETECT, TPS65219_REG_INT_PB_POS), }; +static const struct regmap_irq_chip tps65215_irq_chip = { + .name = "tps65215_irq", + .main_status = TPS65219_REG_INT_SOURCE, + .num_main_regs = 1, + .num_main_status_bits = 8, + .irqs = tps65215_irqs, + .num_irqs = ARRAY_SIZE(tps65215_irqs), + .status_base = TPS65215_REG_INT_LDO_2, + .ack_base = TPS65215_REG_INT_LDO_2, + .clear_ack = 1, + .num_regs = 8, + .sub_reg_offsets = tps65215_sub_irq_offsets, +}; + static const struct regmap_irq_chip tps65219_irq_chip = { .name = "tps65219_irq", .main_status = TPS65219_REG_INT_SOURCE, @@ -218,9 +333,29 @@ static const struct regmap_irq_chip tps65219_irq_chip = { .sub_reg_offsets = tps65219_sub_irq_offsets, }; +struct tps65219_chip_data { + const struct regmap_irq_chip *irq_chip; + const struct mfd_cell *cells; + int n_cells; +}; + +static struct tps65219_chip_data chip_info_table[] = { + [TPS65215] = { + .irq_chip = &tps65215_irq_chip, + .cells = tps65215_cells, + .n_cells = ARRAY_SIZE(tps65215_cells), + }, + [TPS65219] = { + .irq_chip = &tps65219_irq_chip, + .cells = tps65219_cells, + .n_cells = ARRAY_SIZE(tps65219_cells), + }, +}; + static int tps65219_probe(struct i2c_client *client) { struct tps65219 *tps; + struct tps65219_chip_data *pmic; bool pwr_button; int ret; @@ -231,6 +366,8 @@ static int tps65219_probe(struct i2c_client *client) i2c_set_clientdata(client, tps); tps->dev = &client->dev; + tps->chip_id = (uintptr_t)i2c_get_match_data(client); + pmic = &chip_info_table[tps->chip_id]; tps->regmap = devm_regmap_init_i2c(client, &tps65219_regmap_config); if (IS_ERR(tps->regmap)) { @@ -239,14 +376,14 @@ static int tps65219_probe(struct i2c_client *client) return ret; } - ret = devm_regmap_add_irq_chip(&client->dev, tps->regmap, client->irq, - IRQF_ONESHOT, 0, &tps65219_irq_chip, + ret = devm_regmap_add_irq_chip(tps->dev, tps->regmap, client->irq, + IRQF_ONESHOT, 0, pmic->irq_chip, &tps->irq_data); if (ret) return ret; ret = devm_mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO, - tps65219_cells, ARRAY_SIZE(tps65219_cells), + pmic->cells, pmic->n_cells, NULL, 0, regmap_irq_get_domain(tps->irq_data)); if (ret) { dev_err(tps->dev, "Failed to add child devices: %d\n", ret); @@ -284,7 +421,8 @@ static int tps65219_probe(struct i2c_client *client) } static const struct of_device_id of_tps65219_match_table[] = { - { .compatible = "ti,tps65219", }, + { .compatible = "ti,tps65215", .data = (void *)TPS65215, }, + { .compatible = "ti,tps65219", .data = (void *)TPS65219, }, {} }; MODULE_DEVICE_TABLE(of, of_tps65219_match_table); @@ -299,5 +437,5 @@ static struct i2c_driver tps65219_driver = { module_i2c_driver(tps65219_driver); MODULE_AUTHOR("Jerome Neanne "); -MODULE_DESCRIPTION("TPS65219 power management IC driver"); +MODULE_DESCRIPTION("TPS65215/TPS65219 PMIC driver"); MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/tps65219.h b/include/linux/mfd/tps65219.h index 546bceec7173..6047f92b367f 100644 --- a/include/linux/mfd/tps65219.h +++ b/include/linux/mfd/tps65219.h @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Functions to access TPS65219 Power Management IC. + * Functions to access TPS65215/TPS65219 Power Management Integrated Chips * * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/ + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef MFD_TPS65219_H @@ -13,8 +14,11 @@ #include #include -/* TPS chip id list */ -#define TPS65219 0xF0 +/* Chip id list*/ +enum pmic_id { + TPS65215, + TPS65219, +}; /* I2C ID for TPS65219 part */ #define TPS65219_I2C_ID 0x24 @@ -26,6 +30,7 @@ #define TPS65219_REG_BUCKS_CONFIG 0x03 #define TPS65219_REG_LDO4_VOUT 0x04 #define TPS65219_REG_LDO3_VOUT 0x05 +#define TPS65215_REG_LDO2_VOUT 0x05 #define TPS65219_REG_LDO2_VOUT 0x06 #define TPS65219_REG_LDO1_VOUT 0x07 #define TPS65219_REG_BUCK3_VOUT 0x8 @@ -33,6 +38,7 @@ #define TPS65219_REG_BUCK1_VOUT 0xA #define TPS65219_REG_LDO4_SEQUENCE_SLOT 0xB #define TPS65219_REG_LDO3_SEQUENCE_SLOT 0xC +#define TPS65215_REG_LDO2_SEQUENCE_SLOT 0xC #define TPS65219_REG_LDO2_SEQUENCE_SLOT 0xD #define TPS65219_REG_LDO1_SEQUENCE_SLOT 0xE #define TPS65219_REG_BUCK3_SEQUENCE_SLOT 0xF @@ -67,9 +73,16 @@ #define TPS65219_REG_DISCHARGE_CONFIG 0x2A /* main irq registers */ #define TPS65219_REG_INT_SOURCE 0x2B -/* 'sub irq' registers */ + +/* TPS65219 'sub irq' registers */ #define TPS65219_REG_INT_LDO_3_4 0x2C #define TPS65219_REG_INT_LDO_1_2 0x2D + +/* TPS65215 specific 'sub irq' registers */ +#define TPS65215_REG_INT_LDO_2 0x2C +#define TPS65215_REG_INT_LDO_1 0x2D + +/* Common TPS65215 & TPS65219 'sub irq' registers */ #define TPS65219_REG_INT_BUCK_3 0x2E #define TPS65219_REG_INT_BUCK_1_2 0x2F #define TPS65219_REG_INT_SYSTEM 0x30 @@ -86,6 +99,9 @@ #define TPS65219_REG_INT_TO_RV_POS 6 #define TPS65219_REG_INT_PB_POS 7 +#define TPS65215_REG_INT_LDO_2_POS 0 +#define TPS65215_REG_INT_LDO_1_POS 1 + #define TPS65219_REG_USER_NVM_CMD 0x34 #define TPS65219_REG_POWER_UP_STATUS 0x35 #define TPS65219_REG_SPARE_2 0x36 @@ -107,6 +123,7 @@ #define TPS65219_ENABLE_LDO1_EN_MASK BIT(3) #define TPS65219_ENABLE_LDO2_EN_MASK BIT(4) #define TPS65219_ENABLE_LDO3_EN_MASK BIT(5) +#define TPS65215_ENABLE_LDO2_EN_MASK BIT(5) #define TPS65219_ENABLE_LDO4_EN_MASK BIT(6) /* power ON-OFF sequence slot */ #define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK GENMASK(3, 0) @@ -172,6 +189,13 @@ #define TPS65219_INT_LDO2_SCG_MASK BIT(3) #define TPS65219_INT_LDO2_OC_MASK BIT(4) #define TPS65219_INT_LDO2_UV_MASK BIT(5) +/* TPS65215 LDO1-2*/ +#define TPS65215_INT_LDO1_SCG_MASK BIT(0) +#define TPS65215_INT_LDO1_OC_MASK BIT(1) +#define TPS65215_INT_LDO1_UV_MASK BIT(2) +#define TPS65215_INT_LDO2_SCG_MASK BIT(0) +#define TPS65215_INT_LDO2_OC_MASK BIT(1) +#define TPS65215_INT_LDO2_UV_MASK BIT(2) /* BUCK3 */ #define TPS65219_INT_BUCK3_SCG_MASK BIT(0) #define TPS65219_INT_BUCK3_OC_MASK BIT(1) @@ -202,6 +226,7 @@ #define TPS65219_INT_LDO1_RV_MASK BIT(3) #define TPS65219_INT_LDO2_RV_MASK BIT(4) #define TPS65219_INT_LDO3_RV_MASK BIT(5) +#define TPS65215_INT_LDO2_RV_MASK BIT(5) #define TPS65219_INT_LDO4_RV_MASK BIT(6) /* Residual Voltage ShutDown */ #define TPS65219_INT_BUCK1_RV_SD_MASK BIT(0) @@ -210,6 +235,7 @@ #define TPS65219_INT_LDO1_RV_SD_MASK BIT(3) #define TPS65219_INT_LDO2_RV_SD_MASK BIT(4) #define TPS65219_INT_LDO3_RV_SD_MASK BIT(5) +#define TPS65215_INT_LDO2_RV_SD_MASK BIT(5) #define TPS65219_INT_LDO4_RV_SD_MASK BIT(6) #define TPS65219_INT_TIMEOUT_MASK BIT(7) /* Power Button */ @@ -235,6 +261,14 @@ enum { TPS65219_INT_LDO4_SCG, TPS65219_INT_LDO4_OC, TPS65219_INT_LDO4_UV, + /* TPS65215 LDO1*/ + TPS65215_INT_LDO1_SCG, + TPS65215_INT_LDO1_OC, + TPS65215_INT_LDO1_UV, + /* TPS65215 LDO2*/ + TPS65215_INT_LDO2_SCG, + TPS65215_INT_LDO2_OC, + TPS65215_INT_LDO2_UV, /* LDO1-2 */ TPS65219_INT_LDO1_SCG, TPS65219_INT_LDO1_OC, @@ -271,6 +305,7 @@ enum { TPS65219_INT_BUCK3_RV, TPS65219_INT_LDO1_RV, TPS65219_INT_LDO2_RV, + TPS65215_INT_LDO2_RV, TPS65219_INT_LDO3_RV, TPS65219_INT_LDO4_RV, /* Residual Voltage ShutDown */ @@ -278,6 +313,7 @@ enum { TPS65219_INT_BUCK2_RV_SD, TPS65219_INT_BUCK3_RV_SD, TPS65219_INT_LDO1_RV_SD, + TPS65215_INT_LDO2_RV_SD, TPS65219_INT_LDO2_RV_SD, TPS65219_INT_LDO3_RV_SD, TPS65219_INT_LDO4_RV_SD, @@ -287,6 +323,12 @@ enum { TPS65219_INT_PB_RISING_EDGE_DETECT, }; +enum tps65215_regulator_id { + /* DCDC's same as TPS65219 */ + /* LDO1 is the same as TPS65219 */ + TPS65215_LDO_2 = 4, +}; + enum tps65219_regulator_id { /* DCDC's */ TPS65219_BUCK_1, @@ -300,11 +342,26 @@ enum tps65219_regulator_id { }; /* Number of step-down converters available */ -#define TPS65219_NUM_DCDC 3 +#define TPS6521X_NUM_BUCKS 3 /* Number of LDO voltage regulators available */ #define TPS65219_NUM_LDO 4 +#define TPS65215_NUM_LDO 2 /* Number of total regulators available */ -#define TPS65219_NUM_REGULATOR (TPS65219_NUM_DCDC + TPS65219_NUM_LDO) +#define TPS65219_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65219_NUM_LDO) +#define TPS65215_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65215_NUM_LDO) + +/* Define the TPS65215 IRQ numbers */ +enum tps65215_irqs { + /* INT source registers */ + TPS65215_TO_RV_SD_SET_IRQ, + TPS65215_RV_SET_IRQ, + TPS65215_SYS_SET_IRQ, + TPS65215_BUCK_1_2_SET_IRQ, + TPS65215_BUCK_3_SET_IRQ, + TPS65215_LDO_1_SET_IRQ, + TPS65215_LDO_2_SET_IRQ, + TPS65215_PB_SET_IRQ, +}; /* Define the TPS65219 IRQ numbers */ enum tps65219_irqs { @@ -326,6 +383,7 @@ enum tps65219_irqs { * * @dev: MFD device * @regmap: Regmap for accessing the device registers + * @chip_id: Chip ID * @irq_data: Regmap irq data used for the irq chip * @nb: notifier block for the restart handler */ @@ -333,6 +391,7 @@ struct tps65219 { struct device *dev; struct regmap *regmap; + unsigned int chip_id; struct regmap_irq_chip_data *irq_data; struct notifier_block nb; }; From patchwork Wed Mar 5 21:03:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shree Ramamoorthy X-Patchwork-Id: 870720 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 515771547DE; Wed, 5 Mar 2025 21:04:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 5 Mar 2025 15:03:52 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 5 Mar 2025 15:03:52 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 5 Mar 2025 15:03:52 -0600 Received: from DMZ007XYY.dhcp.ti.com (dmz007xyy.dhcp.ti.com [128.247.29.251]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 525L3peF125160; Wed, 5 Mar 2025 15:03:52 -0600 From: Shree Ramamoorthy To: , , , , , , , , , , , , , CC: , Subject: [PATCH v6 5/9] mfd: tps65219: Add support for TI TPS65214 PMIC Date: Wed, 5 Mar 2025 15:03:47 -0600 Message-ID: <20250305210351.249811-6-s-ramamoorthy@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250305210351.249811-1-s-ramamoorthy@ti.com> References: <20250305210351.249811-1-s-ramamoorthy@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Use chip ID and chip_data struct to differentiate between 3 PMIC devices in probe(). Add TPS65214 resource information. Update descriptions and copyright information to reflect the driver supports 3 PMIC devices. Signed-off-by: Shree Ramamoorthy --- drivers/mfd/tps65219.c | 126 ++++++++++++++++++++++++++++++++++- include/linux/mfd/tps65219.h | 65 ++++++++++++++++-- 2 files changed, 184 insertions(+), 7 deletions(-) diff --git a/drivers/mfd/tps65219.c b/drivers/mfd/tps65219.c index d4788ebcb5c4..fd390600fbf0 100644 --- a/drivers/mfd/tps65219.c +++ b/drivers/mfd/tps65219.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 // -// Driver for TPS65215/TPS65219 Power Management Integrated Chips (PMIC) +// Driver for TPS65214/TPS65215/TPS65219 Power Management Integrated Chips // // Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/ // Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ @@ -60,6 +60,44 @@ static const struct resource tps65219_pwrbutton_resources[] = { DEFINE_RES_IRQ_NAMED(TPS65219_INT_PB_RISING_EDGE_DETECT, "rising"), }; +static const struct resource tps65214_regulator_resources[] = { + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_SCG, "LDO1_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_OC, "LDO1_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_UV, "LDO1_UV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_SCG, "LDO2_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_OC, "LDO2_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_UV, "LDO2_UV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_SCG, "BUCK3_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_OC, "BUCK3_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_NEG_OC, "BUCK3_NEG_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_UV, "BUCK3_UV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_SCG, "BUCK1_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_OC, "BUCK1_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_NEG_OC, "BUCK1_NEG_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_UV, "BUCK1_UV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_SCG, "BUCK2_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_OC, "BUCK2_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_NEG_OC, "BUCK2_NEG_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_UV, "BUCK2_UV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV, "BUCK1_RV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV, "BUCK2_RV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV, "BUCK3_RV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_RV, "LDO1_RV"), + DEFINE_RES_IRQ_NAMED(TPS65214_INT_LDO2_RV, "LDO2_RV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV_SD, "BUCK1_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV_SD, "BUCK2_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV_SD, "BUCK3_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65214_INT_LDO1_RV_SD, "LDO1_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_RV_SD, "LDO2_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_TIMEOUT, "TIMEOUT"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_WARM, "SENSOR_2_WARM"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_WARM, "SENSOR_1_WARM"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_WARM, "SENSOR_0_WARM"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_HOT, "SENSOR_2_HOT"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_HOT, "SENSOR_1_HOT"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_HOT, "SENSOR_0_HOT"), +}; + static const struct resource tps65215_regulator_resources[] = { DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO1_SCG, "LDO1_SCG"), DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO1_OC, "LDO1_OC"), @@ -150,6 +188,11 @@ static const struct resource tps65219_regulator_resources[] = { DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_HOT, "SENSOR_0_HOT"), }; +static const struct mfd_cell tps65214_cells[] = { + MFD_CELL_RES("tps65214-regulator", tps65214_regulator_resources), + MFD_CELL_NAME("tps65215-gpio"), +}; + static const struct mfd_cell tps65215_cells[] = { MFD_CELL_RES("tps65215-regulator", tps65215_regulator_resources), MFD_CELL_NAME("tps65215-gpio"), @@ -186,6 +229,15 @@ static unsigned int tps65215_bit5_offsets[] = { TPS65215_REG_INT_LDO_1_POS }; static unsigned int tps65215_bit6_offsets[] = { TPS65215_REG_INT_LDO_2_POS }; static unsigned int bit7_offsets[] = { TPS65219_REG_INT_PB_POS }; /* Power Button */ +/* TPS65214 INT_SOURCE bit 6 is 'RESERVED'*/ +static unsigned int tps65214_bit0_offsets[] = { TPS65214_REG_INT_TO_RV_POS }; +static unsigned int tps65214_bit1_offsets[] = { TPS65214_REG_INT_RV_POS }; +static unsigned int tps65214_bit2_offsets[] = { TPS65214_REG_INT_SYS_POS }; +static unsigned int tps65214_bit3_offsets[] = { TPS65214_REG_INT_BUCK_1_2_POS }; +static unsigned int tps65214_bit4_offsets[] = { TPS65214_REG_INT_BUCK_3_POS }; +static unsigned int tps65214_bit5_offsets[] = { TPS65214_REG_INT_LDO_1_2_POS }; +static unsigned int tps65214_bit7_offsets[] = { TPS65214_REG_INT_PB_POS }; + static struct regmap_irq_sub_irq_map tps65219_sub_irq_offsets[] = { REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), @@ -208,9 +260,59 @@ static struct regmap_irq_sub_irq_map tps65215_sub_irq_offsets[] = { REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), }; +static struct regmap_irq_sub_irq_map tps65214_sub_irq_offsets[] = { + REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit0_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit1_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit2_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit3_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit4_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit5_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit7_offsets), +}; + #define TPS65219_REGMAP_IRQ_REG(int_name, register_position) \ REGMAP_IRQ_REG(int_name, register_position, int_name##_MASK) +static const struct regmap_irq tps65214_irqs[] = { + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_SCG, TPS65214_REG_INT_LDO_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_OC, TPS65214_REG_INT_LDO_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_UV, TPS65214_REG_INT_LDO_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_SCG, TPS65214_REG_INT_LDO_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_OC, TPS65214_REG_INT_LDO_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_UV, TPS65214_REG_INT_LDO_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_SCG, TPS65214_REG_INT_BUCK_3_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_OC, TPS65214_REG_INT_BUCK_3_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_NEG_OC, TPS65214_REG_INT_BUCK_3_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_UV, TPS65214_REG_INT_BUCK_3_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_SCG, TPS65214_REG_INT_BUCK_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_OC, TPS65214_REG_INT_BUCK_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_NEG_OC, TPS65214_REG_INT_BUCK_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_UV, TPS65214_REG_INT_BUCK_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_SCG, TPS65214_REG_INT_BUCK_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_OC, TPS65214_REG_INT_BUCK_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_NEG_OC, TPS65214_REG_INT_BUCK_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_UV, TPS65214_REG_INT_BUCK_1_2_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_WARM, TPS65214_REG_INT_SYS_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_WARM, TPS65214_REG_INT_SYS_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_WARM, TPS65214_REG_INT_SYS_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_HOT, TPS65214_REG_INT_SYS_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_HOT, TPS65214_REG_INT_SYS_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_HOT, TPS65214_REG_INT_SYS_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV, TPS65214_REG_INT_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV, TPS65214_REG_INT_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV, TPS65214_REG_INT_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_RV, TPS65214_REG_INT_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65214_INT_LDO2_RV, TPS65214_REG_INT_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV_SD, TPS65214_REG_INT_TO_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV_SD, TPS65214_REG_INT_TO_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV_SD, TPS65214_REG_INT_TO_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65214_INT_LDO1_RV_SD, TPS65214_REG_INT_TO_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_RV_SD, TPS65214_REG_INT_TO_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_TIMEOUT, TPS65214_REG_INT_TO_RV_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_FALLING_EDGE_DETECT, TPS65214_REG_INT_PB_POS), + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_RISING_EDGE_DETECT, TPS65214_REG_INT_PB_POS), +}; + static const struct regmap_irq tps65215_irqs[] = { TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO1_SCG, TPS65215_REG_INT_LDO_1_POS), TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO1_OC, TPS65215_REG_INT_LDO_1_POS), @@ -305,6 +407,20 @@ static const struct regmap_irq tps65219_irqs[] = { TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_RISING_EDGE_DETECT, TPS65219_REG_INT_PB_POS), }; +static const struct regmap_irq_chip tps65214_irq_chip = { + .name = "tps65214_irq", + .main_status = TPS65219_REG_INT_SOURCE, + .num_main_regs = 1, + .num_main_status_bits = 8, + .irqs = tps65214_irqs, + .num_irqs = ARRAY_SIZE(tps65214_irqs), + .status_base = TPS65214_REG_INT_LDO_1_2, + .ack_base = TPS65214_REG_INT_LDO_1_2, + .clear_ack = 1, + .num_regs = 8, + .sub_reg_offsets = tps65214_sub_irq_offsets, +}; + static const struct regmap_irq_chip tps65215_irq_chip = { .name = "tps65215_irq", .main_status = TPS65219_REG_INT_SOURCE, @@ -340,6 +456,11 @@ struct tps65219_chip_data { }; static struct tps65219_chip_data chip_info_table[] = { + [TPS65214] = { + .irq_chip = &tps65214_irq_chip, + .cells = tps65214_cells, + .n_cells = ARRAY_SIZE(tps65214_cells), + }, [TPS65215] = { .irq_chip = &tps65215_irq_chip, .cells = tps65215_cells, @@ -421,6 +542,7 @@ static int tps65219_probe(struct i2c_client *client) } static const struct of_device_id of_tps65219_match_table[] = { + { .compatible = "ti,tps65214", .data = (void *)TPS65214, }, { .compatible = "ti,tps65215", .data = (void *)TPS65215, }, { .compatible = "ti,tps65219", .data = (void *)TPS65219, }, {} @@ -437,5 +559,5 @@ static struct i2c_driver tps65219_driver = { module_i2c_driver(tps65219_driver); MODULE_AUTHOR("Jerome Neanne "); -MODULE_DESCRIPTION("TPS65215/TPS65219 PMIC driver"); +MODULE_DESCRIPTION("TPS65214/TPS65215/TPS65219 PMIC driver"); MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/tps65219.h b/include/linux/mfd/tps65219.h index 6047f92b367f..3e8d29189267 100644 --- a/include/linux/mfd/tps65219.h +++ b/include/linux/mfd/tps65219.h @@ -16,6 +16,7 @@ /* Chip id list*/ enum pmic_id { + TPS65214, TPS65215, TPS65219, }; @@ -28,17 +29,23 @@ enum pmic_id { #define TPS65219_REG_NVM_ID 0x01 #define TPS65219_REG_ENABLE_CTRL 0x02 #define TPS65219_REG_BUCKS_CONFIG 0x03 +#define TPS65214_REG_LOCK 0x03 #define TPS65219_REG_LDO4_VOUT 0x04 +#define TPS65214_REG_LDO1_VOUT_STBY 0x04 #define TPS65219_REG_LDO3_VOUT 0x05 #define TPS65215_REG_LDO2_VOUT 0x05 +#define TPS65214_REG_LDO1_VOUT 0x05 #define TPS65219_REG_LDO2_VOUT 0x06 +#define TPS65214_REG_LDO2_VOUT 0x06 #define TPS65219_REG_LDO1_VOUT 0x07 +#define TPS65214_REG_LDO2_VOUT_STBY 0x07 #define TPS65219_REG_BUCK3_VOUT 0x8 #define TPS65219_REG_BUCK2_VOUT 0x9 #define TPS65219_REG_BUCK1_VOUT 0xA #define TPS65219_REG_LDO4_SEQUENCE_SLOT 0xB #define TPS65219_REG_LDO3_SEQUENCE_SLOT 0xC #define TPS65215_REG_LDO2_SEQUENCE_SLOT 0xC +#define TPS65214_REG_LDO1_SEQUENCE_SLOT 0xC #define TPS65219_REG_LDO2_SEQUENCE_SLOT 0xD #define TPS65219_REG_LDO1_SEQUENCE_SLOT 0xE #define TPS65219_REG_BUCK3_SEQUENCE_SLOT 0xF @@ -47,15 +54,21 @@ enum pmic_id { #define TPS65219_REG_nRST_SEQUENCE_SLOT 0x12 #define TPS65219_REG_GPIO_SEQUENCE_SLOT 0x13 #define TPS65219_REG_GPO2_SEQUENCE_SLOT 0x14 +#define TPS65214_REG_GPIO_GPI_SEQUENCE_SLOT 0x14 #define TPS65219_REG_GPO1_SEQUENCE_SLOT 0x15 +#define TPS65214_REG_GPO_SEQUENCE_SLOT 0x15 #define TPS65219_REG_POWER_UP_SLOT_DURATION_1 0x16 #define TPS65219_REG_POWER_UP_SLOT_DURATION_2 0x17 +/* _SLOT_DURATION_3 doesn't apply to TPS65215*/ #define TPS65219_REG_POWER_UP_SLOT_DURATION_3 0x18 #define TPS65219_REG_POWER_UP_SLOT_DURATION_4 0x19 +#define TPS65214_REG_BUCK3_VOUT_STBY 0x19 #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_1 0x1A #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_2 0x1B #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_3 0x1C +#define TPS65214_REG_BUCK2_VOUT_STBY 0x1C #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_4 0x1D +#define TPS65214_REG_BUCK1_VOUT_STBY 0x1D #define TPS65219_REG_GENERAL_CONFIG 0x1E #define TPS65219_REG_MFP_1_CONFIG 0x1F #define TPS65219_REG_MFP_2_CONFIG 0x20 @@ -82,6 +95,9 @@ enum pmic_id { #define TPS65215_REG_INT_LDO_2 0x2C #define TPS65215_REG_INT_LDO_1 0x2D +/* TPS65214 specific 'sub irq' register */ +#define TPS65214_REG_INT_LDO_1_2 0x2D + /* Common TPS65215 & TPS65219 'sub irq' registers */ #define TPS65219_REG_INT_BUCK_3 0x2E #define TPS65219_REG_INT_BUCK_1_2 0x2F @@ -102,6 +118,14 @@ enum pmic_id { #define TPS65215_REG_INT_LDO_2_POS 0 #define TPS65215_REG_INT_LDO_1_POS 1 +#define TPS65214_REG_INT_LDO_1_2_POS 0 +#define TPS65214_REG_INT_BUCK_3_POS 1 +#define TPS65214_REG_INT_BUCK_1_2_POS 2 +#define TPS65214_REG_INT_SYS_POS 3 +#define TPS65214_REG_INT_RV_POS 4 +#define TPS65214_REG_INT_TO_RV_POS 5 +#define TPS65214_REG_INT_PB_POS 6 + #define TPS65219_REG_USER_NVM_CMD 0x34 #define TPS65219_REG_POWER_UP_STATUS 0x35 #define TPS65219_REG_SPARE_2 0x36 @@ -124,6 +148,7 @@ enum pmic_id { #define TPS65219_ENABLE_LDO2_EN_MASK BIT(4) #define TPS65219_ENABLE_LDO3_EN_MASK BIT(5) #define TPS65215_ENABLE_LDO2_EN_MASK BIT(5) +#define TPS65214_ENABLE_LDO1_EN_MASK BIT(5) #define TPS65219_ENABLE_LDO4_EN_MASK BIT(6) /* power ON-OFF sequence slot */ #define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK GENMASK(3, 0) @@ -175,14 +200,14 @@ enum pmic_id { #define TPS65219_REG_MASK_EFFECT_MASK GENMASK(2, 1) #define TPS65219_REG_MASK_INT_FOR_PB_MASK BIT(7) /* UnderVoltage - Short to GND - OverCurrent*/ -/* LDO3-4 */ +/* LDO3-4: only for TPS65219*/ #define TPS65219_INT_LDO3_SCG_MASK BIT(0) #define TPS65219_INT_LDO3_OC_MASK BIT(1) #define TPS65219_INT_LDO3_UV_MASK BIT(2) #define TPS65219_INT_LDO4_SCG_MASK BIT(3) #define TPS65219_INT_LDO4_OC_MASK BIT(4) #define TPS65219_INT_LDO4_UV_MASK BIT(5) -/* LDO1-2 */ +/* LDO1-2: TPS65214 & TPS65219 */ #define TPS65219_INT_LDO1_SCG_MASK BIT(0) #define TPS65219_INT_LDO1_OC_MASK BIT(1) #define TPS65219_INT_LDO1_UV_MASK BIT(2) @@ -210,12 +235,13 @@ enum pmic_id { #define TPS65219_INT_BUCK2_OC_MASK BIT(5) #define TPS65219_INT_BUCK2_NEG_OC_MASK BIT(6) #define TPS65219_INT_BUCK2_UV_MASK BIT(7) -/* Thermal Sensor */ +/* Thermal Sensor: TPS65219/TPS65215 */ #define TPS65219_INT_SENSOR_3_WARM_MASK BIT(0) +#define TPS65219_INT_SENSOR_3_HOT_MASK BIT(4) +/* Thermal Sensor: TPS65219/TPS65215/TPS65214 */ #define TPS65219_INT_SENSOR_2_WARM_MASK BIT(1) #define TPS65219_INT_SENSOR_1_WARM_MASK BIT(2) #define TPS65219_INT_SENSOR_0_WARM_MASK BIT(3) -#define TPS65219_INT_SENSOR_3_HOT_MASK BIT(4) #define TPS65219_INT_SENSOR_2_HOT_MASK BIT(5) #define TPS65219_INT_SENSOR_1_HOT_MASK BIT(6) #define TPS65219_INT_SENSOR_0_HOT_MASK BIT(7) @@ -227,6 +253,7 @@ enum pmic_id { #define TPS65219_INT_LDO2_RV_MASK BIT(4) #define TPS65219_INT_LDO3_RV_MASK BIT(5) #define TPS65215_INT_LDO2_RV_MASK BIT(5) +#define TPS65214_INT_LDO2_RV_MASK BIT(5) #define TPS65219_INT_LDO4_RV_MASK BIT(6) /* Residual Voltage ShutDown */ #define TPS65219_INT_BUCK1_RV_SD_MASK BIT(0) @@ -236,6 +263,7 @@ enum pmic_id { #define TPS65219_INT_LDO2_RV_SD_MASK BIT(4) #define TPS65219_INT_LDO3_RV_SD_MASK BIT(5) #define TPS65215_INT_LDO2_RV_SD_MASK BIT(5) +#define TPS65214_INT_LDO1_RV_SD_MASK BIT(5) #define TPS65219_INT_LDO4_RV_SD_MASK BIT(6) #define TPS65219_INT_TIMEOUT_MASK BIT(7) /* Power Button */ @@ -269,7 +297,7 @@ enum { TPS65215_INT_LDO2_SCG, TPS65215_INT_LDO2_OC, TPS65215_INT_LDO2_UV, - /* LDO1-2 */ + /* LDO1-2: TPS65219/TPS65214 */ TPS65219_INT_LDO1_SCG, TPS65219_INT_LDO1_OC, TPS65219_INT_LDO1_UV, @@ -306,6 +334,7 @@ enum { TPS65219_INT_LDO1_RV, TPS65219_INT_LDO2_RV, TPS65215_INT_LDO2_RV, + TPS65214_INT_LDO2_RV, TPS65219_INT_LDO3_RV, TPS65219_INT_LDO4_RV, /* Residual Voltage ShutDown */ @@ -313,6 +342,7 @@ enum { TPS65219_INT_BUCK2_RV_SD, TPS65219_INT_BUCK3_RV_SD, TPS65219_INT_LDO1_RV_SD, + TPS65214_INT_LDO1_RV_SD, TPS65215_INT_LDO2_RV_SD, TPS65219_INT_LDO2_RV_SD, TPS65219_INT_LDO3_RV_SD, @@ -323,6 +353,17 @@ enum { TPS65219_INT_PB_RISING_EDGE_DETECT, }; +enum tps65214_regulator_id { + /* + * DCDC's same as TPS65219 + * LDO1 maps to TPS65219's LDO3 + * LDO2 is the same as TPS65219 + * + */ + TPS65214_LDO_1 = 3, + TPS65214_LDO_2 = 4, +}; + enum tps65215_regulator_id { /* DCDC's same as TPS65219 */ /* LDO1 is the same as TPS65219 */ @@ -346,9 +387,23 @@ enum tps65219_regulator_id { /* Number of LDO voltage regulators available */ #define TPS65219_NUM_LDO 4 #define TPS65215_NUM_LDO 2 +#define TPS65214_NUM_LDO 2 /* Number of total regulators available */ #define TPS65219_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65219_NUM_LDO) #define TPS65215_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65215_NUM_LDO) +#define TPS65214_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65214_NUM_LDO) + +/* Define the TPS65214 IRQ numbers */ +enum tps65214_irqs { + /* INT source registers */ + TPS65214_TO_RV_SD_SET_IRQ, + TPS65214_RV_SET_IRQ, + TPS65214_SYS_SET_IRQ, + TPS65214_BUCK_1_2_SET_IRQ, + TPS65214_BUCK_3_SET_IRQ, + TPS65214_LDO_1_2_SET_IRQ, + TPS65214_PB_SET_IRQ = 7, +}; /* Define the TPS65215 IRQ numbers */ enum tps65215_irqs { From patchwork Wed Mar 5 21:03:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shree Ramamoorthy X-Patchwork-Id: 871043 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) 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, CC: , Subject: [PATCH v6 6/9] regulator: tps65219: Update struct names Date: Wed, 5 Mar 2025 15:03:48 -0600 Message-ID: <20250305210351.249811-7-s-ramamoorthy@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250305210351.249811-1-s-ramamoorthy@ti.com> References: <20250305210351.249811-1-s-ramamoorthy@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Isolate changes that involve renaming to indicate this resource is only for TPS65219 or if it will be common for both devices. The renames are in preparation for adding TPS65215 support. Signed-off-by: Shree Ramamoorthy --- drivers/regulator/tps65219-regulator.c | 37 +++++++++++++++----------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/drivers/regulator/tps65219-regulator.c b/drivers/regulator/tps65219-regulator.c index aa65077f9d41..3c7c3a6d4c15 100644 --- a/drivers/regulator/tps65219-regulator.c +++ b/drivers/regulator/tps65219-regulator.c @@ -125,12 +125,17 @@ static const struct linear_range bucks_ranges[] = { REGULATOR_LINEAR_RANGE(3400000, 0x34, 0x3f, 0), }; -static const struct linear_range ldos_1_2_ranges[] = { +static const struct linear_range ldo_1_range[] = { REGULATOR_LINEAR_RANGE(600000, 0x0, 0x37, 50000), REGULATOR_LINEAR_RANGE(3400000, 0x38, 0x3f, 0), }; -static const struct linear_range ldos_3_4_ranges[] = { +static const struct linear_range tps65219_ldo_2_range[] = { + REGULATOR_LINEAR_RANGE(600000, 0x0, 0x37, 50000), + REGULATOR_LINEAR_RANGE(3400000, 0x38, 0x3f, 0), +}; + +static const struct linear_range tps65219_ldos_3_4_range[] = { REGULATOR_LINEAR_RANGE(1200000, 0x0, 0xC, 0), REGULATOR_LINEAR_RANGE(1250000, 0xD, 0x35, 50000), REGULATOR_LINEAR_RANGE(3300000, 0x36, 0x3F, 0), @@ -174,7 +179,7 @@ static unsigned int tps65219_get_mode(struct regulator_dev *dev) } /* Operations permitted on BUCK1/2/3 */ -static const struct regulator_ops tps65219_bucks_ops = { +static const struct regulator_ops bucks_ops = { .is_enabled = regulator_is_enabled_regmap, .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, @@ -189,7 +194,7 @@ static const struct regulator_ops tps65219_bucks_ops = { }; /* Operations permitted on LDO1/2 */ -static const struct regulator_ops tps65219_ldos_1_2_ops = { +static const struct regulator_ops ldos_1_2_ops = { .is_enabled = regulator_is_enabled_regmap, .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, @@ -204,7 +209,7 @@ static const struct regulator_ops tps65219_ldos_1_2_ops = { }; /* Operations permitted on LDO3/4 */ -static const struct regulator_ops tps65219_ldos_3_4_ops = { +static const struct regulator_ops ldos_3_4_ops = { .is_enabled = regulator_is_enabled_regmap, .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, @@ -218,53 +223,53 @@ static const struct regulator_ops tps65219_ldos_3_4_ops = { static const struct regulator_desc regulators[] = { TPS65219_REGULATOR("BUCK1", "buck1", TPS65219_BUCK_1, - REGULATOR_VOLTAGE, tps65219_bucks_ops, 64, + REGULATOR_VOLTAGE, bucks_ops, 64, TPS65219_REG_BUCK1_VOUT, TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, TPS65219_REG_ENABLE_CTRL, TPS65219_ENABLE_BUCK1_EN_MASK, 0, 0, bucks_ranges, 3, 4000, 0, NULL, 0, 0), TPS65219_REGULATOR("BUCK2", "buck2", TPS65219_BUCK_2, - REGULATOR_VOLTAGE, tps65219_bucks_ops, 64, + REGULATOR_VOLTAGE, bucks_ops, 64, TPS65219_REG_BUCK2_VOUT, TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, TPS65219_REG_ENABLE_CTRL, TPS65219_ENABLE_BUCK2_EN_MASK, 0, 0, bucks_ranges, 3, 4000, 0, NULL, 0, 0), TPS65219_REGULATOR("BUCK3", "buck3", TPS65219_BUCK_3, - REGULATOR_VOLTAGE, tps65219_bucks_ops, 64, + REGULATOR_VOLTAGE, bucks_ops, 64, TPS65219_REG_BUCK3_VOUT, TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, TPS65219_REG_ENABLE_CTRL, TPS65219_ENABLE_BUCK3_EN_MASK, 0, 0, bucks_ranges, 3, 0, 0, NULL, 0, 0), TPS65219_REGULATOR("LDO1", "ldo1", TPS65219_LDO_1, - REGULATOR_VOLTAGE, tps65219_ldos_1_2_ops, 64, + REGULATOR_VOLTAGE, ldos_1_2_ops, 64, TPS65219_REG_LDO1_VOUT, TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, TPS65219_REG_ENABLE_CTRL, - TPS65219_ENABLE_LDO1_EN_MASK, 0, 0, ldos_1_2_ranges, + TPS65219_ENABLE_LDO1_EN_MASK, 0, 0, ldo_1_range, 2, 0, 0, NULL, 0, TPS65219_LDOS_BYP_CONFIG_MASK), TPS65219_REGULATOR("LDO2", "ldo2", TPS65219_LDO_2, - REGULATOR_VOLTAGE, tps65219_ldos_1_2_ops, 64, + REGULATOR_VOLTAGE, ldos_1_2_ops, 64, TPS65219_REG_LDO2_VOUT, TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, TPS65219_REG_ENABLE_CTRL, - TPS65219_ENABLE_LDO2_EN_MASK, 0, 0, ldos_1_2_ranges, + TPS65219_ENABLE_LDO2_EN_MASK, 0, 0, tps65219_ldo_2_range, 2, 0, 0, NULL, 0, TPS65219_LDOS_BYP_CONFIG_MASK), TPS65219_REGULATOR("LDO3", "ldo3", TPS65219_LDO_3, - REGULATOR_VOLTAGE, tps65219_ldos_3_4_ops, 64, + REGULATOR_VOLTAGE, ldos_3_4_ops, 64, TPS65219_REG_LDO3_VOUT, TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, TPS65219_REG_ENABLE_CTRL, - TPS65219_ENABLE_LDO3_EN_MASK, 0, 0, ldos_3_4_ranges, + TPS65219_ENABLE_LDO3_EN_MASK, 0, 0, tps65219_ldos_3_4_range, 3, 0, 0, NULL, 0, 0), TPS65219_REGULATOR("LDO4", "ldo4", TPS65219_LDO_4, - REGULATOR_VOLTAGE, tps65219_ldos_3_4_ops, 64, + REGULATOR_VOLTAGE, ldos_3_4_ops, 64, TPS65219_REG_LDO4_VOUT, TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, TPS65219_REG_ENABLE_CTRL, - TPS65219_ENABLE_LDO4_EN_MASK, 0, 0, ldos_3_4_ranges, + TPS65219_ENABLE_LDO4_EN_MASK, 0, 0, tps65219_ldos_3_4_range, 3, 0, 0, NULL, 0, 0), }; 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Wed, 5 Mar 2025 15:03:52 -0600 Received: from DMZ007XYY.dhcp.ti.com (dmz007xyy.dhcp.ti.com [128.247.29.251]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 525L3peH125160; Wed, 5 Mar 2025 15:03:52 -0600 From: Shree Ramamoorthy To: , , , , , , , , , , , , , CC: , Subject: [PATCH v6 7/9] regulator: tps65219: Add support for TPS65215 regulator resources Date: Wed, 5 Mar 2025 15:03:49 -0600 Message-ID: <20250305210351.249811-8-s-ramamoorthy@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250305210351.249811-1-s-ramamoorthy@ti.com> References: <20250305210351.249811-1-s-ramamoorthy@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Isolate all changes involving TPS65215 regulator desc and range resources. - 'chipid' will identify which PMIC to support, and the corresponding chip_data struct element to use in probe(). The chip_data struct is helpful for any new PMICs added to this driver. The goal is to add future PMIC info to necessary structs and minimize probe() function edits. - The probe() will now loop through common (overlapping) regulators first, then device-specific structs identified in the chip_data struct. - Add TI TPS65215 PMIC to the existing platform_device_id struct, so the regulator probe() can handle which PMIC chip_data information to use. Signed-off-by: Shree Ramamoorthy --- drivers/regulator/Kconfig | 7 ++- drivers/regulator/tps65219-regulator.c | 86 +++++++++++++++++++++----- 2 files changed, 75 insertions(+), 18 deletions(-) diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 39297f7d8177..6cd87443f9bb 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -1579,10 +1579,11 @@ config REGULATOR_TPS65219 tristate "TI TPS65219 Power regulators" depends on MFD_TPS65219 && OF help - This driver supports TPS65219 voltage regulator chips. + This driver supports TPS65219 series and TPS65215 voltage regulator chips. TPS65219 series of PMICs have 3 single phase BUCKs & 4 LDOs - voltage regulators. It supports software based voltage control - for different voltage domains. + voltage regulators. + TPS65215 PMIC has 3 single phase BUCKs & 2 LDOs. + Both PMICs support software based voltage control for different voltage domains. config REGULATOR_TPS6594 tristate "TI TPS6594 Power regulators" diff --git a/drivers/regulator/tps65219-regulator.c b/drivers/regulator/tps65219-regulator.c index 3c7c3a6d4c15..2542ac1453c9 100644 --- a/drivers/regulator/tps65219-regulator.c +++ b/drivers/regulator/tps65219-regulator.c @@ -1,10 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 // -// tps65219-regulator.c -// -// Regulator driver for TPS65219 PMIC +// Regulator driver for TPS65215/TPS65219 PMIC // // Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/ +// Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ // // This implementation derived from tps65218 authored by // "J Keerthy " @@ -130,6 +129,11 @@ static const struct linear_range ldo_1_range[] = { REGULATOR_LINEAR_RANGE(3400000, 0x38, 0x3f, 0), }; +static const struct linear_range tps65215_ldo_2_range[] = { + REGULATOR_LINEAR_RANGE(1200000, 0x0, 0xC, 50000), + REGULATOR_LINEAR_RANGE(3300000, 0x36, 0x3F, 0), +}; + static const struct linear_range tps65219_ldo_2_range[] = { REGULATOR_LINEAR_RANGE(600000, 0x0, 0x37, 50000), REGULATOR_LINEAR_RANGE(3400000, 0x38, 0x3f, 0), @@ -221,7 +225,7 @@ static const struct regulator_ops ldos_3_4_ops = { .map_voltage = regulator_map_voltage_linear_range, }; -static const struct regulator_desc regulators[] = { +static const struct regulator_desc common_regs[] = { TPS65219_REGULATOR("BUCK1", "buck1", TPS65219_BUCK_1, REGULATOR_VOLTAGE, bucks_ops, 64, TPS65219_REG_BUCK1_VOUT, @@ -250,6 +254,20 @@ static const struct regulator_desc regulators[] = { TPS65219_REG_ENABLE_CTRL, TPS65219_ENABLE_LDO1_EN_MASK, 0, 0, ldo_1_range, 2, 0, 0, NULL, 0, TPS65219_LDOS_BYP_CONFIG_MASK), +}; + +static const struct regulator_desc tps65215_regs[] = { + // TPS65215's LDO2 is the same as TPS65219's LDO3 + TPS65219_REGULATOR("LDO2", "ldo2", TPS65215_LDO_2, + REGULATOR_VOLTAGE, ldos_3_4_ops, 64, + TPS65215_REG_LDO2_VOUT, + TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, + TPS65219_REG_ENABLE_CTRL, + TPS65215_ENABLE_LDO2_EN_MASK, 0, 0, tps65215_ldo_2_range, + 3, 0, 0, NULL, 0, 0), +}; + +static const struct regulator_desc tps65219_regs[] = { TPS65219_REGULATOR("LDO2", "ldo2", TPS65219_LDO_2, REGULATOR_VOLTAGE, ldos_1_2_ops, 64, TPS65219_REG_LDO2_VOUT, @@ -292,28 +310,65 @@ static irqreturn_t tps65219_regulator_irq_handler(int irq, void *data) return IRQ_HANDLED; } +struct tps65219_chip_data { + size_t rdesc_size; + size_t common_rdesc_size; + const struct regulator_desc *rdesc; + const struct regulator_desc *common_rdesc; +}; + +static struct tps65219_chip_data chip_info_table[] = { + [TPS65215] = { + .rdesc = tps65215_regs, + .rdesc_size = ARRAY_SIZE(tps65215_regs), + .common_rdesc = common_regs, + .common_rdesc_size = ARRAY_SIZE(common_regs), + }, + [TPS65219] = { + .rdesc = tps65219_regs, + .rdesc_size = ARRAY_SIZE(tps65219_regs), + .common_rdesc = common_regs, + .common_rdesc_size = ARRAY_SIZE(common_regs), + }, +}; + static int tps65219_regulator_probe(struct platform_device *pdev) { - struct tps65219 *tps = dev_get_drvdata(pdev->dev.parent); + struct tps65219_regulator_irq_data *irq_data; + struct tps65219_regulator_irq_type *irq_type; + + struct tps65219_chip_data *pmic; struct regulator_dev *rdev; - struct regulator_config config = { }; - int i; int error; int irq; - struct tps65219_regulator_irq_data *irq_data; - struct tps65219_regulator_irq_type *irq_type; + int i; + + struct tps65219 *tps = dev_get_drvdata(pdev->dev.parent); + struct regulator_config config = { }; + enum pmic_id chip = platform_get_device_id(pdev)->driver_data; + + pmic = &chip_info_table[chip]; config.dev = tps->dev; config.driver_data = tps; config.regmap = tps->regmap; - for (i = 0; i < ARRAY_SIZE(regulators); i++) { - rdev = devm_regulator_register(&pdev->dev, ®ulators[i], + for (i = 0; i < pmic->common_rdesc_size; i++) { + rdev = devm_regulator_register(&pdev->dev, &pmic->common_rdesc[i], + &config); + if (IS_ERR(rdev)) + return dev_err_probe(tps->dev, PTR_ERR(rdev), + "Failed to register %s regulator\n", + pmic->common_rdesc[i].name); + } + + for (i = 0; i < pmic->rdesc_size; i++) { + rdev = devm_regulator_register(&pdev->dev, &pmic->rdesc[i], &config); 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Wed, 5 Mar 2025 15:03:52 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 5 Mar 2025 15:03:52 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 5 Mar 2025 15:03:52 -0600 Received: from DMZ007XYY.dhcp.ti.com (dmz007xyy.dhcp.ti.com [128.247.29.251]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 525L3peI125160; Wed, 5 Mar 2025 15:03:52 -0600 From: Shree Ramamoorthy To: , , , , , , , , , , , , , CC: , Subject: [PATCH v6 8/9] regulator: tps65219: Add support for TPS65215 Regulator IRQs Date: Wed, 5 Mar 2025 15:03:50 -0600 Message-ID: <20250305210351.249811-9-s-ramamoorthy@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250305210351.249811-1-s-ramamoorthy@ti.com> References: <20250305210351.249811-1-s-ramamoorthy@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Isolate all changes involving regulator IRQ types: - Adding in TPS65215 resources - Organize what resources are common vs device-specific - How the chip_data uses these resource structs - Restructure the probe() for multi-PMIC support. Signed-off-by: Shree Ramamoorthy --- drivers/regulator/tps65219-regulator.c | 68 +++++++++++++++++++------- 1 file changed, 50 insertions(+), 18 deletions(-) diff --git a/drivers/regulator/tps65219-regulator.c b/drivers/regulator/tps65219-regulator.c index 2542ac1453c9..5f5a6f3c950b 100644 --- a/drivers/regulator/tps65219-regulator.c +++ b/drivers/regulator/tps65219-regulator.c @@ -36,6 +36,14 @@ static struct tps65219_regulator_irq_type tps65219_regulator_irq_types[] = { { "LDO4_SCG", "LDO4", "short circuit to ground", REGULATOR_EVENT_REGULATION_OUT }, { "LDO4_OC", "LDO4", "overcurrent", REGULATOR_EVENT_OVER_CURRENT }, { "LDO4_UV", "LDO4", "undervoltage", REGULATOR_EVENT_UNDER_VOLTAGE }, + { "LDO3_RV", "LDO3", "residual voltage", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, + { "LDO4_RV", "LDO4", "residual voltage", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, + { "LDO3_RV_SD", "LDO3", "residual voltage on shutdown", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, + { "LDO4_RV_SD", "LDO4", "residual voltage on shutdown", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, +}; + +/* All of TPS65215's irq types are the same as common_regulator_irq_types */ +static struct tps65219_regulator_irq_type common_regulator_irq_types[] = { { "LDO1_SCG", "LDO1", "short circuit to ground", REGULATOR_EVENT_REGULATION_OUT }, { "LDO1_OC", "LDO1", "overcurrent", REGULATOR_EVENT_OVER_CURRENT }, { "LDO1_UV", "LDO1", "undervoltage", REGULATOR_EVENT_UNDER_VOLTAGE }, @@ -59,8 +67,6 @@ static struct tps65219_regulator_irq_type tps65219_regulator_irq_types[] = { { "BUCK3_RV", "BUCK3", "residual voltage", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, { "LDO1_RV", "LDO1", "residual voltage", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, { "LDO2_RV", "LDO2", "residual voltage", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, - { "LDO3_RV", "LDO3", "residual voltage", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, - { "LDO4_RV", "LDO4", "residual voltage", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, { "BUCK1_RV_SD", "BUCK1", "residual voltage on shutdown", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, { "BUCK2_RV_SD", "BUCK2", "residual voltage on shutdown", @@ -69,8 +75,6 @@ static struct tps65219_regulator_irq_type tps65219_regulator_irq_types[] = { REGULATOR_EVENT_OVER_VOLTAGE_WARN }, { "LDO1_RV_SD", "LDO1", "residual voltage on shutdown", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, { "LDO2_RV_SD", "LDO2", "residual voltage on shutdown", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, - { "LDO3_RV_SD", "LDO3", "residual voltage on shutdown", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, - { "LDO4_RV_SD", "LDO4", "residual voltage on shutdown", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, { "SENSOR_3_WARM", "SENSOR3", "warm temperature", REGULATOR_EVENT_OVER_TEMP_WARN}, { "SENSOR_2_WARM", "SENSOR2", "warm temperature", REGULATOR_EVENT_OVER_TEMP_WARN }, { "SENSOR_1_WARM", "SENSOR1", "warm temperature", REGULATOR_EVENT_OVER_TEMP_WARN }, @@ -264,7 +268,7 @@ static const struct regulator_desc tps65215_regs[] = { TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, TPS65219_REG_ENABLE_CTRL, TPS65215_ENABLE_LDO2_EN_MASK, 0, 0, tps65215_ldo_2_range, - 3, 0, 0, NULL, 0, 0), + 2, 0, 0, NULL, 0, 0), }; static const struct regulator_desc tps65219_regs[] = { @@ -313,8 +317,12 @@ static irqreturn_t tps65219_regulator_irq_handler(int irq, void *data) struct tps65219_chip_data { size_t rdesc_size; size_t common_rdesc_size; + size_t dev_irq_size; + size_t common_irq_size; const struct regulator_desc *rdesc; const struct regulator_desc *common_rdesc; + struct tps65219_regulator_irq_type *irq_types; + struct tps65219_regulator_irq_type *common_irq_types; }; static struct tps65219_chip_data chip_info_table[] = { @@ -323,12 +331,20 @@ static struct tps65219_chip_data chip_info_table[] = { .rdesc_size = ARRAY_SIZE(tps65215_regs), .common_rdesc = common_regs, .common_rdesc_size = ARRAY_SIZE(common_regs), + .irq_types = NULL, + .dev_irq_size = 0, + .common_irq_types = common_regulator_irq_types, + .common_irq_size = ARRAY_SIZE(common_regulator_irq_types), }, [TPS65219] = { .rdesc = tps65219_regs, .rdesc_size = ARRAY_SIZE(tps65219_regs), .common_rdesc = common_regs, .common_rdesc_size = ARRAY_SIZE(common_regs), + .irq_types = tps65219_regulator_irq_types, + .dev_irq_size = ARRAY_SIZE(tps65219_regulator_irq_types), + .common_irq_types = common_regulator_irq_types, + .common_irq_size = ARRAY_SIZE(common_regulator_irq_types), }, }; @@ -336,7 +352,6 @@ static int tps65219_regulator_probe(struct platform_device *pdev) { struct tps65219_regulator_irq_data *irq_data; struct tps65219_regulator_irq_type *irq_type; - struct tps65219_chip_data *pmic; struct regulator_dev *rdev; int error; @@ -371,33 +386,50 @@ static int tps65219_regulator_probe(struct platform_device *pdev) pmic->rdesc[i].name); } - irq_data = devm_kmalloc(tps->dev, - ARRAY_SIZE(tps65219_regulator_irq_types) * - sizeof(struct tps65219_regulator_irq_data), - GFP_KERNEL); + irq_data = devm_kmalloc(tps->dev, pmic->common_irq_size, GFP_KERNEL); if (!irq_data) return -ENOMEM; - for (i = 0; i < ARRAY_SIZE(tps65219_regulator_irq_types); ++i) { - irq_type = &tps65219_regulator_irq_types[i]; - + for (i = 0; i < pmic->common_irq_size; ++i) { + irq_type = &pmic->common_irq_types[i]; irq = platform_get_irq_byname(pdev, irq_type->irq_name); if (irq < 0) return -EINVAL; irq_data[i].dev = tps->dev; irq_data[i].type = irq_type; + error = devm_request_threaded_irq(tps->dev, irq, NULL, + tps65219_regulator_irq_handler, + IRQF_ONESHOT, + irq_type->irq_name, + &irq_data[i]); + if (error) + return dev_err_probe(tps->dev, PTR_ERR(rdev), + "Failed to request %s IRQ %d: %d\n", + irq_type->irq_name, irq, error); + } + + irq_data = devm_kmalloc(tps->dev, pmic->dev_irq_size, GFP_KERNEL); + if (!irq_data) + return -ENOMEM; + for (i = 0; i < pmic->dev_irq_size; ++i) { + irq_type = &pmic->irq_types[i]; + irq = platform_get_irq_byname(pdev, irq_type->irq_name); + if (irq < 0) + return -EINVAL; + + irq_data[i].dev = tps->dev; + irq_data[i].type = irq_type; error = devm_request_threaded_irq(tps->dev, irq, NULL, tps65219_regulator_irq_handler, IRQF_ONESHOT, irq_type->irq_name, &irq_data[i]); - if (error) { - dev_err(tps->dev, "failed to request %s IRQ %d: %d\n", - irq_type->irq_name, irq, error); - return error; - } + if (error) + return dev_err_probe(tps->dev, PTR_ERR(rdev), + "Failed to request %s IRQ %d: %d\n", + irq_type->irq_name, irq, error); } return 0; From patchwork Wed Mar 5 21:03:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shree Ramamoorthy X-Patchwork-Id: 871047 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FCEB1DA53; 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Wed, 5 Mar 2025 15:03:52 -0600 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 5 Mar 2025 15:03:52 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 5 Mar 2025 15:03:52 -0600 Received: from DMZ007XYY.dhcp.ti.com (dmz007xyy.dhcp.ti.com [128.247.29.251]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 525L3peJ125160; Wed, 5 Mar 2025 15:03:52 -0600 From: Shree Ramamoorthy To: , , , , , , , , , , , , , CC: , Subject: [PATCH v6 9/9] regulator: tps65219: Add TI TPS65214 Regulator Support Date: Wed, 5 Mar 2025 15:03:51 -0600 Message-ID: <20250305210351.249811-10-s-ramamoorthy@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250305210351.249811-1-s-ramamoorthy@ti.com> References: <20250305210351.249811-1-s-ramamoorthy@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Add support for TPS65214 regulators (bucks and LDOs) to the TPS65219 Regulator Driver as the TPS65214/TPS65214/TPS65219 PMIC devices have significant register map overlap. TPS65214 is a Power Management IC with 3 Buck regulators (like TPS65215/TPS65219) and has 2 LDOs (like TPS65215). Signed-off-by: Shree Ramamoorthy --- drivers/regulator/Kconfig | 9 +++- drivers/regulator/tps65219-regulator.c | 73 ++++++++++++++++++++++---- 2 files changed, 69 insertions(+), 13 deletions(-) diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 6cd87443f9bb..3a694945739c 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -1579,11 +1579,16 @@ config REGULATOR_TPS65219 tristate "TI TPS65219 Power regulators" depends on MFD_TPS65219 && OF help - This driver supports TPS65219 series and TPS65215 voltage regulator chips. + This driver supports TPS65219, TPS65215, and TPS65214 voltage + regulator chips. TPS65219 series of PMICs have 3 single phase BUCKs & 4 LDOs voltage regulators. TPS65215 PMIC has 3 single phase BUCKs & 2 LDOs. - Both PMICs support software based voltage control for different voltage domains. + TPS65214 PMIC has 3 synchronous stepdown DC-DC converters & 2 + LDOs. One LDO supports a maximum output current of 300 mA and the + other a maximum of 500 mA + All 3 PMICs support software based voltage control for different + voltage domains. config REGULATOR_TPS6594 tristate "TI TPS6594 Power regulators" diff --git a/drivers/regulator/tps65219-regulator.c b/drivers/regulator/tps65219-regulator.c index 5f5a6f3c950b..241a7e841d35 100644 --- a/drivers/regulator/tps65219-regulator.c +++ b/drivers/regulator/tps65219-regulator.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 // -// Regulator driver for TPS65215/TPS65219 PMIC +// TPS65214/TPS65215/TPS65219 PMIC Regulator Driver // // Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/ // Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ @@ -29,6 +29,11 @@ struct tps65219_regulator_irq_type { unsigned long event; }; +static struct tps65219_regulator_irq_type tps65215_regulator_irq_types[] = { + { "SENSOR_3_WARM", "SENSOR3", "warm temperature", REGULATOR_EVENT_OVER_TEMP_WARN}, + { "SENSOR_3_HOT", "SENSOR3", "hot temperature", REGULATOR_EVENT_OVER_TEMP}, +}; + static struct tps65219_regulator_irq_type tps65219_regulator_irq_types[] = { { "LDO3_SCG", "LDO3", "short circuit to ground", REGULATOR_EVENT_REGULATION_OUT }, { "LDO3_OC", "LDO3", "overcurrent", REGULATOR_EVENT_OVER_CURRENT }, @@ -40,9 +45,11 @@ static struct tps65219_regulator_irq_type tps65219_regulator_irq_types[] = { { "LDO4_RV", "LDO4", "residual voltage", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, { "LDO3_RV_SD", "LDO3", "residual voltage on shutdown", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, { "LDO4_RV_SD", "LDO4", "residual voltage on shutdown", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, + { "SENSOR_3_WARM", "SENSOR3", "warm temperature", REGULATOR_EVENT_OVER_TEMP_WARN}, + { "SENSOR_3_HOT", "SENSOR3", "hot temperature", REGULATOR_EVENT_OVER_TEMP}, }; -/* All of TPS65215's irq types are the same as common_regulator_irq_types */ +/* All of TPS65214's irq types are the same as common_regulator_irq_types */ static struct tps65219_regulator_irq_type common_regulator_irq_types[] = { { "LDO1_SCG", "LDO1", "short circuit to ground", REGULATOR_EVENT_REGULATION_OUT }, { "LDO1_OC", "LDO1", "overcurrent", REGULATOR_EVENT_OVER_CURRENT }, @@ -75,11 +82,9 @@ static struct tps65219_regulator_irq_type common_regulator_irq_types[] = { REGULATOR_EVENT_OVER_VOLTAGE_WARN }, { "LDO1_RV_SD", "LDO1", "residual voltage on shutdown", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, { "LDO2_RV_SD", "LDO2", "residual voltage on shutdown", REGULATOR_EVENT_OVER_VOLTAGE_WARN }, - { "SENSOR_3_WARM", "SENSOR3", "warm temperature", REGULATOR_EVENT_OVER_TEMP_WARN}, { "SENSOR_2_WARM", "SENSOR2", "warm temperature", REGULATOR_EVENT_OVER_TEMP_WARN }, { "SENSOR_1_WARM", "SENSOR1", "warm temperature", REGULATOR_EVENT_OVER_TEMP_WARN }, { "SENSOR_0_WARM", "SENSOR0", "warm temperature", REGULATOR_EVENT_OVER_TEMP_WARN }, - { "SENSOR_3_HOT", "SENSOR3", "hot temperature", REGULATOR_EVENT_OVER_TEMP}, { "SENSOR_2_HOT", "SENSOR2", "hot temperature", REGULATOR_EVENT_OVER_TEMP }, { "SENSOR_1_HOT", "SENSOR1", "hot temperature", REGULATOR_EVENT_OVER_TEMP }, { "SENSOR_0_HOT", "SENSOR0", "hot temperature", REGULATOR_EVENT_OVER_TEMP }, @@ -133,6 +138,12 @@ static const struct linear_range ldo_1_range[] = { REGULATOR_LINEAR_RANGE(3400000, 0x38, 0x3f, 0), }; +static const struct linear_range tps65214_ldo_1_2_range[] = { + REGULATOR_LINEAR_RANGE(600000, 0x0, 0x2, 0), + REGULATOR_LINEAR_RANGE(650000, 0x3, 0x37, 50000), + REGULATOR_LINEAR_RANGE(3300000, 0x38, 0x3F, 0), +}; + static const struct linear_range tps65215_ldo_2_range[] = { REGULATOR_LINEAR_RANGE(1200000, 0x0, 0xC, 50000), REGULATOR_LINEAR_RANGE(3300000, 0x36, 0x3F, 0), @@ -251,6 +262,32 @@ static const struct regulator_desc common_regs[] = { TPS65219_REG_ENABLE_CTRL, TPS65219_ENABLE_BUCK3_EN_MASK, 0, 0, bucks_ranges, 3, 0, 0, NULL, 0, 0), +}; + +static const struct regulator_desc tps65214_regs[] = { + // TPS65214's LDO3 pin maps to TPS65219's LDO3 pin + TPS65219_REGULATOR("LDO1", "ldo1", TPS65214_LDO_1, + REGULATOR_VOLTAGE, ldos_3_4_ops, 64, + TPS65214_REG_LDO1_VOUT, + TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, + TPS65219_REG_ENABLE_CTRL, + TPS65219_ENABLE_LDO3_EN_MASK, 0, 0, tps65214_ldo_1_2_range, + 3, 0, 0, NULL, 0, 0), + TPS65219_REGULATOR("LDO2", "ldo2", TPS65214_LDO_2, + REGULATOR_VOLTAGE, ldos_3_4_ops, 64, + TPS65214_REG_LDO2_VOUT, + TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, + TPS65219_REG_ENABLE_CTRL, + TPS65219_ENABLE_LDO2_EN_MASK, 0, 0, tps65214_ldo_1_2_range, + 3, 0, 0, NULL, 0, 0), +}; + +static const struct regulator_desc tps65215_regs[] = { + /* + * TPS65215's LDO1 is the same as TPS65219's LDO1. LDO1 is + * configurable as load switch and bypass-mode. + * TPS65215's LDO2 is the same as TPS65219's LDO3 + */ TPS65219_REGULATOR("LDO1", "ldo1", TPS65219_LDO_1, REGULATOR_VOLTAGE, ldos_1_2_ops, 64, TPS65219_REG_LDO1_VOUT, @@ -258,10 +295,6 @@ static const struct regulator_desc common_regs[] = { TPS65219_REG_ENABLE_CTRL, TPS65219_ENABLE_LDO1_EN_MASK, 0, 0, ldo_1_range, 2, 0, 0, NULL, 0, TPS65219_LDOS_BYP_CONFIG_MASK), -}; - -static const struct regulator_desc tps65215_regs[] = { - // TPS65215's LDO2 is the same as TPS65219's LDO3 TPS65219_REGULATOR("LDO2", "ldo2", TPS65215_LDO_2, REGULATOR_VOLTAGE, ldos_3_4_ops, 64, TPS65215_REG_LDO2_VOUT, @@ -272,6 +305,13 @@ static const struct regulator_desc tps65215_regs[] = { }; static const struct regulator_desc tps65219_regs[] = { + TPS65219_REGULATOR("LDO1", "ldo1", TPS65219_LDO_1, + REGULATOR_VOLTAGE, ldos_1_2_ops, 64, + TPS65219_REG_LDO1_VOUT, + TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, + TPS65219_REG_ENABLE_CTRL, + TPS65219_ENABLE_LDO1_EN_MASK, 0, 0, ldo_1_range, + 2, 0, 0, NULL, 0, TPS65219_LDOS_BYP_CONFIG_MASK), TPS65219_REGULATOR("LDO2", "ldo2", TPS65219_LDO_2, REGULATOR_VOLTAGE, ldos_1_2_ops, 64, TPS65219_REG_LDO2_VOUT, @@ -326,13 +366,23 @@ struct tps65219_chip_data { }; static struct tps65219_chip_data chip_info_table[] = { + [TPS65214] = { + .rdesc = tps65214_regs, + .rdesc_size = ARRAY_SIZE(tps65214_regs), + .common_rdesc = common_regs, + .common_rdesc_size = ARRAY_SIZE(common_regs), + .irq_types = NULL, + .dev_irq_size = 0, + .common_irq_types = common_regulator_irq_types, + .common_irq_size = ARRAY_SIZE(common_regulator_irq_types), + }, [TPS65215] = { .rdesc = tps65215_regs, .rdesc_size = ARRAY_SIZE(tps65215_regs), .common_rdesc = common_regs, .common_rdesc_size = ARRAY_SIZE(common_regs), - .irq_types = NULL, - .dev_irq_size = 0, + .irq_types = tps65215_regulator_irq_types, + .dev_irq_size = ARRAY_SIZE(tps65215_regulator_irq_types), .common_irq_types = common_regulator_irq_types, .common_irq_size = ARRAY_SIZE(common_regulator_irq_types), }, @@ -436,6 +486,7 @@ static int tps65219_regulator_probe(struct platform_device *pdev) } static const struct platform_device_id tps65219_regulator_id_table[] = { + { "tps65214-regulator", TPS65214 }, { "tps65215-regulator", TPS65215 }, { "tps65219-regulator", TPS65219 }, { /* sentinel */ } @@ -454,5 +505,5 @@ static struct platform_driver tps65219_regulator_driver = { module_platform_driver(tps65219_regulator_driver); MODULE_AUTHOR("Jerome Neanne "); -MODULE_DESCRIPTION("TPS65215/TPS65219 voltage regulator driver"); +MODULE_DESCRIPTION("TPS65214/TPS65215/TPS65219 Regulator driver"); MODULE_LICENSE("GPL");