From patchwork Mon Mar 2 17:58:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 184098 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp2683828ile; Mon, 2 Mar 2020 10:02:12 -0800 (PST) X-Google-Smtp-Source: ADFU+vsmNYAtKOpfWWltZnVsmQ9t4sb+lP416gZv08lMyl7q5KqbMSslYfWjOZ4Fbs4qzYVxE6cW X-Received: by 2002:a37:341:: with SMTP id 62mr405433qkd.335.1583172132435; Mon, 02 Mar 2020 10:02:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583172132; cv=none; d=google.com; s=arc-20160816; b=LDDzE5t1DFFJTuEbUW1SFShlXqaoNybiuFCfE3ocD8U+rIldL4lZ4NnXzN35zuapPj tplVebQzCc/Obr1NMumZb0gCrlAXGlY2VrYThazYgS74/Vf+r88Kzo0zAy9eSMJaHL68 WiDDDVd2OshKGcluFRjHnE/Qlv4VT6hljvqmx4a12csPl1XC+K6l7AaTUXVslh5rNurx ooqss+hi/aT5yDC8Mz+ru2CZertpkWzsS7ll3Jygoodlw7JDQrqwas6ly7xEwBDueU8t cuGDMnwhlqtyZV4vGDJ9G5lRUPj1gY2qDm9qFWb6HCXn62h9t1FFDgmIYp8H2v9xD/jZ bZtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SmyuQTNOfGklwQG6G7fcasvxH7i/TWvMZQATgc7JYwI=; b=zrvkJ3txCodphZzRXKx9PmtkzfPeqib2pVK5bDbl4EJ1Hs/UzV61JiB06lnIFFg+qh hPy0zjudFEOTlL9bxtXRm1U4smHWCZqdbbjfnYISPpGpKPmTgGX8h4XZHAkHikOzXrsC 41jhjdhrOmi8s/UWznn+dXmE8cQ63fhk00xklhP2AznMrMHVbfw2hTJvLC0VaOz+IvDN T2kNFHII6jJFXYbqEo74iO4YRGkzmE2mIdHvWRf0XBoxjhsvMIpUCeymLGvAQFVmLtTm ijaMBOLP2r8LkPct/CTYgJlHlBIhUpuDjs+ehDSvpDSO+0BvrOPlsV2qolxReKQO24g1 4gFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E5zlf7qR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id s18sm99510pjp.24.2020.03.02.09.58.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Mar 2020 09:58:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 1/9] target/arm: Replicate TBI/TBID bits for single range regimes Date: Mon, 2 Mar 2020 09:58:21 -0800 Message-Id: <20200302175829.2183-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200302175829.2183-1-richard.henderson@linaro.org> References: <20200302175829.2183-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1044 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Replicate the single TBI bit from TCR_EL2 and TCR_EL3 so that we can unconditionally use pointer bit 55 to index into our composite TBI1:TBI0 field. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/helper.c b/target/arm/helper.c index 6be9ffa09e..37ffe06c05 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10316,7 +10316,8 @@ static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) } else if (mmu_idx == ARMMMUIdx_Stage2) { return 0; /* VTCR_EL2 */ } else { - return extract32(tcr, 20, 1); + /* Replicate the single TBI bit so we always have 2 bits. */ + return extract32(tcr, 20, 1) * 3; } } @@ -10327,7 +10328,8 @@ static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) } else if (mmu_idx == ARMMMUIdx_Stage2) { return 0; /* VTCR_EL2 */ } else { - return extract32(tcr, 29, 1); + /* Replicate the single TBID bit so we always have 2 bits. */ + return extract32(tcr, 29, 1) * 3; } } From patchwork Mon Mar 2 17:58:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 184101 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp2685630ile; Mon, 2 Mar 2020 10:03:35 -0800 (PST) X-Google-Smtp-Source: ADFU+vuZT20NijU8TPizl1AaNCZV+LKwxlppO01wjKoUWl+C0AjrS7PhO+B1i41LshmncGgUWth5 X-Received: by 2002:a05:620a:94e:: with SMTP id w14mr423248qkw.277.1583172215536; Mon, 02 Mar 2020 10:03:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583172215; cv=none; d=google.com; s=arc-20160816; b=K4P35rnPnu4o7WindBSjP4g7b+8K1JmXCTpcJ9o852Hwa1WHGDihqcTiRs17Nl4uPf ODwXaihlTyhH4ZACMLunGhrsPu3hdAUr8ipysIWOp/x8Fsa+HCE0/UkPItlPVFDfzXnq IBuJ3lO8e55+PYlVgVm8KGdQtfY6uYyE+fVzCc5pUhXFy3OQbcSGAH5hNpxfkJOIn+Pw 4sr5tuBwMP17bvzBY0hRgIgY600fwpV6567mZy1Sw9yOOjJv1e8rheuEOwGEM1LnsSAE 5ZdtvNBapwwFtH7pHf030sUwsecdw0N6tUDbX678WzgEagGDE3DIC517KApn32l+3sAz aRrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nnZb8apL5HPwafrnPocDxPavn/5fOqQOkEGFTZ+nDV0=; b=Wh3P9lglVGh19vyTO2dfuHtAYvoi19G6PFmjZZR/T5xY/3i1l47t9GO0n6zqC4ogn/ HTqP1+jGYd1dX77aj9UG1YC5guk5EIOZi1V8Es8JkXwi+ylQ5AT02jqusiBv6/8SeM+W 9PU/x4R7rg7aK9RZbqvbuPSaDR6XvZYxfMjNOtEY/P6XzR3oxpr+dgPv/skhrToNQtmn xqgecft0gxDBsObVyj+QQk1nD3XDaJaCrgrndsjzvPBUPVFA4bKCHqYacyR2dWdBcQVw 6EBZpwLVgLyfq6EghAxG/vBy8cvC0be68qeCBqjBZt2aIdqyxOPke+gJq0ciJ79P6Erd 8yvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VhZvQJ5+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id s18sm99510pjp.24.2020.03.02.09.58.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Mar 2020 09:58:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 2/9] target/arm: Optimize cpu_mmu_index Date: Mon, 2 Mar 2020 09:58:22 -0800 Message-Id: <20200302175829.2183-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200302175829.2183-1-richard.henderson@linaro.org> References: <20200302175829.2183-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We now cache the core mmu_idx in env->hflags. Rather than recompute from scratch, extract the field. All of the uses of cpu_mmu_index within target/arm are within helpers, and env->hflags is always stable within a translation block from whence helpers are called. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 23 +++++++++++++---------- target/arm/helper.c | 5 ----- 2 files changed, 13 insertions(+), 15 deletions(-) -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0b84742b66..8f1b949c88 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2936,16 +2936,6 @@ typedef enum ARMMMUIdxBit { #define MMU_USER_IDX 0 -/** - * cpu_mmu_index: - * @env: The cpu environment - * @ifetch: True for code access, false for data access. - * - * Return the core mmu index for the current translation regime. - * This function is used by generic TCG code paths. - */ -int cpu_mmu_index(CPUARMState *env, bool ifetch); - /* Indexes used when registering address spaces with cpu_address_space_init */ typedef enum ARMASIdx { ARMASIdx_NS = 0, @@ -3225,6 +3215,19 @@ FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ FIELD(TBFLAG_A64, TBID, 12, 2) FIELD(TBFLAG_A64, UNPRIV, 14, 1) +/** + * cpu_mmu_index: + * @env: The cpu environment + * @ifetch: True for code access, false for data access. + * + * Return the core mmu index for the current translation regime. + * This function is used by generic TCG code paths. + */ +static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX); +} + static inline bool bswap_code(bool sctlr_b) { #ifdef CONFIG_USER_ONLY diff --git a/target/arm/helper.c b/target/arm/helper.c index 37ffe06c05..addbec91d8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12128,11 +12128,6 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) return arm_mmu_idx_el(env, arm_current_el(env)); } -int cpu_mmu_index(CPUARMState *env, bool ifetch) -{ - return arm_to_core_mmu_idx(arm_mmu_idx(env)); -} - #ifndef CONFIG_USER_ONLY ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) { From patchwork Mon Mar 2 17:58:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 184102 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp2685849ile; Mon, 2 Mar 2020 10:03:45 -0800 (PST) X-Google-Smtp-Source: ADFU+vtULaByaA0wP6KuZddMgaXb1Vbn0zZEj2WaTtylV4kvrhGbjU+Tp+ah1yL7Ds3h+WIckLwc X-Received: by 2002:ac8:6d10:: with SMTP id o16mr891667qtt.308.1583172225361; Mon, 02 Mar 2020 10:03:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583172225; cv=none; d=google.com; s=arc-20160816; b=Wsl1N6otHzqYInstkZ1sHO89iQcMkdDGNkKAtqbfmFYU9xyhJtzZBi0ynJbGdTyKdu ZDslA3mqAHQSu+9ubg5CDeHiUcuhx+zH86hAFNQJw6A6rkVSTvwN8x6JRfsbv+GcfRaQ JMFwL+2K3Mt4XdqEqRGV697rce0J9+UQ+tvEvw0Da649KNfZpIJv1/HjnSKFYQrMXOtp ftlL+oLXXwlwdHWYF3yuxyJU33hxPpaFlBw3AqYX7ggoqrFUBIonyZWJa4faSngRtMhx Im6AntZUqry+X23LOytB+zliplkpKytQrkPPh03oRNQtoyTAzcX61UJTTsVjtscsGk48 fBYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=d7ojpguKqQxB+IoLGq/8Ijh0sitkQS0XaFUwvCJstUc=; b=OFyDES3X8DFzsQH9YM+E/EYcZ2NtGaUsBcGTgo5pkR7ZzIN+eNOxAgxQ0xHNI4lq9c zvZ7jPN9jv5cyZK/i8Akm7F9OE2i+qtXHR7AxG6Ftz8Mb+2MJ1bxyczIcnch8o8Ic8/E idYqgewsrL67dmR4+tRoMqbwbcABKxmreYpb3ax2TcF8t7ggqLU9A/DdAoF+4nEqxU4Q ELMgby5CVbYtOmEIscnQahb+32MBKTnaSYRef1XFNgUdXmUy3JxltuLOs+mjZdMiwYLf qfR0f9+pfGTC4TTAY53wjWXg29j90NfghCw+ppb+/F2gt6TublxD1G5IGkHxv8QmfDI6 /A0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=siSkGF2u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id s18sm99510pjp.24.2020.03.02.09.58.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Mar 2020 09:58:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 3/9] target/arm: Introduce core_to_aa64_mmu_idx Date: Mon, 2 Mar 2020 09:58:23 -0800 Message-Id: <20200302175829.2183-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200302175829.2183-1-richard.henderson@linaro.org> References: <20200302175829.2183-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" If by context we know that we're in AArch64 mode, we need not test for M-profile when reconstructing the full ARMMMUIdx. Signed-off-by: Richard Henderson --- target/arm/internals.h | 6 ++++++ target/arm/translate-a64.c | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index 9f96a2359f..e633aff36e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -783,6 +783,12 @@ static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) } } +static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) +{ + /* AArch64 is always a-profile. */ + return mmu_idx | ARM_MMU_IDX_A; +} + int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 579180af0a..c910a49b4e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14300,7 +14300,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->condexec_mask = 0; dc->condexec_cond = 0; core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); - dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx); + dc->mmu_idx = core_to_aa64_mmu_idx(core_mmu_idx); dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII); dc->tbid = FIELD_EX32(tb_flags, TBFLAG_A64, TBID); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); From patchwork Mon Mar 2 17:58:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 184097 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp2680438ile; Mon, 2 Mar 2020 09:59:17 -0800 (PST) X-Google-Smtp-Source: ADFU+vtyQhWADphvhrirHPuGHuR1Xd1tN4Jg94/B13lPOAra2mFp5ZVA/a2+6VR52244Z/U1SA4L X-Received: by 2002:a05:620a:10b3:: with SMTP id h19mr446673qkk.440.1583171956976; Mon, 02 Mar 2020 09:59:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583171956; cv=none; d=google.com; s=arc-20160816; b=pf2EEBb1kzIvhDbqzFDHKrdNhoKZSfAoKttytIRUpnvtxZoL84jD76/FP/l77cq29n XFN7oDReiRSXew0wLQbuHk6gEgad37GaszT/M/w0gMYISgms6uCg1MtYSVFTVaWOjnDT pisy9r/cjd8qzRe/xFcO1lfxHHCc665bvr1M26C/EqQ0tExZT58L7xznU1omToK2Uj+k yVp3/hBibDexVzu7nJTl7X0+lw0yJvJT8tSaDgtmkfzqbxYuSWTyhg7eul8xubbqFNy/ t8psOa8pP2GtxKsyKOSE0iHrPEPY1WafK5ldy7FTfT1bu0KwvgVl2ccLmrwwM7GVRCsy PBxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Xb4MZkBU7c3SsPvbbpOINi23WCHWKuPEyPWHI7rJrJg=; b=sHQoySBjIPH2o9mt0ELSxtNmOT7+QfmvqN7G6Og6+cqbE3C+W+NWbDujrKPz4LKt5+ 4MtTXZP9q1DYPT/IybFHnnRDiMA94FxLe9xDoSY11bdjlBs2fpwRABT1tDvzIG35whim YgSRZ7YhSgUJwvqI3bBiarmFV8Bp0QzmRKJo6DGtoHVZkfrCakSQmL1arXyHRSSyNVY1 yycvGEx3uZACOFT5j+CZAnJbv94gJA8QaKlJ6tYhEHclaOVEkjvLieYLLUUTReYdNjmI xIwOtCMVczMaurRKqXG7i9bSAw2q3ZpgB3fU6yAIHnf0fn+/vXG6jmQ/YnlswTXqEDej 7qHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lzo2x0RU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id s18sm99510pjp.24.2020.03.02.09.58.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Mar 2020 09:58:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 4/9] target/arm: Apply TBI to ESR_ELx in helper_exception_return Date: Mon, 2 Mar 2020 09:58:24 -0800 Message-Id: <20200302175829.2183-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200302175829.2183-1-richard.henderson@linaro.org> References: <20200302175829.2183-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We missed this case within AArch64.ExceptionReturn. Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 509ae93069..123ce50e7a 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1031,6 +1031,8 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) "AArch32 EL%d PC 0x%" PRIx32 "\n", cur_el, new_el, env->regs[15]); } else { + int tbii; + env->aarch64 = 1; spsr &= aarch64_pstate_valid_mask(&env_archcpu(env)->isar); pstate_write(env, spsr); @@ -1038,8 +1040,27 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) env->pstate &= ~PSTATE_SS; } aarch64_restore_sp(env, new_el); - env->pc = new_pc; helper_rebuild_hflags_a64(env, new_el); + + /* + * Apply TBI to the exception return address. We had to delay this + * until after we selected the new EL, so that we could select the + * correct TBI+TBID bits. This is made easier by waiting until after + * the hflags rebuild, since we can pull the composite TBII field + * from there. + */ + tbii = FIELD_EX32(env->hflags, TBFLAG_A64, TBII); + if ((tbii >> extract64(new_pc, 55, 1)) & 1) { + /* TBI is enabled. */ + int core_mmu_idx = cpu_mmu_index(env, false); + if (regime_has_2_ranges(core_to_aa64_mmu_idx(core_mmu_idx))) { + new_pc = sextract64(new_pc, 0, 56); + } else { + new_pc = extract64(new_pc, 0, 56); + } + } + env->pc = new_pc; + qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); From patchwork Mon Mar 2 17:58:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 184094 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp2680216ile; Mon, 2 Mar 2020 09:58:59 -0800 (PST) X-Google-Smtp-Source: ADFU+vvYt4sPIrbGl8vEoVlwiviySQ5tPab1vFXrACWQn+vjZwqXQZx1CmKplUB3E3EIuDVU+oB/ X-Received: by 2002:a37:6115:: with SMTP id v21mr427617qkb.105.1583171938908; Mon, 02 Mar 2020 09:58:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583171938; cv=none; d=google.com; s=arc-20160816; b=qTgcO6J2ge1uF5raBiMzoNZe6UqaW3LWKNKoIFhZHNQHkPY/aluT590wvzq52G/M0i 22UmugAeL9bRxVPfyLu4lPOxJ8tGK10y22oOSgkUNUlL+T+ERK9TSzSy8Jnoeqd8BS8t pDM0gsWu22iFA73kDtQrar7TEQTXa3Mxqi/1JyTg0CDbqjRJESGsaqZpd/5Oq9L7tket s0/KwfNm32xwoNgRz31KNaEdYEDGpYObJEqa/4rgmiyjWcTlnX+Fvfj+s6giZu8oNAnK 2FJvrmRWPffdEcKUoHWz7QJt86dw2Zr+fXiP4BMsCUKsLdDoja2nF1pTdWpsmAD4RaMR J1zA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5BCED//Us3kOSOmLoxSaLt6O1uc8TXSY7MgfQybd348=; b=LoKxuDYEHMaG6bWpNIiF3K9bRYx9EmlGdwZYhur/P+YiK+7TuBXwPD4zd/8Z39ocPs M0R6SI19G8nCCbVo9ES258Zg66IfguWiUN87WYTxiTf+JXpIbd+ZPq9kuKOmk0W6IK18 RMNW/MZZ/K1K92uh7z81+9oDIYNVX9cx19jnQbJJJH+qdwKfHvlTdwgfqlGFlB2nTrUq 7Vtgdr2SU5HA4WwrivXtS7Lka3f+MljdQVyMZFVoivSoRd29Nu0E52LM9tzjliNGE4DL EyUFMXbpZeRT8LclvnuCAnvbM8NWbnelphsk5+FGj4zUeEdOORPxbq4uHEDn/2Js69/0 gesA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="wMa5i/Yv"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id s18sm99510pjp.24.2020.03.02.09.58.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Mar 2020 09:58:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 5/9] target/arm: Move helper_dc_zva to helper-a64.c Date: Mon, 2 Mar 2020 09:58:25 -0800 Message-Id: <20200302175829.2183-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200302175829.2183-1-richard.henderson@linaro.org> References: <20200302175829.2183-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::629 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is an aarch64-only function. Move it out of the shared file. This patch is code movement only. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 1 + target/arm/helper.h | 1 - target/arm/helper-a64.c | 91 ++++++++++++++++++++++++++++++++++++++++ target/arm/op_helper.c | 93 ----------------------------------------- 4 files changed, 92 insertions(+), 94 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index a915c1247f..b1a5935f61 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -90,6 +90,7 @@ DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) DEF_HELPER_2(sqrt_f16, f16, f16, ptr) DEF_HELPER_2(exception_return, void, env, i64) +DEF_HELPER_2(dc_zva, void, env, i64) DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/arm/helper.h b/target/arm/helper.h index fcbf504121..72eb9e6a1a 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -559,7 +559,6 @@ DEF_HELPER_FLAGS_3(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) -DEF_HELPER_2(dc_zva, void, env, i64) DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 123ce50e7a..bc0649a44a 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "cpu.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" @@ -1109,4 +1110,94 @@ uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp) return float16_sqrt(a, s); } +void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) +{ + /* + * Implement DC ZVA, which zeroes a fixed-length block of memory. + * Note that we do not implement the (architecturally mandated) + * alignment fault for attempts to use this on Device memory + * (which matches the usual QEMU behaviour of not implementing either + * alignment faults or any memory attribute handling). + */ + ARMCPU *cpu = env_archcpu(env); + uint64_t blocklen = 4 << cpu->dcz_blocksize; + uint64_t vaddr = vaddr_in & ~(blocklen - 1); + +#ifndef CONFIG_USER_ONLY + { + /* + * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than + * the block size so we might have to do more than one TLB lookup. + * We know that in fact for any v8 CPU the page size is at least 4K + * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only + * 1K as an artefact of legacy v5 subpage support being present in the + * same QEMU executable. So in practice the hostaddr[] array has + * two entries, given the current setting of TARGET_PAGE_BITS_MIN. + */ + int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); + void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)]; + int try, i; + unsigned mmu_idx = cpu_mmu_index(env, false); + TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); + + assert(maxidx <= ARRAY_SIZE(hostaddr)); + + for (try = 0; try < 2; try++) { + + for (i = 0; i < maxidx; i++) { + hostaddr[i] = tlb_vaddr_to_host(env, + vaddr + TARGET_PAGE_SIZE * i, + 1, mmu_idx); + if (!hostaddr[i]) { + break; + } + } + if (i == maxidx) { + /* + * If it's all in the TLB it's fair game for just writing to; + * we know we don't need to update dirty status, etc. + */ + for (i = 0; i < maxidx - 1; i++) { + memset(hostaddr[i], 0, TARGET_PAGE_SIZE); + } + memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); + return; + } + /* + * OK, try a store and see if we can populate the tlb. This + * might cause an exception if the memory isn't writable, + * in which case we will longjmp out of here. We must for + * this purpose use the actual register value passed to us + * so that we get the fault address right. + */ + helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); + /* Now we can populate the other TLB entries, if any */ + for (i = 0; i < maxidx; i++) { + uint64_t va = vaddr + TARGET_PAGE_SIZE * i; + if (va != (vaddr_in & TARGET_PAGE_MASK)) { + helper_ret_stb_mmu(env, va, 0, oi, GETPC()); + } + } + } + + /* + * Slow path (probably attempt to do this to an I/O device or + * similar, or clearing of a block of code we have translations + * cached for). Just do a series of byte writes as the architecture + * demands. It's not worth trying to use a cpu_physical_memory_map(), + * memset(), unmap() sequence here because: + * + we'd need to account for the blocksize being larger than a page + * + the direct-RAM access case is almost always going to be dealt + * with in the fastpath code above, so there's no speed benefit + * + we would have to deal with the map returning NULL because the + * bounce buffer was in use + */ + for (i = 0; i < blocklen; i++) { + helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); + } + } +#else + memset(g2h(vaddr), 0, blocklen); +#endif +} diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index af3020b78f..eb0de080f1 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -17,7 +17,6 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" -#include "qemu/units.h" #include "qemu/log.h" #include "qemu/main-loop.h" #include "cpu.h" @@ -936,95 +935,3 @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i) return ((uint32_t)x >> shift) | (x << (32 - shift)); } } - -void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) -{ - /* - * Implement DC ZVA, which zeroes a fixed-length block of memory. - * Note that we do not implement the (architecturally mandated) - * alignment fault for attempts to use this on Device memory - * (which matches the usual QEMU behaviour of not implementing either - * alignment faults or any memory attribute handling). - */ - - ARMCPU *cpu = env_archcpu(env); - uint64_t blocklen = 4 << cpu->dcz_blocksize; - uint64_t vaddr = vaddr_in & ~(blocklen - 1); - -#ifndef CONFIG_USER_ONLY - { - /* - * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than - * the block size so we might have to do more than one TLB lookup. - * We know that in fact for any v8 CPU the page size is at least 4K - * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only - * 1K as an artefact of legacy v5 subpage support being present in the - * same QEMU executable. So in practice the hostaddr[] array has - * two entries, given the current setting of TARGET_PAGE_BITS_MIN. - */ - int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); - void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)]; - int try, i; - unsigned mmu_idx = cpu_mmu_index(env, false); - TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); - - assert(maxidx <= ARRAY_SIZE(hostaddr)); - - for (try = 0; try < 2; try++) { - - for (i = 0; i < maxidx; i++) { - hostaddr[i] = tlb_vaddr_to_host(env, - vaddr + TARGET_PAGE_SIZE * i, - 1, mmu_idx); - if (!hostaddr[i]) { - break; - } - } - if (i == maxidx) { - /* - * If it's all in the TLB it's fair game for just writing to; - * we know we don't need to update dirty status, etc. - */ - for (i = 0; i < maxidx - 1; i++) { - memset(hostaddr[i], 0, TARGET_PAGE_SIZE); - } - memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); - return; - } - /* - * OK, try a store and see if we can populate the tlb. This - * might cause an exception if the memory isn't writable, - * in which case we will longjmp out of here. We must for - * this purpose use the actual register value passed to us - * so that we get the fault address right. - */ - helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); - /* Now we can populate the other TLB entries, if any */ - for (i = 0; i < maxidx; i++) { - uint64_t va = vaddr + TARGET_PAGE_SIZE * i; - if (va != (vaddr_in & TARGET_PAGE_MASK)) { - helper_ret_stb_mmu(env, va, 0, oi, GETPC()); - } - } - } - - /* - * Slow path (probably attempt to do this to an I/O device or - * similar, or clearing of a block of code we have translations - * cached for). Just do a series of byte writes as the architecture - * demands. It's not worth trying to use a cpu_physical_memory_map(), - * memset(), unmap() sequence here because: - * + we'd need to account for the blocksize being larger than a page - * + the direct-RAM access case is almost always going to be dealt - * with in the fastpath code above, so there's no speed benefit - * + we would have to deal with the map returning NULL because the - * bounce buffer was in use - */ - for (i = 0; i < blocklen; i++) { - helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); - } - } -#else - memset(g2h(vaddr), 0, blocklen); -#endif -} From patchwork Mon Mar 2 17:58:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 184096 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp2680356ile; Mon, 2 Mar 2020 09:59:10 -0800 (PST) X-Google-Smtp-Source: ADFU+vv7ZbGquLxDzwxXMDZ4SXpU+5c068zqA0+IBEiftpLipwu1qruKilzqCkVQP+TNdOZzMvVs X-Received: by 2002:ad4:5632:: with SMTP id cb18mr586694qvb.124.1583171950778; Mon, 02 Mar 2020 09:59:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583171950; cv=none; d=google.com; s=arc-20160816; b=EGQ0+Qtc+nnClATr4lgMH72+5H+2qSN1Yl53QNUEKCV9UWcKlxct7Tp7KReahxImM/ LrAcFfT0SsQIP9KbTPUVx7PHKtU2oBkeKhswtNFCDzbhs84mLgsH7X2EquMAc57CI2jZ z7QthlhRnokzS0mC4dplaSOzZ6J7Vld55m4UsHWX98Y1C3nQ/B/4BIscOsEVtz0pSFye dX28dIxhoQ7RWweRKPcN5FAKb2Bb8NojXQY/0I9ah5/ibMQM/fwk97wyfN1iRGmNgIWQ 7rAQsjctl59bXhAuSvE/IL6fY0M47A1ERDI642n6y57KR1kZ25/e65e9h8IXEyUaX+au GN7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=sDW3bpZw++8P1yHtjBOvr8FuMKG/oaa/CtErSbPyuzs=; b=PzRqR+s4B0dEg3Rasi+QS2AFUBJesg1ztBDKD5xJtwx4PX3xN3RaVBkPT3dyFeV5C1 NiIEttld9Ul5Izcye9Gw8hFUavAbVlR2HlKf+Fte5Uc9nzT6E38xJHkqn30jLQIT4Wt+ /c5l5vMWKdy/JC55uDpEc1HpkfI8u8S7RXM/WXb32xFYgcjTASRXZp7yM6aZW+3+EEXx VTJwpF1xwnhM+1LdqQyMp1rEi2wEdr6GpfVMEiaxJ00lQdhiiXwxYbXWi+Pg/qjMOGJB ZoP+95HcCLy3iBtSo419AoxOXTK/AzsWBcTsHa5RANX0ee3QtbJDZj5DCEWkDehq1edf ExYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K11Wsy62; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id s18sm99510pjp.24.2020.03.02.09.58.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Mar 2020 09:58:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 6/9] target/arm: Use DEF_HELPER_FLAGS for helper_dc_zva Date: Mon, 2 Mar 2020 09:58:26 -0800 Message-Id: <20200302175829.2183-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200302175829.2183-1-richard.henderson@linaro.org> References: <20200302175829.2183-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1044 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The function does not write registers, and only reads them by implication via the exception path. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index b1a5935f61..3df7c185aa 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -90,7 +90,7 @@ DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) DEF_HELPER_2(sqrt_f16, f16, f16, ptr) DEF_HELPER_2(exception_return, void, env, i64) -DEF_HELPER_2(dc_zva, void, env, i64) +DEF_HELPER_FLAGS_2(dc_zva, TCG_CALL_NO_WG, void, env, i64) DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64) From patchwork Mon Mar 2 17:58:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 184103 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp2688233ile; Mon, 2 Mar 2020 10:05:52 -0800 (PST) X-Google-Smtp-Source: ADFU+vsmBFWIBhnzubfHCmW5DQUMDs7lZ0KjH5TV9iYrPR39syVsck+vufbUtGSMIbb1kX+SXvHl X-Received: by 2002:a05:620a:994:: with SMTP id x20mr398045qkx.489.1583172351797; Mon, 02 Mar 2020 10:05:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583172351; cv=none; d=google.com; s=arc-20160816; b=CugenE5UTqxwckqzcXsJkdGEzAM6EH5MXn5mCIDEDuaq4iF0mHPOuWUK9DHLgG4CNT SAROymyn9H7S5FOnMCiqoFUrDr3dRkovW26bP2Hql6kC/104Hnf8kl1aYXSGmL3epXoD XIMiI9PZuzoCuEF5mvjuMI9lTWIEhxOjGM6PthO7rQuRqME3ZzG4/jt2bY3bFeZm3/FJ jYFs4TzrkEZTrPL9ExNm0nldh3ajNJV1T8FYmCD4YxTeJIaaggKmzX9/PSPcI0Q4B5vY POnrb10XMyNqG3N5Fo8ZZm78dyRy3HCCZ9tgIirAP93WHkiTO1fhGmw7P3RLosdETxK5 AqpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uuvmt8nnRxpkzrlRvGkzXacr9M5W6UoCPdAN4Hxg8gg=; b=n3U5LQ1tOU/wvrsWwy7bwg3znQVF6FyJ4v600jXGpp7cTnSY4gqNaShYI9UU9r3eUa 6O1GUDOoNXKm4ggYMAeLVgf4kTgkaIgdfdN5aErI69GuPCX4MUmnEQhx6gYAyMSufCWD dM3BJsBn69TZmrT7W7ASAwlv6xy9XsUad3NiOlc9KgPUvw9mVqfMGg2zSHKpsNJt9+yu En6M5Zd2+jNt+B4n3CgmZqdnaRW4zWadCvoDbuCtN6VqoGbC+cnrcVfJZbT6W6a73/yG c+DU+iurwvsSc3pCHCGlJDGwmklDdxAAJdR12u5/ER/HGubk5orY9k1jIeR/LEyz7UcP JEww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JgQTd5Ua; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x2si3218685qtp.58.2020.03.02.10.05.51 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 02 Mar 2020 10:05:51 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JgQTd5Ua; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36527 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j8pRv-00016h-8l for patch@linaro.org; Mon, 02 Mar 2020 13:05:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39165) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j8pL0-0006jy-8R for qemu-devel@nongnu.org; Mon, 02 Mar 2020 12:58:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j8pKz-0007bW-By for qemu-devel@nongnu.org; Mon, 02 Mar 2020 12:58:42 -0500 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:44292) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j8pKz-0007av-6g for qemu-devel@nongnu.org; Mon, 02 Mar 2020 12:58:41 -0500 Received: by mail-pg1-x542.google.com with SMTP id a14so167590pgb.11 for ; Mon, 02 Mar 2020 09:58:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uuvmt8nnRxpkzrlRvGkzXacr9M5W6UoCPdAN4Hxg8gg=; b=JgQTd5Uam3c76kYxK5iuzGdkmvCMFZaz2gRBOAzcas+O7KsG7sexziMGBYq5Ih3sQK L7YRkafhys+Ik7+Toag/mRHmKmep7sFRPe8mzj3Bn13ragNfmBXrq/zSDgtDbGTJ6MvK 904SNobNuOdZrEmMQGEXDPpfTEd83OC3WFkCsG5ds0vJ5hliqXfhDTK56Sy2eYHP5cum el1L274mOlUTHMDz7mLzsS3tYKTuizryQI7Qr9yxqKjnp3KmEBm3EE0RtXVvTLg3Jeob BmdY+QGRby4yHiLbErUTsLWN+WwbvIOcTBbcjCjoN8mnDxrGikz2XtIFt8ykZtpHO+Oo sLyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uuvmt8nnRxpkzrlRvGkzXacr9M5W6UoCPdAN4Hxg8gg=; b=GSbV8uRyeFAvjouu+MnwrE56wu4TgYL4wfnVdwW8rRwzDiY9nEV5GpgLVoD4LbC5kj yGbvY3fAzLqRUzgGbZF/U4zcbA0s7NPo8/A2mvOlv2ZUgQLelx9rD1QOlmLGEP5PGLef jPIB7k9Ro7FZf/NiuKTTrIXwx2aMLfhn1AjaEpulrM5Aa11fDryed/TWiE6fmx1Qkz1s hgg571WTM1YIDE73VR15mPoyzDgwW7vfmMV6gfXJtuFHB4K4goaXa258r4ad971wiC2Y vgeRF2mCbOtnKq0iZphSw/+WL+ZowQSmiuXkmm427KwdmbKO9js9qeXVhnEcu9yI42tL w/ZA== X-Gm-Message-State: ANhLgQ1bwjHT4gqFdhUM1/K+XKV0LpnvW4/WPHpdaMtjrBFjeS5tyMbC CipjvfxcZ2GhSRJbuEGr2bn6gx1OWzQ= X-Received: by 2002:a62:be0a:: with SMTP id l10mr250698pff.110.1583171920020; Mon, 02 Mar 2020 09:58:40 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id s18sm99510pjp.24.2020.03.02.09.58.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Mar 2020 09:58:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 7/9] target/arm: Clean address for DC ZVA Date: Mon, 2 Mar 2020 09:58:27 -0800 Message-Id: <20200302175829.2183-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200302175829.2183-1-richard.henderson@linaro.org> References: <20200302175829.2183-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This data access was forgotten when we added support for cleaning addresses of TBI information. Fixes: 3a471103ac1823ba Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c910a49b4e..fefe8af7f5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1784,7 +1784,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, return; case ARM_CP_DC_ZVA: /* Writes clear the aligned block of memory which rt points into. */ - tcg_rt = cpu_reg(s, rt); + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt)); gen_helper_dc_zva(cpu_env, tcg_rt); return; default: From patchwork Mon Mar 2 17:58:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 184100 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp2684224ile; Mon, 2 Mar 2020 10:02:31 -0800 (PST) X-Google-Smtp-Source: ADFU+vsFZWNO2JKi1iW+tc3ANESYOTj1iu4TzUlGmHB8HYo1s1DWaMH+xVyqSUfrxD+awLo1VAnz X-Received: by 2002:ad4:4a69:: with SMTP id cn9mr589427qvb.218.1583172150226; Mon, 02 Mar 2020 10:02:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583172150; cv=none; d=google.com; s=arc-20160816; b=sYnP7ccoZ224IMAVQbtu/BPFyeJ0rBKhX8DcWTDt2jw7qmEN9EW2FoBSEXgsRa4mai b5capRGBR5ms84Xzd22g1oId4qAMT1K5r+nQXiNz4PrfS+XgryVgXnDW8Ol9FhE1W7RT 8RWaOPx88iIKjEoDCnalCHxSJxHC0ae/bAe+xp1Hv6LbQM+09ioKJiCWmA7x5HY1al8p Gw5lr1ohfhsavInRExbp/5afVkMf5L7ugj9bJ+5J5ZMSLCloj7JVX4/rm6YyXvpyXRaJ dnqg8GJuxwIY3wCf6qnWu6NKlxUvM75FOzrjSak9lCLN6zkjlVyT4mW8CL68SoK+zKzV h2Wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dr35bRmDl5K2ZK/zV6tEHz3P5CK2kUhrH8hqSGr33Rw=; b=uDYw+qwzsSdHL/Crx7seVLe7hen4+i9z+gv2JKJpoT/ljDQa0KkbB7l6FADu9oFYoa 7QP+A+muaFwCABSQQRaKQf9tfyViWf23apc7mMZnHVBy3NplZIl/kdw+3oogPhjiknNR 5lVUmoTUqFe6cfAxPlM21hKmsinlaUnuj05JtvhsrceCxZGEnCBlPpws628Bdkaim8HF 8dcBZ2Z7/31GwKiMUwJQ1ogwf/rQ4oVUJeeQ2n8WNGambbEZoPSbFf0o+qz6DOlR21Kt GOwWNDgpHfgOh2Ytst5JWTbuN3nXwjgMFHOYapuXi27iSrhV6Ne03/kgWLTTIS7ttHsW ls9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ZJ0/OEYL"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p17si3340077qtu.318.2020.03.02.10.02.30 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 02 Mar 2020 10:02:30 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ZJ0/OEYL"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36434 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j8pOf-0005ND-P5 for patch@linaro.org; Mon, 02 Mar 2020 13:02:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39197) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j8pL1-0006nN-Lh for qemu-devel@nongnu.org; Mon, 02 Mar 2020 12:58:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j8pL0-0007cJ-Kl for qemu-devel@nongnu.org; Mon, 02 Mar 2020 12:58:43 -0500 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:37803) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j8pL0-0007bv-Fb for qemu-devel@nongnu.org; Mon, 02 Mar 2020 12:58:42 -0500 Received: by mail-pg1-x544.google.com with SMTP id z12so184921pgl.4 for ; Mon, 02 Mar 2020 09:58:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dr35bRmDl5K2ZK/zV6tEHz3P5CK2kUhrH8hqSGr33Rw=; b=ZJ0/OEYLqfjbDLH2HPXWjjFaocOmukBiVGnzk0V+U8OA7hE/kfZ68Gr/1lSpMROAFk pRJKWCQxNS2/QIjxSFwbS60hW2/8hgQVGzJ+HYitny4NgKJec0USwyK6z0jMVKPHmS0Y Sm5ao3zmmc12Nw9vumEe9JcG/wPKSFjiOiasKfYEiTdNoK9JBVX9/LdpttrrDM9B+nuF ZDDnG9rMyp4g3fkU6g20pbGSK4pl7siJ3vRDjPSeDFYkR7QTxtBEE1L6w5hwKW9MgCsF PQH9aerx8NzYc2WB9Gk0QWHs4oZv+oxICiBhKl+uG1/z9Tm6qbU+NvexHSw74WUWlayl doYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dr35bRmDl5K2ZK/zV6tEHz3P5CK2kUhrH8hqSGr33Rw=; b=VAkjxsW8NpCO7A6ic5ahUjWWnpr2DiX5Me/jZ6SqBA2rQxTxD56U7AR5HY619AxT1L +DcdLGUC40M4HbrsjTPw6Wk5yzIVZJEb5Ic3+wcxVJyr/I7HT3KcUtnP4mQXEvsa1kQy tCKSpEmxwUGfu5wkH3PEAKbe5BsQLSYEh918hTPYJtQ9jUz+L/zBGnHcVBlD0YXdDJif q5s32u68d0gWaXbrLEvglMKHa+NurfeboUmvm5N7tgjuwae6wcy/oD3tQmCbG1C29a3E 3mDDFhX/8GRWjm2+RSlLlkjhUgUvH3IgWzHLi611bCEA+DuJmbS+iWv7rDpMua7zFS+x XvuA== X-Gm-Message-State: ANhLgQ3OTj73yOGS7qLVeSmLL5xKN+YI0sUHJvKOFCYXAkZj7Y9VYwl8 z20zN1D6sFwpmTaqLqjuA8e1g6JtQBQ= X-Received: by 2002:aa7:80d1:: with SMTP id a17mr209275pfn.143.1583171921259; Mon, 02 Mar 2020 09:58:41 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id s18sm99510pjp.24.2020.03.02.09.58.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Mar 2020 09:58:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 8/9] target/arm: Check addresses for disabled regimes Date: Mon, 2 Mar 2020 09:58:28 -0800 Message-Id: <20200302175829.2183-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200302175829.2183-1-richard.henderson@linaro.org> References: <20200302175829.2183-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We fail to validate the upper bits of a virtual address on a translation disabled regime, as per AArch64.TranslateAddressS1Off. Signed-off-by: Richard Henderson --- target/arm/helper.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index addbec91d8..0ef32d3c24 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11634,7 +11634,38 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, /* Definitely a real MMU, not an MPU */ if (regime_translation_disabled(env, mmu_idx)) { - /* MMU disabled. */ + /* + * MMU disabled. S1 addresses are still checked for bounds. + * C.f. AArch64.TranslateAddressS1Off. + */ + if (is_a64(env) && mmu_idx != ARMMMUIdx_Stage2) { + int pamax = arm_pamax(env_archcpu(env)); + uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + int addrtop, tbi; + + tbi = aa64_va_parameter_tbi(tcr, mmu_idx); + if (access_type == MMU_INST_FETCH) { + tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi = (tbi >> extract64(address, 55, 1)) & 1; + addrtop = (tbi ? 55 : 63); + + if (extract64(address, pamax, addrtop - pamax + 1) != 0) { + fi->type = ARMFault_AddressSize; + fi->level = 0; + fi->stage2 = false; + return 1; + } + + /* + * The ARM pseudocode copies bits [51:0] to addrdesc.paddress. + * Except for TBI, we've just validated everything above PAMax + * is zero. So we only need to drop TBI. + */ + if (tbi) { + address = extract64(address, 0, 56); + } + } *phys_ptr = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; *page_size = TARGET_PAGE_SIZE; From patchwork Mon Mar 2 17:58:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 184099 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp2683854ile; Mon, 2 Mar 2020 10:02:14 -0800 (PST) X-Google-Smtp-Source: ADFU+vsck54x7rdAMrk3Xnq+aLB73Icc7noEDDTgfp0XkDGVYvRc3FbOZ9geKtxX9IQZ3oNFUAXU X-Received: by 2002:ac8:6bc9:: with SMTP id b9mr890933qtt.108.1583172133967; Mon, 02 Mar 2020 10:02:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583172133; cv=none; d=google.com; s=arc-20160816; b=pIxidZjYwg3qp9wcFocy5DGImMj3fR5SG4V5BU2JlG443oe8VmccZEkwLcdasZRAfY VN1RPtKpUw0jC/mzBdt2l4nrheFskLulhXKH8kQ/qAedqeLLDUPNofg/cFQIfJ/hoyUI 2/pSNgrT3KIJAcCjEU/4XVKHC1k49LUG+7ulle3Em5r1YE0eznDegLvTgZt4QRcXYHTi T6cmcCCRrWAgsGw5p4P3qGWTDyl0BqbxaG73/sly0aTJDl2D5ZEkaiKKOhpjAVhHRwkL uuow4TwWiFo3KDqQrWvj6NCTOk1oDa1LIU8dGXHdeu4VLhsBmWQKOCOFYkBZZy+WkFdG zrHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gv99y10Tw9XL58AqjJTwfCMl/voN1k409rbwq+MWA5w=; b=RP0Jai9B25aqT/a/xC08F9UzZp7XPpIxmxLRAD5vfUQoYYkltstKBpZFkJA2cfAOVQ 1+OWklU+s1b7RmpF4vDYKuqGyK7ewb7nsFrNrlFm+qqRCIYELeFA4J5GV9M56l9+6OGM rBrFWHgSXt1QyKAcvQni1VQ5l6RIaNnPxf6+QLTsGzS6k3PLJQd+ZjKHbe44UhtRP14k eKVqP0vzCtuuO8q8UwkcvzzjJwjpzrQ5s6rL4qHvWUMvRNI9OpW4Afv/lvrEkVD4JbCl vTwcRHoPoL/xkWWN9MqiFShbgFm+T8zwWT+Ck6fuRuj7ssPC+BsUlTrOrSJ4O0WHtnKa z+1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vPXh7Anc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id s18sm99510pjp.24.2020.03.02.09.58.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Mar 2020 09:58:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 9/9] target/arm: Disable clean_data_tbi for system mode Date: Mon, 2 Mar 2020 09:58:29 -0800 Message-Id: <20200302175829.2183-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200302175829.2183-1-richard.henderson@linaro.org> References: <20200302175829.2183-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We must include the tag in the FAR_ELx register when raising an addressing exception. Which means that we should not clear out the tag during translation. We cannot at present comply with this for user mode, so we retain the clean_data_tbi function for the moment, though it no longer does what it says on the tin for system mode. This function is to be replaced with MTE, so don't worry about the slight misnaming. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.20.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fefe8af7f5..8fffb52203 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -228,7 +228,18 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) { TCGv_i64 clean = new_tmp_a64(s); + /* + * In order to get the correct value in the FAR_ELx register, + * we must present the memory subsystem with the "dirty" address + * including the TBI. In system mode we can make this work via + * the TLB, dropping the TBI during translation. But for user-only + * mode we don't have that option, and must remove the top byte now. + */ +#ifdef CONFIG_USER_ONLY gen_top_byte_ignore(s, clean, addr, s->tbid); +#else + tcg_gen_mov_i64(clean, addr); +#endif return clean; }