From patchwork Thu Jun 29 02:54:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 106591 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp605541qge; Wed, 28 Jun 2017 19:55:33 -0700 (PDT) X-Received: by 10.99.111.132 with SMTP id k126mr13670740pgc.76.1498704933338; Wed, 28 Jun 2017 19:55:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498704933; cv=none; d=google.com; s=arc-20160816; b=OFoWTkirpRz3jF0XwQKA7pmKDg+IRb3EfpQhHQ6+I3AcQ+kvCHMMRQJFj4uy1lvS76 A7X0QT7uKggC6QJSch/dQcVr3BTqeaqExF1fHSc/PV7hk22J/1a9LO9oMiqKfTei2Lwe rUi7GBn20MIhFmImEWHAM6myKUtUDd1mRodeYS118Qz+uG5J/uWFbDPOgVH3JEryarh6 5mMOJIhSPAn8P66PLD4/QVoVppsZ8rdaDY7NskzPV/48HUL/rM9eMK2nPdPmhwt/n1f+ FD0Xcbbn+OTlfENpnOr5iHv500/OZOw3K4w5HPZNjIPR3OkRbi89+PtdoEsr/mxN6Jum tAlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dmarc-filter:arc-authentication-results; bh=ZKWBTngGxBSi1EdHpI6Q3Y55RQ/ttoV33ZYugCvbbcc=; b=td87FhJXiiCOubPCoP5QYUC2rnUFwmkWJcT4X4cx3ee+SJOpy60WjL5j6WRvUCA+vt htRNUj/sRcgL/gRD8IOzI9ezU57tPLR8wRDQwxIOB/yYjSEnxDH3AVhtX2IRrOv2K4HN 5qKFjTt3oTDNKEPV64X7nZQh/ySMh+H1yNQYn+8S7FvA2T5+zJZuDkoX0s5h273i767y pLlOey3sqoUzif7726P9as5eFGPsN9ra9DHJ7uXLioQ0cty7a0HWANjAiBckeLyN75Im StH+Gk8GB7VJ9d/FxS3sE2cJEtcig4l9g58oIY0yMGwg+OCToFW9Fw/4Wmu6atRhcwBR 84HQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a20si2780529pfc.137.2017.06.28.19.55.33; Wed, 28 Jun 2017 19:55:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751630AbdF2Cz0 (ORCPT + 7 others); Wed, 28 Jun 2017 22:55:26 -0400 Received: from mail.kernel.org ([198.145.29.99]:50168 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751548AbdF2CzZ (ORCPT ); Wed, 28 Jun 2017 22:55:25 -0400 Received: from localhost.localdomain (li411-102.members.linode.com [106.187.91.102]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 9927C22BD9; Thu, 29 Jun 2017 02:55:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9927C22BD9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=shawnguo@kernel.org From: Shawn Guo To: Thierry Reding , Rob Herring Cc: Baoyou Xie , Xin Zhou , Jun Nie , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Shawn Guo Subject: [PATCH 1/2] dt-bindings: pwm: add bindings doc for ZTE ZX PWM controller Date: Thu, 29 Jun 2017 10:54:33 +0800 Message-Id: <1498704874-14599-2-git-send-email-shawnguo@kernel.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498704874-14599-1-git-send-email-shawnguo@kernel.org> References: <1498704874-14599-1-git-send-email-shawnguo@kernel.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Shawn Guo It adds bindings document for ZTE ZX PWM controller. The device has two clocks: PCLK and WCLK. The PCLK is for register access, and WCLK is the reference clock for calculating period and duty cycles. Also, the device supports polarity configuration, so #pwm-cells should be 3. Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/pwm/pwm-zx.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-zx.txt -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/pwm/pwm-zx.txt b/Documentation/devicetree/bindings/pwm/pwm-zx.txt new file mode 100644 index 000000000000..a6bcc75c9164 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-zx.txt @@ -0,0 +1,22 @@ +ZTE ZX PWM controller + +Required properties: + - compatible: Should be "zte,zx296718-pwm". + - reg: Physical base address and length of the controller's registers. + - clocks : The phandle and specifier referencing the controller's clocks. + - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The + PCLK is for register access, while WCLK is the reference clock for + calculating period and duty cycles. + - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of + the cells format. + +Example: + + pwm: pwm@1439000 { + compatible = "zte,zx296718-pwm"; + reg = <0x1439000 0x1000>; + clocks = <&lsp1crm LSP1_PWM_PCLK>, + <&lsp1crm LSP1_PWM_WCLK>; + clock-names = "pclk", "wclk"; + #pwm-cells = <3>; + }; From patchwork Thu Jun 29 02:54:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 106592 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp605693qge; Wed, 28 Jun 2017 19:55:51 -0700 (PDT) X-Received: by 10.98.59.1 with SMTP id i1mr13934551pfa.147.1498704951398; Wed, 28 Jun 2017 19:55:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498704951; cv=none; d=google.com; s=arc-20160816; b=pXkN8B2C/qNUsJDpajNqlRC1QZW9XMIAlkhfY9ROfvNfKdf7oMM/n1L4jpf61nIhJe Y6AKaDk4Ovy/dyM6jRF7aybqSk90Y4JUk/avrGi9M+/sUKfipsyFynroJq8gM4YhZzn2 OqHtJfz7wrqSMmFHUHqrbpTD4BFJpcM+e04mEMAstEdJrG0Jn5HzWiuuN4FivcYIr9nj 3OTFKXZeN9Y+fFIPqoVmJVcQv1T1ILeN4mlK/1CZTDqVBo42kGsqrExtcnPWXXyPeq5M zaHJfrFkfLR9GG2DTbdAU7LpJ6iiD4Rs8Q/mAgxoniFVdQq+7m+SH7CE1UDjhutaBwMG Pvuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dmarc-filter:arc-authentication-results; bh=tPtDqkZMaibJKuN9tsimzP0v8678pyCIh+Iq53qh2cQ=; b=c5Yqihix+WC36+7RVlYnSWnxKZSWthWhHxmNVlFIVrvNDqj7mjXdKs4SXMmjpbevE6 7ywMMLYMwdujXO0NMq14Pa9yKjblDDEyjVsoxkXBQr0FhPMdmxp/8fJ6/75iNwprBdPy NRecondAYacpWN1vazJuBC6aGLlxxBGUzokGAPfPGYTOhXBlw0hvMBEjP9ImzXoUWaZ6 R6PGxdZWr9p6VWdqXthNMEhyYcXwTXRaJGeq66Wbc7jXr2q9C2isqFiM96xTYcWyOj+j o8xCoGt1i4LFxK+bS4MWRy1MlLMVFa3P0lrukXHuqtx3SrcuBL5jG5zYdx0jrf5E/MM+ MymQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k87si2748029pfj.411.2017.06.28.19.55.51; Wed, 28 Jun 2017 19:55:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751785AbdF2Czj (ORCPT + 7 others); Wed, 28 Jun 2017 22:55:39 -0400 Received: from mail.kernel.org ([198.145.29.99]:50184 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751657AbdF2Cz3 (ORCPT ); Wed, 28 Jun 2017 22:55:29 -0400 Received: from localhost.localdomain (li411-102.members.linode.com [106.187.91.102]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8C7D622BDB; Thu, 29 Jun 2017 02:55:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8C7D622BDB Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=shawnguo@kernel.org From: Shawn Guo To: Thierry Reding , Rob Herring Cc: Baoyou Xie , Xin Zhou , Jun Nie , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Shawn Guo Subject: [PATCH 2/2] pwm: add ZTE ZX PWM device driver Date: Thu, 29 Jun 2017 10:54:34 +0800 Message-Id: <1498704874-14599-3-git-send-email-shawnguo@kernel.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498704874-14599-1-git-send-email-shawnguo@kernel.org> References: <1498704874-14599-1-git-send-email-shawnguo@kernel.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Shawn Guo It adds PWM device driver for ZTE ZX family SoCs. The PWM controller supports 4 devices with polarity configuration. The driver has been tested with pwm-regulator support to scale core voltage via cpufreq. Signed-off-by: Shawn Guo --- drivers/pwm/Kconfig | 9 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-zx.c | 244 +++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 254 insertions(+) create mode 100644 drivers/pwm/pwm-zx.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 313c10789ca2..e98175331a69 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -500,4 +500,13 @@ config PWM_VT8500 To compile this driver as a module, choose M here: the module will be called pwm-vt8500. +config PWM_ZX + tristate "ZTE ZX PWM support" + depends on ARCH_ZX + help + Generic PWM framework driver for ZTE ZX family SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-zx. + endif diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 93da1f79a3b8..75ab74094d7b 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -49,3 +49,4 @@ obj-$(CONFIG_PWM_TIPWMSS) += pwm-tipwmss.o obj-$(CONFIG_PWM_TWL) += pwm-twl.o obj-$(CONFIG_PWM_TWL_LED) += pwm-twl-led.o obj-$(CONFIG_PWM_VT8500) += pwm-vt8500.o +obj-$(CONFIG_PWM_ZX) += pwm-zx.o diff --git a/drivers/pwm/pwm-zx.c b/drivers/pwm/pwm-zx.c new file mode 100644 index 000000000000..5c81c2ddc0a9 --- /dev/null +++ b/drivers/pwm/pwm-zx.c @@ -0,0 +1,244 @@ +/* + * Copyright (C) 2017 Sanechips Technology Co., Ltd. + * Copyright 2017 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define ZX_PWM_MODE 0x0 +#define ZX_PWM_CLKDIV_MASK GENMASK(11, 2) +#define ZX_PWM_CLKDIV(x) (((x) << 8) & ZX_PWM_CLKDIV_MASK) +#define ZX_PWM_POLAR BIT(1) +#define ZX_PWM_EN BIT(0) +#define ZX_PWM_PERIOD 0x4 +#define ZX_PWM_DUTY 0x8 + +#define ZX_PWM_CLKDIV_MAX 1023 +#define ZX_PWM_PERIOD_MAX 65535 + +struct zx_pwm_chip { + struct pwm_chip chip; + struct clk *pclk; + struct clk *wclk; + void __iomem *base; +}; + +#define to_zx_pwm_chip(_chip) container_of(_chip, struct zx_pwm_chip, chip) + +static inline u32 zx_pwm_readl(struct zx_pwm_chip *zpc, unsigned int hwpwm, + unsigned int offset) +{ + return readl(zpc->base + (hwpwm + 1) * 0x10 + offset); +} + +static inline void zx_pwm_writel(struct zx_pwm_chip *zpc, unsigned int hwpwm, + unsigned int offset, u32 val) +{ + writel(val, zpc->base + (hwpwm + 1) * 0x10 + offset); +} + +static int zx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); + unsigned int period_cycles; + unsigned int duty_cycles; + unsigned long long c; + unsigned long rate; + int div = 1; + u32 val; + + /* Find out the best divider */ + rate = clk_get_rate(zpc->wclk); + while (1) { + c = rate / div; + c = c * period_ns; + do_div(c, NSEC_PER_SEC); + if (c < ZX_PWM_PERIOD_MAX) + break; + div++; + if (div > ZX_PWM_CLKDIV_MAX) + return -ERANGE; + } + + /* Calculate duty cycles */ + period_cycles = c; + c *= duty_ns; + do_div(c, period_ns); + duty_cycles = c; + + /* + * If the pwm is being enabled, we have to temporarily disable it + * before configuring the registers. + */ + if (pwm_is_enabled(pwm)) { + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + val &= ~ZX_PWM_EN; + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + } + + /* Set up registers */ + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + val &= ZX_PWM_CLKDIV_MASK; + val |= ZX_PWM_CLKDIV(div); + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_PERIOD, period_cycles); + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_DUTY, duty_cycles); + + /* Re-enable the pwm if needed */ + if (pwm_is_enabled(pwm)) { + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + val |= ZX_PWM_EN; + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + } + + return 0; +} + +static int zx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); + u32 val; + int ret; + + ret = clk_prepare_enable(zpc->wclk); + if (ret) + return ret; + + /* Enable the pwm */ + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + val |= ZX_PWM_EN; + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + + return 0; +} + +static void zx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); + u32 val; + + /* Disable the pwm */ + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + val &= ~ZX_PWM_EN; + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + + clk_disable_unprepare(zpc->wclk); +} + +static int zx_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip); + u32 val; + + val = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE); + + if (polarity == PWM_POLARITY_INVERSED) + val &= ~ZX_PWM_POLAR; + else + val |= ZX_PWM_POLAR; + + zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_MODE, val); + + return 0; +} + +static const struct pwm_ops zx_pwm_ops = { + .config = zx_pwm_config, + .enable = zx_pwm_enable, + .disable = zx_pwm_disable, + .set_polarity = zx_pwm_set_polarity, + .owner = THIS_MODULE, +}; + +static int zx_pwm_probe(struct platform_device *pdev) +{ + struct zx_pwm_chip *zpc; + struct resource *res; + int ret; + + zpc = devm_kzalloc(&pdev->dev, sizeof(*zpc), GFP_KERNEL); + if (!zpc) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + zpc->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(zpc->base)) + return PTR_ERR(zpc->base); + + zpc->pclk = devm_clk_get(&pdev->dev, "pclk"); + if (IS_ERR(zpc->pclk)) + return PTR_ERR(zpc->pclk); + + zpc->wclk = devm_clk_get(&pdev->dev, "wclk"); + if (IS_ERR(zpc->wclk)) + return PTR_ERR(zpc->wclk); + + zpc->chip.dev = &pdev->dev; + zpc->chip.ops = &zx_pwm_ops; + zpc->chip.base = -1; + zpc->chip.npwm = 4; + zpc->chip.of_xlate = of_pwm_xlate_with_flags; + zpc->chip.of_pwm_n_cells = 3; + + ret = pwmchip_add(&zpc->chip); + if (ret < 0) { + dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, zpc); + + ret = clk_prepare_enable(zpc->pclk); + if (ret) + goto pwm_remove; + + return 0; + +pwm_remove: + pwmchip_remove(&zpc->chip); + return ret; +} + +static int zx_pwm_remove(struct platform_device *pdev) +{ + struct zx_pwm_chip *zpc = platform_get_drvdata(pdev); + + clk_disable_unprepare(zpc->pclk); + + return pwmchip_remove(&zpc->chip); +} + +static const struct of_device_id zx_pwm_dt_ids[] = { + { .compatible = "zte,zx296718-pwm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, zx_pwm_dt_ids); + +static struct platform_driver zx_pwm_driver = { + .driver = { + .name = "zx-pwm", + .of_match_table = zx_pwm_dt_ids, + }, + .probe = zx_pwm_probe, + .remove = zx_pwm_remove, +}; +module_platform_driver(zx_pwm_driver); + +MODULE_ALIAS("platform:zx-pwm"); +MODULE_AUTHOR("Shawn Guo "); +MODULE_DESCRIPTION("ZTE ZX PWM Driver"); +MODULE_LICENSE("GPL v2");