From patchwork Tue May 12 16:38:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 186553 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp108353ilb; Tue, 12 May 2020 09:42:57 -0700 (PDT) X-Google-Smtp-Source: APiQypKypH1rBYxjkPaZfuuT2qVztwTxMtzjv8fATGeaI8I6WEZSOIdaD+MjldJFqfXXrR/5uX7o X-Received: by 2002:a37:7e44:: with SMTP id z65mr14687915qkc.37.1589301776985; Tue, 12 May 2020 09:42:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589301776; cv=none; d=google.com; s=arc-20160816; b=L+LhiJirJ+0hF6EXK48IicB2PaM50eG7vDs3lErEt+pXcBFseZXU/cGn5j2UtX7ede xfXShaJ5QNt/iXYZ+2Ft5rXJ5OI/wvJiELSm6yrXMMOmYTPWJyJsvHhlrQeEkeRCGJli IKD9DKxY8UwwEPEON/G3g5EDrdZehWhVZP1hDpiXzReL14mEzPPiE95wfL8wUCybSAMt x+QTIefIz9XY2mX2zN0FxSi1N4ICCKeDfIYy8sKFcpwPkObr5SyHwmB0bCC23ezDkBmZ 1u5hg8lC/DcBhd2xx8Eh5IkcpcYg7w5hDpGnsERGVAvJe+gHk7HOn0xlnIcwno8yKfrV 5kPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=miq5sxrk+TH5OlhT9tqJAy5fKLaSHjQ/CF8bIqx0AcI=; b=Z/fDYLB1MPQYub7IB+mqucI5ofLB37+fd6dvH2rQYHgdOD3qLRYRyKNQ9Xkny7YsTG 6kR8DdUkICmiTJIYuL0tajo4HyOa8vogisMcTH4s+IMBN0JjDK8lroK9Bg/aAy3K6e7l q9jI0XBw+jjSbz1y/tytLUn4Y8MS/5YrElq0ab4ZyNyczklk/EG6ODs46/164weRMN5t ae9olssnbmLOLdFCBFv9HfRTRfhVg4qed10j4RPw/1Kejp7TiZTyWVYVMBcsdmxGuBXG 9HC3pEol2Ri5qYpmtYvkun2oCPUaGWci2WYeTx1BCiRDzVt8WY5R7OAV0FRN6G9vVaB9 dNmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lb4ex40A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g145si7768021qke.107.2020.05.12.09.42.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 May 2020 09:42:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lb4ex40A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43800 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jYXza-0001UL-RO for patch@linaro.org; Tue, 12 May 2020 12:42:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50502) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jYXvy-00068z-7b for qemu-devel@nongnu.org; Tue, 12 May 2020 12:39:10 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:46638) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jYXvx-00060a-BK for qemu-devel@nongnu.org; Tue, 12 May 2020 12:39:09 -0400 Received: by mail-wr1-x441.google.com with SMTP id w7so16303880wre.13 for ; Tue, 12 May 2020 09:39:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=miq5sxrk+TH5OlhT9tqJAy5fKLaSHjQ/CF8bIqx0AcI=; b=Lb4ex40AHjQhSCBPsVnhiyp6TueulsCNnYFWNqytO9xKqxoz/2rxsXrcOD2WFRlm37 4axWh74I88NEiil1u0zk9iaEby+CtF3AUZXDt96juhbLoVujMj2xzZyIAJJQvWvJC+Xe xOUUNji1FU+QTRK/j5rEZnMAoUv3WeflNUa9ZHcDM7Xs6o/SBS47WF7QsoBbHAxjXerK TWji+5YT3CLgbTQ238ipttB/H3BSHKrYq/te9XKgtn8p7B+ZEPfZQUnexXoZ9PxAwk7t Y3nM5IGD7QkZW0GVjhc88R6NiofYyOPER2v4S/7eef5zcluiolfn2pwlSO3EYtiN4Fhi rAUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=miq5sxrk+TH5OlhT9tqJAy5fKLaSHjQ/CF8bIqx0AcI=; b=kMKWmBJR0BlrA8aCmrfTxJYPsB49K9DpEFLziOYLSTq+PDUx9gXyFnkNl4NM7Nr2H7 +I7RyHfJZoBJqpwzLXcaTD+YMUDHnF2gmt+xI58R/m28v65gNKLsLLgb0nbwejhk3lU4 EPwB6wO+U99VV1k1ZmnmXy13IrohhUfrgm5jZHS9Kl+UM8FwTbnUnFo2QyJMdSkctTsg lDhWNgg12J26gf0WurGMJRAyw5LNIpX2tmb7vF5JdP6YU9adVYZo3M/L2nESyW0VFWza kQUShL6Nqt5jpTHc5lkOywkLJiyHAmEOvu0Y87jm8tVotVmq8W3y33G0ht93Hfs6cyYe SfzQ== X-Gm-Message-State: AGi0PuZA6piH3TsIuFijOnizY2ilciK7pGcY3tFhcMeowDD0EGd8jlcL 70TTujsGhgIey0noXRULBbhAsw== X-Received: by 2002:a5d:4806:: with SMTP id l6mr26389228wrq.121.1589301547908; Tue, 12 May 2020 09:39:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 01/17] target/arm: Convert Neon 3-reg-same VQRDMLAH/VQRDMLSH to decodetree Date: Tue, 12 May 2020 17:38:48 +0100 Message-Id: <20200512163904.10918-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the Neon VQRDMLAH and VQRDMLSH insns in the 3-reg-same group to decodetree. These don't use do_3same() because they want to operate on VFP double registers, whose offsets are different from the neon_reg_offset() calculations do_3same does. Signed-off-by: Peter Maydell --- v1->v2: use do_3same() rather than custom do_vqrdlmah() function --- target/arm/neon-dp.decode | 3 +++ target/arm/translate-neon.inc.c | 15 +++++++++++++++ target/arm/translate.c | 14 ++------------ 3 files changed, 20 insertions(+), 12 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 6b0b6566d60..04aff438410 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -89,3 +89,6 @@ VMLS_3s 1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same VMUL_3s 1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same VMUL_p_3s 1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same + +VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same +VQRDMLSH_3s 1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index 099491b16f3..661b5fc4cf2 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -671,3 +671,18 @@ static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a) } return do_3same(s, a, gen_VMUL_p_3s); } + +#define DO_VQRDMLAH(INSN, FUNC) \ + static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ + { \ + if (!dc_isar_feature(aa32_rdm, s)) { \ + return false; \ + } \ + if (a->size != 1 && a->size != 2) { \ + return false; \ + } \ + return do_3same(s, a, FUNC); \ + } + +DO_VQRDMLAH(VQRDMLAH, gen_gvec_sqrdmlah_qc) +DO_VQRDMLAH(VQRDMLSH, gen_gvec_sqrdmlsh_qc) diff --git a/target/arm/translate.c b/target/arm/translate.c index e3d37ef2e99..1f06cb5a87f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5450,12 +5450,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) if (!u) { break; /* VPADD */ } - /* VQRDMLAH */ - if (dc_isar_feature(aa32_rdm, s) && (size == 1 || size == 2)) { - gen_gvec_sqrdmlah_qc(size, rd_ofs, rn_ofs, rm_ofs, - vec_size, vec_size); - return 0; - } + /* VQRDMLAH : handled by decodetree */ return 1; case NEON_3R_VFM_VQRDMLSH: @@ -5466,12 +5461,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } break; } - /* VQRDMLSH */ - if (dc_isar_feature(aa32_rdm, s) && (size == 1 || size == 2)) { - gen_gvec_sqrdmlsh_qc(size, rd_ofs, rn_ofs, rm_ofs, - vec_size, vec_size); - return 0; - } + /* VQRDMLSH : handled by decodetree */ return 1; case NEON_3R_VABD: From patchwork Tue May 12 16:38:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 186550 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp106248ilb; Tue, 12 May 2020 09:40:11 -0700 (PDT) X-Google-Smtp-Source: APiQypLUQhxvkQSZ5Ad2HFZ+TUhL0fZbppCuh9V3LcDnREECSLVaxT+KOgytuZFgCKBGjfKz0IWA X-Received: by 2002:a37:8604:: with SMTP id i4mr21227995qkd.481.1589301611629; Tue, 12 May 2020 09:40:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589301611; cv=none; d=google.com; s=arc-20160816; b=s+Jlp5vEFsP7fS58YibsDjSYayMVxlM7RXtuGhXhAqxQ30e+fH+0dWzghzLcGO7juQ XocXTGdQA4lZh0hBp9SKL4r7Tip7MTu1rk11arpWIL9Ijr8VHijM+bd1NWn2TRgToLIW 89ZIz4JkKloyUFiO75Xl89fQZ1iaPbjP7xijxUp2I4oDTXyRIMG9RZ/B2lK37qMlvnd8 GToQltn8asoRhL3jSAupXcM8GIFt9o91RokwPIMR+qpCYOganCAJLZDvUbnFXF6BtiOU cFQ+vlkYf9d7urMC8E5CvySeUnHTPp+fhaswrPeGDnq9DdbRK5jZcuDTOo/pAvp2gN5o qYaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WX2yhGL+5A/xIoAy1lX3eCz5+m+tDDilj9TcJLBfsZo=; b=v2s3bWWF1m1CEozR85uxhYNewI4NfRzr0rlqW4aUlkSWjP3RZNvTaVQy08Uhi9cEQQ XCN8hnCdJ9eoipHMpmF7ZRaveKmi9lgUP8gyQ2SSYqDnG0KhGjjacdMkGREfrDoNOtvT FsTHRmlzPDZ/o2Q5Ja9Q6CuU5qPa3as+1UMTQcPaBnrHTM4Ys7+JnQCiqfFdcJntkueD tmr055KV6uhLgkmITfOde9deg8mltBob9wRIWMWmeS9W2nwAdhAhVCZJ//SLCyAmvPlG btxxPuG7UcfX77sWPJqFJYWVWLC1r7/tLEqdr5wG0urXBGAR5JvAyhdpdgnjXE9QLDfL sU6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R6BJGvEs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:08 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 02/17] target/arm: Convert Neon 3-reg-same SHA to decodetree Date: Tue, 12 May 2020 17:38:49 +0100 Message-Id: <20200512163904.10918-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the Neon SHA instructions in the 3-reg-same group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 10 +++ target/arm/translate-neon.inc.c | 139 ++++++++++++++++++++++++++++++++ target/arm/translate.c | 46 +---------- 3 files changed, 151 insertions(+), 44 deletions(-) -- 2.20.1 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 04aff438410..68b0a44793f 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -91,4 +91,14 @@ VMUL_3s 1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same VMUL_p_3s 1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same + +SHA1_3s 1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \ + vm=%vm_dp vn=%vn_dp vd=%vd_dp +SHA256H_3s 1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... \ + vm=%vm_dp vn=%vn_dp vd=%vd_dp +SHA256H2_3s 1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... \ + vm=%vm_dp vn=%vn_dp vd=%vd_dp +SHA256SU1_3s 1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... \ + vm=%vm_dp vn=%vn_dp vd=%vd_dp + VQRDMLSH_3s 1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index 661b5fc4cf2..03b3337e460 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -686,3 +686,142 @@ static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a) DO_VQRDMLAH(VQRDMLAH, gen_gvec_sqrdmlah_qc) DO_VQRDMLAH(VQRDMLSH, gen_gvec_sqrdmlsh_qc) + +static bool trans_SHA1_3s(DisasContext *s, arg_SHA1_3s *a) +{ + TCGv_ptr ptr1, ptr2, ptr3; + TCGv_i32 tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON) || + !dc_isar_feature(aa32_sha1, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if ((a->vn | a->vm | a->vd) & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + ptr1 = vfp_reg_ptr(true, a->vd); + ptr2 = vfp_reg_ptr(true, a->vn); + ptr3 = vfp_reg_ptr(true, a->vm); + tmp = tcg_const_i32(a->optype); + gen_helper_crypto_sha1_3reg(ptr1, ptr2, ptr3, tmp); + tcg_temp_free_i32(tmp); + tcg_temp_free_ptr(ptr1); + tcg_temp_free_ptr(ptr2); + tcg_temp_free_ptr(ptr3); + + return true; +} + +static bool trans_SHA256H_3s(DisasContext *s, arg_SHA256H_3s *a) +{ + TCGv_ptr ptr1, ptr2, ptr3; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON) || + !dc_isar_feature(aa32_sha2, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if ((a->vn | a->vm | a->vd) & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + ptr1 = vfp_reg_ptr(true, a->vd); + ptr2 = vfp_reg_ptr(true, a->vn); + ptr3 = vfp_reg_ptr(true, a->vm); + gen_helper_crypto_sha256h(ptr1, ptr2, ptr3); + tcg_temp_free_ptr(ptr1); + tcg_temp_free_ptr(ptr2); + tcg_temp_free_ptr(ptr3); + + return true; +} + +static bool trans_SHA256H2_3s(DisasContext *s, arg_SHA256H2_3s *a) +{ + TCGv_ptr ptr1, ptr2, ptr3; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON) || + !dc_isar_feature(aa32_sha2, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if ((a->vn | a->vm | a->vd) & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + ptr1 = vfp_reg_ptr(true, a->vd); + ptr2 = vfp_reg_ptr(true, a->vn); + ptr3 = vfp_reg_ptr(true, a->vm); + gen_helper_crypto_sha256h2(ptr1, ptr2, ptr3); + tcg_temp_free_ptr(ptr1); + tcg_temp_free_ptr(ptr2); + tcg_temp_free_ptr(ptr3); + + return true; +} + +static bool trans_SHA256SU1_3s(DisasContext *s, arg_SHA256SU1_3s *a) +{ + TCGv_ptr ptr1, ptr2, ptr3; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON) || + !dc_isar_feature(aa32_sha2, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if ((a->vn | a->vm | a->vd) & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + ptr1 = vfp_reg_ptr(true, a->vd); + ptr2 = vfp_reg_ptr(true, a->vn); + ptr3 = vfp_reg_ptr(true, a->vm); + gen_helper_crypto_sha256su1(ptr1, ptr2, ptr3); + tcg_temp_free_ptr(ptr1); + tcg_temp_free_ptr(ptr2); + tcg_temp_free_ptr(ptr3); + + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 1f06cb5a87f..ee2b8d6f6e3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5359,7 +5359,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) int vec_size; uint32_t imm; TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5; - TCGv_ptr ptr1, ptr2, ptr3; + TCGv_ptr ptr1, ptr2; TCGv_i64 tmp64; if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { @@ -5403,49 +5403,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) return 1; } switch (op) { - case NEON_3R_SHA: - /* The SHA-1/SHA-256 3-register instructions require special - * treatment here, as their size field is overloaded as an - * op type selector, and they all consume their input in a - * single pass. - */ - if (!q) { - return 1; - } - if (!u) { /* SHA-1 */ - if (!dc_isar_feature(aa32_sha1, s)) { - return 1; - } - ptr1 = vfp_reg_ptr(true, rd); - ptr2 = vfp_reg_ptr(true, rn); - ptr3 = vfp_reg_ptr(true, rm); - tmp4 = tcg_const_i32(size); - gen_helper_crypto_sha1_3reg(ptr1, ptr2, ptr3, tmp4); - tcg_temp_free_i32(tmp4); - } else { /* SHA-256 */ - if (!dc_isar_feature(aa32_sha2, s) || size == 3) { - return 1; - } - ptr1 = vfp_reg_ptr(true, rd); - ptr2 = vfp_reg_ptr(true, rn); - ptr3 = vfp_reg_ptr(true, rm); - switch (size) { - case 0: - gen_helper_crypto_sha256h(ptr1, ptr2, ptr3); - break; - case 1: - gen_helper_crypto_sha256h2(ptr1, ptr2, ptr3); - break; - case 2: - gen_helper_crypto_sha256su1(ptr1, ptr2, ptr3); - break; - } - } - tcg_temp_free_ptr(ptr1); - tcg_temp_free_ptr(ptr2); - tcg_temp_free_ptr(ptr3); - return 0; - case NEON_3R_VPADD_VQRDMLAH: if (!u) { break; /* VPADD */ @@ -5496,6 +5453,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_VMUL: case NEON_3R_VML: case NEON_3R_VSHL: + case NEON_3R_SHA: /* Already handled by decodetree */ return 1; } From patchwork Tue May 12 16:38:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 186554 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp108651ilb; Tue, 12 May 2020 09:43:26 -0700 (PDT) X-Google-Smtp-Source: APiQypLIrFyUYZOLs/9DSOs9WWwEiULnGhS3sgalRRuFRGv21Jl2c+VS1z+yyjwb7wUaMLUE2f3J X-Received: by 2002:ac8:544e:: with SMTP id d14mr23677235qtq.283.1589301806365; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:10 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 03/17] target/arm: Convert Neon 64-bit element 3-reg-same insns Date: Tue, 12 May 2020 17:38:50 +0100 Message-Id: <20200512163904.10918-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the 64-bit element insns in the 3-reg-same group to decodetree. This covers VQSHL, VRSHL and VQRSHL where size==0b11. Signed-off-by: Peter Maydell --- target/arm/neon-dp.decode | 21 ++++++++++++++++++ target/arm/translate-neon.inc.c | 24 +++++++++++++++++++++ target/arm/translate.c | 38 ++------------------------------- 3 files changed, 47 insertions(+), 36 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 68b0a44793f..fe649038547 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -73,6 +73,27 @@ VCGE_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same_rev VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same_rev +# Insns operating on 64-bit elements (size!=0b11 handled elsewhere) +# The _rev suffix indicates that Vn and Vm are reversed. This is +# the case for shifts. In the Arm ARM these insns are documented +# with the Vm and Vn fields in their usual places, but in the +# assembly the operands are listed "backwards", ie in the order +# Dd, Dm, Dn where other insns use Dd, Dn, Dm. For QEMU we choose +# to consider Vm and Vm as being in different fields in the insn, +# which allows us to avoid special-casing shifts in the trans_ +# function code (where we would otherwise need to manually swap +# the operands over to call Neon helper functions that are shared +# with AArch64 which does not have this odd reversed-operand situation). +@3same_64_rev .... ... . . . 11 .... .... .... . q:1 . . .... \ + &3same vm=%vn_dp vn=%vm_dp vd=%vd_dp size=3 + +VQSHL_S64_3s 1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev +VQSHL_U64_3s 1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev +VRSHL_S64_3s 1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev +VRSHL_U64_3s 1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev +VQRSHL_S64_3s 1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev +VQRSHL_U64_3s 1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev + VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same VMIN_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index 03b3337e460..05c6dcdc9b9 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -825,3 +825,27 @@ static bool trans_SHA256SU1_3s(DisasContext *s, arg_SHA256SU1_3s *a) return true; } + +#define DO_3SAME_64(INSN, FUNC) \ + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ + uint32_t rn_ofs, uint32_t rm_ofs, \ + uint32_t oprsz, uint32_t maxsz) \ + { \ + static const GVecGen3 op = { .fni8 = FUNC }; \ + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &op); \ + } \ + DO_3SAME(INSN, gen_##INSN##_3s) + +#define DO_3SAME_64_ENV(INSN, FUNC) \ + static void gen_##INSN##_elt(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) \ + { \ + FUNC(d, cpu_env, n, m); \ + } \ + DO_3SAME_64(INSN, gen_##INSN##_elt) + +DO_3SAME_64(VRSHL_S64, gen_helper_neon_rshl_s64) +DO_3SAME_64(VRSHL_U64, gen_helper_neon_rshl_u64) +DO_3SAME_64_ENV(VQSHL_S64, gen_helper_neon_qshl_s64) +DO_3SAME_64_ENV(VQSHL_U64, gen_helper_neon_qshl_u64) +DO_3SAME_64_ENV(VQRSHL_S64, gen_helper_neon_qrshl_s64) +DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64) diff --git a/target/arm/translate.c b/target/arm/translate.c index ee2b8d6f6e3..1ce3e182867 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5459,42 +5459,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } if (size == 3) { - /* 64-bit element instructions. */ - for (pass = 0; pass < (q ? 2 : 1); pass++) { - neon_load_reg64(cpu_V0, rn + pass); - neon_load_reg64(cpu_V1, rm + pass); - switch (op) { - case NEON_3R_VQSHL: - if (u) { - gen_helper_neon_qshl_u64(cpu_V0, cpu_env, - cpu_V1, cpu_V0); - } else { - gen_helper_neon_qshl_s64(cpu_V0, cpu_env, - cpu_V1, cpu_V0); - } - break; - case NEON_3R_VRSHL: - if (u) { - gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0); - } else { - gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0); - } - break; - case NEON_3R_VQRSHL: - if (u) { - gen_helper_neon_qrshl_u64(cpu_V0, cpu_env, - cpu_V1, cpu_V0); - } else { - gen_helper_neon_qrshl_s64(cpu_V0, cpu_env, - cpu_V1, cpu_V0); - } - break; - default: - abort(); - } - neon_store_reg64(cpu_V0, rd + pass); - } - return 0; + /* 64-bit element instructions: handled by decodetree */ + return 1; } pairwise = 0; switch (op) { From patchwork Tue May 12 16:38:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 186551 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp106335ilb; Tue, 12 May 2020 09:40:17 -0700 (PDT) X-Google-Smtp-Source: APiQypJYRTMebJG+xcxnU5QTcvB3/lCbF70iEWdMf9j+WKrZrrd2TxEYYB3ggL6gUAkYIhMoxJp8 X-Received: by 2002:ac8:75c1:: with SMTP id z1mr23366858qtq.281.1589301617233; Tue, 12 May 2020 09:40:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589301617; cv=none; d=google.com; s=arc-20160816; b=UM6Wq/xayS5FPv7zy69B8qnui27Bcx9w6WotaeneeFQRfbQsYAVVKg7x3QQnA1NdzW hUyP/gKcafmDAhc+V4jO8x6auv7o9HbmeNEQ5jwrKR/+am6e5ooPkwkOprsuPlcZ3mkA S35B+LJJQbhzyjVswnpw4BNJPgIH7PLrUE5jA8Wm/CD0UTcDTCdZ4acQyY7o1ASHLfEX ucONt8k++E/VDFrxx2Ppdx5HlsOGKf+/ofbW7bXSUQAowO4BS+LYnhD/Zv+4AROY86Tu VacsCs3OTaQEWVHU6KnqTIznUtNj4ye9f9Dy+JdI+Mx2lqzVQfp+f22ukX47gKwDIOLE QFhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WtBRFIcGQ2KxMUWXVFcqCaZ+mGBUmkZ1KykSMd1Jqr0=; b=YGfGLjY75HHFYRvXUcEZQHZUVXbSdzr3h9N0CFxBCtQ2oQXlpq/pHTwT8/2onn6tb6 VXqVVlSVe4elfFvB/aScQaRDN3zfWfVMToZmLlKyWC0mnXorQ6W9fkPjb1ets5WXpXTP dulOYpUWIeXSQwjcAcxCs5l9hdMGGcs4aX1dpsR1EmsZsxaf0Mu4lrnDquW0lc2hvZZQ out9+LuUZtWoF5Jz34PP2gyiMOfjFOvd2qQT53/AsVNrOQuWXbofev1ZIbLDTB6u16yt CK0EIl0icsN7/Vb6x9XioNL+7CG3wJY1YwxXJOwV+AB4VCQVFQd3IfP4PT3kNDeBNpyj onAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CGmcPMrm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:11 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 04/17] target/arm: Convert Neon VHADD 3-reg-same insns Date: Tue, 12 May 2020 17:38:51 +0100 Message-Id: <20200512163904.10918-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the Neon VHADD insns in the 3-reg-same group to decodetree. Signed-off-by: Peter Maydell --- target/arm/neon-dp.decode | 2 ++ target/arm/translate-neon.inc.c | 24 ++++++++++++++++++++++++ target/arm/translate.c | 4 +--- 3 files changed, 27 insertions(+), 3 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index fe649038547..3432aacfe90 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -42,6 +42,8 @@ @3same .... ... . . . size:2 .... .... .... . q:1 . . .... \ &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp +VHADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same +VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same VQADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index 05c6dcdc9b9..0418a84a7de 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -849,3 +849,27 @@ DO_3SAME_64_ENV(VQSHL_S64, gen_helper_neon_qshl_s64) DO_3SAME_64_ENV(VQSHL_U64, gen_helper_neon_qshl_u64) DO_3SAME_64_ENV(VQRSHL_S64, gen_helper_neon_qrshl_s64) DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64) + +#define DO_3SAME_32(INSN, FUNC) \ + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ + uint32_t rn_ofs, uint32_t rm_ofs, \ + uint32_t oprsz, uint32_t maxsz) \ + { \ + static const GVecGen3 ops[4] = { \ + { .fni4 = gen_helper_neon_##FUNC##8 }, \ + { .fni4 = gen_helper_neon_##FUNC##16 }, \ + { .fni4 = gen_helper_neon_##FUNC##32 }, \ + { 0 }, \ + }; \ + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece]); \ + } \ + static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ + { \ + if (a->size > 2) { \ + return false; \ + } \ + return do_3same(s, a, gen_##INSN##_3s); \ + } + +DO_3SAME_32(VHADD_S, hadd_s) +DO_3SAME_32(VHADD_U, hadd_u) diff --git a/target/arm/translate.c b/target/arm/translate.c index 1ce3e182867..8d856ccfe96 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5454,6 +5454,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_VML: case NEON_3R_VSHL: case NEON_3R_SHA: + case NEON_3R_VHADD: /* Already handled by decodetree */ return 1; } @@ -5534,9 +5535,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tmp2 = neon_load_reg(rm, pass); } switch (op) { - case NEON_3R_VHADD: - GEN_NEON_INTEGER_OP(hadd); - break; case NEON_3R_VRHADD: GEN_NEON_INTEGER_OP(rhadd); break; From patchwork Tue May 12 16:38:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 186555 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp108666ilb; Tue, 12 May 2020 09:43:27 -0700 (PDT) X-Google-Smtp-Source: APiQypKtYSfm5GiW3BuABjK69wpWHVgqPspgleFflyZLuGzmG7TYW6SdlZEiM3pmgI+xmfq+cp1s X-Received: by 2002:a0c:f214:: with SMTP id h20mr11982502qvk.200.1589301807415; Tue, 12 May 2020 09:43:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589301807; cv=none; d=google.com; s=arc-20160816; b=liIbVpBqWjA3pKsADZP54wh8hXW5dmzKcYTlPxSo/3X89Nnjk/ObCjtWM0YVwqFIhk W1He3arCtcSTbmwv2V+600zCiJRIHhoV8sEkuZ/OWHFwdCK5X7/qO0UhCYywrmL59z8S lfa611/+9nRtqgBylQbYiWDY//PZbMNjclaByqXXbAq+UCgAWQKNhxACuW7iYWZ7bxGT G07IZzg/zAfNFn2u1OEEz3iO7SR0afOV1TtAKZjVCIMlAnIknW7Gx22k4vMfj6kGuHea 7kAgbVAykGYp9sgmTrJ0+8J+5JbRHJwxvJzi7ub25JZNIk5gINA5nsOO1azSVC3jZhKz 8Q2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gZbv4QYcMc4ag+mpEYLSIdSn4AsHk1XrMWDwADXwYkg=; b=0fLcpTrvKhsMXW8AgzK6fwATt2ClzLzYF0NNbqg122KcmscIi+hDyzWnXOvooigAnJ 2knqpeI1A3FH+dHEGke9f1domv3MAGy1AK+NEZ/70Zj9UZ2agXnDb2mH00ROn7O6aFpK qdHmoWAQHL1z1Xr5ClKB1gNi7sR/VH90hpXaJR9izcFCcqCt5njwHKTuk7jGi4iL4Qo/ HaOoqAdVMXb9XWrTlgyevyfb4C8luDA0kr6zc3rurzXyfqPI05jtUXlI2b5/AmkATlne s3fwc0gWAh6oEcMiQAfZF6MHKz3dVNLup15wIhoJgEfuI3wu/59wYC8/Cg+Q6Lb8H4Pl wzGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xMMnD5DE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:13 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 05/17] target/arm: Convert Neon VABA/VABD 3-reg-same to decodetree Date: Tue, 12 May 2020 17:38:52 +0100 Message-Id: <20200512163904.10918-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the Neon VABA and VABD insns in the 3-reg-same group to decodetree. Signed-off-by: Peter Maydell --- target/arm/neon-dp.decode | 6 ++++++ target/arm/translate-neon.inc.c | 4 ++++ target/arm/translate.c | 22 ++-------------------- 3 files changed, 12 insertions(+), 20 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 3432aacfe90..25c08a4170d 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -101,6 +101,12 @@ VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same VMIN_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same VMIN_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same +VABD_S_3s 1111 001 0 0 . .. .... .... 0111 . . . 0 .... @3same +VABD_U_3s 1111 001 1 0 . .. .... .... 0111 . . . 0 .... @3same + +VABA_S_3s 1111 001 0 0 . .. .... .... 0111 . . . 1 .... @3same +VABA_U_3s 1111 001 1 0 . .. .... .... 0111 . . . 1 .... @3same + VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index 0418a84a7de..20f0f2c8d83 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -641,6 +641,10 @@ DO_3SAME_NO_SZ_3(VMUL, tcg_gen_gvec_mul) DO_3SAME_NO_SZ_3(VMLA, gen_gvec_mla) DO_3SAME_NO_SZ_3(VMLS, gen_gvec_mls) DO_3SAME_NO_SZ_3(VTST, gen_gvec_cmtst) +DO_3SAME_NO_SZ_3(VABD_S, gen_gvec_sabd) +DO_3SAME_NO_SZ_3(VABA_S, gen_gvec_saba) +DO_3SAME_NO_SZ_3(VABD_U, gen_gvec_uabd) +DO_3SAME_NO_SZ_3(VABA_U, gen_gvec_uaba) #define DO_3SAME_CMP(INSN, COND) \ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ diff --git a/target/arm/translate.c b/target/arm/translate.c index 8d856ccfe96..2c842df4451 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5421,26 +5421,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) /* VQRDMLSH : handled by decodetree */ return 1; - case NEON_3R_VABD: - if (u) { - gen_gvec_uabd(size, rd_ofs, rn_ofs, rm_ofs, - vec_size, vec_size); - } else { - gen_gvec_sabd(size, rd_ofs, rn_ofs, rm_ofs, - vec_size, vec_size); - } - return 0; - - case NEON_3R_VABA: - if (u) { - gen_gvec_uaba(size, rd_ofs, rn_ofs, rm_ofs, - vec_size, vec_size); - } else { - gen_gvec_saba(size, rd_ofs, rn_ofs, rm_ofs, - vec_size, vec_size); - } - return 0; - case NEON_3R_VADD_VSUB: case NEON_3R_LOGIC: case NEON_3R_VMAX: @@ -5455,6 +5435,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_VSHL: case NEON_3R_SHA: case NEON_3R_VHADD: + case NEON_3R_VABD: + case NEON_3R_VABA: /* Already handled by decodetree */ return 1; } From patchwork Tue May 12 16:38:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 186558 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp110888ilb; Tue, 12 May 2020 09:46:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx9D910O9O4ywNFsDDFw8Xxuta+WP2QUXeJCwwGQpekphfKw4YswIYWilyQLKlnkY1GqOV1 X-Received: by 2002:a37:8782:: with SMTP id j124mr6787320qkd.349.1589301982007; Tue, 12 May 2020 09:46:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589301982; cv=none; d=google.com; s=arc-20160816; b=mGsSWQt1v5jVDRgmZ9/tF7yANw+ailpqBKdjkaWHp/OQCYbvhegfu/T05cOKb1LU9Q /XEPRFF2Wh2VTl6QLl0R5EraRaEXBS5uJ4SjpU47V6t8B2n8W/6iG5xDsuiHbR8JAnlR v+h96lEX2a6j0r40HkVSOi7P6YRy+0puafceU0i6JowMk31XJ35PXEmu6wgU5Vo6WATR xSHOfnysBewQ28E3AKMQOwSqX8w5DJyonKVPbhsxtMiDY1eFm9gZk0yGfj0F7jPJeT6+ CMn8wD0NAJNVOBUZs6vAIcFt0mHEMgQ5r+dcTi3renuEB1c68092xCr284yZdpPEdtSJ u9Ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yPOdog2d2dwbfs28fCvHLLSNJsF30PqsU53nWUWzmY4=; b=mhh2fdRXCjk6NDvK+D/R59olEL7aAMl3kStsGS/RDKwQIilxymyKDPBQ19f9JLes00 /i3d0ZA6ljHwlIq0e1Ee1W6eEup5W4wb7kKwVpuK2PfOtACRH4MGlQXZ9onJWpQNqJYB QClZKB5AN9h98P8QcuCqm77aOo6fJCfJmVK/A+RTJq+wCH2UkASosD4sszbU+Jx44uVT slRHJi5yrYnrdWYtQmaU042C89s5KltPSME2yh7A8r31BPlgF6XTgyLvrhKGY7x3jON2 m608ZaGL5UIlCO8O5Z+r1FMr7B4qGo+UMiRQN4EFS6yeRnM8jtfXZh7P69rm8Iujui17 Ip7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iNkpzGLP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:14 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 06/17] target/arm: Convert Neon VRHADD, VHSUB 3-reg-same insns to decodetree Date: Tue, 12 May 2020 17:38:53 +0100 Message-Id: <20200512163904.10918-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the Neon VRHADD and VHSUB 3-reg-same insns to decodetree. (These are all the other insns in 3-reg-same which were using GEN_NEON_INTEGER_OP() and which are not pairwise or reversed-operands.) Signed-off-by: Peter Maydell --- target/arm/neon-dp.decode | 6 ++++++ target/arm/translate-neon.inc.c | 4 ++++ target/arm/translate.c | 8 ++------ 3 files changed, 12 insertions(+), 6 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 25c08a4170d..353cb1f4992 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -47,6 +47,9 @@ VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same VQADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same +VRHADD_S_3s 1111 001 0 0 . .. .... .... 0001 . . . 0 .... @3same +VRHADD_U_3s 1111 001 1 0 . .. .... .... 0001 . . . 0 .... @3same + @3same_logic .... ... . . . .. .... .... .... . q:1 .. .... \ &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 @@ -59,6 +62,9 @@ VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic +VHSUB_S_3s 1111 001 0 0 . .. .... .... 0010 . . . 0 .... @3same +VHSUB_U_3s 1111 001 1 0 . .. .... .... 0010 . . . 0 .... @3same + VQSUB_S_3s 1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same VQSUB_U_3s 1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index 20f0f2c8d83..e9da47171c6 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -877,3 +877,7 @@ DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64) DO_3SAME_32(VHADD_S, hadd_s) DO_3SAME_32(VHADD_U, hadd_u) +DO_3SAME_32(VHSUB_S, hsub_s) +DO_3SAME_32(VHSUB_U, hsub_u) +DO_3SAME_32(VRHADD_S, rhadd_s) +DO_3SAME_32(VRHADD_U, rhadd_u) diff --git a/target/arm/translate.c b/target/arm/translate.c index 2c842df4451..ebb899d846e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5435,6 +5435,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_VSHL: case NEON_3R_SHA: case NEON_3R_VHADD: + case NEON_3R_VRHADD: + case NEON_3R_VHSUB: case NEON_3R_VABD: case NEON_3R_VABA: /* Already handled by decodetree */ @@ -5517,12 +5519,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tmp2 = neon_load_reg(rm, pass); } switch (op) { - case NEON_3R_VRHADD: - GEN_NEON_INTEGER_OP(rhadd); - break; - case NEON_3R_VHSUB: - GEN_NEON_INTEGER_OP(hsub); - break; case NEON_3R_VQSHL: GEN_NEON_INTEGER_OP_ENV(qshl); break; From patchwork Tue May 12 16:38:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 186561 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp113302ilb; Tue, 12 May 2020 09:49:47 -0700 (PDT) X-Google-Smtp-Source: APiQypLKOm2kbZJ7lK1Ev44KZMrhnHkTdUTg+uaB7wueVkEwg6Moa5QoZwL24YomkzDaHDD/Me2u X-Received: by 2002:a37:9ac6:: with SMTP id c189mr21560804qke.398.1589302187059; Tue, 12 May 2020 09:49:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589302187; cv=none; d=google.com; s=arc-20160816; b=HJvczSmwJ6zUg16nn+GFDq68dmEQJ6iDu5DUzzWA7E94efaixzoxIMbmzSD0aornhv zUD7ez+IixNnuIKYhmL4q4UXmXzTxrXWBdT7RFtrVzPXvmi42KzbsMdUnxAJsJrUpOL7 QPvga55Cr3UjgCGAlr8exTRh1NAEekeobK94Pmb2m/b40UEFKFDVk86PFR6a61R+xGDA i+sJHvhddc1lsyrC1Q8EesKDSLq46AzhEGZc+sCx519vAWkZyOnFSrmUI9ex0Q8V8SwO ABVRazOTYncfuJk9lDGNzCxj1QFgBv1y+EjAYI7+FCZeF73sw6534BOJmOM3fxYYgaFl UWmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PpEsdABitILB0n477zrURAQAbSkegxBFrS84gleg/2g=; b=II2bG9arRf3tRh3Yk/c5Ya3OUz1Ny+BOb/QzldtaXVsVrmxOjlVIlhEc7hZaiG80Zx T8l1rX7hJuFZmaEqFbiHKKwXzG5gIbxlhcoXLQsMiRbXwoW8k3rtY4TgHr9YMm03oA4W hSOq3PFqIf2vipZfqxuYq2yOWUBKltI5c3tknYKv28OgpxLk2Y2oekQigrH78cP1dBeh 5/ldbBkeKKKaNFFyFB7r6KJHrC0uJzSWbwkOzoi6nDxey4GyRTFoo1/xcLKIv1zhwxim /LCfu15RYm2mp42SCVOywMAqhzLHK6UM+vv5G5Q7AIzgKIBOc0nWE9U9xf0PjGAz2kJ3 wBRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XCaxqqlJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 07/17] target/arm: Convert Neon VQSHL, VRSHL, VQRSHL 3-reg-same insns to decodetree Date: Tue, 12 May 2020 17:38:54 +0100 Message-Id: <20200512163904.10918-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the VQSHL, VRSHL and VQRSHL insns in the 3-reg-same group to decodetree. We have already implemented the size==0b11 case of these insns; this commit handles the remaining sizes. Signed-off-by: Peter Maydell --- target/arm/neon-dp.decode | 47 +++++++++++++++++++++++---------- target/arm/translate-neon.inc.c | 43 ++++++++++++++++++++++++++++++ target/arm/translate.c | 22 +++------------ 3 files changed, 79 insertions(+), 33 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 353cb1f4992..e0da5a39fc2 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -74,14 +74,6 @@ VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same VCGE_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same # The shift operations are of the form Vd = Vm << Vn. -# By reversing the names of the fields here, we can use standard expanders. -@3same_rev .... ... . . . size:2 .... .... .... . q:1 . . .... \ - &3same vn=%vm_dp vm=%vn_dp vd=%vd_dp - -VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same_rev -VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same_rev - -# Insns operating on 64-bit elements (size!=0b11 handled elsewhere) # The _rev suffix indicates that Vn and Vm are reversed. This is # the case for shifts. In the Arm ARM these insns are documented # with the Vm and Vn fields in their usual places, but in the @@ -92,15 +84,42 @@ VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same_rev # function code (where we would otherwise need to manually swap # the operands over to call Neon helper functions that are shared # with AArch64 which does not have this odd reversed-operand situation). +@3same_rev .... ... . . . size:2 .... .... .... . q:1 . . .... \ + &3same vn=%vm_dp vm=%vn_dp vd=%vd_dp + +VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same_rev +VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same_rev + +# Insns operating on 64-bit elements (size!=0b11 handled elsewhere) +# The _rev suffix indicates that Vn and Vm are reversed (as explained +# by the comment for the @3same_rev format). @3same_64_rev .... ... . . . 11 .... .... .... . q:1 . . .... \ &3same vm=%vn_dp vn=%vm_dp vd=%vd_dp size=3 -VQSHL_S64_3s 1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev -VQSHL_U64_3s 1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev -VRSHL_S64_3s 1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev -VRSHL_U64_3s 1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev -VQRSHL_S64_3s 1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev -VQRSHL_U64_3s 1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev +{ + VQSHL_S64_3s 1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev + VQSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_rev +} +{ + VQSHL_U64_3s 1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev + VQSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_rev +} +{ + VRSHL_S64_3s 1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev + VRSHL_S_3s 1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_rev +} +{ + VRSHL_U64_3s 1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev + VRSHL_U_3s 1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_rev +} +{ + VQRSHL_S64_3s 1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev + VQRSHL_S_3s 1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_rev +} +{ + VQRSHL_U64_3s 1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev + VQRSHL_U_3s 1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_rev +} VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index e9da47171c6..7097c18f334 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -875,9 +875,52 @@ DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64) return do_3same(s, a, gen_##INSN##_3s); \ } +/* + * Some helper functions need to be passed the cpu_env. In order + * to use those with the gvec APIs like tcg_gen_gvec_3() we need + * to create wrapper functions whose prototype is a NeonGenTwoOpFn() + * and which call a NeonGenTwoOpEnvFn(). + */ +#define WRAP_ENV_FN(WRAPNAME, FUNC) \ + static void WRAPNAME(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m) \ + { \ + FUNC(d, cpu_env, n, m); \ + } + +#define DO_3SAME_32_ENV(INSN, FUNC) \ + WRAP_ENV_FN(gen_##INSN##_tramp8, gen_helper_neon_##FUNC##8); \ + WRAP_ENV_FN(gen_##INSN##_tramp16, gen_helper_neon_##FUNC##16); \ + WRAP_ENV_FN(gen_##INSN##_tramp32, gen_helper_neon_##FUNC##32); \ + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ + uint32_t rn_ofs, uint32_t rm_ofs, \ + uint32_t oprsz, uint32_t maxsz) \ + { \ + static const GVecGen3 ops[4] = { \ + { .fni4 = gen_##INSN##_tramp8 }, \ + { .fni4 = gen_##INSN##_tramp16 }, \ + { .fni4 = gen_##INSN##_tramp32 }, \ + { 0 }, \ + }; \ + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece]); \ + } \ + static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ + { \ + if (a->size > 2) { \ + return false; \ + } \ + return do_3same(s, a, gen_##INSN##_3s); \ + } + DO_3SAME_32(VHADD_S, hadd_s) DO_3SAME_32(VHADD_U, hadd_u) DO_3SAME_32(VHSUB_S, hsub_s) DO_3SAME_32(VHSUB_U, hsub_u) DO_3SAME_32(VRHADD_S, rhadd_s) DO_3SAME_32(VRHADD_U, rhadd_u) +DO_3SAME_32(VRSHL_S, rshl_s) +DO_3SAME_32(VRSHL_U, rshl_u) + +DO_3SAME_32_ENV(VQSHL_S, qshl_s) +DO_3SAME_32_ENV(VQSHL_U, qshl_u) +DO_3SAME_32_ENV(VQRSHL_S, qrshl_s) +DO_3SAME_32_ENV(VQRSHL_U, qrshl_u) diff --git a/target/arm/translate.c b/target/arm/translate.c index ebb899d846e..3aabb18720b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5439,6 +5439,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_VHSUB: case NEON_3R_VABD: case NEON_3R_VABA: + case NEON_3R_VQSHL: + case NEON_3R_VRSHL: + case NEON_3R_VQRSHL: /* Already handled by decodetree */ return 1; } @@ -5449,17 +5452,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } pairwise = 0; switch (op) { - case NEON_3R_VQSHL: - case NEON_3R_VRSHL: - case NEON_3R_VQRSHL: - { - int rtmp; - /* Shift instruction operands are reversed. */ - rtmp = rn; - rn = rm; - rm = rtmp; - } - break; case NEON_3R_VPADD_VQRDMLAH: case NEON_3R_VPMAX: case NEON_3R_VPMIN: @@ -5519,14 +5511,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tmp2 = neon_load_reg(rm, pass); } switch (op) { - case NEON_3R_VQSHL: - GEN_NEON_INTEGER_OP_ENV(qshl); - break; - case NEON_3R_VRSHL: - GEN_NEON_INTEGER_OP(rshl); - break; - case NEON_3R_VQRSHL: - GEN_NEON_INTEGER_OP_ENV(qrshl); break; case NEON_3R_VPMAX: GEN_NEON_INTEGER_OP(pmax); From patchwork Tue May 12 16:38:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 186557 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp110438ilb; Tue, 12 May 2020 09:45:49 -0700 (PDT) X-Google-Smtp-Source: APiQypLW2IiEhAPSxQTpIUVcRyPJLns0qozD+wx3h69I8dyQqn4NNYYMFrHEZds8CmmmKzULUai3 X-Received: by 2002:aed:3949:: with SMTP id l67mr11191114qte.313.1589301949672; Tue, 12 May 2020 09:45:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589301949; cv=none; d=google.com; s=arc-20160816; b=FXafg+w7ccnFy59fZhHe6eyHZ2Y26fNrimL10iNAOPzzo41aOb5rdaLLIPyYJe1tpw qV3tdFvsXJf7Ub8fQvpIEurtrOOWL93eshWa6HomXnb524DS1Ps0EG4J5X7SnEfqrPDe FJ/jj6UzgI7rkPEvYkHs37GI3UhbH8dKuykP6fEgiOyVH8QNIAmxAceOAV2tcVZQoDc9 Q8whjjPDG1otp1img+4CHKVjVp81IWs6B0lyxZMDUMZKfSVnRzZ/8vlaQyjxoJ9mqrz8 ZXEX/yzQLnDpqGpknT6JOpu5a1OGqgmzJY4EIfnPrNPFqLcnQOJYWwShEvtrYiFuP5/Z j9bA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DO73kxC/ieb1z/wK6QeuNNqcIXsVWMQQ5sDynNEanWc=; b=Hkoi/yEyAd0XhqEvp545Ip1VyM7GdH5T5dZ9g8uXZSKDRKPzuNK5n7AC5MWdq8DcIS VqzsSRQ8DUZRyTFBy1bbSoAlRGQwDUTt3Xg+z0/DGGeMq2kztq79A/sJGlEmJcKCXM+S gCXa5Di085YNgPcXRL4lbAojdpKvNAk5/Gy95RXMg905AHMW1o3/B5V7G2WvQEWjE2bF pDNkNel/8Bzy0JX9FPv3ANuWdBNEEzSoS0iFh5Qx3Y/jI4qXLc7m4Did5UJoHF+TjhoN vcG6v2MvtUTHCPyfniRDWc6l/EMVFGZrC83maRrxz74yYuhf6EXhmiY1Y9+rN+5BfB1f So+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MN77JafK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:17 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 08/17] target/arm: Convert Neon VPMAX/VPMIN 3-reg-same insns to decodetree Date: Tue, 12 May 2020 17:38:55 +0100 Message-Id: <20200512163904.10918-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the Neon integer VPMAX and VPMIN 3-reg-same insns to decodetree. These are 'pairwise' operations. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 9 +++++ target/arm/translate-neon.inc.c | 71 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 17 +------- 3 files changed, 82 insertions(+), 15 deletions(-) -- 2.20.1 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index e0da5a39fc2..03f39a0b44b 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -42,6 +42,9 @@ @3same .... ... . . . size:2 .... .... .... . q:1 . . .... \ &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp +@3same_q0 .... ... . . . size:2 .... .... .... . 0 . . .... \ + &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0 + VHADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same @@ -144,6 +147,12 @@ VMLS_3s 1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same VMUL_3s 1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same VMUL_p_3s 1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same +VPMAX_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 0 .... @3same_q0 +VPMAX_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 0 .... @3same_q0 + +VPMIN_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 1 .... @3same_q0 +VPMIN_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 1 .... @3same_q0 + VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same SHA1_3s 1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \ diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index 7097c18f334..7db6b856598 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -924,3 +924,74 @@ DO_3SAME_32_ENV(VQSHL_S, qshl_s) DO_3SAME_32_ENV(VQSHL_U, qshl_u) DO_3SAME_32_ENV(VQRSHL_S, qrshl_s) DO_3SAME_32_ENV(VQRSHL_U, qrshl_u) + +static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn) +{ + /* Operations handled pairwise 32 bits at a time */ + TCGv_i32 tmp, tmp2, tmp3; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (a->size == 3) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + assert(a->q == 0); /* enforced by decode patterns */ + + /* + * Note that we have to be careful not to clobber the source operands + * in the "vm == vd" case by storing the result of the first pass too + * early. Since Q is 0 there are always just two passes, so instead + * of a complicated loop over each pass we just unroll. + */ + tmp = neon_load_reg(a->vn, 0); + tmp2 = neon_load_reg(a->vn, 1); + fn(tmp, tmp, tmp2); + tcg_temp_free_i32(tmp2); + + tmp3 = neon_load_reg(a->vm, 0); + tmp2 = neon_load_reg(a->vm, 1); + fn(tmp3, tmp3, tmp2); + tcg_temp_free_i32(tmp2); + + neon_store_reg(a->vd, 0, tmp); + neon_store_reg(a->vd, 1, tmp3); + return true; +} + +#define DO_3SAME_PAIR(INSN, func) \ + static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ + { \ + static NeonGenTwoOpFn * const fns[] = { \ + gen_helper_neon_##func##8, \ + gen_helper_neon_##func##16, \ + gen_helper_neon_##func##32, \ + }; \ + if (a->size > 2) { \ + return false; \ + } \ + return do_3same_pair(s, a, fns[a->size]); \ + } + +/* 32-bit pairwise ops end up the same as the elementwise versions. */ +#define gen_helper_neon_pmax_s32 tcg_gen_smax_i32 +#define gen_helper_neon_pmax_u32 tcg_gen_umax_i32 +#define gen_helper_neon_pmin_s32 tcg_gen_smin_i32 +#define gen_helper_neon_pmin_u32 tcg_gen_umin_i32 + +DO_3SAME_PAIR(VPMAX_S, pmax_s) +DO_3SAME_PAIR(VPMIN_S, pmin_s) +DO_3SAME_PAIR(VPMAX_U, pmax_u) +DO_3SAME_PAIR(VPMIN_U, pmin_u) diff --git a/target/arm/translate.c b/target/arm/translate.c index 3aabb18720b..82be4d40282 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3011,12 +3011,6 @@ static inline void gen_neon_rsb(int size, TCGv_i32 t0, TCGv_i32 t1) } } -/* 32-bit pairwise ops end up the same as the elementwise versions. */ -#define gen_helper_neon_pmax_s32 tcg_gen_smax_i32 -#define gen_helper_neon_pmax_u32 tcg_gen_umax_i32 -#define gen_helper_neon_pmin_s32 tcg_gen_smin_i32 -#define gen_helper_neon_pmin_u32 tcg_gen_umin_i32 - #define GEN_NEON_INTEGER_OP_ENV(name) do { \ switch ((size << 1) | u) { \ case 0: \ @@ -5442,6 +5436,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_VQSHL: case NEON_3R_VRSHL: case NEON_3R_VQRSHL: + case NEON_3R_VPMAX: + case NEON_3R_VPMIN: /* Already handled by decodetree */ return 1; } @@ -5453,8 +5449,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) pairwise = 0; switch (op) { case NEON_3R_VPADD_VQRDMLAH: - case NEON_3R_VPMAX: - case NEON_3R_VPMIN: pairwise = 1; break; case NEON_3R_FLOAT_ARITH: @@ -5511,13 +5505,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tmp2 = neon_load_reg(rm, pass); } switch (op) { - break; - case NEON_3R_VPMAX: - GEN_NEON_INTEGER_OP(pmax); - break; - case NEON_3R_VPMIN: - GEN_NEON_INTEGER_OP(pmin); - break; case NEON_3R_VQDMULH_VQRDMULH: /* Multiply high. */ if (!u) { /* VQDMULH */ switch (size) { From patchwork Tue May 12 16:38:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 186559 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp112234ilb; Tue, 12 May 2020 09:48:09 -0700 (PDT) X-Google-Smtp-Source: APiQypIV6WRprqpd/yqL2M4fT7Flu9TTTFdXwCDXvM1BaYkQSyJpmHQuOoPxpDKas45Q9uV4yjjS X-Received: by 2002:a37:a342:: with SMTP id m63mr21117989qke.360.1589302089035; Tue, 12 May 2020 09:48:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589302089; cv=none; d=google.com; s=arc-20160816; b=SCRZ9ldeIaq5UVHLeAJqwPYLl52uxcVT+rigqirRlOONoTIbuQghhllbHsxjATGCtR 03u+hWdpsphpQ5nvQvimHQo3SISEI9/BfkwTx4Bkw+pZqkBTAX2jZ4k/7kKd9H0kKaDh YbY/UfnbZBh2MC/gVWe3FWKpQqwwnY+aCt41rXpT5fp3RXO9w5vRaa7RMDDK78iWEFJb PVl9NOucYfWfPMyaoHda5RvGxPWRBn4Jp+TVUzZ0DOGtKfQx67apJJt7hVPApxDZh6wa XLVXhSNgCVY1JZ/KmJtDN5VRt8WX5xeoOC6e8nwhcWLAQO22dR72WiFKvJARkDfC88It FSLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kVCumtOJ/X5yIQDESAlRm3BAiW9FGll9wJVdRpfR4eg=; b=qXOttvgpedJjm9icKqpSauHPa/7qofnlIMhDdDuTKVJuALLFSZ0LNt4Hvkslb2Cs3c OmNLAGJeL4Jb7O777vncvqrR2XyPGGpievChPaY9cGdURHBURlYWq5xzlpwOxpZ3Rkrg f8q/clJKyC9v4MEPq+Y8wfCcka06nlwT/2Z54bZ+FPl1pELRn3LANPvNZ8dAqICFV9Ov kW+GKoWe6IyZsvf9Fp5TREgK1P18Ca0+ApVuitt9uNG+afJepDC1aaOmDp2EIO6OXEA4 5ZhRrdh8L4/Nq9PQphLyo+7i0ZNnoFLDpyUx6olHDrUYPIG1umu9ObkrxqZOt+MbURu3 Wmxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gYvfBvPU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:19 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 09/17] target/arm: Convert Neon VPADD 3-reg-same insns to decodetree Date: Tue, 12 May 2020 17:38:56 +0100 Message-Id: <20200512163904.10918-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the Neon integer VPADD 3-reg-same insns to decodetree. These are 'pairwise' operations. (Note that VQRDMLAH, which shares the same primary opcode but has U=1, has already been converted.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 2 ++ target/arm/translate-neon.inc.c | 2 ++ target/arm/translate.c | 19 +------------------ 3 files changed, 5 insertions(+), 18 deletions(-) -- 2.20.1 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 03f39a0b44b..9bbb2dd77e0 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -153,6 +153,8 @@ VPMAX_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 0 .... @3same_q0 VPMIN_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 1 .... @3same_q0 VPMIN_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 1 .... @3same_q0 +VPADD_3s 1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0 + VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same SHA1_3s 1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \ diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index 7db6b856598..e0137364075 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -990,8 +990,10 @@ static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn) #define gen_helper_neon_pmax_u32 tcg_gen_umax_i32 #define gen_helper_neon_pmin_s32 tcg_gen_smin_i32 #define gen_helper_neon_pmin_u32 tcg_gen_umin_i32 +#define gen_helper_neon_padd_u32 tcg_gen_add_i32 DO_3SAME_PAIR(VPMAX_S, pmax_s) DO_3SAME_PAIR(VPMIN_S, pmin_s) DO_3SAME_PAIR(VPMAX_U, pmax_u) DO_3SAME_PAIR(VPMIN_U, pmin_u) +DO_3SAME_PAIR(VPADD, padd_u) diff --git a/target/arm/translate.c b/target/arm/translate.c index 82be4d40282..ce30417014d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5397,13 +5397,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) return 1; } switch (op) { - case NEON_3R_VPADD_VQRDMLAH: - if (!u) { - break; /* VPADD */ - } - /* VQRDMLAH : handled by decodetree */ - return 1; - case NEON_3R_VFM_VQRDMLSH: if (!u) { /* VFM, VFMS */ @@ -5438,6 +5431,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_VQRSHL: case NEON_3R_VPMAX: case NEON_3R_VPMIN: + case NEON_3R_VPADD_VQRDMLAH: /* Already handled by decodetree */ return 1; } @@ -5448,9 +5442,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } pairwise = 0; switch (op) { - case NEON_3R_VPADD_VQRDMLAH: - pairwise = 1; - break; case NEON_3R_FLOAT_ARITH: pairwise = (u && size < 2); /* if VPADD (float) */ break; @@ -5528,14 +5519,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } } break; - case NEON_3R_VPADD_VQRDMLAH: - switch (size) { - case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break; - case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break; - case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break; - default: abort(); - } - break; case NEON_3R_FLOAT_ARITH: /* Floating point arithmetic. */ { TCGv_ptr fpstatus = get_fpstatus_ptr(1); From patchwork Tue May 12 16:38:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 186552 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp106769ilb; Tue, 12 May 2020 09:40:50 -0700 (PDT) X-Google-Smtp-Source: APiQypKSakYtp/Zpxxo+YMyrbZTHyXQrN9Qa3kAlFOmWyDgq0VW0BGoAd1b7FoYO+q93/SggdRjD X-Received: by 2002:ac8:75c1:: with SMTP id z1mr23369539qtq.281.1589301650524; Tue, 12 May 2020 09:40:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589301650; cv=none; d=google.com; s=arc-20160816; b=BQ8touHCQbE1vuxQw0xVi1yWwusOLE9Xmwh5LjSOethS8Uc6GQw6gEkGtK3L44zboC 6BCRU6pa1svmVTo71ykJsYRXuNudebsu4loeQHPsa9a0GNcU6uYEHEP/txrt3ENptcp7 4vW+ywpuZ2C9GAYibwfi0YKeRkot3t2hf52Swfv2obfRqRac2He3A8J7UcR7jyGvntq5 8v26aBJ2yCfgMh938rsx2u5Rt7pAClkQuGcRjUfJ+1q/4xQCajHLgbzdLM8yUpa0f8Or FBl+PonODBnZH7fVRiQBsqOCMjAnsSI24KEsHV0OayPch0wWn5gIO+SwGMUPm3WOPdpY rFTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LFie1FH/ju2YqNiDPeao+ABy38l5WYz9XJznVyORJzE=; b=0BEbG+GgNQBeGg/9953iVVvqdPGJQCyH0bJFG+60lyBSBhkQsNTH+9RQvctah2PWmo mGikr3hcYRVFGOA96GxASdadTFklnpDeIy7sENFgRc9pvy8Ke13MO+3vhiVtxfc3JmEG A/YR8Z8oa+JzT+T5mYb9Po019dt46LAgdR56gGuzLnrR/8fhdYRTPhigFoot4Bq1WAAI BxU/ZH1GpJNsR+KgcuYslotqnkuyBONt3ui/yOmza2qAUHU3uhlYuSSVs3kpnOC/Cr/v CYkmB5h75wKYQO7ZPj2OyfI05YkquHO/umkqvM73p9bx3EtNNkHQtIt9sQ5eGiSyC/aO e1Hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KPYHlz8u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:20 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 10/17] target/arm: Convert Neon VQDMULH/VQRDMULH 3-reg-same to decodetree Date: Tue, 12 May 2020 17:38:57 +0100 Message-Id: <20200512163904.10918-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the Neon VQDMULH and VQRDMULH 3-reg-same insns to decodetree. These are the last integer operations in the 3-reg-same group. Signed-off-by: Peter Maydell --- target/arm/neon-dp.decode | 3 +++ target/arm/translate-neon.inc.c | 24 ++++++++++++++++++++++++ target/arm/translate.c | 24 +----------------------- 3 files changed, 28 insertions(+), 23 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 9bbb2dd77e0..28e8333335d 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -153,6 +153,9 @@ VPMAX_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 0 .... @3same_q0 VPMIN_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 1 .... @3same_q0 VPMIN_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 1 .... @3same_q0 +VQDMULH_3s 1111 001 0 0 . .. .... .... 1011 . . . 0 .... @3same +VQRDMULH_3s 1111 001 1 0 . .. .... .... 1011 . . . 0 .... @3same + VPADD_3s 1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0 VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index e0137364075..f52302f42b1 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -997,3 +997,27 @@ DO_3SAME_PAIR(VPMIN_S, pmin_s) DO_3SAME_PAIR(VPMAX_U, pmax_u) DO_3SAME_PAIR(VPMIN_U, pmin_u) DO_3SAME_PAIR(VPADD, padd_u) + +#define DO_3SAME_VQDMULH(INSN, FUNC) \ + WRAP_ENV_FN(gen_##INSN##_tramp16, gen_helper_neon_##FUNC##_s16); \ + WRAP_ENV_FN(gen_##INSN##_tramp32, gen_helper_neon_##FUNC##_s32); \ + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ + uint32_t rn_ofs, uint32_t rm_ofs, \ + uint32_t oprsz, uint32_t maxsz) \ + { \ + static const GVecGen3 ops[2] = { \ + { .fni4 = gen_##INSN##_tramp16 }, \ + { .fni4 = gen_##INSN##_tramp32 }, \ + }; \ + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece - 1]); \ + } \ + static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ + { \ + if (a->size != 1 && a->size != 2) { \ + return false; \ + } \ + return do_3same(s, a, gen_##INSN##_3s); \ + } + +DO_3SAME_VQDMULH(VQDMULH, qdmulh) +DO_3SAME_VQDMULH(VQRDMULH, qrdmulh) diff --git a/target/arm/translate.c b/target/arm/translate.c index ce30417014d..561cb67286d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5432,6 +5432,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_VPMAX: case NEON_3R_VPMIN: case NEON_3R_VPADD_VQRDMLAH: + case NEON_3R_VQDMULH_VQRDMULH: /* Already handled by decodetree */ return 1; } @@ -5496,29 +5497,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tmp2 = neon_load_reg(rm, pass); } switch (op) { - case NEON_3R_VQDMULH_VQRDMULH: /* Multiply high. */ - if (!u) { /* VQDMULH */ - switch (size) { - case 1: - gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2); - break; - case 2: - gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2); - break; - default: abort(); - } - } else { /* VQRDMULH */ - switch (size) { - case 1: - gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2); - break; - case 2: - gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2); - break; - default: abort(); - } - } - break; case NEON_3R_FLOAT_ARITH: /* Floating point arithmetic. */ { TCGv_ptr fpstatus = get_fpstatus_ptr(1); From patchwork Tue May 12 16:38:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 186563 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp114945ilb; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:22 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 11/17] target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns to decodetree Date: Tue, 12 May 2020 17:38:58 +0100 Message-Id: <20200512163904.10918-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the Neon VADD, VSUB, VABD 3-reg-same insns to decodetree. We already have gvec helpers for addition and subtraction, but must add one for fabd. Signed-off-by: Peter Maydell --- target/arm/helper.h | 3 ++- target/arm/neon-dp.decode | 8 ++++++++ target/arm/neon_helper.c | 7 ------- target/arm/translate-neon.inc.c | 28 ++++++++++++++++++++++++++++ target/arm/translate.c | 10 +++------- target/arm/vec_helper.c | 7 +++++++ 6 files changed, 48 insertions(+), 15 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.h b/target/arm/helper.h index 1857f4ee46a..6e9629c87b0 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -396,7 +396,6 @@ DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32) DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32) DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_3(neon_abd_f32, i32, i32, i32, ptr) DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, ptr) DEF_HELPER_3(neon_cge_f32, i32, i32, i32, ptr) DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, ptr) @@ -595,6 +594,8 @@ DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(gvec_ftsmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_ftsmul_s, TCG_CALL_NO_RWG, diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 28e8333335d..06fb8b96aad 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -45,6 +45,10 @@ @3same_q0 .... ... . . . size:2 .... .... .... . 0 . . .... \ &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0 +# For FP insns the high bit of 'size' is used as part of opcode decode +@3same_fp .... ... . . . . size:1 .... .... .... . q:1 . . .... \ + &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp + VHADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same @@ -170,3 +174,7 @@ SHA256SU1_3s 1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... \ vm=%vm_dp vn=%vn_dp vd=%vd_dp VQRDMLSH_3s 1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same + +VADD_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp +VSUB_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 0 .... @3same_fp +VABD_fp_3s 1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index 2ef75e04c83..b637265691a 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -1825,13 +1825,6 @@ uint64_t HELPER(neon_qneg_s64)(CPUARMState *env, uint64_t x) } /* NEON Float helpers. */ -uint32_t HELPER(neon_abd_f32)(uint32_t a, uint32_t b, void *fpstp) -{ - float_status *fpst = fpstp; - float32 f0 = make_float32(a); - float32 f1 = make_float32(b); - return float32_val(float32_abs(float32_sub(f0, f1, fpst))); -} /* Floating point comparisons produce an integer result. * Note that EQ doesn't signal InvalidOp for QNaNs but GE and GT do. diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index f52302f42b1..540720f5e0d 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1021,3 +1021,31 @@ DO_3SAME_PAIR(VPADD, padd_u) DO_3SAME_VQDMULH(VQDMULH, qdmulh) DO_3SAME_VQDMULH(VQRDMULH, qrdmulh) + +/* + * For all the functions using this macro, size == 1 means fp16, + * which is an architecture extension we don't implement yet. + */ +#define DO_3S_FP_GVEC(INSN,FUNC) \ + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ + uint32_t rn_ofs, uint32_t rm_ofs, \ + uint32_t oprsz, uint32_t maxsz) \ + { \ + TCGv_ptr fpst = get_fpstatus_ptr(1); \ + tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpst, \ + oprsz, maxsz, 0, FUNC); \ + tcg_temp_free_ptr(fpst); \ + } \ + static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \ + { \ + if (a->size != 0) { \ + /* TODO fp16 support */ \ + return false; \ + } \ + return do_3same(s, a, gen_##INSN##_3s); \ + } + + +DO_3S_FP_GVEC(VADD, gen_helper_gvec_fadd_s) +DO_3S_FP_GVEC(VSUB, gen_helper_gvec_fsub_s) +DO_3S_FP_GVEC(VABD, gen_helper_gvec_fabd_s) diff --git a/target/arm/translate.c b/target/arm/translate.c index 561cb67286d..8a94856cd28 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5445,6 +5445,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) switch (op) { case NEON_3R_FLOAT_ARITH: pairwise = (u && size < 2); /* if VPADD (float) */ + if (!pairwise) { + return 1; /* handled by decodetree */ + } break; case NEON_3R_FLOAT_MINMAX: pairwise = u; /* if VPMIN/VPMAX (float) */ @@ -5501,16 +5504,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) { TCGv_ptr fpstatus = get_fpstatus_ptr(1); switch ((u << 2) | size) { - case 0: /* VADD */ case 4: /* VPADD */ gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus); break; - case 2: /* VSUB */ - gen_helper_vfp_subs(tmp, tmp, tmp2, fpstatus); - break; - case 6: /* VABD */ - gen_helper_neon_abd_f32(tmp, tmp, tmp2, fpstatus); - break; default: abort(); } diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index fa33df859e5..50a499299fd 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -691,6 +691,11 @@ static float64 float64_ftsmul(float64 op1, uint64_t op2, float_status *stat) return result; } +static float32 float32_abd(float32 op1, float32 op2, float_status *stat) +{ + return float32_abs(float32_sub(op1, op2, stat)); +} + #define DO_3OP(NAME, FUNC, TYPE) \ void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \ { \ @@ -718,6 +723,8 @@ DO_3OP(gvec_ftsmul_h, float16_ftsmul, float16) DO_3OP(gvec_ftsmul_s, float32_ftsmul, float32) DO_3OP(gvec_ftsmul_d, float64_ftsmul, float64) +DO_3OP(gvec_fabd_s, float32_abd, float32) + #ifdef TARGET_AARCH64 DO_3OP(gvec_recps_h, helper_recpsf_f16, float16) From patchwork Tue May 12 16:38:59 2020 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 12/17] target/arm: Convert Neon VPMIN/VPMAX/VPADD float 3-reg-same insns to decodetree Date: Tue, 12 May 2020 17:38:59 +0100 Message-Id: <20200512163904.10918-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the Neon float VPMIN, VPMAX and VPADD 3-reg-same insns to decodetree. These are the only remaining 'pairwise' operations, so we can delete the pairwise-specific bits of the old decoder's for-each-element loop now. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 5 +++ target/arm/translate-neon.inc.c | 63 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 63 +++++---------------------------- 3 files changed, 76 insertions(+), 55 deletions(-) -- 2.20.1 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 06fb8b96aad..1f289750dcd 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -48,6 +48,8 @@ # For FP insns the high bit of 'size' is used as part of opcode decode @3same_fp .... ... . . . . size:1 .... .... .... . q:1 . . .... \ &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp +@3same_fp_q0 .... ... . . . . size:1 .... .... .... . 0 . . .... \ + &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0 VHADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same @@ -177,4 +179,7 @@ VQRDMLSH_3s 1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same VADD_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp VSUB_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 0 .... @3same_fp +VPADD_fp_3s 1111 001 1 0 . 0 . .... .... 1101 ... 0 .... @3same_fp_q0 VABD_fp_3s 1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp +VPMAX_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 0 .... @3same_fp_q0 +VPMIN_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 0 .... @3same_fp_q0 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index 540720f5e0d..7bdf1e3fee8 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1049,3 +1049,66 @@ DO_3SAME_VQDMULH(VQRDMULH, qrdmulh) DO_3S_FP_GVEC(VADD, gen_helper_gvec_fadd_s) DO_3S_FP_GVEC(VSUB, gen_helper_gvec_fsub_s) DO_3S_FP_GVEC(VABD, gen_helper_gvec_fabd_s) + +static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn) +{ + /* FP operations handled pairwise 32 bits at a time */ + TCGv_i32 tmp, tmp2, tmp3; + TCGv_ptr fpstatus; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + assert(a->q == 0); /* enforced by decode patterns */ + + /* + * Note that we have to be careful not to clobber the source operands + * in the "vm == vd" case by storing the result of the first pass too + * early. Since Q is 0 there are always just two passes, so instead + * of a complicated loop over each pass we just unroll. + */ + fpstatus = get_fpstatus_ptr(1); + tmp = neon_load_reg(a->vn, 0); + tmp2 = neon_load_reg(a->vn, 1); + fn(tmp, tmp, tmp2, fpstatus); + tcg_temp_free_i32(tmp2); + + tmp3 = neon_load_reg(a->vm, 0); + tmp2 = neon_load_reg(a->vm, 1); + fn(tmp3, tmp3, tmp2, fpstatus); + tcg_temp_free_i32(tmp2); + tcg_temp_free_ptr(fpstatus); + + neon_store_reg(a->vd, 0, tmp); + neon_store_reg(a->vd, 1, tmp3); + return true; +} + +/* + * For all the functions using this macro, size == 1 means fp16, + * which is an architecture extension we don't implement yet. + */ +#define DO_3S_FP_PAIR(INSN,FUNC) \ + static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \ + { \ + if (a->size != 0) { \ + /* TODO fp16 support */ \ + return false; \ + } \ + return do_3same_fp_pair(s, a, FUNC); \ + } + +DO_3S_FP_PAIR(VPADD, gen_helper_vfp_adds) +DO_3S_FP_PAIR(VPMAX, gen_helper_vfp_maxs) +DO_3S_FP_PAIR(VPMIN, gen_helper_vfp_mins) diff --git a/target/arm/translate.c b/target/arm/translate.c index 8a94856cd28..ca6ed09ec34 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5348,7 +5348,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) int shift; int pass; int count; - int pairwise; int u; int vec_size; uint32_t imm; @@ -5433,6 +5432,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_VPMIN: case NEON_3R_VPADD_VQRDMLAH: case NEON_3R_VQDMULH_VQRDMULH: + case NEON_3R_FLOAT_ARITH: /* Already handled by decodetree */ return 1; } @@ -5441,16 +5441,11 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) /* 64-bit element instructions: handled by decodetree */ return 1; } - pairwise = 0; switch (op) { - case NEON_3R_FLOAT_ARITH: - pairwise = (u && size < 2); /* if VPADD (float) */ - if (!pairwise) { - return 1; /* handled by decodetree */ - } - break; case NEON_3R_FLOAT_MINMAX: - pairwise = u; /* if VPMIN/VPMAX (float) */ + if (u) { + return 1; /* VPMIN/VPMAX handled by decodetree */ + } break; case NEON_3R_FLOAT_CMP: if (!u && size) { @@ -5478,41 +5473,12 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) break; } - if (pairwise && q) { - /* All the pairwise insns UNDEF if Q is set */ - return 1; - } - for (pass = 0; pass < (q ? 4 : 2); pass++) { - if (pairwise) { - /* Pairwise. */ - if (pass < 1) { - tmp = neon_load_reg(rn, 0); - tmp2 = neon_load_reg(rn, 1); - } else { - tmp = neon_load_reg(rm, 0); - tmp2 = neon_load_reg(rm, 1); - } - } else { - /* Elementwise. */ - tmp = neon_load_reg(rn, pass); - tmp2 = neon_load_reg(rm, pass); - } + /* Elementwise. */ + tmp = neon_load_reg(rn, pass); + tmp2 = neon_load_reg(rm, pass); switch (op) { - case NEON_3R_FLOAT_ARITH: /* Floating point arithmetic. */ - { - TCGv_ptr fpstatus = get_fpstatus_ptr(1); - switch ((u << 2) | size) { - case 4: /* VPADD */ - gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus); - break; - default: - abort(); - } - tcg_temp_free_ptr(fpstatus); - break; - } case NEON_3R_FLOAT_MULTIPLY: { TCGv_ptr fpstatus = get_fpstatus_ptr(1); @@ -5603,22 +5569,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } tcg_temp_free_i32(tmp2); - /* Save the result. For elementwise operations we can put it - straight into the destination register. For pairwise operations - we have to be careful to avoid clobbering the source operands. */ - if (pairwise && rd == rm) { - neon_store_scratch(pass, tmp); - } else { - neon_store_reg(rd, pass, tmp); - } + neon_store_reg(rd, pass, tmp); } /* for pass */ - if (pairwise && rd == rm) { - for (pass = 0; pass < (q ? 4 : 2); pass++) { - tmp = neon_load_scratch(pass); - neon_store_reg(rd, pass, tmp); - } - } /* End of 3 register same size operations. */ } else if (insn & (1 << 4)) { if ((insn & 0x00380080) != 0) { From patchwork Tue May 12 16:39:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 186560 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp113097ilb; Tue, 12 May 2020 09:49:28 -0700 (PDT) X-Google-Smtp-Source: APiQypI+JMaMIijDqP1FM2XeKdEKS0JQfoy58VDfu/3num+MJpVCerugO8KnaIiAiB+8UGZ3jE0P X-Received: by 2002:ae9:ebd2:: with SMTP id b201mr21943868qkg.80.1589302168095; Tue, 12 May 2020 09:49:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589302168; cv=none; d=google.com; s=arc-20160816; b=k6Cs3osrUV6iN/CqcVoP3Qgs3EItilr4YPURApH5CvbLs124ajEDS4uiQhQtBGfLvb nuysagkjoXFF2dFSj+3mZAkSwf+xsEnxeizDdMfw0wEBoGhCJ2eD/BV9vwZY7P7zPp2M GskBUGvZJF4T06uJ5raKghYNZWsYAERTa0vOKAb7Kh2OA1FJuYYZxUC1np52Jw44W45c yII6ke3oOGuKybiyprMnpAPx7E8NtAAhFe/6R8Vk70Jjr6yECI3/uIhHvAWP+Ce/SAmc 8XaJMrcy2iATICCuYNK+tYSQ9iGdskxFupXW4HDHwX+ku95esKBcMFFLmAuqZ0Bk3KFy KEsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1c0sA0VXCHDtNOClCYM5tpbz5xGR3LiI9SrLPs+uUSg=; b=BKHYmmKxWqWO2liBo4aCmBmD5GHRc7m6k6RjbBu3J0Iydb8CKcsCQoqWiHM17y9WAK hOrrZKxxKeCIbXugeWnlhIvgPY7XCHy4ifcZQgDmJyjAJGwRfH1edRe526aHe9qa5+K2 7yG0s8aGNDOsVIV/bOs1Qn/1WSLjcK4hbK6KKXyzylr67u50hryQfm4s3IQu3WL06vDR obHtvo8LZ46W/8vUV5AoM6HU6DiBjtMdLMZDeIQv8qZO+PC8BdmhctL/NL9vnni0Vrz4 /e5j+gyetdDQDCvTiNpR9tr1BfIxRpAwrG05atKbVx4E9rKF+RfHuLodiTPL7cATUMYx 6b6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H85ZFcM4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:24 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 13/17] target/arm: Convert Neon fp VMUL, VMLA, VMLS 3-reg-same insns to decodetree Date: Tue, 12 May 2020 17:39:00 +0100 Message-Id: <20200512163904.10918-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the Neon integer VMUL, VMLA, and VMLS 3-reg-same inssn to decodetree. We don't have a gvec helper for multiply-accumulate, so VMLA and VMLS need a loop function do_3same_fp(). This takes a reads_vd parameter to do_3same_fp() which tells it to load the old value into vd before calling the callback function, in the same way that the do_vfp_3op_sp() and do_vfp_3op_dp() functions in translate-vfp.inc.c work. (The only uses in this patch pass reads_vd == true, but later commits will use reads_vd == false.) This conversion fixes in passing an underdecoding for VMUL (originally reported by Fredrik Strupe ): bit 1 of the 'size' field must be 0. The old decoder didn't enforce this, but the decodetree pattern does. The gen_VMLA_fp_reg() function performs the addition operation with the operands in the opposite order to the old decoder: since Neon sets 'default NaN mode' float32_add operations are commutative so there is no behaviour difference, but putting them this way around matches the Arm ARM pseudocode and the required operation order for the subtraction in gen_VMLS_fp_reg(). Signed-off-by: Peter Maydell --- target/arm/neon-dp.decode | 3 ++ target/arm/translate-neon.inc.c | 81 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 17 +------ 3 files changed, 85 insertions(+), 16 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 1f289750dcd..0f74b31dcd1 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -181,5 +181,8 @@ VADD_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp VSUB_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 0 .... @3same_fp VPADD_fp_3s 1111 001 1 0 . 0 . .... .... 1101 ... 0 .... @3same_fp_q0 VABD_fp_3s 1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp +VMLA_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 1 .... @3same_fp +VMLS_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 1 .... @3same_fp +VMUL_fp_3s 1111 001 1 0 . 0 . .... .... 1101 ... 1 .... @3same_fp VPMAX_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 0 .... @3same_fp_q0 VPMIN_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 0 .... @3same_fp_q0 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index 7bdf1e3fee8..18896598bb4 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1022,6 +1022,55 @@ DO_3SAME_PAIR(VPADD, padd_u) DO_3SAME_VQDMULH(VQDMULH, qdmulh) DO_3SAME_VQDMULH(VQRDMULH, qrdmulh) +static bool do_3same_fp(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn, + bool reads_vd) +{ + /* + * FP operations handled elementwise 32 bits at a time. + * If reads_vd is true then the old value of Vd will be + * loaded before calling the callback function. This is + * used for multiply-accumulate type operations. + */ + TCGv_i32 tmp, tmp2; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if ((a->vn | a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + TCGv_ptr fpstatus = get_fpstatus_ptr(1); + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { + tmp = neon_load_reg(a->vn, pass); + tmp2 = neon_load_reg(a->vm, pass); + if (reads_vd) { + TCGv_i32 tmp_rd = neon_load_reg(a->vd, pass); + fn(tmp_rd, tmp, tmp2, fpstatus); + neon_store_reg(a->vd, pass, tmp_rd); + tcg_temp_free_i32(tmp); + } else { + fn(tmp, tmp, tmp2, fpstatus); + neon_store_reg(a->vd, pass, tmp); + } + tcg_temp_free_i32(tmp2); + } + tcg_temp_free_ptr(fpstatus); + return true; +} + /* * For all the functions using this macro, size == 1 means fp16, * which is an architecture extension we don't implement yet. @@ -1049,6 +1098,38 @@ DO_3SAME_VQDMULH(VQRDMULH, qrdmulh) DO_3S_FP_GVEC(VADD, gen_helper_gvec_fadd_s) DO_3S_FP_GVEC(VSUB, gen_helper_gvec_fsub_s) DO_3S_FP_GVEC(VABD, gen_helper_gvec_fabd_s) +DO_3S_FP_GVEC(VMUL, gen_helper_gvec_fmul_s) + +/* + * For all the functions using this macro, size == 1 means fp16, + * which is an architecture extension we don't implement yet. + */ +#define DO_3S_FP(INSN,FUNC,READS_VD) \ + static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \ + { \ + if (a->size != 0) { \ + /* TODO fp16 support */ \ + return false; \ + } \ + return do_3same_fp(s, a, FUNC, READS_VD); \ + } + +static void gen_VMLA_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, + TCGv_ptr fpstatus) +{ + gen_helper_vfp_muls(vn, vn, vm, fpstatus); + gen_helper_vfp_adds(vd, vd, vn, fpstatus); +} + +static void gen_VMLS_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, + TCGv_ptr fpstatus) +{ + gen_helper_vfp_muls(vn, vn, vm, fpstatus); + gen_helper_vfp_subs(vd, vd, vn, fpstatus); +} + +DO_3S_FP(VMLA, gen_VMLA_fp_3s, true) +DO_3S_FP(VMLS, gen_VMLS_fp_3s, true) static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn) { diff --git a/target/arm/translate.c b/target/arm/translate.c index ca6ed09ec34..06b6925d31e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5433,6 +5433,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_VPADD_VQRDMLAH: case NEON_3R_VQDMULH_VQRDMULH: case NEON_3R_FLOAT_ARITH: + case NEON_3R_FLOAT_MULTIPLY: /* Already handled by decodetree */ return 1; } @@ -5479,22 +5480,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tmp = neon_load_reg(rn, pass); tmp2 = neon_load_reg(rm, pass); switch (op) { - case NEON_3R_FLOAT_MULTIPLY: - { - TCGv_ptr fpstatus = get_fpstatus_ptr(1); - gen_helper_vfp_muls(tmp, tmp, tmp2, fpstatus); - if (!u) { - tcg_temp_free_i32(tmp2); - tmp2 = neon_load_reg(rd, pass); - if (size == 0) { - gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus); - } else { - gen_helper_vfp_subs(tmp, tmp2, tmp, fpstatus); - } - } - tcg_temp_free_ptr(fpstatus); - break; - } case NEON_3R_FLOAT_CMP: { TCGv_ptr fpstatus = get_fpstatus_ptr(1); From patchwork Tue May 12 16:39:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 186565 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp116176ilb; Tue, 12 May 2020 09:53:59 -0700 (PDT) X-Google-Smtp-Source: APiQypKu15gQ6r5Z3PtPyHQcg7JFQ+tRJf4DHKAJMfxVTUj7A0ATTt7LTm/ROAYUg3TmWY+xOV2R X-Received: by 2002:ac8:3808:: with SMTP id q8mr23009768qtb.245.1589302439219; Tue, 12 May 2020 09:53:59 -0700 (PDT) ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:25 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 14/17] target/arm: Convert Neon 3-reg-same compare insns to decodetree Date: Tue, 12 May 2020 17:39:01 +0100 Message-Id: <20200512163904.10918-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the Neon integer 3-reg-same compare insns VCGE, VCGT, VCEQ, VACGE and VACGT to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 5 +++++ target/arm/translate-neon.inc.c | 6 +++++ target/arm/translate.c | 39 ++------------------------------- 3 files changed, 13 insertions(+), 37 deletions(-) -- 2.20.1 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 0f74b31dcd1..bc5a3e0295c 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -184,5 +184,10 @@ VABD_fp_3s 1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp VMLA_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 1 .... @3same_fp VMLS_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 1 .... @3same_fp VMUL_fp_3s 1111 001 1 0 . 0 . .... .... 1101 ... 1 .... @3same_fp +VCEQ_fp_3s 1111 001 0 0 . 0 . .... .... 1110 ... 0 .... @3same_fp +VCGE_fp_3s 1111 001 1 0 . 0 . .... .... 1110 ... 0 .... @3same_fp +VACGE_fp_3s 1111 001 1 0 . 0 . .... .... 1110 ... 1 .... @3same_fp +VCGT_fp_3s 1111 001 1 0 . 1 . .... .... 1110 ... 0 .... @3same_fp +VACGT_fp_3s 1111 001 1 0 . 1 . .... .... 1110 ... 1 .... @3same_fp VPMAX_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 0 .... @3same_fp_q0 VPMIN_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 0 .... @3same_fp_q0 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index 18896598bb4..eeea71e3bec 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1114,6 +1114,12 @@ DO_3S_FP_GVEC(VMUL, gen_helper_gvec_fmul_s) return do_3same_fp(s, a, FUNC, READS_VD); \ } +DO_3S_FP(VCEQ, gen_helper_neon_ceq_f32, false) +DO_3S_FP(VCGE, gen_helper_neon_cge_f32, false) +DO_3S_FP(VCGT, gen_helper_neon_cgt_f32, false) +DO_3S_FP(VACGE, gen_helper_neon_acge_f32, false) +DO_3S_FP(VACGT, gen_helper_neon_acgt_f32, false) + static void gen_VMLA_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpstatus) { diff --git a/target/arm/translate.c b/target/arm/translate.c index 06b6925d31e..b9fcbbcbcb5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5434,6 +5434,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_VQDMULH_VQRDMULH: case NEON_3R_FLOAT_ARITH: case NEON_3R_FLOAT_MULTIPLY: + case NEON_3R_FLOAT_CMP: + case NEON_3R_FLOAT_ACMP: /* Already handled by decodetree */ return 1; } @@ -5448,17 +5450,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) return 1; /* VPMIN/VPMAX handled by decodetree */ } break; - case NEON_3R_FLOAT_CMP: - if (!u && size) { - /* no encoding for U=0 C=1x */ - return 1; - } - break; - case NEON_3R_FLOAT_ACMP: - if (!u) { - return 1; - } - break; case NEON_3R_FLOAT_MISC: /* VMAXNM/VMINNM in ARMv8 */ if (u && !arm_dc_feature(s, ARM_FEATURE_V8)) { @@ -5480,32 +5471,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tmp = neon_load_reg(rn, pass); tmp2 = neon_load_reg(rm, pass); switch (op) { - case NEON_3R_FLOAT_CMP: - { - TCGv_ptr fpstatus = get_fpstatus_ptr(1); - if (!u) { - gen_helper_neon_ceq_f32(tmp, tmp, tmp2, fpstatus); - } else { - if (size == 0) { - gen_helper_neon_cge_f32(tmp, tmp, tmp2, fpstatus); - } else { - gen_helper_neon_cgt_f32(tmp, tmp, tmp2, fpstatus); - } - } - tcg_temp_free_ptr(fpstatus); - break; - } - case NEON_3R_FLOAT_ACMP: - { - TCGv_ptr fpstatus = get_fpstatus_ptr(1); - if (size == 0) { - gen_helper_neon_acge_f32(tmp, tmp, tmp2, fpstatus); - } else { - gen_helper_neon_acgt_f32(tmp, tmp, tmp2, fpstatus); - } - tcg_temp_free_ptr(fpstatus); - break; - } case NEON_3R_FLOAT_MINMAX: { TCGv_ptr fpstatus = get_fpstatus_ptr(1); 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:26 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 15/17] target/arm: Move 'env' argument of recps_f32 and rsqrts_f32 helpers to usual place Date: Tue, 12 May 2020 17:39:02 +0100 Message-Id: <20200512163904.10918-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The usual location for the env argument in the argument list of a TCG helper is immediately after the return-value argument. recps_f32 and rsqrts_f32 differ in that they put it at the end. Move the env argument to its usual place; this will allow us to more easily use these helper functions with the gvec APIs. Signed-off-by: Peter Maydell --- target/arm/helper.h | 4 ++-- target/arm/translate.c | 4 ++-- target/arm/vfp_helper.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.h b/target/arm/helper.h index 6e9629c87b0..49336dc432c 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -203,8 +203,8 @@ DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, ptr, i32) DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr) DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr) -DEF_HELPER_3(recps_f32, f32, f32, f32, env) -DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env) +DEF_HELPER_3(recps_f32, f32, env, f32, f32) +DEF_HELPER_3(rsqrts_f32, f32, env, f32, f32) DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr) diff --git a/target/arm/translate.c b/target/arm/translate.c index b9fcbbcbcb5..23e3705172b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5494,9 +5494,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_temp_free_ptr(fpstatus); } else { if (size == 0) { - gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env); + gen_helper_recps_f32(tmp, cpu_env, tmp, tmp2); } else { - gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env); + gen_helper_rsqrts_f32(tmp, cpu_env, tmp, tmp2); } } break; diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index a7926611665..f5ecaab2d4a 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -581,7 +581,7 @@ uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode) #define float32_three make_float32(0x40400000) #define float32_one_point_five make_float32(0x3fc00000) -float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) +float32 HELPER(recps_f32)(CPUARMState *env, float32 a, float32 b) { float_status *s = &env->vfp.standard_fp_status; if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || @@ -594,7 +594,7 @@ float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) return float32_sub(float32_two, float32_mul(a, b, s), s); } -float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) +float32 HELPER(rsqrts_f32)(CPUARMState *env, float32 a, float32 b) { float_status *s = &env->vfp.standard_fp_status; float32 product; From patchwork Tue May 12 16:39:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 186564 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp115547ilb; Tue, 12 May 2020 09:53:01 -0700 (PDT) X-Google-Smtp-Source: APiQypJF5TstccyRpXImyka/hh8x3fmacHFDJ9RQY+6eM1min9hWYYQFWDiCc+C629HqUZ0+q8DB X-Received: by 2002:ad4:4a8b:: with SMTP id h11mr11540279qvx.232.1589302381843; Tue, 12 May 2020 09:53:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589302381; cv=none; d=google.com; s=arc-20160816; b=ATYPmXDZMHjDPMjubsuoKoPz8EJYJRl7vPgLuPLDAIzR4vQZUhiDjAxc7wkCPBKtKj WKceeQVu2/VioPgIt2eEXKTC/9/mRBM3goe4aN6eMDtBUWXlrzPBDxsAkqYy8qo/BNiv /CoLvIL9U/tb98tW8WWC5b4rLCkO1D3CJ42xvwz50h5CfIJAXk5DwtV4YPRLX8/XaeDx uU+M0BevesBekhaeMjmmk5jeHIB8JUBZYyyaxIrpX1XSwJ38390gtOs/5zGabGCJBSJI /cBJPCgTpN5lF46/clMhgOEe5/295GQGPC5uFC2VfModalAyFuVGd4UBvIk2TlUew5FO snYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rYOYRtg99xSCr5ET97yS6jthFxSiidOBBESmPdEt8oM=; b=BeqyE3uhn9lSik6mKYTua1cOrCuUR4zkUDKFHMyMcoA+WPSKaKM1rQzeer2BU4fxND Al3lqdQFzDkV/GifMtM8Xi/SxXI4BFeJfiALv7gBA5FqX0VMGjwEqcFVMVaOOWgjv5x+ 2TYndhrUf3NbPJA7LmnFJZbBPnePk+nACoA7xR+5t+NXvAKNxIRyXh75OhA779WdZehu 2ivRcBS9XcqemoHegYVtxuXQ/1ZSYV+oN7xZNOtRpCP1Yf8vwXr0IWWe0VnWmb9oaozb Ey8ouimcg5+4VjheWp9nCk5BNcD7HazABdF0yEkbuLHf+OT4am0spXx2b2QCRZn//14j dAUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aj+xLkG5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:27 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 16/17] target/arm: Convert Neon fp VMAX/VMIN/VMAXNM/VMINNM/VRECPS/VRSQRTS to decodetree Date: Tue, 12 May 2020 17:39:03 +0100 Message-Id: <20200512163904.10918-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the Neon fp VMAX/VMIN/VMAXNM/VMINNM/VRECPS/VRSQRTS 3-reg-same insns to decodetree. (These are all the remaining non-accumulation instructions in this group.) Signed-off-by: Peter Maydell --- target/arm/neon-dp.decode | 6 +++ target/arm/translate-neon.inc.c | 70 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 42 +------------------- 3 files changed, 78 insertions(+), 40 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index bc5a3e0295c..c276faf8cce 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -189,5 +189,11 @@ VCGE_fp_3s 1111 001 1 0 . 0 . .... .... 1110 ... 0 .... @3same_fp VACGE_fp_3s 1111 001 1 0 . 0 . .... .... 1110 ... 1 .... @3same_fp VCGT_fp_3s 1111 001 1 0 . 1 . .... .... 1110 ... 0 .... @3same_fp VACGT_fp_3s 1111 001 1 0 . 1 . .... .... 1110 ... 1 .... @3same_fp +VMAX_fp_3s 1111 001 0 0 . 0 . .... .... 1111 ... 0 .... @3same_fp +VMIN_fp_3s 1111 001 0 0 . 1 . .... .... 1111 ... 0 .... @3same_fp VPMAX_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 0 .... @3same_fp_q0 VPMIN_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 0 .... @3same_fp_q0 +VRECPS_fp_3s 1111 001 0 0 . 0 . .... .... 1111 ... 1 .... @3same_fp +VRSQRTS_fp_3s 1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp +VMAXNM_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp +VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index eeea71e3bec..263d2b47132 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1119,6 +1119,8 @@ DO_3S_FP(VCGE, gen_helper_neon_cge_f32, false) DO_3S_FP(VCGT, gen_helper_neon_cgt_f32, false) DO_3S_FP(VACGE, gen_helper_neon_acge_f32, false) DO_3S_FP(VACGT, gen_helper_neon_acgt_f32, false) +DO_3S_FP(VMAX, gen_helper_vfp_maxs, false) +DO_3S_FP(VMIN, gen_helper_vfp_mins, false) static void gen_VMLA_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpstatus) @@ -1137,6 +1139,74 @@ static void gen_VMLS_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, DO_3S_FP(VMLA, gen_VMLA_fp_3s, true) DO_3S_FP(VMLS, gen_VMLS_fp_3s, true) +static bool trans_VMAXNM_fp_3s(DisasContext *s, arg_3same *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + + if (a->size != 0) { + /* TODO fp16 support */ + return false; + } + + return do_3same_fp(s, a, gen_helper_vfp_maxnums, false); +} + +static bool trans_VMINNM_fp_3s(DisasContext *s, arg_3same *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + + if (a->size != 0) { + /* TODO fp16 support */ + return false; + } + + return do_3same_fp(s, a, gen_helper_vfp_minnums, false); +} + +WRAP_ENV_FN(gen_VRECPS_tramp, gen_helper_recps_f32) + +static void gen_VRECPS_fp_3s(unsigned vece, uint32_t rd_ofs, + uint32_t rn_ofs, uint32_t rm_ofs, + uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen3 ops = { .fni4 = gen_VRECPS_tramp }; + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops); +} + +static bool trans_VRECPS_fp_3s(DisasContext *s, arg_3same *a) +{ + if (a->size != 0) { + /* TODO fp16 support */ + return false; + } + + return do_3same(s, a, gen_VRECPS_fp_3s); +} + +WRAP_ENV_FN(gen_VRSQRTS_tramp, gen_helper_rsqrts_f32) + +static void gen_VRSQRTS_fp_3s(unsigned vece, uint32_t rd_ofs, + uint32_t rn_ofs, uint32_t rm_ofs, + uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen3 ops = { .fni4 = gen_VRSQRTS_tramp }; + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops); +} + +static bool trans_VRSQRTS_fp_3s(DisasContext *s, arg_3same *a) +{ + if (a->size != 0) { + /* TODO fp16 support */ + return false; + } + + return do_3same(s, a, gen_VRSQRTS_fp_3s); +} + static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn) { /* FP operations handled pairwise 32 bits at a time */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 23e3705172b..c1d4fab8e80 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5436,6 +5436,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_FLOAT_MULTIPLY: case NEON_3R_FLOAT_CMP: case NEON_3R_FLOAT_ACMP: + case NEON_3R_FLOAT_MINMAX: + case NEON_3R_FLOAT_MISC: /* Already handled by decodetree */ return 1; } @@ -5445,17 +5447,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) return 1; } switch (op) { - case NEON_3R_FLOAT_MINMAX: - if (u) { - return 1; /* VPMIN/VPMAX handled by decodetree */ - } - break; - case NEON_3R_FLOAT_MISC: - /* VMAXNM/VMINNM in ARMv8 */ - if (u && !arm_dc_feature(s, ARM_FEATURE_V8)) { - return 1; - } - break; case NEON_3R_VFM_VQRDMLSH: if (!dc_isar_feature(aa32_simdfmac, s)) { return 1; @@ -5471,35 +5462,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tmp = neon_load_reg(rn, pass); tmp2 = neon_load_reg(rm, pass); switch (op) { - case NEON_3R_FLOAT_MINMAX: - { - TCGv_ptr fpstatus = get_fpstatus_ptr(1); - if (size == 0) { - gen_helper_vfp_maxs(tmp, tmp, tmp2, fpstatus); - } else { - gen_helper_vfp_mins(tmp, tmp, tmp2, fpstatus); - } - tcg_temp_free_ptr(fpstatus); - break; - } - case NEON_3R_FLOAT_MISC: - if (u) { - /* VMAXNM/VMINNM */ - TCGv_ptr fpstatus = get_fpstatus_ptr(1); - if (size == 0) { - gen_helper_vfp_maxnums(tmp, tmp, tmp2, fpstatus); - } else { - gen_helper_vfp_minnums(tmp, tmp, tmp2, fpstatus); - } - tcg_temp_free_ptr(fpstatus); - } else { - if (size == 0) { - gen_helper_recps_f32(tmp, cpu_env, tmp, tmp2); - } else { - gen_helper_rsqrts_f32(tmp, cpu_env, tmp, tmp2); - } - } - break; case NEON_3R_VFM_VQRDMLSH: { /* VFMA, VFMS: fused multiply-add */ From patchwork Tue May 12 16:39:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 186566 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp117255ilb; Tue, 12 May 2020 09:55:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyZYkLm7TYODUtgl1BSH9Qki9cnWMPejFm5JnEL8SVo+1gbUMRzPzyiGcLunu8gDDaqz1kZ X-Received: by 2002:a37:f517:: with SMTP id l23mr2656137qkk.475.1589302538426; Tue, 12 May 2020 09:55:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589302538; cv=none; d=google.com; s=arc-20160816; b=ckzq5ywbzzM6IxT7PyRwTme8D7wSiCJfN4Vq9rGXLhtSjoi3YE4VIp/45hFdOYd149 fQ/VyxmNdkRIwGdGdYkGkkWhBfx+TA8PDFvupxdLVzqEFz50rAqWfIMc7m9PufERljG7 jpflNbRsmVaca1bz/o0BE6SocYBfHit2zaRAy4xPx+o8A4gUHEEB5zKY+uV/Nmzg/0og JgnyTCXE07gH4e68GZqW/33LEDUSKkvgjYWOtBVIT+nsXwObdv1LBe8RlkOhVu0Qju9+ 1PPh+45Z8os6yMPB6egrb9MS/SrBNqJiVjn6WdlxSThVQ8josyJNxXbpKN3vveYkDgUd T40A== ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o205sm18525981wmo.32.2020.05.12.09.39.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:39:29 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 17/17] target/arm: Convert NEON VFMA, VFMS 3-reg-same insns to decodetree Date: Tue, 12 May 2020 17:39:04 +0100 Message-Id: <20200512163904.10918-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org> References: <20200512163904.10918-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the Neon floating point VFMA and VFMS insn to decodetree. These are the last insns in the 3-reg-same group so we can remove all the support/loop code from the old decoder. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 3 + target/arm/translate-neon.inc.c | 41 ++++++++ target/arm/translate.c | 176 +------------------------------- 3 files changed, 46 insertions(+), 174 deletions(-) -- 2.20.1 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index c276faf8cce..f53bf8a4494 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -175,6 +175,9 @@ SHA256H2_3s 1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... \ SHA256SU1_3s 1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... \ vm=%vm_dp vn=%vn_dp vd=%vd_dp +VFMA_fp_3s 1111 001 0 0 . 0 . .... .... 1100 ... 1 .... @3same_fp +VFMS_fp_3s 1111 001 0 0 . 1 . .... .... 1100 ... 1 .... @3same_fp + VQRDMLSH_3s 1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same VADD_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index 263d2b47132..7212876e8f0 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1207,6 +1207,47 @@ static bool trans_VRSQRTS_fp_3s(DisasContext *s, arg_3same *a) return do_3same(s, a, gen_VRSQRTS_fp_3s); } +static void gen_VFMA_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, + TCGv_ptr fpstatus) +{ + gen_helper_vfp_muladds(vd, vn, vm, vd, fpstatus); +} + +static bool trans_VFMA_fp_3s(DisasContext *s, arg_3same *a) +{ + if (!dc_isar_feature(aa32_simdfmac, s)) { + return false; + } + + if (a->size != 0) { + /* TODO fp16 support */ + return false; + } + + return do_3same_fp(s, a, gen_VFMA_fp_3s, true); +} + +static void gen_VFMS_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, + TCGv_ptr fpstatus) +{ + gen_helper_vfp_negs(vn, vn); + gen_helper_vfp_muladds(vd, vn, vm, vd, fpstatus); +} + +static bool trans_VFMS_fp_3s(DisasContext *s, arg_3same *a) +{ + if (!dc_isar_feature(aa32_simdfmac, s)) { + return false; + } + + if (a->size != 0) { + /* TODO fp16 support */ + return false; + } + + return do_3same_fp(s, a, gen_VFMS_fp_3s, true); +} + static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn) { /* FP operations handled pairwise 32 bits at a time */ diff --git a/target/arm/translate.c b/target/arm/translate.c index c1d4fab8e80..4c9bb8b5ac0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3391,78 +3391,6 @@ static void gen_neon_narrow_op(int op, int u, int size, } } -/* Symbolic constants for op fields for Neon 3-register same-length. - * The values correspond to bits [11:8,4]; see the ARM ARM DDI0406B - * table A7-9. - */ -#define NEON_3R_VHADD 0 -#define NEON_3R_VQADD 1 -#define NEON_3R_VRHADD 2 -#define NEON_3R_LOGIC 3 /* VAND,VBIC,VORR,VMOV,VORN,VEOR,VBIF,VBIT,VBSL */ -#define NEON_3R_VHSUB 4 -#define NEON_3R_VQSUB 5 -#define NEON_3R_VCGT 6 -#define NEON_3R_VCGE 7 -#define NEON_3R_VSHL 8 -#define NEON_3R_VQSHL 9 -#define NEON_3R_VRSHL 10 -#define NEON_3R_VQRSHL 11 -#define NEON_3R_VMAX 12 -#define NEON_3R_VMIN 13 -#define NEON_3R_VABD 14 -#define NEON_3R_VABA 15 -#define NEON_3R_VADD_VSUB 16 -#define NEON_3R_VTST_VCEQ 17 -#define NEON_3R_VML 18 /* VMLA, VMLS */ -#define NEON_3R_VMUL 19 -#define NEON_3R_VPMAX 20 -#define NEON_3R_VPMIN 21 -#define NEON_3R_VQDMULH_VQRDMULH 22 -#define NEON_3R_VPADD_VQRDMLAH 23 -#define NEON_3R_SHA 24 /* SHA1C,SHA1P,SHA1M,SHA1SU0,SHA256H{2},SHA256SU1 */ -#define NEON_3R_VFM_VQRDMLSH 25 /* VFMA, VFMS, VQRDMLSH */ -#define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */ -#define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */ -#define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */ -#define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */ -#define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */ -#define NEON_3R_FLOAT_MISC 31 /* float VRECPS, VRSQRTS, VMAXNM/MINNM */ - -static const uint8_t neon_3r_sizes[] = { - [NEON_3R_VHADD] = 0x7, - [NEON_3R_VQADD] = 0xf, - [NEON_3R_VRHADD] = 0x7, - [NEON_3R_LOGIC] = 0xf, /* size field encodes op type */ - [NEON_3R_VHSUB] = 0x7, - [NEON_3R_VQSUB] = 0xf, - [NEON_3R_VCGT] = 0x7, - [NEON_3R_VCGE] = 0x7, - [NEON_3R_VSHL] = 0xf, - [NEON_3R_VQSHL] = 0xf, - [NEON_3R_VRSHL] = 0xf, - [NEON_3R_VQRSHL] = 0xf, - [NEON_3R_VMAX] = 0x7, - [NEON_3R_VMIN] = 0x7, - [NEON_3R_VABD] = 0x7, - [NEON_3R_VABA] = 0x7, - [NEON_3R_VADD_VSUB] = 0xf, - [NEON_3R_VTST_VCEQ] = 0x7, - [NEON_3R_VML] = 0x7, - [NEON_3R_VMUL] = 0x7, - [NEON_3R_VPMAX] = 0x7, - [NEON_3R_VPMIN] = 0x7, - [NEON_3R_VQDMULH_VQRDMULH] = 0x6, - [NEON_3R_VPADD_VQRDMLAH] = 0x7, - [NEON_3R_SHA] = 0xf, /* size field encodes op type */ - [NEON_3R_VFM_VQRDMLSH] = 0x7, /* For VFM, size bit 1 encodes op */ - [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */ - [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */ - [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */ - [NEON_3R_FLOAT_ACMP] = 0x5, /* size bit 1 encodes op */ - [NEON_3R_FLOAT_MINMAX] = 0x5, /* size bit 1 encodes op */ - [NEON_3R_FLOAT_MISC] = 0x5, /* size bit 1 encodes op */ -}; - /* Symbolic constants for op fields for Neon 2-register miscellaneous. * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B * table A7-13. @@ -5383,108 +5311,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) rm_ofs = neon_reg_offset(rm, 0); if ((insn & (1 << 23)) == 0) { - /* Three register same length. */ - op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1); - /* Catch invalid op and bad size combinations: UNDEF */ - if ((neon_3r_sizes[op] & (1 << size)) == 0) { - return 1; - } - /* All insns of this form UNDEF for either this condition or the - * superset of cases "Q==1"; we catch the latter later. - */ - if (q && ((rd | rn | rm) & 1)) { - return 1; - } - switch (op) { - case NEON_3R_VFM_VQRDMLSH: - if (!u) { - /* VFM, VFMS */ - if (size == 1) { - return 1; - } - break; - } - /* VQRDMLSH : handled by decodetree */ - return 1; - - case NEON_3R_VADD_VSUB: - case NEON_3R_LOGIC: - case NEON_3R_VMAX: - case NEON_3R_VMIN: - case NEON_3R_VTST_VCEQ: - case NEON_3R_VCGT: - case NEON_3R_VCGE: - case NEON_3R_VQADD: - case NEON_3R_VQSUB: - case NEON_3R_VMUL: - case NEON_3R_VML: - case NEON_3R_VSHL: - case NEON_3R_SHA: - case NEON_3R_VHADD: - case NEON_3R_VRHADD: - case NEON_3R_VHSUB: - case NEON_3R_VABD: - case NEON_3R_VABA: - case NEON_3R_VQSHL: - case NEON_3R_VRSHL: - case NEON_3R_VQRSHL: - case NEON_3R_VPMAX: - case NEON_3R_VPMIN: - case NEON_3R_VPADD_VQRDMLAH: - case NEON_3R_VQDMULH_VQRDMULH: - case NEON_3R_FLOAT_ARITH: - case NEON_3R_FLOAT_MULTIPLY: - case NEON_3R_FLOAT_CMP: - case NEON_3R_FLOAT_ACMP: - case NEON_3R_FLOAT_MINMAX: - case NEON_3R_FLOAT_MISC: - /* Already handled by decodetree */ - return 1; - } - - if (size == 3) { - /* 64-bit element instructions: handled by decodetree */ - return 1; - } - switch (op) { - case NEON_3R_VFM_VQRDMLSH: - if (!dc_isar_feature(aa32_simdfmac, s)) { - return 1; - } - break; - default: - break; - } - - for (pass = 0; pass < (q ? 4 : 2); pass++) { - - /* Elementwise. */ - tmp = neon_load_reg(rn, pass); - tmp2 = neon_load_reg(rm, pass); - switch (op) { - case NEON_3R_VFM_VQRDMLSH: - { - /* VFMA, VFMS: fused multiply-add */ - TCGv_ptr fpstatus = get_fpstatus_ptr(1); - TCGv_i32 tmp3 = neon_load_reg(rd, pass); - if (size) { - /* VFMS */ - gen_helper_vfp_negs(tmp, tmp); - } - gen_helper_vfp_muladds(tmp, tmp, tmp2, tmp3, fpstatus); - tcg_temp_free_i32(tmp3); - tcg_temp_free_ptr(fpstatus); - break; - } - default: - abort(); - } - tcg_temp_free_i32(tmp2); - - neon_store_reg(rd, pass, tmp); - - } /* for pass */ - /* End of 3 register same size operations. */ + /* Three register same length: handled by decodetree */ + return 1; } else if (insn & (1 << 4)) { if ((insn & 0x00380080) != 0) { /* Two registers and shift. */