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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id k18sm2643672pfg.217.2020.05.20.10.28.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2020 10:28:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 1/5] linux-user/aarch64: Reset btype for signals Date: Wed, 20 May 2020 10:27:56 -0700 Message-Id: <20200520172800.8499-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200520172800.8499-1-richard.henderson@linaro.org> References: <20200520172800.8499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The kernel sets btype for the signal handler as if for a call. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index cd521ee42d..2c596a7088 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -506,10 +506,16 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, + offsetof(struct target_rt_frame_record, tramp); } env->xregs[0] = usig; - env->xregs[31] = frame_addr; env->xregs[29] = frame_addr + fr_ofs; - env->pc = ka->_sa_handler; env->xregs[30] = return_addr; + env->xregs[31] = frame_addr; + env->pc = ka->_sa_handler; + + /* Invoke the signal handler as if by indirect call. */ + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { + env->btype = 2; + } + if (info) { tswap_siginfo(&frame->info, info); env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info); From patchwork Wed May 20 17:27:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186994 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp817541ilb; Wed, 20 May 2020 10:28:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzIdHNw1ub3UCDeFXEpVgyCmI89BmkFbMjrjHk6ZuEqf73BII4rLoCKPjniqQYwWqIt1oH/ X-Received: by 2002:a37:7105:: with SMTP id m5mr6090522qkc.370.1589995707765; Wed, 20 May 2020 10:28:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589995707; cv=none; d=google.com; s=arc-20160816; b=gdN/jEaOnDXaH7y/mVN/+WqMUYtuNVxBLoRYmlTPdxxWkjryXpIiol38uLDCaU4UQb tv90yAv+V8FsnGCkrIJCSuvuabsyZ41RvOUdAkODX4fOkJ6Ny3cDwtgaJMYbxZ5EhlZF R3pmrUUM193+pA8KByM0tIc5/h3PHApu5m092H5cnjp1z4kh9/Mvaj9KG6aS1Bu4+xde hQwQCB3iq5B/8qf5tT5D7VB8AEz39Kdh5k6iBdYp9wZ9YWkK1DmRQqkUyTKrndoI+2hO V9gDlt8QNGRR7riFKmQVTNIXMDHJw8WjLSYuSBlVWlwtUxRsLVzy4uiFfIUJ8QV4aQpe IaIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HKxQYKn1u7z/RK4+55flzx7HAaMyO56swf2SUfshigE=; b=iafheCIqteGM565EljSUUgw5M1Hc43ABjhXAkMDSlZvpYgZVi8L99vsoDpLZVWZJmN gDWEhT6Y5vg6ZP6CNrP2HtpfEsQOAp6qdQBZysLhJsX+xo0pN/t9yoE4Bqhy6rDZCbME Ywb1qcGBcuydZbEYckS42USQD7/ibhPfcsT5XyT3kLoj3TLghVmB7DvTHpiSPPifFhL2 6ey/dZOwlsYI033/fYvN2zobYVa4s59bmr7mrOlrRjTruasAetnubEoDCwv65KKOHHAR wYzeUy9glo7FoLOxnulSlUK7FVOsNmSuJ8KrWIHHBGcQl3hmyJozbUx3zj37YqiAOqgB hAOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TbdUyK7y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id k18sm2643672pfg.217.2020.05.20.10.28.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2020 10:28:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 2/5] linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI Date: Wed, 20 May 2020 10:27:57 -0700 Message-Id: <20200520172800.8499-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200520172800.8499-1-richard.henderson@linaro.org> References: <20200520172800.8499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Transform the prot bit to a qemu internal page bit, and save it in the page tables. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 2 ++ linux-user/syscall_defs.h | 4 ++++ linux-user/mmap.c | 16 ++++++++++++++++ target/arm/translate-a64.c | 6 +++--- 4 files changed, 25 insertions(+), 3 deletions(-) -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index d14374bdd4..2bd023d692 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -276,6 +276,8 @@ extern intptr_t qemu_host_page_mask; /* FIXME: Code that sets/uses this is broken and needs to go away. */ #define PAGE_RESERVED 0x0020 #endif +/* Target-specific bits that will be used via page_get_flags(). */ +#define PAGE_TARGET_1 0x0080 #if defined(CONFIG_USER_ONLY) void page_dump(FILE *f); diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index 152ec637cb..36bdafb3f1 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -1194,6 +1194,10 @@ struct target_winsize { #define TARGET_PROT_SEM 0x08 #endif +#ifdef TARGET_AARCH64 +#define TARGET_PROT_BTI 0x10 +#endif + /* Common */ #define TARGET_MAP_SHARED 0x01 /* Share changes */ #define TARGET_MAP_PRIVATE 0x02 /* Changes are private */ diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 84662c3311..40f03e3174 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -83,6 +83,22 @@ static int validate_prot_to_pageflags(int *host_prot, int prot) *host_prot = (prot & (PROT_READ | PROT_WRITE)) | (prot & PROT_EXEC ? PROT_READ : 0); +#ifdef TARGET_AARCH64 + /* + * The PROT_BTI bit is only accepted if the cpu supports the feature. + * Since this is the unusual case, don't bother checking unless + * the bit has been requested. If set and valid, record the bit + * within QEMU's page_flags as PAGE_TARGET_1. + */ + if (prot & TARGET_PROT_BTI) { + ARMCPU *cpu = ARM_CPU(thread_cpu); + if (cpu_isar_feature(aa64_bti, cpu)) { + valid |= TARGET_PROT_BTI; + page_flags |= PAGE_TARGET_1; + } + } +#endif + return prot & ~valid ? 0 : page_flags; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 991e451644..59ae236c84 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13989,10 +13989,10 @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) */ static bool is_guarded_page(CPUARMState *env, DisasContext *s) { -#ifdef CONFIG_USER_ONLY - return false; /* FIXME */ -#else uint64_t addr = s->base.pc_first; +#ifdef CONFIG_USER_ONLY + return page_get_flags(addr) & PAGE_TARGET_1; +#else int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx); unsigned int index = tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); From patchwork Wed May 20 17:27:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186997 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp818353ilb; Wed, 20 May 2020 10:29:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwwXXDlElwmt8pECzoTKNLjV8BvQWcaTQVabb7XBMvjwra6S5zPuZcDuyczRRB/FMoyF/lt X-Received: by 2002:aed:3fe8:: with SMTP id w37mr6217961qth.335.1589995782746; Wed, 20 May 2020 10:29:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589995782; cv=none; d=google.com; s=arc-20160816; b=kF6359IRKt4uSdXSlHTlpTKGEwKjUmSwew1ybZJzht19vo2M1UKKq9CuKEHZLyxIrr 0FhZe3Rt+4Y5JpgEG770WmBH/Q1VNb6RnpChtx3TUKU+bTTjRvS0eix3s75TNcU8QoMN hbOXM5D+hUrI1OMKQGITV9KJzEVdr9A1YvNbOz5nIBISR4/ibJRkyc8pjIBUbnu5bsHh +3NEdK49o4yNikwLRalLcWw6Pi6P4T3LmFRhYqj8Yb0BbZW37EbK8uqxr/ik8dE7D50A PedV9UzBTuzJNesyqJmxl+rHGbnMkneQtPw9UEJLkMMgx0B0rY79r+Be030Iyv4JqC/n a1Gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pfOqd0W163btym5ANgJ/IhyJiwPH1qS8Yj0O7sKwHiQ=; b=GqVXiBA+9686Pg3nXBXmu1fcVLxa8IsxY/hxPZMBiRKfb2dVuZ+KBH+cGe1CPDRMMz z89NNijyrWTATV2c4PLJjZtpvMTZ1e21WqgAgfV2CQyHEaD5C73g5xc34vfctNvP5G+J hVrLJeh9+9qFlk7mnKfVwWbIuvn3I63UzpynTIWeiSfmYcg/PHHTq8Piogmp5KTemk/g OaOS6o4As/pUZ9Znyrd2v1WKwrrOzk2Mtz0BkEqyqxLT4J+HRua1IXmYzrwMW5Nmlgq2 fqlMwPztBRfx9bNKpjGMXGVMlRwydeiN3DOpZLODLngJIUOoTof3vpmybs+BiSZOTGcp 0XnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LTlYbEmG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id k18sm2643672pfg.217.2020.05.20.10.28.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2020 10:28:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 3/5] include/elf: Add defines related to GNU property notes for AArch64 Date: Wed, 20 May 2020 10:27:58 -0700 Message-Id: <20200520172800.8499-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200520172800.8499-1-richard.henderson@linaro.org> References: <20200520172800.8499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are all of the defines required to parse GNU_PROPERTY_AARCH64_FEATURE_1_AND, copied from binutils. Other missing defines related to other GNU program headers and notes are elided for now. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/elf.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.20.1 diff --git a/include/elf.h b/include/elf.h index 8fbfe60e09..9db4aae40c 100644 --- a/include/elf.h +++ b/include/elf.h @@ -26,9 +26,13 @@ typedef int64_t Elf64_Sxword; #define PT_NOTE 4 #define PT_SHLIB 5 #define PT_PHDR 6 +#define PT_LOOS 0x60000000 +#define PT_HIOS 0x6fffffff #define PT_LOPROC 0x70000000 #define PT_HIPROC 0x7fffffff +#define PT_GNU_PROPERTY (PT_LOOS + 0x474e553) + #define PT_MIPS_REGINFO 0x70000000 #define PT_MIPS_RTPROC 0x70000001 #define PT_MIPS_OPTIONS 0x70000002 @@ -1652,6 +1656,24 @@ typedef struct elf64_shdr { #define NT_ARM_SYSTEM_CALL 0x404 /* ARM system call number */ #define NT_ARM_SVE 0x405 /* ARM Scalable Vector Extension regs */ +/* Defined note types for GNU systems. */ + +#define NT_GNU_PROPERTY_TYPE_0 5 /* Program property */ + +/* Values used in GNU .note.gnu.property notes (NT_GNU_PROPERTY_TYPE_0). */ + +#define GNU_PROPERTY_STACK_SIZE 1 +#define GNU_PROPERTY_NO_COPY_ON_PROTECTED 2 + +#define GNU_PROPERTY_LOPROC 0xc0000000 +#define GNU_PROPERTY_HIPROC 0xdfffffff +#define GNU_PROPERTY_LOUSER 0xe0000000 +#define GNU_PROPERTY_HIUSER 0xffffffff + +#define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000 +#define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1u << 0) +#define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1u << 1) + /* * Physical entry point into the kernel. * From patchwork Wed May 20 17:27:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186998 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp819390ilb; Wed, 20 May 2020 10:31:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxw0qvWodkeOq8fpJZhNok+RBK3P30pZ5nGdSrNXZ3jT49lPCw2MogqSOD6ZviciZrh9IFz X-Received: by 2002:aed:2b67:: with SMTP id p94mr6448099qtd.255.1589995864675; Wed, 20 May 2020 10:31:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589995864; cv=none; d=google.com; s=arc-20160816; b=j2BI6omFEe4EAtItInf9EbDkpfcQxQ+93A+hs3bhdYgl3JH+cula4kKrq2h83eOnAI JsKQdCHRpnqQMTSIxYAx6QaSbv/sB3kUML2JUSVWcQYJwtOTBaZRuZ8uAN0UB4lhDl6D YhsOZ/NT7wIb8Upe0J+plKLiwWcxLXlphGpoCN0MYX5h5qbCJ9J/k2LiyAsdPpYYjJjS lzawIp6f0zEF8AWR89TudW7qMvfLLxN2/YESQfn5S92gv4b0UJsiMrcPrb2B5HbO9daZ S2qaGbV9m/5mSnbsasaAlg2ZjZ96ewnoJ5aPUkddbjluMeFH80ETXU3UrtuvUdUm74Lz teEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kNZVz8klhhmHc+6CSnLmSvrnq7KlJ9l7rdqsf1uPN3I=; b=QdEuBcbdy4udyEBT8dJ0RLYTaTVlD/JPV9Jz4jwBclQD10/gfIG/GSiXyHC9Kts0xu FJmTrfrK/9lovngy8tp6v7cHcBf5qvuZLYlZ+D0girv0FnSm2jP5CRgzhk6jI2nX5prg LPJW2N6S6YwXfcN8qm4nR6HN/Sul53Lz2GQL4QdsdvIykXg1z5a5w5OlgWFV1UPuNFqc RvthFAuIXTyD3wqQdGYL5TR24Hi0TATUjTbvPG1b0z96nf5bAFs3MyCUjpqyfEszF04H P1q56tIauHXqfnYxFW0woOSn5IT5qlJbmJFMyPQ4rHfsGIw4WY6WIoqAroc1oL4aBEU3 zOuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qe1KLMgo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id k18sm2643672pfg.217.2020.05.20.10.28.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2020 10:28:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 4/5] linux-user: Parse NT_GNU_PROPERTY_TYPE_0 notes Date: Wed, 20 May 2020 10:27:59 -0700 Message-Id: <20200520172800.8499-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200520172800.8499-1-richard.henderson@linaro.org> References: <20200520172800.8499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For aarch64, this includes the GNU_PROPERTY_AARCH64_FEATURE_1_BTI bit, which indicates that the image should be mapped with guarded pages. Signed-off-by: Richard Henderson --- v9: Only map the startup executable with BTI; anything else must be handled by the interpreter. --- linux-user/qemu.h | 4 ++ linux-user/elfload.c | 143 ++++++++++++++++++++++++++++++++----------- 2 files changed, 112 insertions(+), 35 deletions(-) -- 2.20.1 diff --git a/linux-user/qemu.h b/linux-user/qemu.h index ce902f5132..d36b18b678 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -61,6 +61,10 @@ struct image_info { abi_ulong interpreter_loadmap_addr; abi_ulong interpreter_pt_dynamic_addr; struct image_info *other_info; + + /* For target-specific processing of NT_GNU_PROPERTY_TYPE_0. */ + uint32_t note_flags; + #ifdef TARGET_MIPS int fp_abi; int interp_fp_abi; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 01a9323a63..c84c9991fd 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2319,7 +2319,7 @@ static void load_elf_image(const char *image_name, int image_fd, struct elfhdr *ehdr = (struct elfhdr *)bprm_buf; struct elf_phdr *phdr; abi_ulong load_addr, load_bias, loaddr, hiaddr, error; - int i, retval; + int i, retval, prot_exec; const char *errmsg; /* First of all, some simple consistency checks */ @@ -2354,17 +2354,90 @@ static void load_elf_image(const char *image_name, int image_fd, loaddr = -1, hiaddr = 0; info->alignment = 0; for (i = 0; i < ehdr->e_phnum; ++i) { - if (phdr[i].p_type == PT_LOAD) { - abi_ulong a = phdr[i].p_vaddr - phdr[i].p_offset; + struct elf_phdr *eppnt = phdr + i; + + if (eppnt->p_type == PT_LOAD) { + abi_ulong a = eppnt->p_vaddr - eppnt->p_offset; if (a < loaddr) { loaddr = a; } - a = phdr[i].p_vaddr + phdr[i].p_memsz; + a = eppnt->p_vaddr + eppnt->p_memsz; if (a > hiaddr) { hiaddr = a; } ++info->nsegs; - info->alignment |= phdr[i].p_align; + info->alignment |= eppnt->p_align; + } else if (eppnt->p_type == PT_INTERP && pinterp_name) { + char *interp_name; + + if (*pinterp_name) { + errmsg = "Multiple PT_INTERP entries"; + goto exit_errmsg; + } + interp_name = malloc(eppnt->p_filesz); + if (!interp_name) { + goto exit_perror; + } + + if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) { + memcpy(interp_name, bprm_buf + eppnt->p_offset, + eppnt->p_filesz); + } else { + retval = pread(image_fd, interp_name, eppnt->p_filesz, + eppnt->p_offset); + if (retval != eppnt->p_filesz) { + goto exit_perror; + } + } + if (interp_name[eppnt->p_filesz - 1] != 0) { + errmsg = "Invalid PT_INTERP entry"; + goto exit_errmsg; + } + *pinterp_name = interp_name; + } else if (eppnt->p_type == PT_GNU_PROPERTY) { + /* Process NT_GNU_PROPERTY_TYPE_0. */ + const uint32_t gnu0_magic = const_le32('G' | 'N' << 8 | 'U' << 16); + uint32_t note[7]; + + /* + * The note contents are 7 words, but depending on LP64 vs ILP32 + * there may be an 8th padding word at the end. Check for and + * read the minimum size. Further checks below will validate + * that the sizes of everything involved are as we expect. + */ + if (eppnt->p_filesz < sizeof(note)) { + continue; + } + if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) { + memcpy(note, bprm_buf + eppnt->p_offset, sizeof(note)); + } else { + retval = pread(image_fd, note, sizeof(note), eppnt->p_offset); + if (retval != sizeof(note)) { + goto exit_perror; + } + } +#ifdef BSWAP_NEEDED + for (i = 0; i < ARRAY_SIZE(note); ++i) { + bswap32s(note + i); + } +#endif + /* + * Check that this is a NT_GNU_PROPERTY_TYPE_0 note. + * Again, descsz includes padding. Full size validation + * awaits checking the final payload. + */ + if (note[0] != 4 || /* namesz */ + note[1] < 12 || /* descsz */ + note[2] != NT_GNU_PROPERTY_TYPE_0 || /* type */ + note[3] != gnu0_magic) { /* name */ + continue; + } +#ifdef TARGET_AARCH64 + if (note[4] == GNU_PROPERTY_AARCH64_FEATURE_1_AND && + note[5] == 4) { + info->note_flags = note[6]; + } +#endif /* TARGET_AARCH64 */ } } @@ -2453,15 +2526,42 @@ static void load_elf_image(const char *image_name, int image_fd, info->brk = 0; info->elf_flags = ehdr->e_flags; + prot_exec = PROT_EXEC; +#ifdef TARGET_AARCH64 + /* + * If the BTI feature is present, this indicates that the executable + * pages of the startup binary should be mapped with PROT_BTI, so that + * branch targets are enforced. + * + * The startup executable is either the interpreter or the static + * binary. The interpreter is responsible for all pages of a + * dynamic executable. + * + * Elf notes are backward compatible to older cpus. + * Do not enable BTI unless it is supported. + */ + if ((info->note_flags & GNU_PROPERTY_AARCH64_FEATURE_1_BTI) + && (pinterp_name == NULL || *pinterp_name == 0) + && cpu_isar_feature(aa64_bti, ARM_CPU(thread_cpu))) { + prot_exec |= TARGET_PROT_BTI; + } +#endif + for (i = 0; i < ehdr->e_phnum; i++) { struct elf_phdr *eppnt = phdr + i; if (eppnt->p_type == PT_LOAD) { abi_ulong vaddr, vaddr_po, vaddr_ps, vaddr_ef, vaddr_em, vaddr_len; int elf_prot = 0; - if (eppnt->p_flags & PF_R) elf_prot = PROT_READ; - if (eppnt->p_flags & PF_W) elf_prot |= PROT_WRITE; - if (eppnt->p_flags & PF_X) elf_prot |= PROT_EXEC; + if (eppnt->p_flags & PF_R) { + elf_prot |= PROT_READ; + } + if (eppnt->p_flags & PF_W) { + elf_prot |= PROT_WRITE; + } + if (eppnt->p_flags & PF_X) { + elf_prot |= prot_exec; + } vaddr = load_bias + eppnt->p_vaddr; vaddr_po = TARGET_ELF_PAGEOFFSET(vaddr); @@ -2511,33 +2611,6 @@ static void load_elf_image(const char *image_name, int image_fd, info->brk = vaddr_em; } } - } else if (eppnt->p_type == PT_INTERP && pinterp_name) { - char *interp_name; - - if (*pinterp_name) { - errmsg = "Multiple PT_INTERP entries"; - goto exit_errmsg; - } - interp_name = malloc(eppnt->p_filesz); - if (!interp_name) { - goto exit_perror; - } - - if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) { - memcpy(interp_name, bprm_buf + eppnt->p_offset, - eppnt->p_filesz); - } else { - retval = pread(image_fd, interp_name, eppnt->p_filesz, - eppnt->p_offset); - if (retval != eppnt->p_filesz) { - goto exit_perror; - } - } - if (interp_name[eppnt->p_filesz - 1] != 0) { - errmsg = "Invalid PT_INTERP entry"; - goto exit_errmsg; - } - *pinterp_name = interp_name; #ifdef TARGET_MIPS } else if (eppnt->p_type == PT_MIPS_ABIFLAGS) { Mips_elf_abiflags_v0 abiflags; From patchwork Wed May 20 17:28:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186999 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp820278ilb; Wed, 20 May 2020 10:32:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzKvdHes1mX5Tt3ql4Hni3tKwaXb8GrofpXZMIkZOwwuy8Sybr7i3VDV+YzdTnbVctApbaO X-Received: by 2002:a05:6214:186b:: with SMTP id eh11mr5896103qvb.35.1589995936692; Wed, 20 May 2020 10:32:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589995936; cv=none; d=google.com; s=arc-20160816; b=Vgw98ALyyIq/6MTMHV+L+poRKb2Ocf6pPaVXmXdHZLZpHCkvvyB1/XqmzhEb/UpO5s aLl2o6/CXm2mtx5jtWH0dvZfphl3MNZRyMWEQOVRp7Xk73rh07BEfyKzMu67w3eNBDZ0 d9JYjBmuC4QVjjpW6MV2NZNreMz393zRrpxigctIMQv9KfSuYg3JfU4pCRyOhyj1SI5u 2FSWikD78R9G9zzJIC4bepezGgPsGLnzwi6a2mVGIM12NeHerMfF77czjRGwKLG9OuTi DvTFlHDTW1UxnpHDMn8f2s16ydlhytuMqqq0ipFTXvKI+zS60KIuJmNQYhwINA9jiq4l ZCwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aq4v7IxgSTWwXHpmoImcRMGs5taMUuju/WMDtCLJnVA=; b=fwKdMY50AQ0aEwKoR1uivGNxfDnYiX0bo0aaTfvdtj7L5+rMKYc0rPsCbnFVtY8Q1F ULcmSsnOstzw9JA6YJUmJqEZ8esjPxKh6CkjatLOhMxD+97yg//f9qnranBwtJCc8bs7 VYaWHqwxiHW5/F3ZzB1D6YXHXfsj5Jo0j8jOmmpmqt2gEOzfEUR9nwtwn4fPc8jReyun wfR4mqiqg3ycupUg0qOEuUjLdEGYPDbx6zX3xEFkEWoxgQI7HfbQC6KZHsFxl5uWO/eE aWCuPB3GYy/Lvwb7DHmR00vvZPAhaT4on4LUcBs6HUb9+1+pqQ/1oHruK/sx6pE1rAEe 8rDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=saSDNi8L; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id k18sm2643672pfg.217.2020.05.20.10.28.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2020 10:28:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 5/5] tests/tcg/aarch64: Add bti smoke test Date: Wed, 20 May 2020 10:28:00 -0700 Message-Id: <20200520172800.8499-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200520172800.8499-1-richard.henderson@linaro.org> References: <20200520172800.8499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. 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Signed-off-by: Richard Henderson --- v9: Expect and require gcc 10. --- tests/tcg/aarch64/bti-1.c | 62 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/bti-crt.inc.c | 51 +++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 7 ++++ tests/tcg/configure.sh | 4 ++ 4 files changed, 124 insertions(+) create mode 100644 tests/tcg/aarch64/bti-1.c create mode 100644 tests/tcg/aarch64/bti-crt.inc.c -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/tests/tcg/aarch64/bti-1.c b/tests/tcg/aarch64/bti-1.c new file mode 100644 index 0000000000..61924f0d7a --- /dev/null +++ b/tests/tcg/aarch64/bti-1.c @@ -0,0 +1,62 @@ +/* + * Branch target identification, basic notskip cases. + */ + +#include "bti-crt.inc.c" + +static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc) +{ + uc->uc_mcontext.pc += 8; + uc->uc_mcontext.pstate = 1; +} + +#define NOP "nop" +#define BTI_N "hint #32" +#define BTI_C "hint #34" +#define BTI_J "hint #36" +#define BTI_JC "hint #38" + +#define BTYPE_1(DEST) \ + asm("mov %0,#1; adr x16, 1f; br x16; 1: " DEST "; mov %0,#0" \ + : "=r"(skipped) : : "x16") + +#define BTYPE_2(DEST) \ + asm("mov %0,#1; adr x16, 1f; blr x16; 1: " DEST "; mov %0,#0" \ + : "=r"(skipped) : : "x16", "x30") + +#define BTYPE_3(DEST) \ + asm("mov %0,#1; adr x15, 1f; br x15; 1: " DEST "; mov %0,#0" \ + : "=r"(skipped) : : "x15") + +#define TEST(WHICH, DEST, EXPECT) \ + do { WHICH(DEST); fail += skipped ^ EXPECT; } while (0) + + +int main() +{ + int fail = 0; + int skipped; + + /* Signal-like with SA_SIGINFO. */ + signal_info(SIGILL, skip2_sigill); + + TEST(BTYPE_1, NOP, 1); + TEST(BTYPE_1, BTI_N, 1); + TEST(BTYPE_1, BTI_C, 0); + TEST(BTYPE_1, BTI_J, 0); + TEST(BTYPE_1, BTI_JC, 0); + + TEST(BTYPE_2, NOP, 1); + TEST(BTYPE_2, BTI_N, 1); + TEST(BTYPE_2, BTI_C, 0); + TEST(BTYPE_2, BTI_J, 1); + TEST(BTYPE_2, BTI_JC, 0); + + TEST(BTYPE_3, NOP, 1); + TEST(BTYPE_3, BTI_N, 1); + TEST(BTYPE_3, BTI_C, 1); + TEST(BTYPE_3, BTI_J, 0); + TEST(BTYPE_3, BTI_JC, 0); + + return fail; +} diff --git a/tests/tcg/aarch64/bti-crt.inc.c b/tests/tcg/aarch64/bti-crt.inc.c new file mode 100644 index 0000000000..47805f4e35 --- /dev/null +++ b/tests/tcg/aarch64/bti-crt.inc.c @@ -0,0 +1,51 @@ +/* + * Minimal user-environment for testing BTI. + * + * Normal libc is not (yet) built with BTI support enabled, + * and so could generate a BTI TRAP before ever reaching main. + */ + +#include +#include +#include +#include + +int main(void); + +void _start(void) +{ + exit(main()); +} + +void exit(int ret) +{ + register int x0 __asm__("x0") = ret; + register int x8 __asm__("x8") = __NR_exit; + + asm volatile("svc #0" : : "r"(x0), "r"(x8)); + __builtin_unreachable(); +} + +/* + * Irritatingly, the user API struct sigaction does not match the + * kernel API struct sigaction. So for simplicity, isolate the + * kernel ABI here, and make this act like signal. + */ +void signal_info(int sig, void (*fn)(int, siginfo_t *, ucontext_t *)) +{ + struct kernel_sigaction { + void (*handler)(int, siginfo_t *, ucontext_t *); + unsigned long flags; + unsigned long restorer; + unsigned long mask; + } sa = { fn, SA_SIGINFO, 0, 0 }; + + register int x0 __asm__("x0") = sig; + register void *x1 __asm__("x1") = &sa; + register void *x2 __asm__("x2") = 0; + register int x3 __asm__("x3") = sizeof(unsigned long); + register int x8 __asm__("x8") = __NR_rt_sigaction; + + asm volatile("svc #0" + : : "r"(x0), "r"(x1), "r"(x2), "r"(x3), "r"(x8) : "memory"); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 312f36cde5..cf84787eb6 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -24,6 +24,13 @@ run-pauth-%: QEMU_OPTS += -cpu max pauth-%: CFLAGS += -march=armv8.3-a endif +# BTI Tests +ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_BTI),) +AARCH64_TESTS += bti-1 +bti-%: CFLAGS += -mbranch-protection=standard +bti-%: LDFLAGS += -nostdlib +endif + # Semihosting smoke test for linux-user AARCH64_TESTS += semihosting run-semihosting: semihosting diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index 2326f97856..ebfe3e2ce5 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -231,6 +231,10 @@ for target in $target_list; do -march=armv8.3-a -o $TMPE $TMPC; then echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak fi + if do_compiler "$target_compiler" $target_compiler_cflags \ + -mbranch-protection=standard -o $TMPE $TMPC; then + echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak + fi ;; esac