From patchwork Wed Jun 11 09:33:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 896181 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF52241C69; Wed, 11 Jun 2025 09:33:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749634409; cv=none; b=Wottc1tv29Dpqn46O8lPyJBLUQAOkRZspJHNL/he9NmUb8Gt2wqyQPoAQ2y5BswOshVhqEFO/tujliJ+GZRUyDW8ABDPvZCBVEC5bN+Lj7R0w4AdUfXxaOdp6KFspXsRXP83RZS7bcmKZwCC0vM8yaedkTp3SLXYc2tXKe/aQ70= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749634409; c=relaxed/simple; bh=tNva/wal8+pzgbVVJObgRAKljanokSBTcRFs03EX+oc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=n9ORHFD9UQ5q9jwcWl9en9zZGYZaEZ9T57MYrIkxhHNA0/8cGunqKMm4bSXC3wPKhRPo1Ns6a8yvpANejm0F/NckUqpklnzqF2gnqfvTU/vx9Q2RiwsVhDHTIwNkcGgjwFAj4TqffWCTHREFbEEDR1TsPWh/VZgBnFCM3R86YlU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RVEMPM1u; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RVEMPM1u" Received: by smtp.kernel.org (Postfix) with ESMTPS id 80EB0C4CEF1; Wed, 11 Jun 2025 09:33:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749634408; bh=tNva/wal8+pzgbVVJObgRAKljanokSBTcRFs03EX+oc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=RVEMPM1uuqzF2XP1L0vmnGR71lBqo6LDjqJ9lwCYz6SRJlrRnAQ8/iTXMbPjncFAh 9Z8waWvCfkqmd8xBNkPB9WTF5Vgd5+UDd6UChC4hvm8Uv+1jtacHEwUE+YXdQ+mt27 DsZ6tj2DDSUin0T0NCIo7q4/GETgYQo2yzQ+jLpdLYELsmyhQz4c6gCwq2M28X1z/v Gboh10gnv2pUCiQ5CmoSrJXNjavX8DRVdpywEm1YvZj+U/Ib2GcDB/V2UyPgUyOCuJ o6m03ftDOm81CmV6MKtVn0kzeB8p5rxGuit5UChAiTKHuqI8NxVizDMhlrvLjxBFEI IsZIQz5cUxCpQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65B23C71133; Wed, 11 Jun 2025 09:33:28 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 11 Jun 2025 13:33:21 +0400 Subject: [PATCH v12 1/2] dt-bindings: thermal: qcom-tsens: make ipq5018 tsens standalone compatible Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250611-ipq5018-tsens-v12-1-a61374a5517d@outlook.com> References: <20250611-ipq5018-tsens-v12-0-a61374a5517d@outlook.com> In-Reply-To: <20250611-ipq5018-tsens-v12-0-a61374a5517d@outlook.com> To: Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Sricharan Ramabadhran , George Moussalem Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749634406; l=1481; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=RrfwkZTGbLqY30+ytKz/HO9wG4uq1c9Mr1ofBKoxP4E=; b=uSS6oEbXYaZWYfPMJ4LGi4HC6UK87th9GkY7K38TmPHbR6RzIbPWARIZ7g8oR6a3Dwi+3iw+2 VHUhy1UEGlBA3MHCwL3aMK5Q9V3EgFBZJpPUo4aVi+LnlTLkApEdp20 X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem IPQ5018 tsens should not use qcom,tsens-v1 as fallback since it has no RPM and, as such, must deviates from the standard v1 init routine in the driver as this version of tsens needs to be explicitly reset and enabled in the driver. So let's make qcom,ipq5018-tsens a standalone compatible in the bindings. Fixes: 77c6d28192ef ("dt-bindings: thermal: qcom-tsens: Add ipq5018 compatible") Signed-off-by: George Moussalem --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 0e653bbe9884953b58c4d8569b8d096db47fd54f..3cf16f6734fcfee20735d3da2cfb0f708a11bca4 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -36,10 +36,15 @@ properties: - qcom,msm8974-tsens - const: qcom,tsens-v0_1 + - description: + v1 of TSENS without RPM which requires to be explicitly reset + and enabled in the driver. + enum: + - qcom,ipq5018-tsens + - description: v1 of TSENS items: - enum: - - qcom,ipq5018-tsens - qcom,msm8937-tsens - qcom,msm8956-tsens - qcom,msm8976-tsens From patchwork Wed Jun 11 09:33:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 895674 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04B95155316; Wed, 11 Jun 2025 09:33:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749634409; cv=none; b=ghzQNczoxeSb/6IiiAJTQw4XYk7xjtvqe4YYiJauKzP6GJMh8/l0UVtq5JYgeaKddiYl7ZCxXC9V5RykdHp8pHIJ+FHwDOc5RtxoIPz2hGUNQSEyFJVgMtjcYuDLHa+ULCxFw+MBmPDsXUIERoxOQK7o7fGSKhPaE7DPsdvGZGM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749634409; c=relaxed/simple; bh=BkxTyX33gHEtjP2JawH8Psdf9hWjmqaryNkUQiqnx24=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=f5RTSZQ+YjwxYL+JDIw+8by8os9WFhy+I+k+OHOpGzgrQXQZWdM39k4elDxoQ2hvJ85RE3OyBPCsfUka959DMQ03ghfsVjm8tEIm6itr0BSGWjY2s1JulC4r/K4qXXaravtqrcRZcPOiGS5nXRmpsB8UXDxjskO9of3w/ioKOu4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lwddOD4B; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lwddOD4B" Received: by smtp.kernel.org (Postfix) with ESMTPS id 925E5C4CEF5; Wed, 11 Jun 2025 09:33:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749634408; bh=BkxTyX33gHEtjP2JawH8Psdf9hWjmqaryNkUQiqnx24=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lwddOD4BUITNJefvLV6urjbZ6VG2JK+Z7fIw1tUFOhjhQhbThJYak9wFBuWK3rki+ f6W0z3KpNQSN5n2QSMJNAZMZuYhv25FXblabKi/TqgfoLrU+N+4g4i4tJ6pABGf6+T lH4b5FlOKAxybiMIROSzL9/2DOSY50FjgxI8z4zym4d5mFWsotU7b6+rGLx4OYLWKm 7eQfYbaKo2rgHVPPKksfEoWdnoZtbFVAUOtnEAhoNdkSeqYfhYFVVDE9DRsIEt/wsU vDfMM3GXrEqzl1l1LGttjitJN9dPlugMbl1PR6YQ8UhkccHA0hAVPrbh07ievsBYlQ Bb5SNFMHgPw0A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7520BC61CE7; Wed, 11 Jun 2025 09:33:28 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 11 Jun 2025 13:33:22 +0400 Subject: [PATCH v12 2/2] arm64: dts: qcom: ipq5018: Add tsens node Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250611-ipq5018-tsens-v12-2-a61374a5517d@outlook.com> References: <20250611-ipq5018-tsens-v12-0-a61374a5517d@outlook.com> In-Reply-To: <20250611-ipq5018-tsens-v12-0-a61374a5517d@outlook.com> To: Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Sricharan Ramabadhran , George Moussalem Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749634406; l=5540; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=8VbrGnbVEEGlTeBi9Ev67z9HvHAIvHkO/H7Vls/aG78=; b=zOlvLASLbZRV6aQmyd1XNl5LHAn0Ynoz4pQvZyTDfjrUW1bRaF+HVymXg0yjlmU4dOYWadTK7 4YN5He6yOuwAv5T6tIhAhure5IoUI1Dq3VlHgzlC6IY7yn/DEeWn9he X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Sricharan Ramabadhran IPQ5018 has tsens V1.0 IP with 5 sensors, though 4 are in use. There is no RPM, so tsens has to be manually enabled. Adding the tsens and nvmem nodes and adding 4 thermal sensors (zones). The critical trip temperature is set to 120'C with an action to reboot. In addition, adding a cooling device to the CPU thermal zone which uses CPU frequency scaling. Reviewed-by: Dmitry Baryshkov Signed-off-by: Sricharan Ramabadhran Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 182 ++++++++++++++++++++++++++++++++++ 1 file changed, 182 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 130360014c5e14c778e348d37e601f60325b0b14..defeb697c8d89686e3aaf2e6f7b6cb7493219336 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -39,6 +40,7 @@ cpu0: cpu@0 { next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -49,6 +51,7 @@ cpu1: cpu@1 { next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; l2_0: l2-cache { @@ -182,6 +185,117 @@ pcie0_phy: phy@86000 { status = "disabled"; }; + qfprom: qfprom@a0000 { + compatible = "qcom,ipq5018-qfprom", "qcom,qfprom"; + reg = <0x000a0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_mode: mode@249 { + reg = <0x249 0x1>; + bits = <0 3>; + }; + + tsens_base1: base1@249 { + reg = <0x249 0x2>; + bits = <3 8>; + }; + + tsens_base2: base2@24a { + reg = <0x24a 0x2>; + bits = <3 8>; + }; + + tsens_s0_p1: s0-p1@24b { + reg = <0x24b 0x2>; + bits = <2 6>; + }; + + tsens_s0_p2: s0-p2@24c { + reg = <0x24c 0x1>; + bits = <1 6>; + }; + + tsens_s1_p1: s1-p1@24c { + reg = <0x24c 0x2>; + bits = <7 6>; + }; + + tsens_s1_p2: s1-p2@24d { + reg = <0x24d 0x2>; + bits = <5 6>; + }; + + tsens_s2_p1: s2-p1@24e { + reg = <0x24e 0x2>; + bits = <3 6>; + }; + + tsens_s2_p2: s2-p2@24f { + reg = <0x24f 0x1>; + bits = <1 6>; + }; + + tsens_s3_p1: s3-p1@24f { + reg = <0x24f 0x2>; + bits = <7 6>; + }; + + tsens_s3_p2: s3-p2@250 { + reg = <0x250 0x2>; + bits = <5 6>; + }; + + tsens_s4_p1: s4-p1@251 { + reg = <0x251 0x2>; + bits = <3 6>; + }; + + tsens_s4_p2: s4-p2@254 { + reg = <0x254 0x1>; + bits = <0 6>; + }; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq5018-tsens"; + reg = <0x004a9000 0x1000>, + <0x004a8000 0x1000>; + + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, + <&tsens_base2>, + <&tsens_s0_p1>, + <&tsens_s0_p2>, + <&tsens_s1_p1>, + <&tsens_s1_p2>, + <&tsens_s2_p1>, + <&tsens_s2_p2>, + <&tsens_s3_p1>, + <&tsens_s3_p2>, + <&tsens_s4_p1>, + <&tsens_s4_p2>; + + nvmem-cell-names = "mode", + "base1", + "base2", + "s0_p1", + "s0_p2", + "s1_p1", + "s1_p2", + "s2_p1", + "s2_p2", + "s3_p1", + "s3_p2", + "s4_p1", + "s4_p2"; + + interrupts = ; + interrupt-names = "uplow"; + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>; @@ -631,6 +745,74 @@ pcie@0 { }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&tsens 2>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <2>; + type = "critical"; + }; + + cpu_alert: cpu-passive { + temperature = <100000>; + hysteresis = <2>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gephy-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&tsens 4>; + + trips { + gephy-critical { + temperature = <120000>; + hysteresis = <2>; + type = "critical"; + }; + }; + }; + + top-glue-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&tsens 3>; + + trips { + top-glue-critical { + temperature = <120000>; + hysteresis = <2>; + type = "critical"; + }; + }; + }; + + ubi32-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&tsens 1>; + + trips { + ubi32-critical { + temperature = <120000>; + hysteresis = <2>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = ,