From patchwork Wed Jun 18 10:22:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 897868 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80C2D291C0C for ; Wed, 18 Jun 2025 10:22:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750242151; cv=none; b=rI3UzVNSAR9gi3OJe2YPHPNzRRI1Q3nPpu6K9XvcFbOOevKKeMerSTfxpQ6tdc8If8iz6Vr3hPsMkCzzHEJwp5cYBtkWZ4VYD8Lw2n8hSM2QWOaHrziFOAb+jyMqxdxL1GG/tPKlfIM1a+t7zpujdvGrdGFhjTZLg5eCA3aC1dE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750242151; c=relaxed/simple; bh=WRlTrsWOi/i85ebZasssiJ4ZtiiHBTtd9LezuNSNDfQ=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=dTTItHhcJJUAeHOiIw0taBXOrAz2ObvwPo1lLItMAotjXTmbwGhHeuYkDUZji3OKJ9pdAgGqUkWVIO1P6vLZetw32ZWndmUuL/YDgRKuNCWQBxJhOdowZFq07Z7QzFF619YvF3joYD6WuhMOKJjDQ3bQF+OWNF2Z96JhetxHXOE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=hpYusI0q; arc=none smtp.client-ip=210.118.77.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="hpYusI0q" Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20250618102227euoutp02700b785ab473cf201c9bde724ba2f606~KG-XcMZsP2430624306euoutp02S for ; Wed, 18 Jun 2025 10:22:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20250618102227euoutp02700b785ab473cf201c9bde724ba2f606~KG-XcMZsP2430624306euoutp02S DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1750242148; bh=63b01qSumkcLmIEY0xdhZ+QcRoYutlUuGjICSf4+AW0=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=hpYusI0qCOndIuRLvKCeZBjC0dnxXjV80+FYxNTKDN6s5FU3G34pYQWlP50+2A9J3 LXO+LAXkmmnEoslHpaGTdoZU3CoTg12HvhlXYMQ20mlmKKWp1+zTK8l3fe2a+/m84R 3CW94IW9i3XodpoKjEDROtKk4EPDpdxb+LryZGNU= Received: from eusmtip1.samsung.com (unknown [203.254.199.221]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20250618102227eucas1p26e8968805092c3ce0ecbe84e9724a6e2~KG-W6T4lR2901029010eucas1p2W; Wed, 18 Jun 2025 10:22:27 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250618102226eusmtip130e43c3ee9d13c7c00906f7347907b07~KG-V8arCD1490514905eusmtip1H; Wed, 18 Jun 2025 10:22:26 +0000 (GMT) From: Michal Wilczynski Date: Wed, 18 Jun 2025 12:22:08 +0200 Subject: [PATCH v5 2/8] dt-bindings: firmware: thead,th1520: Add resets for GPU clkgen Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250618-apr_14_for_sending-v5-2-27ed33ea5c6f@samsung.com> In-Reply-To: <20250618-apr_14_for_sending-v5-0-27ed33ea5c6f@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250618102227eucas1p26e8968805092c3ce0ecbe84e9724a6e2 X-Msg-Generator: CA X-RootMTR: 20250618102227eucas1p26e8968805092c3ce0ecbe84e9724a6e2 X-EPHeader: CA X-CMS-RootMailID: 20250618102227eucas1p26e8968805092c3ce0ecbe84e9724a6e2 References: <20250618-apr_14_for_sending-v5-0-27ed33ea5c6f@samsung.com> Extend the TH1520 AON to describe the GPU clkgen reset line, required for proper GPU clock and reset sequencing. The T-HEAD TH1520 GPU requires coordinated management of two clocks (core and sys) and two resets (GPU core reset and GPU clkgen reset). Only the clkgen reset is exposed at the AON level, to support SoC specific initialization handled through a dedicated auxiliary power sequencing driver. The GPU core reset remains described in the GPU device node, as from the GPU driver's perspective, there is only a single reset line [1]. This follows upstream maintainers' recommendations [2] to abstract SoC specific details into the PM domain layer rather than exposing them to drivers directly. Link: https://lore.kernel.org/all/816db99d-7088-4c1a-af03-b9a825ac09dc@imgtec.com/ - [1] Link: https://lore.kernel.org/all/38d9650fc11a674c8b689d6bab937acf@kernel.org/ - [2] Reviewed-by: Ulf Hansson Signed-off-by: Michal Wilczynski --- Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml index bbc183200400de7aadbb21fea21911f6f4227b09..3365124c7fd4736922717bd31caa13272f4a4ea6 100644 --- a/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml +++ b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml @@ -32,6 +32,13 @@ properties: items: - const: aon + resets: + maxItems: 1 + + reset-names: + items: + - const: gpu-clkgen + "#power-domain-cells": const: 1 From patchwork Wed Jun 18 10:22:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 897867 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36652215F4B for ; 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Wed, 18 Jun 2025 10:22:30 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250618102229eusmtip132bf2e8d5ca6d3dcb5878ee5cd672b4c~KG-ZDGa291490514905eusmtip1I; Wed, 18 Jun 2025 10:22:29 +0000 (GMT) From: Michal Wilczynski Date: Wed, 18 Jun 2025 12:22:11 +0200 Subject: [PATCH v5 5/8] dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU compatible Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250618-apr_14_for_sending-v5-5-27ed33ea5c6f@samsung.com> In-Reply-To: <20250618-apr_14_for_sending-v5-0-27ed33ea5c6f@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, Krzysztof Kozlowski X-Mailer: b4 0.15-dev X-CMS-MailID: 20250618102230eucas1p2573610db9d4a9f3543d0048c30b2df9e X-Msg-Generator: CA X-RootMTR: 20250618102230eucas1p2573610db9d4a9f3543d0048c30b2df9e X-EPHeader: CA X-CMS-RootMailID: 20250618102230eucas1p2573610db9d4a9f3543d0048c30b2df9e References: <20250618-apr_14_for_sending-v5-0-27ed33ea5c6f@samsung.com> Update the img,powervr-rogue.yaml to include the T-HEAD TH1520 SoC's specific GPU compatible string. The thead,th1520-gpu compatible, along with its full chain img,img-bxm-4-64, and img,img-rogue, is added to the list of recognized GPU types. The power-domains property requirement for img,img-bxm-4-64 is also ensured by adding it to the relevant allOf condition. Acked-by: Krzysztof Kozlowski Reviewed-by: Ulf Hansson Signed-off-by: Michal Wilczynski --- Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 4450e2e73b3ccf74d29f0e31e2e6687d7cbe5d65..9b241a0c1f5941dc58a1e23970f6d3773d427c22 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -21,6 +21,11 @@ properties: # work with newer dts. - const: img,img-axe - const: img,img-rogue + - items: + - enum: + - thead,th1520-gpu + - const: img,img-bxm-4-64 + - const: img,img-rogue - items: - enum: - ti,j721s2-gpu @@ -93,7 +98,9 @@ allOf: properties: compatible: contains: - const: img,img-axe-1-16m + enum: + - img,img-axe-1-16m + - img,img-bxm-4-64 then: properties: power-domains: From patchwork Wed Jun 18 10:22:12 2025 Content-Type: text/plain; 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a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1750242152; bh=03clYuLUe6lZViLZ7J3QsFCYeiK6qNUgF531eyi5Uj4=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=ApxDq+q7YQ8RwciF1FUJBLaE/9u/BOkQbAR48Dk6iJzTtmqFEpHk4O7CXjpIUtjJB tQXuBxNbHQLPsjJog0QeABHnGwJ1rw8WWFBUvfi/KfppVTg7BtjSRW5Ux9ecCRHGZu +TxZ4x5c1tw4hzyTQJ3ec16qiSYMYz5sdgSDWwpo= Received: from eusmtip1.samsung.com (unknown [203.254.199.221]) by eucas1p1.samsung.com (KnoxPortal) with ESMTPA id 20250618102231eucas1p1ec99058179825cb1250a1f189313b3eb~KG-bGe0in2809028090eucas1p1_; Wed, 18 Jun 2025 10:22:31 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250618102230eusmtip198543fedf6efd80d3c0af56b4c5c4765~KG-aIXtgN1490914909eusmtip1I; Wed, 18 Jun 2025 10:22:30 +0000 (GMT) From: Michal Wilczynski Date: Wed, 18 Jun 2025 12:22:12 +0200 Subject: [PATCH v5 6/8] riscv: dts: thead: th1520: Add GPU clkgen reset to AON node Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250618-apr_14_for_sending-v5-6-27ed33ea5c6f@samsung.com> In-Reply-To: <20250618-apr_14_for_sending-v5-0-27ed33ea5c6f@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250618102231eucas1p1ec99058179825cb1250a1f189313b3eb X-Msg-Generator: CA X-RootMTR: 20250618102231eucas1p1ec99058179825cb1250a1f189313b3eb X-EPHeader: CA X-CMS-RootMailID: 20250618102231eucas1p1ec99058179825cb1250a1f189313b3eb References: <20250618-apr_14_for_sending-v5-0-27ed33ea5c6f@samsung.com> Add the "gpu-clkgen" reset property to the AON device tree node. This allows the AON power domain driver to detect the capability to power sequence the GPU and spawn the necessary pwrseq-thead-gpu auxiliary driver for managing the GPU's complex power sequence. This commit also adds the prerequisite dt-bindings/reset/thead,th1520-reset.h include to make the TH1520_RESET_ID_GPU_CLKGEN available. This include was previously dropped during a conflict resolution [1]. Link: https://lore.kernel.org/all/aAvfn2mq0Ksi8DF2@x1/ [1] Reviewed-by: Ulf Hansson Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 1db0054c4e093400e9dbebcee5fcfa5b5cae6e32..f3f5db0201ab8c0306d4d63072a1573431e51893 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { compatible = "thead,th1520"; @@ -234,6 +235,8 @@ aon: aon { compatible = "thead,th1520-aon"; mboxes = <&mbox_910t 1>; mbox-names = "aon"; + resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; + reset-names = "gpu-clkgen"; #power-domain-cells = <1>; }; From patchwork Wed Jun 18 10:22:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 897865 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A337B288C3E for ; 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Wed, 18 Jun 2025 10:22:34 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250618102233eusmtip19348d4038a9799137d47f88522c45772~KG-cMZhq41210412104eusmtip1r; Wed, 18 Jun 2025 10:22:33 +0000 (GMT) From: Michal Wilczynski Date: Wed, 18 Jun 2025 12:22:14 +0200 Subject: [PATCH v5 8/8] drm/imagination: Enable PowerVR driver for RISC-V Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250618-apr_14_for_sending-v5-8-27ed33ea5c6f@samsung.com> In-Reply-To: <20250618-apr_14_for_sending-v5-0-27ed33ea5c6f@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250618102234eucas1p2a1899b494c5ed75e0f39ea517d81c81d X-Msg-Generator: CA X-RootMTR: 20250618102234eucas1p2a1899b494c5ed75e0f39ea517d81c81d X-EPHeader: CA X-CMS-RootMailID: 20250618102234eucas1p2a1899b494c5ed75e0f39ea517d81c81d References: <20250618-apr_14_for_sending-v5-0-27ed33ea5c6f@samsung.com> Several RISC-V boards feature Imagination GPUs that are compatible with the PowerVR driver. An example is the IMG BXM-4-64 GPU on the Lichee Pi 4A board. This commit adjusts the driver's Kconfig dependencies to allow the PowerVR driver to be compiled on the RISC-V architecture. By enabling compilation on RISC-V, we expand support for these GPUs, providing graphics acceleration capabilities and enhancing hardware compatibility on RISC-V platforms. Add a dependency on MMU to fix a build warning on RISC-V configurations without an MMU and enable COMPILE_TEST to improve build coverage. Reviewed-by: Ulf Hansson Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/Kconfig b/drivers/gpu/drm/imagination/Kconfig index 5f9fff43d6baadc42ebf48d91729bfbf27e06caa..48fd31c031628c70b1e0952271baccf7f4694810 100644 --- a/drivers/gpu/drm/imagination/Kconfig +++ b/drivers/gpu/drm/imagination/Kconfig @@ -3,9 +3,10 @@ config DRM_POWERVR tristate "Imagination Technologies PowerVR (Series 6 and later) & IMG Graphics" - depends on ARM64 + depends on (ARM64 || RISCV) || COMPILE_TEST depends on DRM depends on PM + depends on MMU select DRM_EXEC select DRM_GEM_SHMEM_HELPER select DRM_SCHED