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X-Received-From: 2a00:1450:400c:c0c::22d Subject: [Qemu-devel] [RISU PATCH 01/11] risu: make match status take tracing into account X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- reginfo.c | 14 +++++++++----- risu.c | 4 ++-- risu.h | 2 +- 3 files changed, 12 insertions(+), 8 deletions(-) -- 2.13.0 diff --git a/reginfo.c b/reginfo.c index 13879d5..d9d37b3 100644 --- a/reginfo.c +++ b/reginfo.c @@ -138,7 +138,7 @@ int recv_and_compare_register_info(read_fn read_fn, * Should return 0 if it was a good match (ie end of test) * and 1 for a mismatch. */ -int report_match_status(void) +int report_match_status(int trace) { int resp = 0; fprintf(stderr, "match status...\n"); @@ -148,7 +148,7 @@ int report_match_status(void) /* We don't have valid reginfo from the apprentice side * so stop now rather than printing anything about it. */ - fprintf(stderr, "master reginfo:\n"); + fprintf(stderr, "%s reginfo:\n", trace ? "this":"master"); reginfo_dump(&master_ri, stderr); return 1; } @@ -166,11 +166,15 @@ int report_match_status(void) return 0; } - fprintf(stderr, "master reginfo:\n"); + fprintf(stderr, "%s reginfo:\n", trace ? "this":"master"); reginfo_dump(&master_ri, stderr); - fprintf(stderr, "apprentice reginfo:\n"); + fprintf(stderr, "%s reginfo:\n", trace ? "trace":"apprentice"); reginfo_dump(&apprentice_ri, stderr); - reginfo_dump_mismatch(&master_ri, &apprentice_ri, stderr); + if (trace) { + reginfo_dump_mismatch(&apprentice_ri, &master_ri, stderr); + } else { + reginfo_dump_mismatch(&master_ri, &apprentice_ri, stderr); + } return resp; } diff --git a/risu.c b/risu.c index 6f213dc..47471c6 100644 --- a/risu.c +++ b/risu.c @@ -228,7 +228,7 @@ int master(void) signal_count); return 0; } else { - return report_match_status(); + return report_match_status(0); } } set_sigill_handler(&master_sigill); @@ -250,7 +250,7 @@ int apprentice(void) #endif close(apprentice_fd); fprintf(stderr, "finished early after %zd checkpoints\n", signal_count); - return report_match_status(); + return report_match_status(1); } set_sigill_handler(&apprentice_sigill); fprintf(stderr, "starting apprentice image at 0x%"PRIxPTR"\n", diff --git a/risu.h b/risu.h index 9f15662..1c8ecee 100644 --- a/risu.h +++ b/risu.h @@ -91,7 +91,7 @@ int recv_and_compare_register_info(read_fn read_fn, * Should return 0 if it was a good match (ie end of test) * and 1 for a mismatch. */ -int report_match_status(void); +int report_match_status(int trace); /* Interface provided by CPU-specific code: */ From patchwork Tue Jul 4 14:48:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 106985 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp1092931qge; Tue, 4 Jul 2017 07:53:15 -0700 (PDT) X-Received: by 10.55.183.129 with SMTP id h123mr45091917qkf.75.1499179995519; Tue, 04 Jul 2017 07:53:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1499179995; cv=none; d=google.com; s=arc-20160816; b=qa1YDPq23rigwCH21VXvdAJCLlkRMRuBy/CR80mIJoepzuCaRCjqekpjyRJBFlwdfQ 5WoDd334NB70qFo0II/2IBZo+YTj1qxb31cSgD8YWFcGFmrEeggCSbx91iG+QItv7PeM GXI1SEtXbYTWXI+icp1kF0i5eD21KEVO1aHh+YpUpXmESUtdDb/QURM/sLddiLwiFsRk KyrfQPiSQtBdkuhLO828a4EMvUWBNeNBYyRI5q8vU+qBiq25207M71bxpaCOjpPIjRs6 kDC3HvwtVrjVpX//GemktXTqsGLdrGGcffIzcnB48jjOh8zgocNuxnMNqrEtldHI+QNF MpnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=F8yl9dSoVDbMRq5dc/P7Ahv4mo8YJHu1zH25w5Joy/E=; b=lTdv8Z0FeRoq1fAbaSTv+JUarcICyduakAboROnEcg9uue8gxVK5CK0c+bCLJPZ0Ow atRMvgWXbCliewv8mRMctFYKPWRKZeFNsx7TGICjcIayygMJMTFXwrN3f7sXPPubJn8o 0xDQ5rHPXlc35vJvl4wCzglrKIyNW2tHTiZYBq1SC7EpwM9FOTH1bnZPfUFTtebDiZQD iJNkgxHxOku7BXPb5NzOCWPqFeJF/pjmU4+UMuWw8n6+LKmvkSr9NNcNjTZ2HvUcvO5b C74OcMS2+VtasLGDaWV8PCu+1nXr6gmRs+ceTq2Uonbwss2+PzJGopVAUhHDB92r597F wUzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.b=ahPYOnqK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::232 Subject: [Qemu-devel] [RISU PATCH 02/11] reginfo.c: always return 1 on OP_TESTEND X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In the master/apprentice setup the response byte of 1 is returned by write_fn. However when tracing it will happily report 0 as it successfully writes the last bytes. To avoid running of the end when tracing we just always return 1 at this point. Signed-off-by: Alex Bennée --- reginfo.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.13.0 diff --git a/reginfo.c b/reginfo.c index d9d37b3..76f24f9 100644 --- a/reginfo.c +++ b/reginfo.c @@ -39,7 +39,10 @@ int send_register_info(write_fn write_fn, void *uc) switch (op) { case OP_TESTEND: - return write_fn(&ri, sizeof(ri)); + write_fn(&ri, sizeof(ri)); + /* if we are tracing write_fn will return 0 unlike a remote + end, hence we force return of 1 here */ + return 1; case OP_SETMEMBLOCK: memblock = (void *)(uintptr_t)get_reginfo_paramreg(&ri); break; From patchwork Tue Jul 4 14:48:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 106979 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp1089144qge; Tue, 4 Jul 2017 07:48:54 -0700 (PDT) X-Received: by 10.55.141.198 with SMTP id p189mr51799113qkd.97.1499179734598; Tue, 04 Jul 2017 07:48:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1499179734; cv=none; d=google.com; s=arc-20160816; b=yZjCUr+YSzWOlwPSK/9VH0eITogJ0srPNpxyTXtusU9r+GJ/xcLoythP3C9gy4bNbU Pa7ezsXjo/yzgNP4C1vtuE4QeHwyaQd3Hc97Xi4imfrQhPX+nvzqSFH3/cs333KSZSxz Up4ggoWYomKsFz/TjsNAOMlpld77Qj9eB7CJPT3fTGMU8Gvf+08SFCQfu+FoBMGZ2ud7 eOxGxyb2H176Wj/ITo/2xthC/Vt3yyiY1k7q59FH5qXYhZRVBms2tmd0Z7OBTLPzRm8S kEhukUtruL20afTHzQrBCxjXGtFH0SBIum6VShhjCO3hypxzt6iPYWLZcZmjubquFwkq 5tzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=81S40Mta2D6KRS1shdF2cFudpSKzvnPh8QMj2aasreM=; b=BwcnPakpCddQc2OEevMN2nFnDDMabudTP5Urtkm1TAC/iuV7tx8K+Tb9oeTyQqoUSj fgllSTVTBnCfR5PwExfX8MTDckZ3EjBUzVUnjL9035J4kwLGwH3VqV0Bz4xdn75JjYcj jfc0qbZQ3g/uK7rXlK3wP+1LZ0UaqTyWS88zdxFcypvqbR03Ix7RuoDiQtHpLtiQYgAO VxOHrkKJNJKtVI4QfPZH/VCeZ8wTHpcHS89UC/UF+ga1/XhpIaTiMSj3UdHV7nZutkG6 P+LSt0UvZuVYhbaNi5dVafuUVH0vZKxE9qD4GjHbdyalzZfwD9qThS6wH23iNnNwkrPD teyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.b=bA3rHbXs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::231 Subject: [Qemu-devel] [RISU PATCH 03/11] README: document --static builds X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- README | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) -- 2.13.0 diff --git a/README b/README index 858a349..e0bf5c5 100644 --- a/README +++ b/README @@ -17,7 +17,7 @@ test blobs (which can be run anywhere), and a Linux executable 'risu' which runs on the target architecture (ie ARM). To build the executable part: - [VAR=VALUE] ... ./configure + [VAR=VALUE] ... ./configure [--static] make where [VAR=VALUE] ... allows you to specify any options. @@ -25,6 +25,10 @@ Most useful is CROSS_PREFIX= which specifies the cross compiler prefix; you'll need this if you're not building on the target system (Example: CROSS_PREFIX=arm-linux-gnueabihf- ) + +Passing --static will build a statically linked binary which is useful +if you don't want to mess around with chroot's to run the binary. + For other possibilities run 'configure --help'. Building into a separate build tree from the source code is supported: @@ -86,8 +90,14 @@ as simple as: However since you actually need to run it under qemu or similar you probably need an ARM chroot to run it in, and to do something -like - sudo chroot /srv/chroot/arm-mav /risu --host ipaddr vqshlimm.out +like: + + sudo chroot /srv/chroot/arm-mav /risu --host ipaddr vqshlimm.out + +If you built the binary statically you can simply run: + + /path/to/qemu ./risu --host ipaddr vqshlimm.out + When the apprentice connects to the master, they will both start running the binary and checking results with each other. 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X-Received-From: 2a00:1450:400c:c0c::22c Subject: [Qemu-devel] [RISU PATCH 04/11] README: document record/replay support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- README | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) -- 2.13.0 diff --git a/README b/README index e0bf5c5..5f16f60 100644 --- a/README +++ b/README @@ -107,6 +107,26 @@ mismatch status to its standard output. NB that in the register dump the r15 (pc) value will be given as an offset from the start of the binary, not an absolute value. +While the master/slave setup works well it is a bit fiddly for running +regression tests and other sorts of automation. For this reason risu +supports recording a trace of its execution to a file. For example: + + risu --master FxxV_across_lanes.risu.bin -t FxxV_across_lanes.risu.trace + +And then playback with: + + risu FxxV_across_lanes.risu.bin -t FxxV_across_lanes.risu.trace + +Ideally it should be built with zlib to compress the trace files which +would otherwise be huge. If building with zlib proves too tricky you +can pipe to stdout and an external compression binary using "-t -". + + risu --master FxxV_across_lanes.risu.bin -t - | gzip --best > trace.file + +and: + + gunzip -c trace.file | risu -t - FxxV_across_lanes.risu.bin + File format ----------- @@ -203,10 +223,6 @@ implementation, for example) but only ARM is tested. * we don't actually compare FP status flags, simply because I'm pretty sure qemu doesn't get them right yet and I'm more interested in fixing gross bugs first. - * there isn't currently any support for a "record and replay -results" mode. This would allow you to record the correct -results from the ARM host once and then test a model implementation -even if you didn't have the corresponding native hardware. * You can compile statically to avoid the requirement for the ARM chroot for qemu testing but you can no longer use gethostbyname() and need to specify your hosts by IP address. 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X-Received-From: 2a00:1450:400c:c0c::22b Subject: [Qemu-devel] [RISU PATCH 05/11] risu.el: derive from text-mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As RISU files have copious commentary it seems better to derive from text-mode so we can access things like spell-checker short cuts ;-) Signed-off-by: Alex Bennée --- risu.el | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.13.0 diff --git a/risu.el b/risu.el index dff9337..1875d02 100644 --- a/risu.el +++ b/risu.el @@ -39,7 +39,7 @@ ;;; Code -(define-derived-mode risu-mode fundamental-mode "RISU" +(define-derived-mode risu-mode text-mode "RISU" "Major mode for editing RISU control files." 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X-Received-From: 2a00:1450:400c:c09::236 Subject: [Qemu-devel] [RISU PATCH 06/11] risugen: fix bad indent X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- risugen | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.13.0 diff --git a/risugen b/risugen index 8b20425..347cf12 100755 --- a/risugen +++ b/risugen @@ -262,7 +262,7 @@ Valid options: These REs are applied after the matching pattern which is useful if you want to exclude a specific instruction from a general set you have excluded. - --no-fp : disable floating point: no fp init, randomization etc. + --no-fp : disable floating point: no fp init, randomization etc. Useful to test before support for FP is available. --be : generate instructions in Big-Endian byte order (ppc64 only). --help : print this message From patchwork Tue Jul 4 14:48:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 106987 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp1093716qge; Tue, 4 Jul 2017 07:54:05 -0700 (PDT) X-Received: by 10.237.33.69 with SMTP id 63mr22806533qtc.11.1499180045126; Tue, 04 Jul 2017 07:54:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1499180045; cv=none; d=google.com; s=arc-20160816; b=fBbbtbNIHJWvt/K7ZiiHnvahgcFwDBYXBne2Rqab2fJ9H9/NflHHo1JjDIrSWoicTM /WC1wrSb4Q7EmNafjMA0kBilmlil3F8oUYkuN/XxjsNE5sIFSmX02vtpT1MwrG/Dqg3/ MMN2PldEmJUm54oI+yeSJjbfwknSLSEqdxPxP3LdkDJOgP7V2amZF4w1s2pYQWiVe8Qi gQfnj+IsHytxfu7JVUDBADojmoSWB3UXhIq22on1vSXIDPiGSo+QeN8SYzB+Gm7AhLQn 1I7/7xLkz3D3kmORDwtX1RJRXwtPgQP+572QT9ql2qUO984NEb8oCCRO1rkbXDG3JMpN oqcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=6edPI3sV3IojOpL+0ihRIIsv1ygwoR/EzfaS2rzc4zw=; b=I1M6qTUf1UarDOsb5YYEKZ+MWP0HpITk7nYXrDflFSLsEHaMCpLMdyOwh3YxgiwEu8 QdfQkxLuu05s3ZWD4XhDoO+jfiGSFGR05fc5N4YUI2wfm/Yusix5dl2T4R8kOGAg/+To MLvWB+b7euh15glor3Num1YpLGYhmUFI4+KpkXHECOQe3wp1CngWXLeIPSPzChKV9Adc V8616D5yN6sPDrZ1cMSQvm/R0QeKTx7z6WyI/Iy906XF+cKLjtDFaUwwQXjO4elnvEp3 arr9cQBjICWyRh0FWkZMCkX9QyK/zF0FonpUX+TXK5dVf+fFzPw8C/ONybHSAw2krDil u8ZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.b=Uvwzb/wO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::22c Subject: [Qemu-devel] [RISU PATCH 07/11] risugen: support @GroupName in risu files X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The existing pattern support is useful but it does get a little tedious when faced with large groups of instructions. This introduces the concept of a @GroupName which can be sprinkled in the risu definition and is attached to all instructions following its definition until the next group or an empty group "@" is specified. It can be combined with the existing pattern support to do things like: ./risugen --group AdvSIMDAcrossVector --not-pattern ".*_RES" aarch64.risu foo.bin Signed-off-by: Alex Bennée --- risugen | 15 +++++++++++++++ risugen_arm.pm | 7 +++++++ 2 files changed, 22 insertions(+) -- 2.13.0 diff --git a/risugen b/risugen index 347cf12..97ffa83 100755 --- a/risugen +++ b/risugen @@ -30,7 +30,10 @@ my %insn_details; # The arch will be selected based on .mode directive defined in risu file. my $arch = ""; +# Current group, updated by @GroupName +my $insn_group = ""; +my @group = (); # include groups my @pattern_re = (); # include pattern my @not_pattern_re = (); # exclude pattern @@ -118,6 +121,11 @@ sub parse_config_file($) exit(1); } + if ($tokens[0] =~ /^@(.*)/ ) { + $insn_group = $1; + next; + } + if ($tokens[0] =~ /^\./) { parse_risu_directive($file, $seen_pattern, @tokens); next; @@ -235,6 +243,9 @@ sub parse_config_file($) $insnrec->{fixedbits} = $fixedbits; $insnrec->{fixedbitmask} = $fixedbitmask; $insnrec->{fields} = [ @fields ]; + if (length $insn_group) { + $insnrec->{group} = $insn_group; + } $insn_details{$insnname} = $insnrec; } close(CFILE) or die "can't close $file: $!"; @@ -253,6 +264,7 @@ Valid options: --fpscr n : set initial FPSCR (arm) or FPCR (aarch64) value (default is 0) --condprob p : [ARM only] make instructions conditional with probability p (default is 0, ie all instructions are always executed) + --group name[,name..]: only use instructions in defined groups --pattern re[,re...] : only use instructions matching regular expression Each re must match a full word (that is, we match on the perl regex '\\b((re)|(re))\\b'). This means that @@ -281,6 +293,7 @@ sub main() GetOptions( "help" => sub { usage(); exit(0); }, "numinsns=i" => \$numinsns, "fpscr=o" => \$fpscr, + "group=s" => \@group, "pattern=s" => \@pattern_re, "not-pattern=s" => \@not_pattern_re, "condprob=f" => sub { @@ -295,6 +308,7 @@ sub main() # allow "--pattern re,re" and "--pattern re --pattern re" @pattern_re = split(/,/,join(',',@pattern_re)); @not_pattern_re = split(/,/,join(',',@not_pattern_re)); + @group = split(/,/,join(',',@group)); if ($#ARGV != 1) { usage(); @@ -316,6 +330,7 @@ sub main() 'numinsns' => $numinsns, 'fp_enabled' => $fp_enabled, 'outfile' => $outfile, + 'group' => \@group, 'pattern_re' => \@pattern_re, 'not_pattern_re' => \@not_pattern_re, 'details' => \%insn_details, diff --git a/risugen_arm.pm b/risugen_arm.pm index 1024660..8ad208a 100644 --- a/risugen_arm.pm +++ b/risugen_arm.pm @@ -895,6 +895,7 @@ sub write_test_code($$$$$$$$) my $fp_enabled = $params->{ 'fp_enabled' }; my $outfile = $params->{ 'outfile' }; + my @group = @{ $params->{ 'group' } }; my @pattern_re = @{ $params->{ 'pattern_re' } }; my @not_pattern_re = @{ $params->{ 'not_pattern_re' } }; my %insn_details = %{ $params->{ 'details' } }; @@ -910,6 +911,12 @@ sub write_test_code($$$$$$$$) # Get a list of the insn keys which are permitted by the re patterns my @keys = sort keys %insn_details; + if (@group) { + my $re = join("|",@group); + @keys = grep { + defined($insn_details{$_}->{group}) && + grep /$re/, $insn_details{$_}->{group}} @keys + } if (@pattern_re) { my $re = '\b((' . join(')|(',@pattern_re) . '))\b'; @keys = grep /$re/, @keys; From patchwork Tue Jul 4 14:48:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 106989 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp1095887qge; Tue, 4 Jul 2017 07:56:26 -0700 (PDT) X-Received: by 10.55.75.204 with SMTP id y195mr49683095qka.183.1499180186649; Tue, 04 Jul 2017 07:56:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1499180186; cv=none; d=google.com; s=arc-20160816; b=UX4ElXAezT/tOJpQXWEtVdoT3P7RHqZRHxOl4Tukoj3uWC19CihX9mCRZUDBmEj2Se I1Q3IoRUkI2kyBsRAPBQ2bu9zvhGzckbIT+/BYbUBWhJ5T7kfLfrOGgG7XlzgdFE10xY RvPadhmFOrTc967qWkp5yfXGvCKlK97C2DRFN+7+pJtTt4l78Hug7yOYHiqVp/KPZEsh PDxtWoM6J8I4uK0FiJd/6eVFy/krtkoXCXxzoCd1bPq7ccqeStoJ212Fh5b/1L4H0Iwu bVW+HqdCSNl+u/y8LHKxttDhF1cBh9X8h7rfM8Fc1m72pmzK5/IBTjsyVgxx3N+VDrL6 J6nQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=KQqE8ziyU+KLpr0wuWEOdSSUtfqGjLdjxYDtaGm4tsk=; b=Rb9rq5MQ7iAg2Rj7iWFa7eGoIaSeMfq+BJRX/XpyQXfGLYnGZVLHViSFxfnEkBNWyD 2nZAPn5nPyvncSYtMd5RjOrhFn4zUbl6ExjcRCZ9R3yMRo0Du0fhH5ZL8U2ice9l91Fc wp+m0GjJ1L30htnaiT7RxuP2Xc17c1gRSiHs1utej4y5ZTG4oG6wATu050EtepLN9lGF mrm/YqxG9sxeHJ9xePJcUJT4JsJlLcDUxr18gCZPdAEihBxVnRu7Ukq7a/uHbLzDbbB9 JgMhvlho4jzAM/LBS+ULJyXWeACR2THrCI8ahQUFMl6XLCPHORZywUPEDrPhfa+98m21 cbMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.b=bWqBn6JH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::230 Subject: [Qemu-devel] [RISU PATCH 08/11] aarch64.risu: document naming conventions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- aarch64.risu | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.13.0 diff --git a/aarch64.risu b/aarch64.risu index 2f3341c..bfca45f 100644 --- a/aarch64.risu +++ b/aarch64.risu @@ -7,6 +7,7 @@ # # Contributors: # Claudio Fontana - initial implementation +# Alex Bennée - a number of additions including v8.2 FP16 # based on arm.risu by Peter Maydell ############################################################################### @@ -19,6 +20,15 @@ # XXX NIY: SP-related instructions # XXX NIY: floating point and SIMD specific insns +# Instruction suffixes to identify variants +# m - memory (loads/stores) +# s - scalar +# v - vector +# z - zero (e.g. compare to zero) +# f - fixed point +# +# _FP16 for ARMv8.2 half-precision extensions + # - - - - 1 - 0 - - - - - - - - - - - - - - - Loads and stores # C3.3 Loads and stores From patchwork Tue Jul 4 14:48:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 106988 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp1095309qge; Tue, 4 Jul 2017 07:55:47 -0700 (PDT) X-Received: by 10.55.188.69 with SMTP id m66mr45212671qkf.63.1499180147395; Tue, 04 Jul 2017 07:55:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1499180147; cv=none; d=google.com; s=arc-20160816; b=xcXCsBEe1mqQuGUG++Mhpsz15Kl6x/tMjP7LaQuqeNWNOL7okPDQUhbLw2xiV/pjFM K/tW2c5K5K4cj0lSFIqyCB14gB8jeAHkoVXVCFKc/IdduL1Rf29OWIP9D0p1bwLrz2Dk j2N8kQ6qDlFGHIDmAGxpVSVbomGIrbw2/doB4rlrVfLRiZ9l8GddqpDuJgWCKguKNi/K vTACeCvmSwacGQYFMj37wASo6fB4FXqJIS6yCSCBJ5sX2LSdheMQHvxUP6/McU0W/EIq H+Lb3yUbyr5lQ0Sl2OFIRUg4DPNtEXvSvNY1mnjC7INNevXm1MhXBWQ8O1eVdqX1fOfK 5qhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=K7H+/PVsQu2fTl0M8UyBL23eYX1332tcbGalx5FkTkw=; b=H2CPi9Zj6fJmqSB2rMpAJ/9iovy07LD1uywx6jM/919ORyBY87BreHfcfECl13TX2c KTf13+EQJdeswyLHrM1+JawRgXQ5CqmpMUTpfk9yYP/uVZgA82I1odmo11XBjTbkGzrx qzZ5KRmxfNbtojbyhJjA11XJjMdo86VXl1w8MBGjfzeejgRel3dwjAg7I3UY+7NEj+05 awvsFOllvsBTI8ThkkJL3ZUKacDvPiubjl47GIck5qiI9VVfmP5Vl7nPvOQeBCgSwI9g azIWJtffKxT1PGB9cnxQ2W/TZDzmfOyyW3tdgRIFWenfUwPmTJ6BV782yTnEA6XHUS0c zEUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.b=WIjDkDgA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::234 Subject: [Qemu-devel] [RISU PATCH 09/11] aarch64.risu: remove duplicate AdvSIMD Scalar 3 same block X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A chunk of the AArch64 definitions repeat themselves. Clean that up. Signed-off-by: Alex Bennée --- aarch64.risu | 25 +++---------------------- 1 file changed, 3 insertions(+), 22 deletions(-) -- 2.13.0 diff --git a/aarch64.risu b/aarch64.risu index bfca45f..609021a 100644 --- a/aarch64.risu +++ b/aarch64.risu @@ -2130,6 +2130,8 @@ SQDMULL_S3D A64_V 0 1 U 11110 size:2 1 rm:5 1101 00 rn:5 rd:5 # 31 30 29 28 27 26 25 24 23 22 21 20 16 15 11 10 9 5 4 0 # 0 1 U 1 1 1 1 0 size 1 [ Rm ] [ opcode ] 1 [ Rn ] [ Rd ] # +@AdvSIMDScalar3Same + SQADD A64_V 01 0 11110 size:2 1 rm:5 00001 1 rn:5 rd:5 SQSUB A64_V 01 0 11110 size:2 1 rm:5 00101 1 rn:5 rd:5 CMGT A64_V 01 0 11110 size:2 1 rm:5 00110 1 rn:5 rd:5 @@ -2167,28 +2169,7 @@ FCMGT A64_V 01 1 11110 1 size:1 1 rm:5 11100 1 rn:5 rd:5 FACGT A64_V 01 1 11110 1 size:1 1 rm:5 11101 1 rn:5 rd:5 \ !constraints { $size != 11; } -CMTST A64_v 01 0 11110 size:2 1 rm:5 10001 1 rn:5 rd:5 -SQDMULH A64_v 01 0 11110 size:2 1 rm:5 10110 1 rn:5 rd:5 -FMULX A64_v 01 0 11110 0 size:1 1 rm:5 11011 1 rn:5 rd:5 -FCMEQ A64_v 01 0 11110 0 size:1 1 rm:5 11100 1 rn:5 rd:5 -FRECPS A64_v 01 0 11110 0 size:1 1 rm:5 11111 1 rn:5 rd:5 -FRSQRTS A64_v 01 0 11110 1 size:1 1 rm:5 11111 1 rn:5 rd:5 -UQADD A64_v 01 1 11110 size:2 1 rm:5 00001 1 rn:5 rd:5 -UQSUB A64_v 01 1 11110 size:2 1 rm:5 00101 1 rn:5 rd:5 -CMHI A64_v 01 1 11110 size:2 1 rm:5 00110 1 rn:5 rd:5 -CMHS A64_v 01 1 11110 size:2 1 rm:5 00111 1 rn:5 rd:5 -USHL A64_v 01 1 11110 size:2 1 rm:5 01000 1 rn:5 rd:5 -UQSHL A64_v 01 1 11110 size:2 1 rm:5 01001 1 rn:5 rd:5 -URSHL A64_v 01 1 11110 size:2 1 rm:5 01010 1 rn:5 rd:5 -UQRSHL A64_v 01 1 11110 size:2 1 rm:5 01011 1 rn:5 rd:5 -SUBv A64_v 01 1 11110 size:2 1 rm:5 10000 1 rn:5 rd:5 -CMEQ A64_v 01 1 11110 size:2 1 rm:5 10001 1 rn:5 rd:5 -SQRDMULH A64_v 01 1 11110 size:2 1 rm:5 10110 1 rn:5 rd:5 -FCMGE A64_v 01 1 11110 0 size:1 1 rm:5 11100 1 rn:5 rd:5 -FACGE A64_v 01 1 11110 0 size:1 1 rm:5 11101 1 rn:5 rd:5 -FABD A64_v 01 1 11110 1 size:1 1 rm:5 11010 1 rn:5 rd:5 -FCMGT A64_v 01 1 11110 1 size:1 1 rm:5 11100 1 rn:5 rd:5 -FACGT A64_v 01 1 11110 1 size:1 1 rm:5 11101 1 rn:5 rd:5 +@ # C3.6.12 AdvSIMD scalar 2reg misc CMGTzero A64_V 01 0 11110 size:2 10000 01000 10 rn:5 rd:5 From patchwork Tue Jul 4 14:48:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 106990 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp1097503qge; Tue, 4 Jul 2017 07:58:11 -0700 (PDT) X-Received: by 10.55.54.196 with SMTP id d187mr50855611qka.96.1499180291212; Tue, 04 Jul 2017 07:58:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1499180291; cv=none; d=google.com; s=arc-20160816; b=sHd7ywvIpu4AC9yPzKY3qHcdvoswZWPRtApK9MjvapgtnG2rZ/DdoxeIgrdhu+wLp1 JFhi8Hcsp4I9TmPjCWBDmwNjlfnOyzUKimusIXDKi+VkjjKEFZMD006mfFMTxX3ggWwM ZcH5bZB5u9WlbhbS/PSHGrzMKeHdaGjlKctksotwKOoX3OaYuKT1OLWamDB9N2Ksfp+N j9OCPdXx/orpxQWbYz1UeVHQHgTCkEusiOrG6+iEFUNvpmIU5QgfG7i39wvgqlUWi6U/ kzdACy+/rbnQJGvVTUOPkpU2yTqRTduy9F9+FyroZG0YcI2OxE+kN/j0n5dbqrZPB8KX JnbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=HedIcq5dXQSyerl1kIPqUhsGec0lF93YS4nOILHPMZ0=; b=QZCvMzHmWOxWqkWDQZm7uq3kxV5HWeVCmhtocX0hb7L52uPnRTY0YPWgLVNxFF3sVf YUKlk5xMY14/FdywNR6z34dLhta5OaD2n0kp2qhZqwOMWwSLEnGdL/FvgTBT1zaAxQDh bU4Levb0uipAZArTARf9mu6XAsMtLLgtVQnvZ5dysj6s2FoL37GJshzRN3Ufm7EnwrVC QmEi42GfOobhkfMMAg5MFE5mpr8v4FNAFUil/u9agRl8aOea4OVZamcp4UNju5KbmLZe m3uonf1scXyw5jsKwIaMNdWlODrNrnaMOmLzPTT3N2r7x9/pSJfUhFGqQiV+nTxZ9jDR diKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.b=WSHTlku8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id g2si18131226qtg.323.2017.07.04.07.58.10 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 04 Jul 2017 07:58:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.b=WSHTlku8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41815 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSPHE-0000RR-Mi for patch@linaro.org; Tue, 04 Jul 2017 10:58:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35892) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSP7r-0008Jx-L4 for qemu-devel@nongnu.org; Tue, 04 Jul 2017 10:48:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSP7n-0001Dh-VD for qemu-devel@nongnu.org; Tue, 04 Jul 2017 10:48:27 -0400 Received: from mail-wm0-x22d.google.com ([2a00:1450:400c:c09::22d]:38799) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dSP7n-0001Ct-Mp for qemu-devel@nongnu.org; Tue, 04 Jul 2017 10:48:23 -0400 Received: by mail-wm0-x22d.google.com with SMTP id f67so87108920wmh.1 for ; Tue, 04 Jul 2017 07:48:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HedIcq5dXQSyerl1kIPqUhsGec0lF93YS4nOILHPMZ0=; b=WSHTlku84oUAYI+OBNOPxFQA0H1+nNTLfvr51UQCUzmSTta6eyqVT35MbAmLsaEyLd FDVkR8gJaHa00BeC4zNLM1CRBPqkGpjMnlQdudIGaHEagEz/GvqmN7QAoFLRxdKKXWa5 PsXRiuSArwMybQ/hmP/dg8c0OHAKJsERbZC4Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HedIcq5dXQSyerl1kIPqUhsGec0lF93YS4nOILHPMZ0=; b=J94ee47EbsuS7UJH7XdrfSwtaPNLYPFTcXcCf7+Qrerb3vIl1L4j2vvJyohTEccARz BT1FwKFJnpCWCN0iu8CbfrkxnMwCeDUoqHAiJBj8HzgFxT0qBBrh3xRqtg+Yk9VJ/qIF sR27/JUaoy0bGIe6uXMq+n468qdIU640D2p4Ab5qDF5ZCKSNHzaLkIBriQACHmMpW2t0 Hc6ajYT7hfumfhDvKi0ocaOQ/h9pIWRMGvMWK1fN6NPGIEPkyM4jvVDlpEBACxD0b8gW pS7U6NAh1X8vzD2Sh1lvCe18isjwOMH/47fo/SOMZdGwAqU2HIZ2WIm86e/yS/VI2tzJ /FMg== X-Gm-Message-State: AKS2vOwvEkdSYWrBfgTbQmqcVDbzhZLS8ZatGkmil56JZmjj8toZHXYe AdVMgLmeCRQuOJmY X-Received: by 10.28.153.81 with SMTP id b78mr17573829wme.85.1499179702265; Tue, 04 Jul 2017 07:48:22 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id y192sm18342573wmy.6.2017.07.04.07.48.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jul 2017 07:48:15 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 362883E21FF; Tue, 4 Jul 2017 15:49:11 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Tue, 4 Jul 2017 15:48:58 +0100 Message-Id: <20170704144859.17644-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170704144859.17644-1-alex.bennee@linaro.org> References: <20170704144859.17644-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22d Subject: [Qemu-devel] [RISU PATCH 10/11] aarch64.risu: remove duplicate AdvSIMD scalar 2 reg misc block X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While at that also: - sort alphabetically - add to @AdvSIMDScalar2RegMisc group Signed-off-by: Alex Bennée --- aarch64.risu | 114 ++++++++++++++++++++--------------------------------------- 1 file changed, 39 insertions(+), 75 deletions(-) -- 2.13.0 diff --git a/aarch64.risu b/aarch64.risu index 609021a..5450cd3 100644 --- a/aarch64.risu +++ b/aarch64.risu @@ -2171,85 +2171,49 @@ FACGT A64_V 01 1 11110 1 size:1 1 rm:5 11101 1 rn:5 rd:5 \ @ -# C3.6.12 AdvSIMD scalar 2reg misc -CMGTzero A64_V 01 0 11110 size:2 10000 01000 10 rn:5 rd:5 -CMGEzero A64_V 01 1 11110 size:2 10000 01000 10 rn:5 rd:5 -CMEQzero A64_V 01 0 11110 size:2 10000 01001 10 rn:5 rd:5 -CMLEzero A64_V 01 1 11110 size:2 10000 01001 10 rn:5 rd:5 -CMLTzero A64_V 01 0 11110 size:2 10000 01010 10 rn:5 rd:5 -ABS A64_V 01 0 11110 size:2 10000 01011 10 rn:5 rd:5 -NEG A64_V 01 1 11110 size:2 10000 01011 10 rn:5 rd:5 - -FCMGT_S2MISC A64_V 01 0 11110 size:2 10000 01100 10 rn:5 rd:5 -FCMEQ_S2MISC A64_V 01 0 11110 size:2 10000 01101 10 rn:5 rd:5 -FCMLT_S2MISC A64_V 01 0 11110 size:2 10000 01110 10 rn:5 rd:5 -FCMGE_S2MISC A64_V 01 1 11110 size:2 10000 01100 10 rn:5 rd:5 -FCMLE_S2MISC A64_V 01 1 11110 size:2 10000 01101 10 rn:5 rd:5 - -SCVTF_S2MISC A64_V 01 0 11110 0 sz 10000 11101 10 rn:5 rd:5 -UCVTF_S2MISC A64_V 01 1 11110 0 sz 10000 11101 10 rn:5 rd:5 - -FCVTNS_S2MISC A64_V 01 0 11110 0 sz 10000 11010 10 rn:5 rd:5 -FCVTMS_S2MISC A64_V 01 0 11110 0 sz 10000 11011 10 rn:5 rd:5 -FCVTAS_S2MISC A64_V 01 0 11110 0 sz 10000 11100 10 rn:5 rd:5 -FCVTPS_S2MISC A64_V 01 0 11110 1 sz 10000 11010 10 rn:5 rd:5 -FCVTZS_S2MISC A64_V 01 0 11110 1 sz 10000 11011 10 rn:5 rd:5 - -FCVTNU_S2MISC A64_V 01 1 11110 0 sz 10000 11010 10 rn:5 rd:5 -FCVTMU_S2MISC A64_V 01 1 11110 0 sz 10000 11011 10 rn:5 rd:5 -FCVTAU_S2MISC A64_V 01 1 11110 0 sz 10000 11100 10 rn:5 rd:5 -FCVTPU_S2MISC A64_V 01 1 11110 1 sz 10000 11010 10 rn:5 rd:5 -FCVTZU_S2MISC A64_V 01 1 11110 1 sz 10000 11011 10 rn:5 rd:5 - -FCVTXN_S2MISC A64_V 01 1 11110 0 sz 10000 10110 10 rn:5 rd:5 - -SUQADD_S2MISC A64_V 01 0 11110 size:2 10000 00011 10 rn:5 rd:5 -USQADD_S2MISC A64_V 01 1 11110 size:2 10000 00011 10 rn:5 rd:5 -SQABS_S2MISC A64_V 01 0 11110 size:2 10000 00111 10 rn:5 rd:5 -SQNEG_S2MISC A64_V 01 1 11110 size:2 10000 00111 10 rn:5 rd:5 - -# XXX lots of others in this group - # C3.6.12 AdvSIMD scalar two-reg misc # 31 30 29 28 27 26 25 24 23 22 21 20 16 12 11 10 9 5 4 0 # 0 1 U 1 1 1 1 0 size 1 0 0 0 0 [ opcode ] 1 0 [ Rn ] [ Rd ] # U size opcode -SUQADDs A64_V 01 0 11110 size:2 10000 00011 10 rn:5 rd:5 -SQABSs A64_V 01 0 11110 size:2 10000 00111 10 rn:5 rd:5 -CMGTzs A64_V 01 0 11110 size:2 10000 01000 10 rn:5 rd:5 -CMEQzs A64_V 01 0 11110 size:2 10000 01001 10 rn:5 rd:5 -CMLTzs A64_V 01 0 11110 size:2 10000 01010 10 rn:5 rd:5 -ABSs A64_V 01 0 11110 size:2 10000 01011 10 rn:5 rd:5 -SQXTN_SQXTN2s A64_V 01 0 11110 size:2 10000 10100 10 rn:5 rd:5 -FCVTNSvs A64_V 01 0 11110 0 size:1 10000 11010 10 rn:5 rd:5 -FCVTMSvs A64_V 01 0 11110 0 size:1 10000 11011 10 rn:5 rd:5 -FCVTASvs A64_V 01 0 11110 0 size:1 10000 11100 10 rn:5 rd:5 -SCVTFvis A64_V 01 0 11110 0 size:1 10000 11101 10 rn:5 rd:5 -FCMGTzs A64_V 01 0 11110 1 size:1 10000 01100 10 rn:5 rd:5 -FCMEQzs A64_V 01 0 11110 1 size:1 10000 01101 10 rn:5 rd:5 -FCMLTzs A64_V 01 0 11110 1 size:1 10000 01110 10 rn:5 rd:5 -FCVTPSvs A64_V 01 0 11110 1 size:1 10000 11010 10 rn:5 rd:5 -FCVTZSvis A64_V 01 0 11110 1 size:1 10000 11011 10 rn:5 rd:5 -FRECPEs A64_V 01 0 11110 1 size:1 10000 11101 10 rn:5 rd:5 -FRECPX A64_V 01 0 11110 1 size:1 10000 11111 10 rn:5 rd:5 -USQADDs A64_V 01 1 11110 size:2 10000 00011 10 rn:5 rd:5 -SQNEGs A64_V 01 1 11110 size:2 10000 00111 10 rn:5 rd:5 -CMGzs A64_V 01 1 11110 size:2 10000 01000 10 rn:5 rd:5 -CMLEzs A64_V 01 1 11110 size:2 10000 01001 10 rn:5 rd:5 -NEGvs A64_V 01 1 11110 size:2 10000 01011 10 rn:5 rd:5 -SQXTUN_SQXTUN2s A64_V 01 1 11110 size:2 10000 10010 10 rn:5 rd:5 -UQXTN_UQXTN2s A64_V 01 1 11110 size:2 10000 10100 10 rn:5 rd:5 -FCVTXN_FCVTXN2s A64_V 01 1 11110 0 size:1 10000 10110 10 rn:5 rd:5 -FCVTNUvs A64_V 01 1 11110 0 size:1 10000 11010 10 rn:5 rd:5 -FCVTMUvs A64_V 01 1 11110 0 size:1 10000 11011 10 rn:5 rd:5 -FCVTAUvs A64_V 01 1 11110 0 size:1 10000 11100 10 rn:5 rd:5 -UCVTFvis A64_V 01 1 11110 0 size:1 10000 11101 10 rn:5 rd:5 -FCMGEzs A64_V 01 1 11110 1 size:1 10000 01100 10 rn:5 rd:5 -FCMLEzs A64_V 01 1 11110 1 size:1 10000 01101 10 rn:5 rd:5 -FCVTPUvs A64_V 01 1 11110 1 size:1 10000 11010 10 rn:5 rd:5 -FCVTZUvis A64_V 01 1 11110 1 size:1 10000 11011 10 rn:5 rd:5 -FRSQRTEs A64_V 01 1 11110 1 size:1 10000 11101 10 rn:5 rd:5 - +@AdvSIMDScalar2RegMisc + +ABSs A64_V 01 0 11110 size:2 10000 01011 10 rn:5 rd:5 +CMEQzs A64_V 01 0 11110 size:2 10000 01001 10 rn:5 rd:5 +CMGTzs A64_V 01 0 11110 size:2 10000 01000 10 rn:5 rd:5 +CMGzs A64_V 01 1 11110 size:2 10000 01000 10 rn:5 rd:5 +CMLEzs A64_V 01 1 11110 size:2 10000 01001 10 rn:5 rd:5 +CMLTzs A64_V 01 0 11110 size:2 10000 01010 10 rn:5 rd:5 +FCMEQzs A64_V 01 0 11110 1 size:1 10000 01101 10 rn:5 rd:5 +FCMGEzs A64_V 01 1 11110 1 size:1 10000 01100 10 rn:5 rd:5 +FCMGTzs A64_V 01 0 11110 1 size:1 10000 01100 10 rn:5 rd:5 +FCMLEzs A64_V 01 1 11110 1 size:1 10000 01101 10 rn:5 rd:5 +FCMLTzs A64_V 01 0 11110 1 size:1 10000 01110 10 rn:5 rd:5 +FCVTASvs A64_V 01 0 11110 0 size:1 10000 11100 10 rn:5 rd:5 +FCVTAUvs A64_V 01 1 11110 0 size:1 10000 11100 10 rn:5 rd:5 +FCVTMSvs A64_V 01 0 11110 0 size:1 10000 11011 10 rn:5 rd:5 +FCVTMUvs A64_V 01 1 11110 0 size:1 10000 11011 10 rn:5 rd:5 +FCVTNSvs A64_V 01 0 11110 0 size:1 10000 11010 10 rn:5 rd:5 +FCVTNUvs A64_V 01 1 11110 0 size:1 10000 11010 10 rn:5 rd:5 +FCVTPSvs A64_V 01 0 11110 1 size:1 10000 11010 10 rn:5 rd:5 +FCVTPUvs A64_V 01 1 11110 1 size:1 10000 11010 10 rn:5 rd:5 +FCVTXN_FCVTXN2s A64_V 01 1 11110 0 size:1 10000 10110 10 rn:5 rd:5 +FCVTZSvis A64_V 01 0 11110 1 size:1 10000 11011 10 rn:5 rd:5 +FCVTZUvis A64_V 01 1 11110 1 size:1 10000 11011 10 rn:5 rd:5 +FRECPEs A64_V 01 0 11110 1 size:1 10000 11101 10 rn:5 rd:5 +FRECPX A64_V 01 0 11110 1 size:1 10000 11111 10 rn:5 rd:5 +FRSQRTEs A64_V 01 1 11110 1 size:1 10000 11101 10 rn:5 rd:5 +NEGvs A64_V 01 1 11110 size:2 10000 01011 10 rn:5 rd:5 +SCVTFvis A64_V 01 0 11110 0 size:1 10000 11101 10 rn:5 rd:5 +SQABSs A64_V 01 0 11110 size:2 10000 00111 10 rn:5 rd:5 +SQNEGs A64_V 01 1 11110 size:2 10000 00111 10 rn:5 rd:5 +SQXTN_SQXTN2s A64_V 01 0 11110 size:2 10000 10100 10 rn:5 rd:5 +SQXTUN_SQXTUN2s A64_V 01 1 11110 size:2 10000 10010 10 rn:5 rd:5 +SUQADDs A64_V 01 0 11110 size:2 10000 00011 10 rn:5 rd:5 +UCVTFvis A64_V 01 1 11110 0 size:1 10000 11101 10 rn:5 rd:5 +UQXTN_UQXTN2s A64_V 01 1 11110 size:2 10000 10100 10 rn:5 rd:5 +USQADDs A64_V 01 1 11110 size:2 10000 00011 10 rn:5 rd:5 + +@ # C3.6.13 AdvSIMD scalar x indexed element # Complete coverage. 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X-Received-From: 2a00:1450:400c:c0c::22e Subject: [Qemu-devel] [RISU PATCH 11/11] aarch64.risu: update AdvancedSIMD across lanes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" - sorted alphabetically - aligned the instructions patterns - adding half-precision F[MAX|MIN][NMV|V] - add @AdvSIMDAcrossVector group Signed-off-by: Alex Bennée --- aarch64.risu | 90 +++++++++++++++++++++++++++++++++--------------------------- 1 file changed, 49 insertions(+), 41 deletions(-) -- 2.13.0 diff --git a/aarch64.risu b/aarch64.risu index 5450cd3..215882e 100644 --- a/aarch64.risu +++ b/aarch64.risu @@ -1955,50 +1955,58 @@ ZIP2 A64_V 0 Q:1 001110 size:2 0 rm:5 0 111 10 rn:5 rd:5 \ # ReservedValue: break the !($size == 3 && $Q == 0) constraint ZIP2_RES A64_V 0 0 001110 11 0 rm:5 0 111 10 rn:5 rd:5 -# C3.6.4 AdvSIMD across lanes +# C4-286 AdvSIMD across vector lanes # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 12 11 10 9 5 4 0 # 0 Q U 0 1 1 1 0 size 1 1 0 0 0 opcode 1 0 Rn Rd +@AdvSIMDAcrossVector + +ADDV A64_V 0 Q:1 0 01110 s:2 11000 11011 10 rn:5 rd:5 \ +!constraints { $s < 2 || ($s == 2 && $Q == 1); } +# ReservedValue: break the constraint (s==2) => (Q=1) +ADDV_RES A64_V 0 0 0 01110 10 11000 11011 10 rn:5 rd:5 + +FMAXNMV A64_V 0 1 1 01110 00 11000 01100 10 rn:5 rd:5 +FMAXV A64_V 0 1 1 01110 00 11000 01111 10 rn:5 rd:5 +FMINNMV A64_V 0 1 1 01110 10 11000 01100 10 rn:5 rd:5 +FMINV A64_V 0 1 1 01110 10 11000 01111 10 rn:5 rd:5 + +# ARMv8.2 Half-precision variants +FMAXNMV_FP16 A64_V 0 q:1 0 01110 00 11000 01100 10 rn:5 rd:5 +FMAXV_FP16 A64_V 0 q:1 0 01110 00 11000 01111 10 rn:5 rd:5 +FMINNMV_FP16 A64_V 0 q:1 0 01110 10 11000 01100 10 rn:5 rd:5 +FMINV_FP16 A64_V 0 q:1 0 01110 10 11000 01111 10 rn:5 rd:5 + +SADDLV A64_V 0 Q:1 0 01110 s:2 11000 00011 10 rn:5 rd:5 \ +!constraints { $s < 2 || ($s == 2 && $Q == 1); } +# ReservedValue: break the constraint (s==2) => (Q=1) +SADDLV_RES A64_V 0 0 0 01110 10 11000 00011 10 rn:5 rd:5 + +SMAXV A64_V 0 Q:1 0 01110 s:2 11000 01010 10 rn:5 rd:5 \ +!constraints { $s < 2 || ($s == 2 && $Q == 1); } +# ReservedValue: break the constraint (s==2) => (Q=1) +SMAXV_RES A64_V 0 0 0 01110 10 11000 01010 10 rn:5 rd:5 + +SMINV A64_V 0 Q:1 0 01110 s:2 11000 11010 10 rn:5 rd:5 \ +!constraints { $s < 2 || ($s == 2 && $Q == 1); } +# ReservedValue: break the constraint (s==2) => (Q=1) +SMINV_RES A64_V 0 0 0 01110 10 11000 11010 10 rn:5 rd:5 + +UADDLV A64_V 0 Q:1 1 01110 s:2 11000 00011 10 rn:5 rd:5 \ +!constraints { $s < 2 || ($s == 2 && $Q == 1); } +# ReservedValue: break the constraint (s==2) => (Q=1) +UADDLV_RES A64_V 0 0 1 01110 10 11000 00011 10 rn:5 rd:5 + +UMAXV A64_V 0 Q:1 1 01110 s:2 11000 01010 10 rn:5 rd:5 \ +!constraints { $s < 2 || ($s == 2 && $Q == 1); } +# ReservedValue: break the constraint (s==2) => (Q=1) +UMAXV_RES A64_V 0 0 1 01110 10 11000 01010 10 rn:5 rd:5 + +UMINV A64_V 0 Q:1 1 01110 s:2 11000 11010 10 rn:5 rd:5 \ +!constraints { $s < 2 || ($s == 2 && $Q == 1); } +# ReservedValue: break the constraint (s==2) => (Q=1) +UMINV_RES A64_V 0 0 1 01110 10 11000 11010 10 rn:5 rd:5 -SADDLV A64_V 0 Q:1 0 01110 size:2 11000 00011 10 rn:5 rd:5 \ -!constraints { $size < 2 || ($size == 2 && $Q == 1); } -# ReservedValue: break the constraint (size==2) => (Q=1) -SADDLV_RES A64_V 0 0 0 01110 10 11000 00011 10 rn:5 rd:5 - -SMAXV A64_V 0 Q:1 0 01110 size:2 11000 01010 10 rn:5 rd:5 \ -!constraints { $size < 2 || ($size == 2 && $Q == 1); } -# ReservedValue: break the constraint (size==2) => (Q=1) -SMAXV_RES A64_V 0 0 0 01110 10 11000 01010 10 rn:5 rd:5 - -SMINV A64_V 0 Q:1 0 01110 size:2 11000 11010 10 rn:5 rd:5 \ -!constraints { $size < 2 || ($size == 2 && $Q == 1); } -# ReservedValue: break the constraint (size==2) => (Q=1) -SMINV_RES A64_V 0 0 0 01110 10 11000 11010 10 rn:5 rd:5 - -ADDV A64_V 0 Q:1 0 01110 size:2 11000 11011 10 rn:5 rd:5 \ -!constraints { $size < 2 || ($size == 2 && $Q == 1); } -# ReservedValue: break the constraint (size==2) => (Q=1) -ADDV_RES A64_V 0 0 0 01110 10 11000 11011 10 rn:5 rd:5 - -UADDLV A64_V 0 Q:1 1 01110 size:2 11000 00011 10 rn:5 rd:5 \ -!constraints { $size < 2 || ($size == 2 && $Q == 1); } -# ReservedValue: break the constraint (size==2) => (Q=1) -UADDLV_RES A64_V 0 0 1 01110 10 11000 00011 10 rn:5 rd:5 - -UMAXV A64_V 0 Q:1 1 01110 size:2 11000 01010 10 rn:5 rd:5 \ -!constraints { $size < 2 || ($size == 2 && $Q == 1); } -# ReservedValue: break the constraint (size==2) => (Q=1) -UMAXV_RES A64_V 0 0 1 01110 10 11000 01010 10 rn:5 rd:5 - -UMINV A64_V 0 Q:1 1 01110 size:2 11000 11010 10 rn:5 rd:5 \ -!constraints { $size < 2 || ($size == 2 && $Q == 1); } -# ReservedValue: break the constraint (size==2) => (Q=1) -UMINV_RES A64_V 0 0 1 01110 10 11000 11010 10 rn:5 rd:5 - -FMAXNMV A64_V 0 1 1 01110 00 11000 01100 10 rn:5 rd:5 -FMAXV A64_V 0 1 1 01110 00 11000 01111 10 rn:5 rd:5 - -FMINNMV A64_V 0 1 1 01110 10 11000 01100 10 rn:5 rd:5 -FMINV A64_V 0 1 1 01110 10 11000 01111 10 rn:5 rd:5 +@ # C3.6.5 AdvSIMD copy # 31 30 29 28 27 26 25 24 23 22 21 20 16 15 14 11 10 9 5 4 0