From patchwork Tue May 26 03:22:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 188980 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44DB7C433E0 for ; Tue, 26 May 2020 03:22:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 15BF020706 for ; Tue, 26 May 2020 03:22:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=marek-ca.20150623.gappssmtp.com header.i=@marek-ca.20150623.gappssmtp.com header.b="Tgt4N8kV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388658AbgEZDWw (ORCPT ); Mon, 25 May 2020 23:22:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388634AbgEZDWv (ORCPT ); Mon, 25 May 2020 23:22:51 -0400 Received: from mail-qt1-x843.google.com (mail-qt1-x843.google.com [IPv6:2607:f8b0:4864:20::843]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A652DC05BD43 for ; Mon, 25 May 2020 20:22:51 -0700 (PDT) Received: by mail-qt1-x843.google.com with SMTP id x29so1940854qtv.4 for ; Mon, 25 May 2020 20:22:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0aukViFYkWYp/K9yYo92xKnCtfc8hTIQaEXbl52IaZ8=; b=Tgt4N8kVCx8INaPF8RhRybzswqn/fGftWK4dMElqK4rNRtOA4cO7fRq0cjTrPS0Ctj 3c0ZlcgGdbIc2fOxql/MR2Ofw2qvOW5bNe4wravNPVWjYlG368ayw3MZa5EBbQFM/ari aqM+UswF8Qp3PsLlApvaccAJJKb8KdtdVQbvluCvZFVuLQGEu9KH+AJd4OG88kymtHri cjtAxjgWakTwbO35pVY8EIbz3qqkQJvcSaGhFV/Vwv3z8apeS3s5mPsZj0l/UsajIPX6 45JxcHrX2Z+7mHpcO3K1Opb1lGJDjXE2bdZgh+ejwTjCbaEvE6c2q9+ZhlvQG0cxHonj moHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0aukViFYkWYp/K9yYo92xKnCtfc8hTIQaEXbl52IaZ8=; b=FSYscgOSZ9Y06KXjEQSOCZApOqCK9VsMXPJCGtRRtS6JoKhjhY/rE1uQwutR67wWlu ebKO0EOIR8Di+mD9CdB0PWz9UF4b2O2ffXXhqIDNDT/LozHLZ8FMaK4SOZUSgFU5onac 64vQN4CNAChzUiM6r5pLa+qrTU1xo3U+CyX8nuyms1k8jqj+7y1xOEuFAjRxYz0rg52L ahqpES4vVr3g4bi6DwZ4+M8j3Awyqvjk2r9eP5GzAxKKS6aEx3eUO8qDvcIWkUWUdXPT IZSA5GV4GlAvuOV/pXl5ZU8gtth7syKvb070ttbuwnPAmY7YNcZCuJxHcTc32+ba0lW3 mS8g== X-Gm-Message-State: AOAM533TeqcAuE6iwB8vRfDgelicwKf0ofCdxOuEHU7rENwkEYz7019a zIS+emU+ZM8uhy1mWkJomYnEqg== X-Google-Smtp-Source: ABdhPJyp/x6LxHiaA+wdxllBtBNimzBgnQdxAd1AP/SFGV8pJEaagwqilkXctY/9NR+faURv5kRG/A== X-Received: by 2002:ac8:2f64:: with SMTP id k33mr30597408qta.105.1590463370834; Mon, 25 May 2020 20:22:50 -0700 (PDT) Received: from localhost.localdomain ([147.253.86.153]) by smtp.gmail.com with ESMTPSA id k20sm2530796qtu.16.2020.05.25.20.22.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 May 2020 20:22:50 -0700 (PDT) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Drew Davenport , Zheng Bin , Sam Ravnborg , Chandan Uddaraju , Kalyan Thota , Shubhashree Dhar , Raviteja Tamatam , Stephen Boyd , Thomas Gleixner , Greg Kroah-Hartman , Allison Randal , Alexios Zavras , Abhinav Kumar , Linus Walleij , Georgi Djakov , Jayant Shekhar , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 2/8] drm/msm/dpu: update UBWC config for sm8150 and sm8250 Date: Mon, 25 May 2020 23:22:09 -0400 Message-Id: <20200526032235.21930-3-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20200526032235.21930-1-jonathan@marek.ca> References: <20200526032235.21930-1-jonathan@marek.ca> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Update the UBWC registers to the right values for sm8150 and sm8250. This removes broken dpu_hw_reset_ubwc, which doesn't work because the "force blk offset to zero to access beginning of register region" hack is copied from downstream, where mapped region starts 0x1000 below what is used in the upstream driver. Also simplifies the overly complicated change that was introduced in e4f9bbe9f8beab9a1ce4 to work around dpu_hw_reset_ubwc being broken. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 -- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 8 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 16 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 18 ----- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 7 -- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 75 ++++++------------- 6 files changed, 42 insertions(+), 88 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 1b960d9d1b33..3b48257886c6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1090,12 +1090,6 @@ static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) return; } - if (dpu_enc->cur_master->hw_mdptop && - dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc) - dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc( - dpu_enc->cur_master->hw_mdptop, - dpu_kms->catalog); - _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 09df7d87dd43..f45f031a3a05 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -37,7 +37,9 @@ #define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */ #define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */ #define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */ -#define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sdm855 v1.0 */ +#define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */ +#define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */ +#define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ @@ -65,10 +67,9 @@ enum { DPU_HW_UBWC_VER_10 = 0x100, DPU_HW_UBWC_VER_20 = 0x200, DPU_HW_UBWC_VER_30 = 0x300, + DPU_HW_UBWC_VER_40 = 0x400, }; -#define IS_UBWC_20_SUPPORTED(rev) ((rev) >= DPU_HW_UBWC_VER_20) - /** * MDP TOP BLOCK features * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe @@ -426,7 +427,6 @@ struct dpu_clk_ctrl_reg { struct dpu_mdp_cfg { DPU_HW_BLK_INFO; u32 highest_bank_bit; - u32 ubwc_static; u32 ubwc_swizzle; struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 82c5dbfdabc7..c940b69435e1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -303,11 +303,25 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx, DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, DPU_FETCH_CONFIG_RESET_VALUE | ctx->mdp->highest_bank_bit << 18); - if (IS_UBWC_20_SUPPORTED(ctx->catalog->caps->ubwc_version)) { + switch (ctx->catalog->caps->ubwc_version) { + case DPU_HW_UBWC_VER_10: + /* TODO: UBWC v1 case */ + break; + case DPU_HW_UBWC_VER_20: fast_clear = fmt->alpha_enable ? BIT(31) : 0; DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, fast_clear | (ctx->mdp->ubwc_swizzle) | (ctx->mdp->highest_bank_bit << 4)); + break; + case DPU_HW_UBWC_VER_30: + DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, + BIT(30) | (ctx->mdp->ubwc_swizzle) | + (ctx->mdp->highest_bank_bit << 4)); + break; + case DPU_HW_UBWC_VER_40: + DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, + DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); + break; } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index f9af52ae9f3e..01b76766a9a8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -8,7 +8,6 @@ #include "dpu_kms.h" #define SSPP_SPARE 0x28 -#define UBWC_STATIC 0x144 #define FLD_SPLIT_DISPLAY_CMD BIT(1) #define FLD_SMART_PANEL_FREE_RUN BIT(2) @@ -249,22 +248,6 @@ static void dpu_hw_get_safe_status(struct dpu_hw_mdp *mdp, status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1; } -static void dpu_hw_reset_ubwc(struct dpu_hw_mdp *mdp, struct dpu_mdss_cfg *m) -{ - struct dpu_hw_blk_reg_map c; - - if (!mdp || !m) - return; - - if (!IS_UBWC_20_SUPPORTED(m->caps->ubwc_version)) - return; - - /* force blk offset to zero to access beginning of register region */ - c = mdp->hw; - c.blk_off = 0x0; - DPU_REG_WRITE(&c, UBWC_STATIC, m->mdp[0].ubwc_static); -} - static void dpu_hw_intf_audio_select(struct dpu_hw_mdp *mdp) { struct dpu_hw_blk_reg_map *c; @@ -285,7 +268,6 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops, ops->get_danger_status = dpu_hw_get_danger_status; ops->setup_vsync_source = dpu_hw_setup_vsync_source; ops->get_safe_status = dpu_hw_get_safe_status; - ops->reset_ubwc = dpu_hw_reset_ubwc; ops->intf_audio_select = dpu_hw_intf_audio_select; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h index 1d9d32edf619..8018fff5667a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h @@ -126,13 +126,6 @@ struct dpu_hw_mdp_ops { void (*get_safe_status)(struct dpu_hw_mdp *mdp, struct dpu_danger_safe_status *status); - /** - * reset_ubwc - reset top level UBWC configuration - * @mdp: mdp top context driver - * @m: pointer to mdss catalog data - */ - void (*reset_ubwc)(struct dpu_hw_mdp *mdp, struct dpu_mdss_cfg *m); - /** * intf_audio_select - select the external interface for audio * @mdp: mdp top context driver diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c index 80d3cfc14007..fcfc3d6b71e7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c @@ -15,6 +15,10 @@ #define HW_REV 0x0 #define HW_INTR_STATUS 0x0010 +#define UBWC_STATIC 0x144 +#define UBWC_CTRL_2 0x150 +#define UBWC_PREDICTION_MODE 0x154 + /* Max BW defined in KBps */ #define MAX_BW 6800000 @@ -23,17 +27,6 @@ struct dpu_irq_controller { struct irq_domain *domain; }; -struct dpu_hw_cfg { - u32 val; - u32 offset; -}; - -struct dpu_mdss_hw_init_handler { - u32 hw_rev; - u32 hw_reg_count; - struct dpu_hw_cfg* hw_cfg; -}; - struct dpu_mdss { struct msm_mdss base; void __iomem *mmio; @@ -44,44 +37,6 @@ struct dpu_mdss { u32 num_paths; }; -static struct dpu_hw_cfg hw_cfg[] = { - { - /* UBWC global settings */ - .val = 0x1E, - .offset = 0x144, - } -}; - -static struct dpu_mdss_hw_init_handler cfg_handler[] = { - { .hw_rev = DPU_HW_VER_620, - .hw_reg_count = ARRAY_SIZE(hw_cfg), - .hw_cfg = hw_cfg - }, -}; - -static void dpu_mdss_hw_init(struct dpu_mdss *dpu_mdss, u32 hw_rev) -{ - int i; - u32 count = 0; - struct dpu_hw_cfg *hw_cfg = NULL; - - for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) { - if (cfg_handler[i].hw_rev == hw_rev) { - hw_cfg = cfg_handler[i].hw_cfg; - count = cfg_handler[i].hw_reg_count; - break; - } - } - - for (i = 0; i < count; i++ ) { - writel_relaxed(hw_cfg->val, - dpu_mdss->mmio + hw_cfg->offset); - hw_cfg++; - } - - return; -} - static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev, struct dpu_mdss *dpu_mdss) { @@ -224,7 +179,6 @@ static int dpu_mdss_enable(struct msm_mdss *mdss) struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss); struct dss_module_power *mp = &dpu_mdss->mp; int ret; - u32 mdss_rev; dpu_mdss_icc_request_bw(mdss); @@ -234,8 +188,25 @@ static int dpu_mdss_enable(struct msm_mdss *mdss) return ret; } - mdss_rev = readl_relaxed(dpu_mdss->mmio + HW_REV); - dpu_mdss_hw_init(dpu_mdss, mdss_rev); + /* + * ubwc config is part of the "mdss" region which is not accessible + * from the rest of the driver. hardcode known configurations here + */ + switch (readl_relaxed(dpu_mdss->mmio + HW_REV)) { + case DPU_HW_VER_500: + case DPU_HW_VER_501: + writel_relaxed(0x420, dpu_mdss->mmio + UBWC_STATIC); + break; + case DPU_HW_VER_600: + /* TODO: 0x102e for LP_DDR4 */ + writel_relaxed(0x103e, dpu_mdss->mmio + UBWC_STATIC); + writel_relaxed(2, dpu_mdss->mmio + UBWC_CTRL_2); + writel_relaxed(1, dpu_mdss->mmio + UBWC_PREDICTION_MODE); + break; + case DPU_HW_VER_620: + writel_relaxed(0x1e, dpu_mdss->mmio + UBWC_STATIC); + break; + } return ret; } From patchwork Tue May 26 03:22:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 188979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 562FEC433E0 for ; Tue, 26 May 2020 03:23:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3039D20878 for ; Tue, 26 May 2020 03:23:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=marek-ca.20150623.gappssmtp.com header.i=@marek-ca.20150623.gappssmtp.com header.b="NJcNULoK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388688AbgEZDXB (ORCPT ); Mon, 25 May 2020 23:23:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388523AbgEZDXA (ORCPT ); Mon, 25 May 2020 23:23:00 -0400 Received: from mail-qv1-xf41.google.com (mail-qv1-xf41.google.com [IPv6:2607:f8b0:4864:20::f41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ACB15C061A0E for ; Mon, 25 May 2020 20:23:00 -0700 (PDT) Received: by mail-qv1-xf41.google.com with SMTP id er16so8879097qvb.0 for ; Mon, 25 May 2020 20:23:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0VQLDJpM0rzdzDwm9I6kouTPUairFozQ0XrP2bnKQaY=; b=NJcNULoKv4NTrppdnuI1+h6RhDKoXrmM6JtatFLsfOU7I8waj2Ifw89KeuWMQ5n2zo pi69Ue+pxkHGB3+dsoYlFCRr6sn3d64Fl4rmlEri8x3CcCXBlpmcyNIA0bPcs1l11caV EpipHiynmq+wK10YYvIBIz052Id+EV8iIPD4vC7ThqFFrmtQrzNSvGJFsYbiclxRKrb3 WInCrSKQla1PUza022LkBosYzettz/bQFh3JybaecbWizZCIZq7qK11t70/6tbJwaeul 2MQt/MV0J3b/+x0PkXEVCmHX0naCuvMWiKqG2pV/03nWLi7vdFs0+ZQHEOtx0Zseq4HD dsmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0VQLDJpM0rzdzDwm9I6kouTPUairFozQ0XrP2bnKQaY=; b=ncKM5106ezUYSBVdfej/slGjCV8td2WsTkrvANhbqJzh0YhHH0jBnrRqxz9QDFRad+ VIuiwuylldiXKSRI52vTe1omcMEsYFFx316Wd/dQiWZzTM+T7dSIQ+SnBc7jzTYEcbFK CrOZQykzwZtUncJe7O179ZsZHjvHgdR7+kLUitwY5WCjgZPLNIcw1ywdTtVOIsTDZrhG 5vy8dmBbGLQ3b4gN5ZFn/9st7YjzwMD2oAEi+uIJJ50pmcjuFcJc2K7VBcIhgNu+TPMe djhO2V2lq2N2YH2n5vCNGQ7U1nLLJfuDnDo4z4APWIlGk7GYhihgsu5JLto2fkc9AkzQ MorA== X-Gm-Message-State: AOAM531PUq888UMUTnr5EsZqCZT8oigvIA4dUBOA6o7THjArCh6WnQYS 809aTWW8SsFjEArhX/sEJ5DO3A== X-Google-Smtp-Source: ABdhPJw0FxDLBwKiMcLrAc0fJx7TnkPhTvNdxnKJ59MX5rI8k4IsAOABxr6CSBMqKcG1Pe9PdZRJ5Q== X-Received: by 2002:a05:6214:8c1:: with SMTP id da1mr17194373qvb.135.1590463379940; Mon, 25 May 2020 20:22:59 -0700 (PDT) Received: from localhost.localdomain ([147.253.86.153]) by smtp.gmail.com with ESMTPSA id k20sm2530796qtu.16.2020.05.25.20.22.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 May 2020 20:22:59 -0700 (PDT) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Shubhashree Dhar , Raviteja Tamatam , Kalyan Thota , Stephen Boyd , Thomas Gleixner , Allison Randal , Greg Kroah-Hartman , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 4/8] drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845 Date: Mon, 25 May 2020 23:22:11 -0400 Message-Id: <20200526032235.21930-5-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20200526032235.21930-1-jonathan@marek.ca> References: <20200526032235.21930-1-jonathan@marek.ca> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The INTF_INPUT_CTRL feature is not available on sdm845, so don't set it. This also adds separate feature bits for INTF (based on downstream) instead of using CTL feature bit for it, and removes the unnecessary NULL check in the added bind_pingpong_blk function. Fixes: 73bfb790ac786ca55fa2786a06f59 ("msm:disp:dpu1: setup display datapath for SC7180 target") Signed-off-by: Jonathan Marek --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++-------- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 ++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 9 ++------- 3 files changed, 27 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 496407f1cd08..1e64fa08c219 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -41,6 +41,10 @@ #define PINGPONG_SDM845_SPLIT_MASK \ (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) +#define INTF_SDM845_MASK (0) + +#define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) + #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) #define DEFAULT_DPU_LINE_WIDTH 2048 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 @@ -376,26 +380,26 @@ static struct dpu_pingpong_cfg sc7180_pp[] = { /************************************************************* * INTF sub blocks config *************************************************************/ -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id) \ +#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _features) \ {\ .name = _name, .id = _id, \ .base = _base, .len = 0x280, \ - .features = BIT(DPU_CTL_ACTIVE_CFG), \ + .features = _features, \ .type = _type, \ .controller_id = _ctrl_id, \ .prog_fetch_lines_worst_case = 24 \ } static const struct dpu_intf_cfg sdm845_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0), - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1), - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1), + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SDM845_MASK), + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SDM845_MASK), + INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, INTF_SDM845_MASK), + INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, INTF_SDM845_MASK), }; static const struct dpu_intf_cfg sc7180_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0), + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SC7180_MASK), + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SC7180_MASK), }; /************************************************************* diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 7a8d1c6658d2..31ddb2be9c57 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -175,6 +175,19 @@ enum { DPU_CTL_MAX }; +/** + * INTF sub-blocks + * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which + * pixel data arrives to this INTF + * @DPU_INTF_TE INTF block has TE configuration support + * @DPU_INTF_MAX + */ +enum { + DPU_INTF_INPUT_CTRL = 0x1, + DPU_INTF_TE, + DPU_INTF_MAX +}; + /** * VBIF sub-blocks and features * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index efe9a5719c6b..64f556d693dd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -225,14 +225,9 @@ static void dpu_hw_intf_bind_pingpong_blk( bool enable, const enum dpu_pingpong pp) { - struct dpu_hw_blk_reg_map *c; + struct dpu_hw_blk_reg_map *c = &intf->hw; u32 mux_cfg; - if (!intf) - return; - - c = &intf->hw; - mux_cfg = DPU_REG_READ(c, INTF_MUX); mux_cfg &= ~0xf; @@ -280,7 +275,7 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, ops->get_status = dpu_hw_intf_get_status; ops->enable_timing = dpu_hw_intf_enable_timing_engine; ops->get_line_count = dpu_hw_intf_get_line_count; - if (cap & BIT(DPU_CTL_ACTIVE_CFG)) + if (cap & BIT(DPU_INTF_INPUT_CTRL)) ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; } From patchwork Tue May 26 03:22:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 188977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DC55C433E0 for ; Tue, 26 May 2020 03:23:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 299A82086A for ; Tue, 26 May 2020 03:23:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=marek-ca.20150623.gappssmtp.com header.i=@marek-ca.20150623.gappssmtp.com header.b="GTWzOqvE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388714AbgEZDXF (ORCPT ); Mon, 25 May 2020 23:23:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388614AbgEZDXD (ORCPT ); Mon, 25 May 2020 23:23:03 -0400 Received: from mail-qv1-xf42.google.com (mail-qv1-xf42.google.com [IPv6:2607:f8b0:4864:20::f42]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ECD83C05BD43 for ; Mon, 25 May 2020 20:23:02 -0700 (PDT) Received: by mail-qv1-xf42.google.com with SMTP id r16so46568qvm.6 for ; Mon, 25 May 2020 20:23:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AWAnzxFlBG6fffzFUdxDOCWUGLZUTqYmdG/nfLxRIYw=; b=GTWzOqvEA7APlKZrtWytxI3UiIPa9Y6MaUsjnygPQbcUyaVx4c8XiCqiNr7Cff/a9G KgjjDLdUPGOfF7m9HbgzYwegRZ28LwBDg8+/wHxjDDe2zYW/RU5qqo50EXMqB5rfxOB7 Fhmi6xUUmFAA6ClbRVu/6DWDq/MJWeN/LcpMRH89Vt1qVWcMNTtNRo+rYJE80hL6au+5 BvNQuPooPe8liULVPK/iZkNHC++tBaF4M0at4yOAAPYbVW86K4Dqh+ITCYl+ipj7ufOF Q/ayVJCWCKD9JqufTNPlTcwRadXX/x/k4NoHaJPkyPyCto0vOwXgTGv+1Eqd1ACMJZsx idtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AWAnzxFlBG6fffzFUdxDOCWUGLZUTqYmdG/nfLxRIYw=; b=ADUMwJ3F/IET0z0B0k3YspQsLbZgm/n3rqaDimw1uTHUvVkx1PkiycoF/S8717IY5V meV/SSlFbMavmpPS3kFTXDM88ilLO5kjOQLF/WGvjYVUcgi1Y6KqU+BSo0+67rrelAZ6 w1ktwjEkxak2mcyXiCb+nTgNGho7NP8DbeaV2SEfXa5OXaAJ8JwM/HHlVHC1L5TsFmAk MEQmzjzHjfbJh3YbIu3MCFqcVX2L2vMxkxsSqd1gFtgrYR+mALH9L8hsMYFDLo2XdINR vI9vJAEZq8/XY9Vq9D3PBf9lwBHziTPztBncvsQcgUXyNXZJxJBbpTyS+7aWdTDzhlOi 45eA== X-Gm-Message-State: AOAM531E1j9t1cJjGLYC92FY2gAg97kQ1euI74KmAgr4RMoh/Tl7/bkE yBpF1GOliiqxfoxoTfaS7R3TTQ== X-Google-Smtp-Source: ABdhPJwQ99YZM55+rNFn66oLsnyuqhfzXbeGT/sUdIanmJgqga8K7kurbsvipAlWTxcAKJBZ3WarOA== X-Received: by 2002:ad4:5684:: with SMTP id bc4mr18783129qvb.85.1590463382263; Mon, 25 May 2020 20:23:02 -0700 (PDT) Received: from localhost.localdomain ([147.253.86.153]) by smtp.gmail.com with ESMTPSA id k20sm2530796qtu.16.2020.05.25.20.23.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 May 2020 20:23:01 -0700 (PDT) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Allison Randal , Stephen Boyd , Alexios Zavras , Thomas Gleixner , Kalyan Thota , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 5/8] drm/msm/dpu: set missing flush bits for INTF_2 and INTF_3 Date: Mon, 25 May 2020 23:22:12 -0400 Message-Id: <20200526032235.21930-6-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20200526032235.21930-1-jonathan@marek.ca> References: <20200526032235.21930-1-jonathan@marek.ca> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This fixes flushing of INTF_2 and INTF_3 on SM8150 and SM8250 hardware. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 831e5f7a9b7f..996666afdd66 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -245,30 +245,14 @@ static int dpu_hw_ctl_get_bitmask_intf(struct dpu_hw_ctl *ctx, static int dpu_hw_ctl_get_bitmask_intf_v1(struct dpu_hw_ctl *ctx, u32 *flushbits, enum dpu_intf intf) { - switch (intf) { - case INTF_0: - case INTF_1: - *flushbits |= BIT(31); - break; - default: - return 0; - } + *flushbits |= BIT(31); return 0; } static int dpu_hw_ctl_active_get_bitmask_intf(struct dpu_hw_ctl *ctx, u32 *flushbits, enum dpu_intf intf) { - switch (intf) { - case INTF_0: - *flushbits |= BIT(0); - break; - case INTF_1: - *flushbits |= BIT(1); - break; - default: - return 0; - } + *flushbits |= BIT(intf - INTF_0); return 0; } From patchwork Tue May 26 03:22:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 188978 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAD60C433E1 for ; Tue, 26 May 2020 03:23:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B9DF120706 for ; Tue, 26 May 2020 03:23:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=marek-ca.20150623.gappssmtp.com header.i=@marek-ca.20150623.gappssmtp.com header.b="iAcLYGIm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388736AbgEZDXJ (ORCPT ); Mon, 25 May 2020 23:23:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388727AbgEZDXG (ORCPT ); Mon, 25 May 2020 23:23:06 -0400 Received: from mail-qv1-xf41.google.com (mail-qv1-xf41.google.com [IPv6:2607:f8b0:4864:20::f41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FE0AC05BD43 for ; Mon, 25 May 2020 20:23:05 -0700 (PDT) Received: by mail-qv1-xf41.google.com with SMTP id p4so8831859qvr.10 for ; Mon, 25 May 2020 20:23:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DZjkvReBVpxbpSNmHSMVv60YPHC0WHPyESfR7wPaf0g=; b=iAcLYGImXt7qU+Oj1+OrSH57RdqT0EzL8qM0lMEU0Fw9Z2OuBXZsRENIkFPa7zKuqd dhDJFAVOXSO/u5g85UjqfVfA38EJhysYo/k2Jr5sCg8MhlaWXp/jT9hvrWbxNg+Khr9f ZbuugSxq4Z+4ysN6DfC4lnb1zQw+Xy3nHU23FKOHHJCxGI/yDixXer5//HYetBpzSuta gRmqtXHWrkK5sPPWQyRLYjgTRomva9uRYh392t/3EjtehTLwNzgmLnymLpbUlYAYrhhi 0I/egqEEolBC8qVZcKTW8GZqcSVbLwwvrJDN7/kBlW4R8tPYALp3l7vrcmzI+PyvDhWx A10w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DZjkvReBVpxbpSNmHSMVv60YPHC0WHPyESfR7wPaf0g=; b=UIIpEEfx2wiOdHRug00TJ7Gvtae/DU2V6iFDgd3SUs9cv5vjdknoQeFPZdxG6xGMz2 Ju0rRiy4ZWvCzKiLiCHhPbBhrmDq9oR2B0fTuEktPwKbUZZOg1mMV8E+k2SUFtGimR3l /0khoK1efsORLfjdjAwp6ioKbCs/gp6fFz/tQNs0++Jy1d0YyqE8dVcskDRi+Fsi6ymj Tg/gXV6V9GdDralpJSYhLl67c8F17o1RKUxXNchTlnYRhviZgfCc1CErexY354E32Mmr b0xjky8F074tOfQERoSnclRaTECsaPm7J+543tDgoviZx/dch+IZYvopxhWH3QOUeM0z JddQ== X-Gm-Message-State: AOAM531AWrY4V/vrpfaqoVHfDgLrsJ1sVuJNBfQdNmGnx90/MO53/2oo Fv6IwMOzelfUl9uelT236fOIog== X-Google-Smtp-Source: ABdhPJzRkywAd6OOmXgCnPe/1+ksB8fOOWAWM2ed8Hl4/LLIF4lXfUb2uE2H7ftcxkzujzi2+9sbxg== X-Received: by 2002:a0c:fe88:: with SMTP id d8mr17702304qvs.208.1590463384541; Mon, 25 May 2020 20:23:04 -0700 (PDT) Received: from localhost.localdomain ([147.253.86.153]) by smtp.gmail.com with ESMTPSA id k20sm2530796qtu.16.2020.05.25.20.23.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 May 2020 20:23:04 -0700 (PDT) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Shubhashree Dhar , Alexios Zavras , Raviteja Tamatam , Thomas Gleixner , Kalyan Thota , Stephen Boyd , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 6/8] drm/msm/dpu: intf timing path for displayport Date: Mon, 25 May 2020 23:22:13 -0400 Message-Id: <20200526032235.21930-7-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20200526032235.21930-1-jonathan@marek.ca> References: <20200526032235.21930-1-jonathan@marek.ca> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Calculate the correct timings for displayport, from downstream driver. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 64f556d693dd..6f0f54588124 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -107,11 +107,6 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) + p->hsync_skew - 1; - if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) { - display_v_start += p->hsync_pulse_width + p->h_back_porch; - display_v_end -= p->h_front_porch; - } - hsync_start_x = p->h_back_porch + p->hsync_pulse_width; hsync_end_x = hsync_period - p->h_front_porch - 1; @@ -144,10 +139,25 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width; display_hctl = (hsync_end_x << 16) | hsync_start_x; + if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) { + active_h_start = hsync_start_x; + active_h_end = active_h_start + p->xres - 1; + active_v_start = display_v_start; + active_v_end = active_v_start + (p->yres * hsync_period) - 1; + + display_v_start += p->hsync_pulse_width + p->h_back_porch; + + active_hctl = (active_h_end << 16) | active_h_start; + display_hctl = active_hctl; + } + den_polarity = 0; if (ctx->cap->type == INTF_HDMI) { hsync_polarity = p->yres >= 720 ? 0 : 1; vsync_polarity = p->yres >= 720 ? 0 : 1; + } else if (ctx->cap->type == INTF_DP) { + hsync_polarity = p->hsync_polarity; + vsync_polarity = p->vsync_polarity; } else { hsync_polarity = 0; vsync_polarity = 0;