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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:32 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/17] hw/arm/spitz: Detabify Date: Sun, 28 Jun 2020 15:24:13 +0100 Message-Id: <20200628142429.17111-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The spitz board has been around a long time, and still has a fair number of hard-coded tab characters in it. We're about to do some work on this source file, so start out by expanding out the tabs. This commit is a pure whitespace only change. Signed-off-by: Peter Maydell --- Couple of checkpatch errors due to the QUEUE_KEY macro which can be ignored as this is just a detabify. --- hw/arm/spitz.c | 156 ++++++++++++++++++++++++------------------------- 1 file changed, 78 insertions(+), 78 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index fc18212e686..9eaedab79b5 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -34,25 +34,25 @@ #include "cpu.h" #undef REG_FMT -#define REG_FMT "0x%02lx" +#define REG_FMT "0x%02lx" /* Spitz Flash */ -#define FLASH_BASE 0x0c000000 -#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */ -#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */ -#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */ -#define FLASH_ECCCNTR 0x0c /* ECC byte counter */ -#define FLASH_ECCCLRR 0x10 /* Clear ECC */ -#define FLASH_FLASHIO 0x14 /* Flash I/O */ -#define FLASH_FLASHCTL 0x18 /* Flash Control */ +#define FLASH_BASE 0x0c000000 +#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */ +#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */ +#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */ +#define FLASH_ECCCNTR 0x0c /* ECC byte counter */ +#define FLASH_ECCCLRR 0x10 /* Clear ECC */ +#define FLASH_FLASHIO 0x14 /* Flash I/O */ +#define FLASH_FLASHCTL 0x18 /* Flash Control */ -#define FLASHCTL_CE0 (1 << 0) -#define FLASHCTL_CLE (1 << 1) -#define FLASHCTL_ALE (1 << 2) -#define FLASHCTL_WP (1 << 3) -#define FLASHCTL_CE1 (1 << 4) -#define FLASHCTL_RYBY (1 << 5) -#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1) +#define FLASHCTL_CE0 (1 << 0) +#define FLASHCTL_CLE (1 << 1) +#define FLASHCTL_ALE (1 << 2) +#define FLASHCTL_WP (1 << 3) +#define FLASHCTL_CE1 (1 << 4) +#define FLASHCTL_RYBY (1 << 5) +#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1) #define TYPE_SL_NAND "sl-nand" #define SL_NAND(obj) OBJECT_CHECK(SLNANDState, (obj), TYPE_SL_NAND) @@ -74,12 +74,12 @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size) int ryby; switch (addr) { -#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to)) +#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to)) case FLASH_ECCLPLB: return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) | BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7); -#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to)) +#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to)) case FLASH_ECCLPUB: return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) | BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7); @@ -191,8 +191,8 @@ static void sl_nand_realize(DeviceState *dev, Error **errp) /* Spitz Keyboard */ -#define SPITZ_KEY_STROBE_NUM 11 -#define SPITZ_KEY_SENSE_NUM 7 +#define SPITZ_KEY_STROBE_NUM 11 +#define SPITZ_KEY_SENSE_NUM 7 static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = { 12, 17, 91, 34, 36, 38, 39 @@ -214,11 +214,11 @@ static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = { { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 }, }; -#define SPITZ_GPIO_AK_INT 13 /* Remote control */ -#define SPITZ_GPIO_SYNC 16 /* Sync button */ -#define SPITZ_GPIO_ON_KEY 95 /* Power button */ -#define SPITZ_GPIO_SWA 97 /* Lid */ -#define SPITZ_GPIO_SWB 96 /* Tablet mode */ +#define SPITZ_GPIO_AK_INT 13 /* Remote control */ +#define SPITZ_GPIO_SYNC 16 /* Sync button */ +#define SPITZ_GPIO_ON_KEY 95 /* Power button */ +#define SPITZ_GPIO_SWA 97 /* Lid */ +#define SPITZ_GPIO_SWB 96 /* Tablet mode */ /* The special buttons are mapped to unused keys */ static const int spitz_gpiomap[5] = { @@ -300,7 +300,7 @@ static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode) #define SPITZ_MOD_CTRL (1 << 8) #define SPITZ_MOD_FN (1 << 9) -#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c +#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c static void spitz_keyboard_handler(void *opaque, int keycode) { @@ -308,25 +308,25 @@ static void spitz_keyboard_handler(void *opaque, int keycode) uint16_t code; int mapcode; switch (keycode) { - case 0x2a: /* Left Shift */ + case 0x2a: /* Left Shift */ s->modifiers |= 1; break; case 0xaa: s->modifiers &= ~1; break; - case 0x36: /* Right Shift */ + case 0x36: /* Right Shift */ s->modifiers |= 2; break; case 0xb6: s->modifiers &= ~2; break; - case 0x1d: /* Control */ + case 0x1d: /* Control */ s->modifiers |= 4; break; case 0x9d: s->modifiers &= ~4; break; - case 0x38: /* Alt */ + case 0x38: /* Alt */ s->modifiers |= 8; break; case 0xb8: @@ -536,14 +536,14 @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp) /* LCD backlight controller */ -#define LCDTG_RESCTL 0x00 -#define LCDTG_PHACTRL 0x01 -#define LCDTG_DUTYCTRL 0x02 -#define LCDTG_POWERREG0 0x03 -#define LCDTG_POWERREG1 0x04 -#define LCDTG_GPOR3 0x05 -#define LCDTG_PICTRL 0x06 -#define LCDTG_POLCTRL 0x07 +#define LCDTG_RESCTL 0x00 +#define LCDTG_PHACTRL 0x01 +#define LCDTG_DUTYCTRL 0x02 +#define LCDTG_POWERREG0 0x03 +#define LCDTG_POWERREG1 0x04 +#define LCDTG_GPOR3 0x05 +#define LCDTG_PICTRL 0x06 +#define LCDTG_POLCTRL 0x07 typedef struct { SSISlave ssidev; @@ -623,12 +623,12 @@ static void spitz_lcdtg_realize(SSISlave *dev, Error **errp) /* SSP devices */ -#define CORGI_SSP_PORT 2 +#define CORGI_SSP_PORT 2 -#define SPITZ_GPIO_LCDCON_CS 53 -#define SPITZ_GPIO_ADS7846_CS 14 -#define SPITZ_GPIO_MAX1111_CS 20 -#define SPITZ_GPIO_TP_INT 11 +#define SPITZ_GPIO_LCDCON_CS 53 +#define SPITZ_GPIO_ADS7846_CS 14 +#define SPITZ_GPIO_MAX1111_CS 20 +#define SPITZ_GPIO_TP_INT 11 static DeviceState *max1111; @@ -659,13 +659,13 @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level) s->enable[line] = !level; } -#define MAX1111_BATT_VOLT 1 -#define MAX1111_BATT_TEMP 2 -#define MAX1111_ACIN_VOLT 3 +#define MAX1111_BATT_VOLT 1 +#define MAX1111_BATT_TEMP 2 +#define MAX1111_ACIN_VOLT 3 -#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */ -#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */ -#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */ +#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */ +#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */ +#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */ static void spitz_adc_temp_on(void *opaque, int line, int level) { @@ -735,11 +735,11 @@ static void spitz_microdrive_attach(PXA2xxState *cpu, int slot) /* Wm8750 and Max7310 on I2C */ -#define AKITA_MAX_ADDR 0x18 -#define SPITZ_WM_ADDRL 0x1b -#define SPITZ_WM_ADDRH 0x1a +#define AKITA_MAX_ADDR 0x18 +#define SPITZ_WM_ADDRL 0x1b +#define SPITZ_WM_ADDRH 0x1a -#define SPITZ_GPIO_WM 5 +#define SPITZ_GPIO_WM 5 static void spitz_wm8750_addr(void *opaque, int line, int level) { @@ -806,20 +806,20 @@ static void spitz_out_switch(void *opaque, int line, int level) } } -#define SPITZ_SCP_LED_GREEN 1 -#define SPITZ_SCP_JK_B 2 -#define SPITZ_SCP_CHRG_ON 3 -#define SPITZ_SCP_MUTE_L 4 -#define SPITZ_SCP_MUTE_R 5 -#define SPITZ_SCP_CF_POWER 6 -#define SPITZ_SCP_LED_ORANGE 7 -#define SPITZ_SCP_JK_A 8 -#define SPITZ_SCP_ADC_TEMP_ON 9 -#define SPITZ_SCP2_IR_ON 1 -#define SPITZ_SCP2_AKIN_PULLUP 2 -#define SPITZ_SCP2_BACKLIGHT_CONT 7 -#define SPITZ_SCP2_BACKLIGHT_ON 8 -#define SPITZ_SCP2_MIC_BIAS 9 +#define SPITZ_SCP_LED_GREEN 1 +#define SPITZ_SCP_JK_B 2 +#define SPITZ_SCP_CHRG_ON 3 +#define SPITZ_SCP_MUTE_L 4 +#define SPITZ_SCP_MUTE_R 5 +#define SPITZ_SCP_CF_POWER 6 +#define SPITZ_SCP_LED_ORANGE 7 +#define SPITZ_SCP_JK_A 8 +#define SPITZ_SCP_ADC_TEMP_ON 9 +#define SPITZ_SCP2_IR_ON 1 +#define SPITZ_SCP2_AKIN_PULLUP 2 +#define SPITZ_SCP2_BACKLIGHT_CONT 7 +#define SPITZ_SCP2_BACKLIGHT_ON 8 +#define SPITZ_SCP2_MIC_BIAS 9 static void spitz_scoop_gpio_setup(PXA2xxState *cpu, DeviceState *scp0, DeviceState *scp1) @@ -839,15 +839,15 @@ static void spitz_scoop_gpio_setup(PXA2xxState *cpu, qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); } -#define SPITZ_GPIO_HSYNC 22 -#define SPITZ_GPIO_SD_DETECT 9 -#define SPITZ_GPIO_SD_WP 81 -#define SPITZ_GPIO_ON_RESET 89 -#define SPITZ_GPIO_BAT_COVER 90 -#define SPITZ_GPIO_CF1_IRQ 105 -#define SPITZ_GPIO_CF1_CD 94 -#define SPITZ_GPIO_CF2_IRQ 106 -#define SPITZ_GPIO_CF2_CD 93 +#define SPITZ_GPIO_HSYNC 22 +#define SPITZ_GPIO_SD_DETECT 9 +#define SPITZ_GPIO_SD_WP 81 +#define SPITZ_GPIO_ON_RESET 89 +#define SPITZ_GPIO_BAT_COVER 90 +#define SPITZ_GPIO_CF1_IRQ 105 +#define SPITZ_GPIO_CF1_CD 94 +#define SPITZ_GPIO_CF2_IRQ 106 +#define SPITZ_GPIO_CF2_CD 93 static int spitz_hsync; @@ -907,8 +907,8 @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots) /* Board init. */ enum spitz_model_e { spitz, akita, borzoi, terrier }; -#define SPITZ_RAM 0x04000000 -#define SPITZ_ROM 0x00800000 +#define SPITZ_RAM 0x04000000 +#define SPITZ_ROM 0x00800000 static struct arm_boot_info spitz_binfo = { .loader_start = PXA2XX_SDRAM_BASE, From patchwork Sun Jun 28 14:24:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 191963 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2136405ilg; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:34 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/17] hw/arm/spitz: Create SpitzMachineClass abstract base class Date: Sun, 28 Jun 2020 15:24:14 +0100 Message-Id: <20200628142429.17111-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For the four Spitz-family machines (akita, borzoi, spitz, terrier) create a proper abstract class SpitzMachineClass which encapsulates the common behaviour, rather than having them all derive directly from TYPE_MACHINE: * instead of each machine class setting mc->init to a wrapper function which calls spitz_common_init() with parameters, put that data in the SpitzMachineClass and make spitz_common_init the SpitzMachineClass machine-init function * move the settings of mc->block_default_type and mc->ignore_memory_transaction_failures into the SpitzMachineClass class init rather than repeating them in each machine's class init (The motivation is that we're going to want to keep some state in the SpitzMachineState so we can connect GPIOs between devices created in one sub-function of the machine init to devices created in a different sub-function.) Signed-off-by: Peter Maydell --- hw/arm/spitz.c | 91 ++++++++++++++++++++++++++++++-------------------- 1 file changed, 55 insertions(+), 36 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 9eaedab79b5..c70e912a33d 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -33,6 +33,26 @@ #include "exec/address-spaces.h" #include "cpu.h" +enum spitz_model_e { spitz, akita, borzoi, terrier }; + +typedef struct { + MachineClass parent; + enum spitz_model_e model; + int arm_id; +} SpitzMachineClass; + +typedef struct { + MachineState parent; +} SpitzMachineState; + +#define TYPE_SPITZ_MACHINE "spitz-common" +#define SPITZ_MACHINE(obj) \ + OBJECT_CHECK(SpitzMachineState, obj, TYPE_SPITZ_MACHINE) +#define SPITZ_MACHINE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(SpitzMachineClass, obj, TYPE_SPITZ_MACHINE) +#define SPITZ_MACHINE_CLASS(klass) \ + OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE) + #undef REG_FMT #define REG_FMT "0x%02lx" @@ -905,8 +925,6 @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots) } /* Board init. */ -enum spitz_model_e { spitz, akita, borzoi, terrier }; - #define SPITZ_RAM 0x04000000 #define SPITZ_ROM 0x00800000 @@ -915,9 +933,10 @@ static struct arm_boot_info spitz_binfo = { .ram_size = 0x04000000, }; -static void spitz_common_init(MachineState *machine, - enum spitz_model_e model, int arm_id) +static void spitz_common_init(MachineState *machine) { + SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine); + enum spitz_model_e model = smc->model; PXA2xxState *mpu; DeviceState *scp0, *scp1 = NULL; MemoryRegion *address_space_mem = get_system_memory(); @@ -958,100 +977,100 @@ static void spitz_common_init(MachineState *machine, /* A 4.0 GB microdrive is permanently sitting in CF slot 0. */ spitz_microdrive_attach(mpu, 0); - spitz_binfo.board_id = arm_id; + spitz_binfo.board_id = smc->arm_id; arm_load_kernel(mpu->cpu, machine, &spitz_binfo); sl_bootparam_write(SL_PXA_PARAM_BASE); } -static void spitz_init(MachineState *machine) +static void spitz_common_class_init(ObjectClass *oc, void *data) { - spitz_common_init(machine, spitz, 0x2c9); + MachineClass *mc = MACHINE_CLASS(oc); + + mc->block_default_type = IF_IDE; + mc->ignore_memory_transaction_failures = true; + mc->init = spitz_common_init; } -static void borzoi_init(MachineState *machine) -{ - spitz_common_init(machine, borzoi, 0x33f); -} - -static void akita_init(MachineState *machine) -{ - spitz_common_init(machine, akita, 0x2e8); -} - -static void terrier_init(MachineState *machine) -{ - spitz_common_init(machine, terrier, 0x33f); -} +static const TypeInfo spitz_common_info = { + .name = TYPE_SPITZ_MACHINE, + .parent = TYPE_MACHINE, + .abstract = true, + .instance_size = sizeof(SpitzMachineState), + .class_size = sizeof(SpitzMachineClass), + .class_init = spitz_common_class_init, +}; static void akitapda_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc); mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)"; - mc->init = akita_init; - mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); + smc->model = akita; + smc->arm_id = 0x2e8; } static const TypeInfo akitapda_type = { .name = MACHINE_TYPE_NAME("akita"), - .parent = TYPE_MACHINE, + .parent = TYPE_SPITZ_MACHINE, .class_init = akitapda_class_init, }; static void spitzpda_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc); mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)"; - mc->init = spitz_init; - mc->block_default_type = IF_IDE; - mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); + smc->model = spitz; + smc->arm_id = 0x2c9; } static const TypeInfo spitzpda_type = { .name = MACHINE_TYPE_NAME("spitz"), - .parent = TYPE_MACHINE, + .parent = TYPE_SPITZ_MACHINE, .class_init = spitzpda_class_init, }; static void borzoipda_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc); mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)"; - mc->init = borzoi_init; - mc->block_default_type = IF_IDE; - mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); + smc->model = borzoi; + smc->arm_id = 0x33f; } static const TypeInfo borzoipda_type = { .name = MACHINE_TYPE_NAME("borzoi"), - .parent = TYPE_MACHINE, + .parent = TYPE_SPITZ_MACHINE, .class_init = borzoipda_class_init, }; static void terrierpda_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc); mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)"; - mc->init = terrier_init; - mc->block_default_type = IF_IDE; - mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5"); + smc->model = terrier; + smc->arm_id = 0x33f; } static const TypeInfo terrierpda_type = { .name = MACHINE_TYPE_NAME("terrier"), - .parent = TYPE_MACHINE, + .parent = TYPE_SPITZ_MACHINE, .class_init = terrierpda_class_init, }; static void spitz_machine_init(void) { + type_register_static(&spitz_common_info); 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:35 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/17] hw/arm/spitz: Keep pointers to MPU and SSI devices in SpitzMachineState Date: Sun, 28 Jun 2020 15:24:15 +0100 Message-Id: <20200628142429.17111-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Keep pointers to the MPU and the SSI devices in SpitzMachineState. We're going to want to make GPIO connections between some of the SSI devices and the SCPs, so we want to keep hold of a pointer to those; putting the MPU into the struct allows us to pass just one thing to spitz_ssp_attach() rather than two. We have to retain the setting of the global "max1111" variable for the moment as it is used in spitz_adc_temp_on(); later in this series of commits we will be able to remove it. Signed-off-by: Peter Maydell --- hw/arm/spitz.c | 50 ++++++++++++++++++++++++++++---------------------- 1 file changed, 28 insertions(+), 22 deletions(-) -- 2.20.1 Reviewed-by: Alistair Francis diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index c70e912a33d..f48e966c047 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -43,6 +43,11 @@ typedef struct { typedef struct { MachineState parent; + PXA2xxState *mpu; + DeviceState *mux; + DeviceState *lcdtg; + DeviceState *ads7846; + DeviceState *max1111; } SpitzMachineState; #define TYPE_SPITZ_MACHINE "spitz-common" @@ -709,34 +714,33 @@ static void corgi_ssp_realize(SSISlave *d, Error **errp) s->bus[2] = ssi_create_bus(dev, "ssi2"); } -static void spitz_ssp_attach(PXA2xxState *cpu) +static void spitz_ssp_attach(SpitzMachineState *sms) { - DeviceState *mux; - DeviceState *dev; void *bus; - mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp"); + sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp"); - bus = qdev_get_child_bus(mux, "ssi0"); - ssi_create_slave(bus, "spitz-lcdtg"); + bus = qdev_get_child_bus(sms->mux, "ssi0"); + sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg"); - bus = qdev_get_child_bus(mux, "ssi1"); - dev = ssi_create_slave(bus, "ads7846"); - qdev_connect_gpio_out(dev, 0, - qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT)); + bus = qdev_get_child_bus(sms->mux, "ssi1"); + sms->ads7846 = ssi_create_slave(bus, "ads7846"); + qdev_connect_gpio_out(sms->ads7846, 0, + qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT)); - bus = qdev_get_child_bus(mux, "ssi2"); - max1111 = ssi_create_slave(bus, "max1111"); - max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT); - max111x_set_input(max1111, MAX1111_BATT_TEMP, 0); - max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN); + bus = qdev_get_child_bus(sms->mux, "ssi2"); + sms->max1111 = ssi_create_slave(bus, "max1111"); + max1111 = sms->max1111; + max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT); + max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0); + max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN); - qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS, - qdev_get_gpio_in(mux, 0)); - qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS, - qdev_get_gpio_in(mux, 1)); - qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS, - qdev_get_gpio_in(mux, 2)); + qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS, + qdev_get_gpio_in(sms->mux, 0)); + qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_ADS7846_CS, + qdev_get_gpio_in(sms->mux, 1)); + qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_MAX1111_CS, + qdev_get_gpio_in(sms->mux, 2)); } /* CF Microdrive */ @@ -936,6 +940,7 @@ static struct arm_boot_info spitz_binfo = { static void spitz_common_init(MachineState *machine) { SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine); + SpitzMachineState *sms = SPITZ_MACHINE(machine); enum spitz_model_e model = smc->model; PXA2xxState *mpu; DeviceState *scp0, *scp1 = NULL; @@ -945,6 +950,7 @@ static void spitz_common_init(MachineState *machine) /* Setup CPU & memory */ mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, machine->cpu_type); + sms->mpu = mpu; sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M); @@ -954,7 +960,7 @@ static void spitz_common_init(MachineState *machine) /* Setup peripherals */ spitz_keyboard_register(mpu); - spitz_ssp_attach(mpu); + spitz_ssp_attach(sms); scp0 = sysbus_create_simple("scoop", 0x10800000, NULL); if (model != akita) { From patchwork Sun Jun 28 14:24:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 191965 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2136691ilg; Sun, 28 Jun 2020 07:27:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw5CsHapSDfLgeFC0XbI8C07eAclkAeQG1vrgTetFZ0YV5ELgWiUC+2sXTfccm1EK3ktXU6 X-Received: by 2002:a5b:610:: with SMTP id d16mr18623720ybq.289.1593354476270; Sun, 28 Jun 2020 07:27:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593354476; cv=none; d=google.com; s=arc-20160816; b=f87lBlo0vFOMSSvCN1I5jHGe48qzIfnaHtUlcjo9/WHW6dqYVURk6x7iZw5G/KjiZJ YOWs0u09LqdlJzmEnu1GgHWsg0z10+e9dODASuRuk6fgcC80XnODRa/T0HQhqO4KJHP2 PU3s99qRY26ThlZ0cO89R9QR+lL/tkFQi+igy0b58z7KEqg+Au9hSngqplSxJ5sXv8Ru p2QPKvSdItCeZ6KGQFm+2I92YeGZgAVwWCKMgQo8jz26zVUtQfBoG5qy/dixsW+5eg9A Vsl8VFWDQif5G4J1SorjCbKGyLx17aAmvYmhK3mWvTWt8K1jtQvKk8ZMaNH/hJZwIpaP SlqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GNnYdzaF3r1xGcDpbFt33icK43InuylWrRKeXCca234=; b=B1KyYG28kUqcuLSAuAkeTN1XEsKld7C1N1dSqc+tzW1CDNn/8AfIKf86nyw9g/N2D3 1zAhxNlpEwcUIbiVn+rr5svi+PnbGgivbwdPP8P0UBKWrRh36S/BaCVsbBLQcS2ZhDJk OS8l8g9gk7ix+2BXgQ0KxG3mTpm3qIKJANiYSLp0eFRCWALBvfIZ5CUTN6qGy0PPWXHc IlMJbKf7RyVJKKRsG454ym38P+aiWYTftBF1AcYyw13oJs2kBvtmXSV+jd8CrmIjRMv6 aX1mnmRO/66jt9KhADQDFQkuSKW7j76cXLzOpARk1TrtQWFzZvu+xpxZGWEnP73Y60pz +obw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="xgLGtE/G"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:36 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/17] hw/arm/spitz: Keep pointers to scp0, scp1 in SpitzMachineState Date: Sun, 28 Jun 2020 15:24:16 +0100 Message-Id: <20200628142429.17111-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Keep pointers to scp0, scp1 in SpitzMachineState, and just pass that to spitz_scoop_gpio_setup(). (We'll want to use some of the other fields in SpitzMachineState in that function in the next commit.) Signed-off-by: Peter Maydell --- hw/arm/spitz.c | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) -- 2.20.1 Reviewed-by: Alistair Francis diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index f48e966c047..69bc2b3fa10 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -48,6 +48,8 @@ typedef struct { DeviceState *lcdtg; DeviceState *ads7846; DeviceState *max1111; + DeviceState *scp0; + DeviceState *scp1; } SpitzMachineState; #define TYPE_SPITZ_MACHINE "spitz-common" @@ -845,22 +847,23 @@ static void spitz_out_switch(void *opaque, int line, int level) #define SPITZ_SCP2_BACKLIGHT_ON 8 #define SPITZ_SCP2_MIC_BIAS 9 -static void spitz_scoop_gpio_setup(PXA2xxState *cpu, - DeviceState *scp0, DeviceState *scp1) +static void spitz_scoop_gpio_setup(SpitzMachineState *sms) { - qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8); + qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, sms->mpu, 8); - qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]); - qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]); - qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]); - qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, outsignals[0]); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, outsignals[1]); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, outsignals[2]); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]); - if (scp1) { - qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]); - qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]); + if (sms->scp1) { + qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT, + outsignals[4]); + qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON, + outsignals[5]); } - qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); } #define SPITZ_GPIO_HSYNC 22 @@ -943,7 +946,6 @@ static void spitz_common_init(MachineState *machine) SpitzMachineState *sms = SPITZ_MACHINE(machine); enum spitz_model_e model = smc->model; PXA2xxState *mpu; - DeviceState *scp0, *scp1 = NULL; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *rom = g_new(MemoryRegion, 1); @@ -962,12 +964,14 @@ static void spitz_common_init(MachineState *machine) spitz_ssp_attach(sms); - scp0 = sysbus_create_simple("scoop", 0x10800000, NULL); + sms->scp0 = sysbus_create_simple("scoop", 0x10800000, NULL); if (model != akita) { - scp1 = sysbus_create_simple("scoop", 0x08800040, NULL); + sms->scp1 = sysbus_create_simple("scoop", 0x08800040, NULL); + } else { + sms->scp1 = NULL; } - spitz_scoop_gpio_setup(mpu, scp0, scp1); + spitz_scoop_gpio_setup(sms); spitz_gpio_setup(mpu, (model == akita) ? 1 : 2); From patchwork Sun Jun 28 14:24:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 191967 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2137415ilg; Sun, 28 Jun 2020 07:29:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx8Bg0bNx8WtQHV1PUViOB+D1tFfu7lfW+agLtvtC1bKCexkD95xisuqvruaNTbwxqc26w2 X-Received: by 2002:a25:31c6:: with SMTP id x189mr19737370ybx.264.1593354556764; Sun, 28 Jun 2020 07:29:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593354556; cv=none; d=google.com; s=arc-20160816; b=qPv/bMMwTEKt4N7MecyDMxcmFpymVHmUhVbokJsT3bAGdUMTOfICRRb9silQwR2TRn 26LFjv0nGdgb1aHGTkX4XJoNGDFKOdpC/6VTG12EVW3q5ambXrm/b1qbc4pfhnRawx/4 wOZ4sDjXGbGFwjTfd9GxZ2lLCxM1BjEFU0sw9/Asz5I505hYBEjWL0vYKIcmzdyv8Q7y Osp+3Y+juQSFVwlfTJzpJy6eEObwoFwJjUvDQi8Jbxcq58JvCjamrjIMIFx//MluMiRH WEYxTy9xGEYMf76Z9AF1d5pR+ewMFnAmhTGRmsiJlhe0bWn+Hih1BhO2E/6GdTtegagb 15Fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uwJ6AMnZ4BeCXoBcjEvXgzYDqM09D0Grg4qI2GYORlA=; b=ttIK0reUHGqC+LlnGPNtys+auetApdY9Nrg7h1BQ1vbV4JjO0QzAadPHcMOrruHeIj 0WQewygzRWnGBIk0kAiBNlW+R7maNZRJ6kjxdswDiw5BILxFcahdDD+87W4+sT4gFQT+ hZqOREAuHnW3ShkU4zz6INRJj7NhtY+uZXDnVrhujiO6bkz/Ob8Z6PM7Eyn15bBbqHyf iSD5nLepXxF+96tAFcCPNkZZnXAx5gODmt9faIYSDxpyFCs3QmQrAKl+o1KHkz8PTzCH BjG1UzdCW6IMn5SA42kublY9bRQ5rcFK1nPQYgzVUi3yCAHVyugoiXJ0tfnWcb2hrfI6 SAFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=w9idSx+0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:37 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/17] hw/arm/spitz: Implement inbound GPIO lines for bit5 and power signals Date: Sun, 28 Jun 2020 15:24:17 +0100 Message-Id: <20200628142429.17111-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently the Spitz board uses a nasty hack for the GPIO lines that pass "bit5" and "power" information to the LCD controller: the lcdtg realize function sets a global variable to point to the instance it just realized, and then the functions spitz_bl_power() and spitz_bl_bit5() use that to find the device they are changing the internal state of. There is a comment reading: FIXME: Implement GPIO properly and remove this hack. which was added in 2009. Implement GPIO properly and remove this hack. Signed-off-by: Peter Maydell --- hw/arm/spitz.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) -- 2.20.1 Reviewed-by: Alistair Francis diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 69bc2b3fa10..11e413723f4 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -586,12 +586,9 @@ static void spitz_bl_update(SpitzLCDTG *s) zaurus_printf("LCD Backlight now off\n"); } -/* FIXME: Implement GPIO properly and remove this hack. */ -static SpitzLCDTG *spitz_lcdtg; - static inline void spitz_bl_bit5(void *opaque, int line, int level) { - SpitzLCDTG *s = spitz_lcdtg; + SpitzLCDTG *s = opaque; int prev = s->bl_intensity; if (level) @@ -605,7 +602,7 @@ static inline void spitz_bl_bit5(void *opaque, int line, int level) static inline void spitz_bl_power(void *opaque, int line, int level) { - SpitzLCDTG *s = spitz_lcdtg; + SpitzLCDTG *s = opaque; s->bl_power = !!level; spitz_bl_update(s); } @@ -639,13 +636,16 @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value) return 0; } -static void spitz_lcdtg_realize(SSISlave *dev, Error **errp) +static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp) { - SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev); + SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi); + DeviceState *dev = DEVICE(s); - spitz_lcdtg = s; s->bl_power = 0; s->bl_intensity = 0x20; + + qdev_init_gpio_in_named(dev, spitz_bl_bit5, "bl_bit5", 1); + qdev_init_gpio_in_named(dev, spitz_bl_power, "bl_power", 1); } /* SSP devices */ @@ -820,15 +820,11 @@ static void spitz_out_switch(void *opaque, int line, int level) case 3: zaurus_printf("Orange LED %s.\n", level ? "on" : "off"); break; - case 4: - spitz_bl_bit5(opaque, line, level); - break; - case 5: - spitz_bl_power(opaque, line, level); - break; case 6: spitz_adc_temp_on(opaque, line, level); break; + default: + g_assert_not_reached(); } } @@ -858,9 +854,9 @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms) if (sms->scp1) { qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT, - outsignals[4]); + qdev_get_gpio_in_named(sms->lcdtg, "bl_bit5", 0)); qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON, - outsignals[5]); + qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0)); } qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); From patchwork Sun Jun 28 14:24:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 191968 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2137419ilg; Sun, 28 Jun 2020 07:29:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwWsX9onhSpt+1YWQP3s1wJf0EZq77JBoX3kB6N6d30yAeFuPpxEJfOVFsKJiTd/GJjfWma X-Received: by 2002:a25:dc0a:: with SMTP id y10mr11518207ybe.223.1593354556994; Sun, 28 Jun 2020 07:29:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593354556; cv=none; d=google.com; s=arc-20160816; b=HsInTohEOupLsOYgYObeEnQ4VXLqnVi1+U7CY9WHg0u1IYamOZbItH9xcSQvHNbSyT W7hPGnK7yt+dLVo/oDScLSePAZsQ+WIkkMVq2hb8tVQX19jNBUZOYLinRg/Cz8YZwUE5 qR/qt5S5h8T/gXTGCLqPhptm5Revbs6DUa10wDZ2TfLP7+17ayBYtJ+qNSq8ebqGsuMZ fh5OzuDLQ+IK78OidkRcRT12/llLhZVDpkYrzip8ibKRnu4OfbVbXMh1Iv4hWLGOZvKW AiF49z1qCj1WNgXuZyIJQ3GZWO1k3zqs13acjvrD3IThEJIVbfJ02Cn+XOFiDIBPMhs7 0GHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ysv1uk4fUAcPUnh8atox5ci4JG0ni1jWyD3+T3R5UZg=; b=0oAnhYFAppN1y9VU69JV0vQ+LUzOwzXZl1Ext3cPEqk1oaNV2pxeltJT78Yu9mrTyn XyIG1lC1icSYCYXDZXw2lcRboUdmGv8ctAnTyoPSxbGgYit1pAdF4QAsU5Dk46vDxeAC eN4HJmDxohGNkOYjp7TvxBvA73sW70wDVfOp/JqBKqYgYKfse5OXE8DVBgd8kcHffev5 oaR8FUdyen64R3msXormY46b6Mjivt4jklLMcQkHv8gMOUpPg9AnK8exRfEHQaWKPYxF PzyMW8inqh40k7Racq4N9tIBLhCLDY/8RchPK56K7pvrvdz3Ai9tPHPvDHy5/P1yx7je Iedg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eaNfHj38; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:38 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/17] hw/misc/max111x: provide QOM properties for setting initial values Date: Sun, 28 Jun 2020 15:24:18 +0100 Message-Id: <20200628142429.17111-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add some QOM properties to the max111x ADC device to allow the initial values to be configured. Currently this is done by board code calling max111x_set_input() after it creates the device, which doesn't work on system reset. This requires us to implement a reset method for this device, so while we're doing that make sure we reset the other parts of the device state. Signed-off-by: Peter Maydell --- hw/misc/max111x.c | 57 ++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 47 insertions(+), 10 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c index 2b87bdee5b7..d0e5534e4f5 100644 --- a/hw/misc/max111x.c +++ b/hw/misc/max111x.c @@ -15,11 +15,15 @@ #include "hw/ssi/ssi.h" #include "migration/vmstate.h" #include "qemu/module.h" +#include "hw/qdev-properties.h" typedef struct { SSISlave parent_obj; qemu_irq interrupt; + /* Values of inputs at system reset (settable by QOM property) */ + uint8_t reset_input[8]; + uint8_t tb1, rb2, rb3; int cycle; @@ -135,16 +139,6 @@ static int max111x_init(SSISlave *d, int inputs) qdev_init_gpio_out(dev, &s->interrupt, 1); s->inputs = inputs; - /* TODO: add a user interface for setting these */ - s->input[0] = 0xf0; - s->input[1] = 0xe0; - s->input[2] = 0xd0; - s->input[3] = 0xc0; - s->input[4] = 0xb0; - s->input[5] = 0xa0; - s->input[6] = 0x90; - s->input[7] = 0x80; - s->com = 0; vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY, &vmstate_max111x, s); @@ -168,11 +162,50 @@ void max111x_set_input(DeviceState *dev, int line, uint8_t value) s->input[line] = value; } +static void max111x_reset(DeviceState *dev) +{ + MAX111xState *s = MAX_111X(dev); + int i; + + for (i = 0; i < s->inputs; i++) { + s->input[i] = s->reset_input[i]; + } + s->com = 0; + s->tb1 = 0; + s->rb2 = 0; + s->rb3 = 0; + s->cycle = 0; +} + +static Property max1110_properties[] = { + /* Reset values for ADC inputs */ + DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0), + DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0), + DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0), + DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0), + DEFINE_PROP_END_OF_LIST(), +}; + +static Property max1111_properties[] = { + /* Reset values for ADC inputs */ + DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0), + DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0), + DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0), + DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0), + DEFINE_PROP_UINT8("input4", MAX111xState, reset_input[4], 0xb0), + DEFINE_PROP_UINT8("input5", MAX111xState, reset_input[5], 0xa0), + DEFINE_PROP_UINT8("input6", MAX111xState, reset_input[6], 0x90), + DEFINE_PROP_UINT8("input7", MAX111xState, reset_input[7], 0x80), + DEFINE_PROP_END_OF_LIST(), +}; + static void max111x_class_init(ObjectClass *klass, void *data) { SSISlaveClass *k = SSI_SLAVE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); k->transfer = max111x_transfer; + dc->reset = max111x_reset; } static const TypeInfo max111x_info = { @@ -186,8 +219,10 @@ static const TypeInfo max111x_info = { static void max1110_class_init(ObjectClass *klass, void *data) { SSISlaveClass *k = SSI_SLAVE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); k->realize = max1110_realize; + device_class_set_props(dc, max1110_properties); } static const TypeInfo max1110_info = { @@ -199,8 +234,10 @@ static const TypeInfo max1110_info = { static void max1111_class_init(ObjectClass *klass, void *data) { SSISlaveClass *k = SSI_SLAVE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); k->realize = max1111_realize; + device_class_set_props(dc, max1111_properties); } static const TypeInfo max1111_info = { From patchwork Sun Jun 28 14:24:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 191962 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2135718ilg; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:39 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 07/17] hw/misc/max111x: Don't use vmstate_register() Date: Sun, 28 Jun 2020 15:24:19 +0100 Message-Id: <20200628142429.17111-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The max111x is a proper qdev device; we can use dc->vmsd rather than directly calling vmstate_register(). It's possible that this is a migration compat break, but the only boards that use this device are the spitz-family ('akita', 'borzoi', 'spitz', 'terrier'). Signed-off-by: Peter Maydell --- hw/misc/max111x.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c index d0e5534e4f5..abddfa3c660 100644 --- a/hw/misc/max111x.c +++ b/hw/misc/max111x.c @@ -140,8 +140,6 @@ static int max111x_init(SSISlave *d, int inputs) s->inputs = inputs; - vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY, - &vmstate_max111x, s); return 0; } @@ -206,6 +204,7 @@ static void max111x_class_init(ObjectClass *klass, void *data) k->transfer = max111x_transfer; dc->reset = max111x_reset; + dc->vmsd = &vmstate_max111x; } static const TypeInfo max111x_info = { From patchwork Sun Jun 28 14:24:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 191966 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2136790ilg; Sun, 28 Jun 2020 07:28:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzHPdv2aP5biHffIzmB1hexjAw/N8zxYot3f221fiv++XniNnPyKzJYfs47oA37DESg7x5N X-Received: by 2002:a25:2d4c:: with SMTP id s12mr18666592ybe.307.1593354489849; Sun, 28 Jun 2020 07:28:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593354489; cv=none; d=google.com; s=arc-20160816; b=Tf3HV2oP6I3qjquRUTjnB2JPCXiuNHs3R6eO2TOPIYuvhhrs2ZjOUqrwoNG4y1oTU9 ziCB1e8DHLdL6XxScmYEolZybvDTXz4CYNfCphO29TioC4RBj8XjF7dTF+yJ1nc9ctnM /i6NOYGbBAMkrkatD2erbEkoub/XgvHdeBPV4QuX4fb68hfMdBAAXXGYsCgXxjYB60lZ Y5la0r374m/fyYtG6LVPmgsl6U375RfdqTktAQa+J/zBp1QhoGhIH8VD8FSZcbAgBOTl PS2qo/PlvEoyAFM0/MnroJvgGOB35AueDGf1t01Ug6NRN2lt5BaNfQqyQPQ1Qffu0l3P 2Itw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QBXoGJBUT/9dmeWjNdX79gBYw0pAnLWbE1PUY4IQSc0=; b=HP3EPxo/veIJ3LswKXAmnQqhWzxWqxV+Qnv6H3SA2NCORtl+DsIoQQiHBgOuWwJqul hWqlYEhQLWZEHIiNk9u1UhB2souCHfRzV1cCZeit7ALRNcuh7cetLh8v/yrUzduWNZ61 Y8ZkrvPYW0VW8kbmh4xI/u2RptYapKj/R0NFHFwL4g7WxD6lQYB0vXyn7CihdvAzaKkl cGTFnEZObtpEj8pgYu/MzkJRZXvZZFLwmRvNkBmuABq7eU84EPCK3J/onf9C1+iEvam1 4V2peoYwwfIsGATJptgzTXQkWHm2imVwKydImAWfsGrDZNLoAHu3s63hyR9nmURIFRlU W31Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=iMo5t55+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:40 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/17] ssi: Add ssi_realize_and_unref() Date: Sun, 28 Jun 2020 15:24:20 +0100 Message-Id: <20200628142429.17111-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add an ssi_realize_and_unref(), for the benefit of callers who want to be able to create an SSI device, set QOM properties on it, and then do the realize-and-unref afterwards. The API works on the same principle as the recently added qdev_realize_and_undef(), sysbus_realize_and_undef(), etc. Signed-off-by: Peter Maydell --- include/hw/ssi/ssi.h | 26 ++++++++++++++++++++++++++ hw/ssi/ssi.c | 7 ++++++- 2 files changed, 32 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h index 93f2b8b0beb..4be5325e654 100644 --- a/include/hw/ssi/ssi.h +++ b/include/hw/ssi/ssi.h @@ -79,6 +79,32 @@ extern const VMStateDescription vmstate_ssi_slave; } DeviceState *ssi_create_slave(SSIBus *bus, const char *name); +/** + * ssi_realize_and_unref: realize and unref an SSI slave device + * @dev: SSI slave device to realize + * @bus: SSI bus to put it on + * @errp: error pointer + * + * Call 'realize' on @dev, put it on the specified @bus, and drop the + * reference to it. Errors are reported via @errp and by returning + * false. + * + * This function is useful if you have created @dev via qdev_new() + * (which takes a reference to the device it returns to you), so that + * you can set properties on it before realizing it. If you don't need + * to set properties then ssi_create_slave() is probably better (as it + * does the create, init and realize in one step). + * + * If you are embedding the SSI slave into another QOM device and + * initialized it via some variant on object_initialize_child() then + * do not use this function, because that family of functions arrange + * for the only reference to the child device to be held by the parent + * via the child<> property, and so the reference-count-drop done here + * would be incorrect. (Instead you would want ssi_realize(), which + * doesn't currently exist but would be trivial to create if we had + * any code that wanted it.) + */ +bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp); /* Master interface. */ SSIBus *ssi_create_bus(DeviceState *parent, const char *name); diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c index 67b48c31cd6..a35d7ebb266 100644 --- a/hw/ssi/ssi.c +++ b/hw/ssi/ssi.c @@ -90,11 +90,16 @@ static const TypeInfo ssi_slave_info = { .abstract = true, }; +bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp) +{ + return qdev_realize_and_unref(dev, &bus->parent_obj, errp); +} + DeviceState *ssi_create_slave(SSIBus *bus, const char *name) { DeviceState *dev = qdev_new(name); - qdev_realize_and_unref(dev, &bus->parent_obj, &error_fatal); + ssi_realize_and_unref(dev, bus, &error_fatal); return dev; } From patchwork Sun Jun 28 14:24:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 191969 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2137554ilg; Sun, 28 Jun 2020 07:29:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxTWYAWHMJaEs9NiXGOPZPoCgjq1BDmMa4fr5SSoqscOoi9yJcDdKyEyalTJRKdEptDMU9O X-Received: by 2002:a25:3f87:: with SMTP id m129mr20390328yba.371.1593354570984; Sun, 28 Jun 2020 07:29:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593354570; cv=none; d=google.com; s=arc-20160816; b=xeMDYIBLVQmc1kEOYmqhdaM2rMgOMS80iu6P1XN1tDvr6LYsE/wbZuPkL3JrWvPBL1 GA7hFry4sdNbZTrwrsPgaxI5Ez8OUe3FXhVCK3FvYT+3+C2/JFmUlfkmDW1dxsAn07QJ f55zAKa+bnrlEvTz32wbPOlmJDijc4+HEUPrEf0DDCRBVfi5dlnOh2fqMqFEGOW0UShM 2H3Cmk8BVBar/Fyz1OuL/Qb2OpeOtjDHoFJwLieq8ZjHixZXhI5V7CA/tSc/7o/uIt24 0JMgoIcsHR0XeqrCfkQ3A52pyJ+AEPZyemEOJ1X+8FeuVccUJrTvrEJgXNv/ejPNa4y1 VaZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SgwIMScr/FIQnW8BnMJTzdrdEBtyQPvg038hPjzvKgw=; b=cGmGD5pORtT6iAFucaHn78lDob81jBIGD+sJ8K257H5gLrqS2194IUloDWZzJAdkKI 9fK+TAMrS6LnoloAO3cvF4QgbL2Q+voxAmWjsjglCtMnp3gv4stA/mwv5OpiSuD5x+k2 mnlTU2k78ZrQLEwrMoccnqtA7VIjmq9J5UG1xC3ruPjvkA4jzRCyiruOkrJCdtxp4/wl hPaX9MeqlmadGfRZ4xOD+vAOqBeUgt11oQRySZ9lWBehHCFGXtrpIcd0XZ8xSZToxa5m Rj5V0x7YdFolz5ykwu5n2S47qHdCpPCa5eaunLR5HnqiXeVEEORXCLsO9/pIvp3S1lao XxgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DmLjHksG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 136si32360179ybf.378.2020.06.28.07.29.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 28 Jun 2020 07:29:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DmLjHksG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34578 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jpYJG-0005y8-F5 for patch@linaro.org; Sun, 28 Jun 2020 10:29:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38422) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jpYEh-0006HT-2u for qemu-devel@nongnu.org; Sun, 28 Jun 2020 10:24:47 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:42803) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jpYEd-0004iv-VQ for qemu-devel@nongnu.org; Sun, 28 Jun 2020 10:24:46 -0400 Received: by mail-wr1-x442.google.com with SMTP id o11so14033388wrv.9 for ; Sun, 28 Jun 2020 07:24:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SgwIMScr/FIQnW8BnMJTzdrdEBtyQPvg038hPjzvKgw=; b=DmLjHksG4vO/ptD6HFqYBPrTo4WYlILaUNvZcw+idizCY/oRkwwWVZ4RghhTBfHnW2 fo6lP9TJ7mBzXlJJNYGAdW/r+ZmxDJ02iASOvfUy+tZ0DixaAc9afnqGMU+3KzDu+klk kYNr0hbinaRIvohzRWrJRSY4cZDKjv07YsE/Qi/GZLE4mlgj2Gz3Q0ZHtPgnXqTbhyyZ nietcuGRTi9bo37Ts98fdLL2fp5BKm25s9NLS8RxLPHjykAfjCs6N3YrMhKcKTPwplI3 gPFtHbCGHX1MW9XRZ9QAN0L3wIBFtMTd413vNabXYI5pOZuEdc0B+rxWz8NraEooGYwL 7k5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SgwIMScr/FIQnW8BnMJTzdrdEBtyQPvg038hPjzvKgw=; b=HpcT59+uWjS8HMb8gTzFRvs2gVkEuDyuph0X9GF8GfSORAdBee4Us4ElQ0huKXikAT nH8d4YdNvdmOp5KCRgvtoApx6lQMgctAnD3MhM+QrFmCx+1DY6+w6ubXLoDLPizIVQHC q6pSy7xA6rtw8YwJ/UAxbdm2fEIOHogrGSkbYmwS8l3tZxnSVgdW39rJNEM2AL3/ZUXh 5xSvh3L+Fr7t8MFD9OKyLi3yrxi/Qs6O+r52/GkzjRFl7UPoLPdO9AsHZGDTGMNSHxKo X3+t5I7yIkQrvpXBInrpLmueCAPm0Qo05+ySe4xeePdbUEWyDR2tLx+Z57qSx+1mjToE vIvw== X-Gm-Message-State: AOAM532wsA/tLnWDfLu5eheQsLSeqX9xcIddmYPJ7dqQRPJeAfvOWWTx uBT5wOyRkTdJ9qJ+0wdsr+GxEQ== X-Received: by 2002:adf:f38f:: with SMTP id m15mr11548083wro.173.1593354282790; Sun, 28 Jun 2020 07:24:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:42 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/17] hw/arm/spitz: Use max111x properties to set initial values Date: Sun, 28 Jun 2020 15:24:21 +0100 Message-Id: <20200628142429.17111-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the new max111x qdev properties to set the initial input values rather than calling max111x_set_input(); this means that on system reset the inputs will correctly return to their initial values. Signed-off-by: Peter Maydell --- hw/arm/spitz.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 11e413723f4..93a25edcb5b 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -731,11 +731,14 @@ static void spitz_ssp_attach(SpitzMachineState *sms) qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT)); bus = qdev_get_child_bus(sms->mux, "ssi2"); - sms->max1111 = ssi_create_slave(bus, "max1111"); + sms->max1111 = qdev_new("max1111"); max1111 = sms->max1111; - max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT); - max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0); - max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN); + qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */, + SPITZ_BATTERY_VOLT); + qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0); + qdev_prop_set_uint8(sms->max1111, "input3" /* ACIN_VOLT */, + SPITZ_CHARGEON_ACIN); + ssi_realize_and_unref(sms->max1111, bus, &error_fatal); qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS, qdev_get_gpio_in(sms->mux, 0)); From patchwork Sun Jun 28 14:24:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 191964 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2136478ilg; Sun, 28 Jun 2020 07:27:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw8r1QBYDS8H0w8hTUiWDCF6pliBxFnUEWC/XRlsD8MfSAERizixyjYgjj/Ut1OOV0mEAnz X-Received: by 2002:a25:428c:: with SMTP id p134mr21085211yba.467.1593354451982; Sun, 28 Jun 2020 07:27:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593354451; cv=none; d=google.com; s=arc-20160816; b=B75mhWrlygfbs7ynM+JAvsRdw6fCBzDSiHPepX8oEKlrRnkiyqaZCmFyjpYy+CHXta gueXEv6F6y9XEwEQU5QGimw1T4hO7M/yRe+jwL2tAlX28Tu0rWl65f43D6syLVdur41G LMpiWjDrb7kdOok7gW1Z122Na0bEkxhsceWbdzHqc4c6dxkPdpo2h4MOv5rh9Weq5aSK XHUz0j+VLYGcmR98Zqc3sy5RYxb2LfJq9iP8+hdAT5shx8+FUMQHd+znDACxL2PqFoXK yDRJEZv3oxROKXAIbOw4+iaQwendmAtLwLfFm8ZYPOsOGbHqdaNpTKksAPNCrb504WBV ucVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=2DdwiLV6b1TNMiDc5ffJEq+J0urqTVL76KQisyKN10I=; b=LcKkWkiu5fexUVVCZnwVr7bR/iblpLFbVEXZ1ckicH12pKcmJfLaiTjXBi5wnVQKXH SAj0WKhFInGqGcUNWwPLoebIVYo1W4BtkYEL8P672QzzsJ4VnMsgahm7VyIbi1KbfmK/ 9LOMAbQZ57/z6v3J819M+X9oavWz7caDxxOzAYPPNGNwqV42F72OOUWnnGCjjgabI+gC kOzx8KL6jITIPuVvHFX3eJL139/UjocimPjzTh7zceU5yMJlYqrQDabTYdTbNjo0Oqlk 1yDQgK6SgJG+71ocjb3yGRSumQCg41jiibKOGfiJz46fkaecP9rOl7Su+iJ0VTsc8YHD 9f4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jbeQVPCj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:43 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/17] hw/misc/max111x: Use GPIO lines rather than max111x_set_input() Date: Sun, 28 Jun 2020 15:24:22 +0100 Message-Id: <20200628142429.17111-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The max111x ADC device model allows other code to set the level on the 8 ADC inputs using the max111x_set_input() function. Replace this with generic qdev GPIO inputs, which also allow inputs to be set to arbitrary values. Using GPIO lines will make it easier for board code to wire things up, so that if device A wants to set the ADC input it doesn't need to have a direct pointer to the max111x but can just set that value on its output GPIO, which is then wired up by the board to the appropriate max111x input. Signed-off-by: Peter Maydell --- include/hw/ssi/ssi.h | 3 --- hw/arm/spitz.c | 9 +++++---- hw/misc/max111x.c | 16 +++++++++------- 3 files changed, 14 insertions(+), 14 deletions(-) -- 2.20.1 Reviewed-by: Alistair Francis diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h index 4be5325e654..5fd411f2e4e 100644 --- a/include/hw/ssi/ssi.h +++ b/include/hw/ssi/ssi.h @@ -111,7 +111,4 @@ SSIBus *ssi_create_bus(DeviceState *parent, const char *name); uint32_t ssi_transfer(SSIBus *bus, uint32_t val); -/* max111x.c */ -void max111x_set_input(DeviceState *dev, int line, uint8_t value); - #endif diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 93a25edcb5b..fa592aad6d6 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -696,13 +696,14 @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level) static void spitz_adc_temp_on(void *opaque, int line, int level) { + int batt_temp; + if (!max1111) return; - if (level) - max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP); - else - max111x_set_input(max1111, MAX1111_BATT_TEMP, 0); + batt_temp = level ? SPITZ_BATTERY_TEMP : 0; + + qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp); } static void corgi_ssp_realize(SSISlave *d, Error **errp) diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c index abddfa3c660..3a5cb838445 100644 --- a/hw/misc/max111x.c +++ b/hw/misc/max111x.c @@ -131,12 +131,21 @@ static const VMStateDescription vmstate_max111x = { } }; +static void max111x_input_set(void *opaque, int line, int value) +{ + MAX111xState *s = MAX_111X(opaque); + + assert(line >= 0 && line < s->inputs); + s->input[line] = value; +} + static int max111x_init(SSISlave *d, int inputs) { DeviceState *dev = DEVICE(d); MAX111xState *s = MAX_111X(dev); qdev_init_gpio_out(dev, &s->interrupt, 1); + qdev_init_gpio_in(dev, max111x_input_set, inputs); s->inputs = inputs; @@ -153,13 +162,6 @@ static void max1111_realize(SSISlave *dev, Error **errp) max111x_init(dev, 4); } -void max111x_set_input(DeviceState *dev, int line, uint8_t value) -{ - MAX111xState *s = MAX_111X(dev); - assert(line >= 0 && line < s->inputs); - s->input[line] = value; -} - static void max111x_reset(DeviceState *dev) { MAX111xState *s = MAX_111X(dev); From patchwork Sun Jun 28 14:24:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 191971 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2138972ilg; Sun, 28 Jun 2020 07:31:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyql/jdD3vTixaEPBbT3t91gOfXMmCjHCT29tNmq+8Uth8S/CA5Z78U9t3SoBhUiCFuWhBb X-Received: by 2002:a25:3752:: with SMTP id e79mr14040792yba.263.1593354707037; Sun, 28 Jun 2020 07:31:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593354707; cv=none; d=google.com; s=arc-20160816; b=w9buHQELdxDCBHIkiloC9OXFCKJtV120+Lsi/WS1omw2uZaZ/G4BwMeRMEvGhDnrXu SmpycSw8QLjbQnENNymhsjvW7VpunLtWFiMpJt1aoU3875AcVtcfr5qV9agXr8XfeRid LV1cRbx+2udvRpfIY75ggF27aemQZMqCjPF+tX5zLRAaVcdOOXwJP6h9Ad5w7r099wqY HNmk0PgMG51PIt6/7+t1e42W3yZYdqmbjxC52XDl901Pqt9wGI1+LiNLKb/AjGundHLj 9pWQFaAQsgaiaJK1mmhTNDcsCiXeVoB4iryV6iUtoKoLxxIn4Gk6XnwF0x6teZzPKoux PmGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WciP4YXlhY7aEQRA6uEhlFST0m8DbBOd0N16ZxZywy0=; b=oHcOSAZ3fDSw4oBnl5QsRkacWaU5hI5xMmL9mGVkhlS9mj/mfyq4DsLxvszRP0Fiop 9RDSegVj6OMiGwLNGjd58JogrJj0gc8gM2zbZcE4DJDPSpTsYSsO6nVVWZX0Ls1L8F9Q 0OyGSLHOvJ2aZ9J+QTyyDAmGFALPnkt68HoThx4V4kk+JxoUdKCi0MeNa2Y3T1qD7viC PTVWcdw7KxQ4/tXkUELGXJgsQs4P7qtGg81YRunlFOKTxq0DY4q1gWb34aFxTj/hz2GE izBMJ/+3ESwPiQ237MKe1XigMNvNkev3qFqrZESzxHjq6bOaator3qrKTTuVK5pYkugR 3A2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=qsX2bKMn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:44 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/17] hw/misc/max111x: Create header file for documentation, TYPE_ macros Date: Sun, 28 Jun 2020 15:24:23 +0100 Message-Id: <20200628142429.17111-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a header file for the hw/misc/max111x device, in the usual modern style for QOM devices: * definition of the TYPE_ constants and macros * definition of the device's state struct so that it can be embedded in other structs if desired * documentation of the interface This allows us to use TYPE_MAX_1111 in the spitz.c code rather than the string "max1111". Signed-off-by: Peter Maydell --- To be honest the main driver here is that I wanted a header file to put the documentation comment in :-) --- include/hw/misc/max111x.h | 57 +++++++++++++++++++++++++++++++++++++++ hw/arm/spitz.c | 3 ++- hw/misc/max111x.c | 25 +---------------- MAINTAINERS | 1 + 4 files changed, 61 insertions(+), 25 deletions(-) create mode 100644 include/hw/misc/max111x.h -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/hw/misc/max111x.h b/include/hw/misc/max111x.h new file mode 100644 index 00000000000..337ba63d588 --- /dev/null +++ b/include/hw/misc/max111x.h @@ -0,0 +1,57 @@ +/* + * Maxim MAX1110/1111 ADC chip emulation. + * + * Copyright (c) 2006 Openedhand Ltd. + * Written by Andrzej Zaborowski + * + * This code is licensed under the GNU GPLv2. + * + * Contributions after 2012-01-13 are licensed under the terms of the + * GNU GPL, version 2 or (at your option) any later version. + */ + +#ifndef HW_MISC_MAX111X_H +#define HW_MISC_MAX111X_H + +#include "hw/ssi/ssi.h" +#include "hw/irq.h" + +/* + * This is a model of the Maxim MAX1110/1111 ADC chip, which for QEMU + * is an SSI slave device. It has either 4 (max1110) or 8 (max1111) + * 8-bit ADC channels. + * + * QEMU interface: + * + GPIO inputs 0..3 (for max1110) or 0..7 (for max1111): set the value + * of each ADC input, as an unsigned 8-bit value + * + GPIO output 0: interrupt line + * + Properties "input0" to "input3" (max1110) or "input0" to "input7" + * (max1111): initial reset values for ADC inputs. + * + * Known bugs: + * + the interrupt line is not correctly implemented, and will never + * be lowered once it has been asserted. + */ +typedef struct { + SSISlave parent_obj; + + qemu_irq interrupt; + /* Values of inputs at system reset (settable by QOM property) */ + uint8_t reset_input[8]; + + uint8_t tb1, rb2, rb3; + int cycle; + + uint8_t input[8]; + int inputs, com; +} MAX111xState; + +#define TYPE_MAX_111X "max111x" + +#define MAX_111X(obj) \ + OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X) + +#define TYPE_MAX_1110 "max1110" +#define TYPE_MAX_1111 "max1111" + +#endif diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index fa592aad6d6..1400a56729d 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -29,6 +29,7 @@ #include "audio/audio.h" #include "hw/boards.h" #include "hw/sysbus.h" +#include "hw/misc/max111x.h" #include "migration/vmstate.h" #include "exec/address-spaces.h" #include "cpu.h" @@ -732,7 +733,7 @@ static void spitz_ssp_attach(SpitzMachineState *sms) qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT)); bus = qdev_get_child_bus(sms->mux, "ssi2"); - sms->max1111 = qdev_new("max1111"); + sms->max1111 = qdev_new(TYPE_MAX_1111); max1111 = sms->max1111; qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */, SPITZ_BATTERY_VOLT); diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c index 3a5cb838445..d41cfd92a8d 100644 --- a/hw/misc/max111x.c +++ b/hw/misc/max111x.c @@ -11,34 +11,11 @@ */ #include "qemu/osdep.h" -#include "hw/irq.h" -#include "hw/ssi/ssi.h" +#include "hw/misc/max111x.h" #include "migration/vmstate.h" #include "qemu/module.h" #include "hw/qdev-properties.h" -typedef struct { - SSISlave parent_obj; - - qemu_irq interrupt; - /* Values of inputs at system reset (settable by QOM property) */ - uint8_t reset_input[8]; - - uint8_t tb1, rb2, rb3; - int cycle; - - uint8_t input[8]; - int inputs, com; -} MAX111xState; - -#define TYPE_MAX_111X "max111x" - -#define MAX_111X(obj) \ - OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X) - -#define TYPE_MAX_1110 "max1110" -#define TYPE_MAX_1111 "max1111" - /* Control-byte bitfields */ #define CB_PD0 (1 << 0) #define CB_PD1 (1 << 1) diff --git a/MAINTAINERS b/MAINTAINERS index 1b40446c739..550844d1514 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -787,6 +787,7 @@ F: hw/gpio/max7310.c F: hw/gpio/zaurus.c F: hw/misc/mst_fpga.c F: hw/misc/max111x.c +F: include/hw/misc/max111x.h F: include/hw/arm/pxa.h F: include/hw/arm/sharpsl.h F: include/hw/display/tc6393xb.h From patchwork Sun Jun 28 14:24:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 191972 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2140134ilg; Sun, 28 Jun 2020 07:33:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyhHW1k9gPsaOOgw/EQ19rJS5HsoCbbfxCPhlOq+5wP9H+ns2MDK63wuVWAP2m7kCrQ8njA X-Received: by 2002:a5b:48f:: with SMTP id n15mr10655500ybp.115.1593354812042; Sun, 28 Jun 2020 07:33:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593354812; cv=none; d=google.com; s=arc-20160816; b=X6f7sZhRtoz2XH111XLODqTQKTpeiUj6oicKx9mP5Bmf1zkyW46/WJzxXAj61cJgaY uafVaw7bGguDQSKvvEQbUQXHqXEQazA9NALtK56xRciVPKaPQbgld4RNtm4B73f7E9ky XC5x3OGIkYRB40cBsSEUj+w1qXfdS6ipa2NwyYT70c0c9OwRcQj61dHdGH1Rfk9rpK18 BST0IymJo8vkosDM2uWti3/RIgzkHYToaSxgX6dY9TLemJnbOFZ0gqV1pE784G8YOE6m YB+awOL9mkSCtA5FsgCZjhiVKAtZ7JSKXoAu6YvhVl98zL9XiDOzZ6LtA15hVIw6SCH1 UfXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=f9cb+FEDC8NDU7u9+mTpSdy4O/EQL4qnuAeS5rgyprA=; b=iaXGkOLZI6Mk0yp3+928mZQ2t97Al8qFZcrnvM87eL1+w6lk0dH8nRNh5R/kR4LA/p mEqgr8nTFpFNwtQTCj7hUMn+EFvJ0oFXJcL/lM4tMtkIjCcuet6i4qfSp17Cn7LRiEzM Qa2k+HBPntjOdq1f63DsDeirzddG5MFc8dBMlO6Nr7+xC8xFb7KqX+gngvQyz/iQ06RE PE9WGMcK6drcJHLuswRWxn0MYzP7MI5ryjXX60Q+vlgrL/NhIHuNFAXaQ3ti37MiVNyF Wh7BhDt4y6vTx19Uq4vFeiXegkUS8CnAvX6oKNhe2NnpiWipQ/zAzwd34VxWgxjm85CV xQYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GCUVfe7m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:45 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 12/17] hw/arm/spitz: Encapsulate misc GPIO handling in a device Date: Sun, 28 Jun 2020 15:24:24 +0100 Message-Id: <20200628142429.17111-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently we have a free-floating set of IRQs and a function spitz_out_switch() which handle some miscellaneous GPIO lines for the spitz board. Encapsulate this behaviour in a simple QOM device. At this point we can finally remove the 'max1111' global, because the ADC battery-temperature value is now handled by the misc-gpio device writing the value to its outbound "adc-temp" GPIO, which the board code wires up to the appropriate inbound GPIO line on the max1111. This commit also fixes Coverity issue CID 1421913 (which pointed out that the 'outsignals' in spitz_scoop_gpio_setup() were leaked), because it removes the use of the qemu_allocate_irqs() API from this code entirely. Signed-off-by: Peter Maydell --- hw/arm/spitz.c | 129 +++++++++++++++++++++++++++++++++---------------- 1 file changed, 87 insertions(+), 42 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 1400a56729d..bab9968ccee 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -51,6 +51,7 @@ typedef struct { DeviceState *max1111; DeviceState *scp0; DeviceState *scp1; + DeviceState *misc_gpio; } SpitzMachineState; #define TYPE_SPITZ_MACHINE "spitz-common" @@ -658,8 +659,6 @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp) #define SPITZ_GPIO_MAX1111_CS 20 #define SPITZ_GPIO_TP_INT 11 -static DeviceState *max1111; - /* "Demux" the signal based on current chipselect */ typedef struct { SSISlave ssidev; @@ -695,18 +694,6 @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level) #define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */ #define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */ -static void spitz_adc_temp_on(void *opaque, int line, int level) -{ - int batt_temp; - - if (!max1111) - return; - - batt_temp = level ? SPITZ_BATTERY_TEMP : 0; - - qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp); -} - static void corgi_ssp_realize(SSISlave *d, Error **errp) { DeviceState *dev = DEVICE(d); @@ -734,7 +721,6 @@ static void spitz_ssp_attach(SpitzMachineState *sms) bus = qdev_get_child_bus(sms->mux, "ssi2"); sms->max1111 = qdev_new(TYPE_MAX_1111); - max1111 = sms->max1111; qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */, SPITZ_BATTERY_VOLT); qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0); @@ -810,27 +796,66 @@ static void spitz_akita_i2c_setup(PXA2xxState *cpu) /* Other peripherals */ -static void spitz_out_switch(void *opaque, int line, int level) +/* + * Encapsulation of some miscellaneous GPIO line behaviour for the Spitz boards. + * + * QEMU interface: + * + named GPIO inputs "green-led", "orange-led", "charging", "discharging": + * these currently just print messages that the line has been signalled + * + named GPIO input "adc-temp-on": set to cause the battery-temperature + * value to be passed to the max111x ADC + * + named GPIO output "adc-temp": the ADC value, to be wired up to the max111x + */ +#define TYPE_SPITZ_MISC_GPIO "spitz-misc-gpio" +#define SPITZ_MISC_GPIO(obj) \ + OBJECT_CHECK(SpitzMiscGPIOState, (obj), TYPE_SPITZ_MISC_GPIO) + +typedef struct SpitzMiscGPIOState { + SysBusDevice parent_obj; + + qemu_irq adc_value; +} SpitzMiscGPIOState; + +static void spitz_misc_charging(void *opaque, int n, int level) { - switch (line) { - case 0: - zaurus_printf("Charging %s.\n", level ? "off" : "on"); - break; - case 1: - zaurus_printf("Discharging %s.\n", level ? "on" : "off"); - break; - case 2: - zaurus_printf("Green LED %s.\n", level ? "on" : "off"); - break; - case 3: - zaurus_printf("Orange LED %s.\n", level ? "on" : "off"); - break; - case 6: - spitz_adc_temp_on(opaque, line, level); - break; - default: - g_assert_not_reached(); - } + zaurus_printf("Charging %s.\n", level ? "off" : "on"); +} + +static void spitz_misc_discharging(void *opaque, int n, int level) +{ + zaurus_printf("Discharging %s.\n", level ? "off" : "on"); +} + +static void spitz_misc_green_led(void *opaque, int n, int level) +{ + zaurus_printf("Green LED %s.\n", level ? "off" : "on"); +} + +static void spitz_misc_orange_led(void *opaque, int n, int level) +{ + zaurus_printf("Orange LED %s.\n", level ? "off" : "on"); +} + +static void spitz_misc_adc_temp(void *opaque, int n, int level) +{ + SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(opaque); + int batt_temp = level ? SPITZ_BATTERY_TEMP : 0; + + qemu_set_irq(s->adc_value, batt_temp); +} + +static void spitz_misc_gpio_init(Object *obj) +{ + SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(obj); + DeviceState *dev = DEVICE(obj); + + qdev_init_gpio_in_named(dev, spitz_misc_charging, "charging", 1); + qdev_init_gpio_in_named(dev, spitz_misc_discharging, "discharging", 1); + qdev_init_gpio_in_named(dev, spitz_misc_green_led, "green-led", 1); + qdev_init_gpio_in_named(dev, spitz_misc_orange_led, "orange-led", 1); + qdev_init_gpio_in_named(dev, spitz_misc_adc_temp, "adc-temp-on", 1); + + qdev_init_gpio_out_named(dev, &s->adc_value, "adc-temp", 1); } #define SPITZ_SCP_LED_GREEN 1 @@ -850,12 +875,22 @@ static void spitz_out_switch(void *opaque, int line, int level) static void spitz_scoop_gpio_setup(SpitzMachineState *sms) { - qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, sms->mpu, 8); + DeviceState *miscdev = sysbus_create_simple(TYPE_SPITZ_MISC_GPIO, -1, NULL); - qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, outsignals[0]); - qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, outsignals[1]); - qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, outsignals[2]); - qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]); + sms->misc_gpio = miscdev; + + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, + qdev_get_gpio_in_named(miscdev, "charging", 0)); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, + qdev_get_gpio_in_named(miscdev, "discharging", 0)); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, + qdev_get_gpio_in_named(miscdev, "green-led", 0)); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, + qdev_get_gpio_in_named(miscdev, "orange-led", 0)); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, + qdev_get_gpio_in_named(miscdev, "adc-temp-on", 0)); + qdev_connect_gpio_out_named(miscdev, "adc-temp", 0, + qdev_get_gpio_in(sms->max1111, MAX1111_BATT_TEMP)); if (sms->scp1) { qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT, @@ -863,8 +898,6 @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms) qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON, qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0)); } - - qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); } #define SPITZ_GPIO_HSYNC 22 @@ -1217,12 +1250,24 @@ static const TypeInfo spitz_lcdtg_info = { .class_init = spitz_lcdtg_class_init, }; +static const TypeInfo spitz_misc_gpio_info = { + .name = TYPE_SPITZ_MISC_GPIO, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SpitzMiscGPIOState), + .instance_init = spitz_misc_gpio_init, + /* + * No class_init required: device has no internal state so does not + * need to set up reset or vmstate, and does not have a realize method. + */ +}; + static void spitz_register_types(void) { type_register_static(&corgi_ssp_info); type_register_static(&spitz_lcdtg_info); type_register_static(&spitz_keyboard_info); type_register_static(&sl_nand_info); + type_register_static(&spitz_misc_gpio_info); } type_init(spitz_register_types) From patchwork Sun Jun 28 14:24:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 191974 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2140739ilg; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:47 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 13/17] hw/gpio/zaurus.c: Use LOG_GUEST_ERROR for bad guest register accesses Date: Sun, 28 Jun 2020 15:24:25 +0100 Message-Id: <20200628142429.17111-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Instead of logging guest accesses to invalid register offsets in this device using zaurus_printf() (which just prints to stderr), use the usual qemu_log_mask(LOG_GUEST_ERROR,...). Since this was the only use of the zaurus_printf() macro outside spitz.c, we can move the definition of that macro from sharpsl.h to spitz.c. Signed-off-by: Peter Maydell --- include/hw/arm/sharpsl.h | 3 --- hw/arm/spitz.c | 3 +++ hw/gpio/zaurus.c | 12 +++++++----- 3 files changed, 10 insertions(+), 8 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis diff --git a/include/hw/arm/sharpsl.h b/include/hw/arm/sharpsl.h index 89e168fbff3..e986b28c527 100644 --- a/include/hw/arm/sharpsl.h +++ b/include/hw/arm/sharpsl.h @@ -9,9 +9,6 @@ #include "exec/hwaddr.h" -#define zaurus_printf(format, ...) \ - fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__) - /* zaurus.c */ #define SL_PXA_PARAM_BASE 0xa0000a00 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index bab9968ccee..6eb46869157 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -62,6 +62,9 @@ typedef struct { #define SPITZ_MACHINE_CLASS(klass) \ OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE) +#define zaurus_printf(format, ...) \ + fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__) + #undef REG_FMT #define REG_FMT "0x%02lx" diff --git a/hw/gpio/zaurus.c b/hw/gpio/zaurus.c index 9a12c683420..258e9264930 100644 --- a/hw/gpio/zaurus.c +++ b/hw/gpio/zaurus.c @@ -22,9 +22,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "qemu/module.h" - -#undef REG_FMT -#define REG_FMT "0x%02lx" +#include "qemu/log.h" /* SCOOP devices */ @@ -104,7 +102,9 @@ static uint64_t scoop_read(void *opaque, hwaddr addr, case SCOOP_GPRR: return s->gpio_level; default: - zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); + qemu_log_mask(LOG_GUEST_ERROR, + "scoop_read: bad register offset 0x%02" HWADDR_PRIx "\n", + addr); } return 0; @@ -150,7 +150,9 @@ static void scoop_write(void *opaque, hwaddr addr, scoop_gpio_handler_update(s); break; default: - zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); + qemu_log_mask(LOG_GUEST_ERROR, + "scoop_write: bad register offset 0x%02" HWADDR_PRIx "\n", + addr); } } From patchwork Sun Jun 28 14:24:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 191973 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2140327ilg; Sun, 28 Jun 2020 07:33:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzIOBJJwoyc7XNYGOAGfnF/OH4ky/FA8+aaAybvjeh/joCyKGkibmSu5ErDTWxKEhbvnfsH X-Received: by 2002:a25:e68f:: with SMTP id d137mr20205976ybh.422.1593354832592; Sun, 28 Jun 2020 07:33:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593354832; cv=none; d=google.com; s=arc-20160816; b=GObuXsXbhHmsCkdyg9+SJA/oCDBKu9nziI7R39Z0sDRtF7Yz4rm49iKZHyFp7g3K+a hLO7lO/sYO6uVuHJ6wne3zdcgs3iGP2TSp/HALCUcyCA+148gQO3Znj4A7BE8re64/Fp 7cpzRMGZOqlJBNBYofVyBSLXWT14p2M4yMoug2ho12ur6rBIXdKVVhTOHGMm1IrfeElE 1xSUDbN1g6l+jMKcwxMztDKXY2AduPvYyud0HUHxk/S5drJO0SN4KIJWzxx3abJY0aC2 GSKTq7miTZnPfPpucOHp8ZOiDQvh7oEVnZPLemQSXhZlHBTV95p+ZzaNnlH4J3bl2Yqt uviQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dJ0W5rRE5YZi83vxM8j/ufJhgS7qKl+8QXLVWJzvwUI=; b=AfBkXJbY0XP9zDS7u0Z8sNv+jjUM57kQKsNYSD3URS0sF12vS8WeNFwZXrBoqvZG2O N4MTLfEVHx04ykeBuPL9o1sN9D9BpCwXa9DNFaVdAYZusv7r88cUbJm/iJXyOxoPBcKM j3GEw4JZ3XNzm+gFLnM2PQp/r0Xlrj6IHNWEM98QP134RHOL2dTQyKokCclHbSfYINdM fwscULyXBgl5sTtzA03SCImMxcZXrGxChoU3gwtYMU5VrD27mWtmEdFoMhfwxV/oKOFc E7tVAYyEAMpq0KLbmlGVmYZQMbnAUQ33Wlotq7aFDfwagOGo5OEE1LFQPQuPb2NqfXzn xTeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ke3gNQQE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:48 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 14/17] hw/arm/spitz: Use LOG_GUEST_ERROR for bad guest register accesses Date: Sun, 28 Jun 2020 15:24:26 +0100 Message-Id: <20200628142429.17111-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Instead of logging guest accesses to invalid register offsets in the Spitz flash device with zaurus_printf() (which just prints to stderr), use the usual qemu_log_mask(LOG_GUEST_ERROR,...). Signed-off-by: Peter Maydell --- hw/arm/spitz.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 6eb46869157..49eae3fce4e 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -23,6 +23,7 @@ #include "hw/ssi/ssi.h" #include "hw/block/flash.h" #include "qemu/timer.h" +#include "qemu/log.h" #include "hw/arm/sharpsl.h" #include "ui/console.h" #include "hw/audio/wm8750.h" @@ -65,9 +66,6 @@ typedef struct { #define zaurus_printf(format, ...) \ fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__) -#undef REG_FMT -#define REG_FMT "0x%02lx" - /* Spitz Flash */ #define FLASH_BASE 0x0c000000 #define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */ @@ -137,7 +135,9 @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size) return ecc_digest(&s->ecc, nand_getio(s->nand)); default: - zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); + qemu_log_mask(LOG_GUEST_ERROR, + "sl_read: bad register offset 0x%02" HWADDR_PRIx "\n", + addr); } return 0; } @@ -168,7 +168,9 @@ static void sl_write(void *opaque, hwaddr addr, break; default: - zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); + qemu_log_mask(LOG_GUEST_ERROR, + "sl_write: bad register offset 0x%02" HWADDR_PRIx "\n", + addr); } } From patchwork Sun Jun 28 14:24:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 191970 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2137634ilg; Sun, 28 Jun 2020 07:29:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyfBe+5sxHr1/Y30D5dXK+7iywb9V5IaPDR1fvePpryKbp9hyv+pDrO46ZbvDprt5S6WvvP X-Received: by 2002:a25:beca:: with SMTP id k10mr20133985ybm.9.1593354581719; Sun, 28 Jun 2020 07:29:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593354581; cv=none; d=google.com; s=arc-20160816; b=u6RTHMWJGlSXOdr2RiCzihPg+sNKUsw5pj13GbgG+aEwyU4utQmEgzzBlaLWdJ9z9R xYwNX1dWPIo5sGR4Pw4bJWX85+gpEHzGuVCGhan/pAJ09mxbfSotxBQYdNt+HOFyfZYb ja901O062im5wz54gJgZvyTc/VUtQsHrkDC/mKv1BNcqAQ2fN196iAPD34fobbqr/M6W V6LqHUgdy5OBuWxRPyf18SElKRJ+aumNiN5G+88YWR05sCrZIICcCat3VJ8QFHH1v9AK PZ45zfBe6wHra8qF3Y0vFW40LKmVsEpqTUQiTcy6O+48kolgycVOWypaCZnXVfiMXgTL FexA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Vmpo8pB4pBMBpoqr8J9eP1BB+PRV+N1N9F23e1inTwA=; b=qt+CD3J+AY53WyDvJ1rA1cVM9GwIaPphXH77EMgP1WFRuHP1jmN1m+ak/Nbs0FfkKk LlHzairWjdPzLzMJGZuglfbBDKnyiZXjJFVI5gRfUJHytJBDIWT/MpCin43VUCozDxfl HsEPZR4A23BI14GLbkwhvFmEtmkWptYF7pgCz+RwxP4cbjMxieAZT07eL0O8YhHHNQS7 b/Twzn1Y9TzXeKjaugR6qOj1ghw4lSt4N7+DEXLhfEd/7TuvUZXWqpNnKVRyq/9m11Pf 1ooOwG5GeiLX8VfzTWACkhP+8k2PsTJpQ8qnXfWHT9gDGzRp28u0WYErcjYt5CCnpDxn 68YA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DWewYRK+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:49 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 15/17] hw/arm/pxa2xx_pic: Use LOG_GUEST_ERROR for bad guest register accesses Date: Sun, 28 Jun 2020 15:24:27 +0100 Message-Id: <20200628142429.17111-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Instead of using printf() for logging guest accesses to invalid register offsets in the pxa2xx PIC device, use the usual qemu_log_mask(LOG_GUEST_ERROR,...). This was the only user of the REG_FMT macro in pxa.h, so we can remove that. Signed-off-by: Peter Maydell --- include/hw/arm/pxa.h | 1 - hw/arm/pxa2xx_pic.c | 9 +++++++-- 2 files changed, 7 insertions(+), 3 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h index f6dfb5c0cf0..8843e5f9107 100644 --- a/include/hw/arm/pxa.h +++ b/include/hw/arm/pxa.h @@ -184,7 +184,6 @@ struct PXA2xxI2SState { }; # define PA_FMT "0x%08lx" -# define REG_FMT "0x" TARGET_FMT_plx PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size, const char *revision); diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index 105c5e63f2f..ceee6aa48db 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -11,6 +11,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/log.h" #include "cpu.h" #include "hw/arm/pxa.h" #include "hw/sysbus.h" @@ -166,7 +167,9 @@ static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset, case ICHP: /* Highest Priority register */ return pxa2xx_pic_highest(s); default: - printf("%s: Bad register offset " REG_FMT "\n", __func__, offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pxa2xx_pic_mem_read: bad register offset 0x%" HWADDR_PRIx + "\n", offset); return 0; } } @@ -199,7 +202,9 @@ static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset, s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; break; default: - printf("%s: Bad register offset " REG_FMT "\n", __func__, offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pxa2xx_pic_mem_write: bad register offset 0x%" + HWADDR_PRIx "\n", offset); return; } pxa2xx_pic_update(opaque); From patchwork Sun Jun 28 14:24:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 191975 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2141723ilg; Sun, 28 Jun 2020 07:36:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyht/W0XgmS0Ksmjz+GGAN5XvtlghqSjoE633FOST/WOIDIsWJeaRzStBpEaiIf8oleztFL X-Received: by 2002:a25:ba09:: with SMTP id t9mr20412534ybg.128.1593354973009; Sun, 28 Jun 2020 07:36:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593354973; cv=none; d=google.com; s=arc-20160816; b=v8kxps3yg+I4nK0y+xNlzu1bQg2Arp+rUTqY549OsFOw8MbV4Dh3erjq8fPy1WgjZi 4Yk2qyb/J5ddUlP349MZ+eF/yTuHOeMYDg6DaCH4mCuH6IAdNystsg8UteZzMyVlkx+G sS+jptRbDfwA9tR5A0fRzqU684go3TdzRMOAsNvDIs5sk/t4Hzu2E6P79jqK2Id0nmzV BBK5TukJDOUrttSECXwD7dNM8GCJ0qoMSmQKf3cs2x2YLlwHeUSUhMoMOv3gA+QEBKOa AKIdP37OIPiITkPnnzwrFVwbGCXGVIHlopTXBPw/ELU+MPSy/vC8JMlLFJx1wBSjE/GJ OKyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=03unWo1zzivuM0us7q7fEwDLp9zh0qzy8bL3l2XLj/Q=; b=gpSBMLnpnhDgRJ6gMpvD8pIirCYmC1vgF0QYvzdHxzFVxGSpCVYYeSias/vvvEZ7Nx zYE1+ZzLReguEzGs/ErJLX2RGXNCuUOSp66kh/JZ95PJ2mvmueWwk4tKjmeDjmVfveto OUydYQTLNQZ6/3IMH2jgI3UxBZTEsDIFLiTycGxkpiV1AWbbc2ge+jU+bR4LXx7Vd/He 5woAf3MNkRtKqw4PXi3pqlf0lBMPKqlJLUGaRChaNhSpfuCwRnSBj1rK7gPJI2RJR5AS R5ar0WmLsEcJOGj6WAfEkl6LB/oKQ56p3PxA72dRhEfcLUM4kVvErqHByGa1kDJCIAjY 7Dlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vIG40ChM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:50 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 16/17] hw/arm/spitz: Provide usual QOM macros for corgi-ssp and spitz-lcdtg Date: Sun, 28 Jun 2020 15:24:28 +0100 Message-Id: <20200628142429.17111-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The QOM types "spitz-lcdtg" and "corgi-ssp" are missing the usual QOM TYPE and casting macros; provide and use them. In particular, we can safely use the QOM cast macros instead of FROM_SSI_SLAVE() because in both cases the 'ssidev' field of the instance state struct is the first field in it. Signed-off-by: Peter Maydell --- hw/arm/spitz.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 49eae3fce4e..f020aff9747 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -579,6 +579,9 @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp) #define LCDTG_PICTRL 0x06 #define LCDTG_POLCTRL 0x07 +#define TYPE_SPITZ_LCDTG "spitz-lcdtg" +#define SPITZ_LCDTG(obj) OBJECT_CHECK(SpitzLCDTG, (obj), TYPE_SPITZ_LCDTG) + typedef struct { SSISlave ssidev; uint32_t bl_intensity; @@ -616,7 +619,7 @@ static inline void spitz_bl_power(void *opaque, int line, int level) static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value) { - SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev); + SpitzLCDTG *s = SPITZ_LCDTG(dev); int addr; addr = value >> 5; value &= 0x1f; @@ -645,7 +648,7 @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value) static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp) { - SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi); + SpitzLCDTG *s = SPITZ_LCDTG(ssi); DeviceState *dev = DEVICE(s); s->bl_power = 0; @@ -664,6 +667,9 @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp) #define SPITZ_GPIO_MAX1111_CS 20 #define SPITZ_GPIO_TP_INT 11 +#define TYPE_CORGI_SSP "corgi-ssp" +#define CORGI_SSP(obj) OBJECT_CHECK(CorgiSSPState, (obj), TYPE_CORGI_SSP) + /* "Demux" the signal based on current chipselect */ typedef struct { SSISlave ssidev; @@ -673,7 +679,7 @@ typedef struct { static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value) { - CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev); + CorgiSSPState *s = CORGI_SSP(dev); int i; for (i = 0; i < 3; i++) { @@ -702,7 +708,7 @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level) static void corgi_ssp_realize(SSISlave *d, Error **errp) { DeviceState *dev = DEVICE(d); - CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, d); + CorgiSSPState *s = CORGI_SSP(d); qdev_init_gpio_in(dev, corgi_ssp_gpio_cs, 3); s->bus[0] = ssi_create_bus(dev, "ssi0"); @@ -714,10 +720,11 @@ static void spitz_ssp_attach(SpitzMachineState *sms) { void *bus; - sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp"); + sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], + TYPE_CORGI_SSP); bus = qdev_get_child_bus(sms->mux, "ssi0"); - sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg"); + sms->lcdtg = ssi_create_slave(bus, TYPE_SPITZ_LCDTG); bus = qdev_get_child_bus(sms->mux, "ssi1"); sms->ads7846 = ssi_create_slave(bus, "ads7846"); @@ -1220,7 +1227,7 @@ static void corgi_ssp_class_init(ObjectClass *klass, void *data) } static const TypeInfo corgi_ssp_info = { - .name = "corgi-ssp", + .name = TYPE_CORGI_SSP, .parent = TYPE_SSI_SLAVE, .instance_size = sizeof(CorgiSSPState), .class_init = corgi_ssp_class_init, @@ -1249,7 +1256,7 @@ static void spitz_lcdtg_class_init(ObjectClass *klass, void *data) } static const TypeInfo spitz_lcdtg_info = { - .name = "spitz-lcdtg", + .name = TYPE_SPITZ_LCDTG, .parent = TYPE_SSI_SLAVE, .instance_size = sizeof(SpitzLCDTG), .class_init = spitz_lcdtg_class_init, From patchwork Sun Jun 28 14:24:29 2020 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h13sm5321555wml.42.2020.06.28.07.24.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2020 07:24:51 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 17/17] Replace uses of FROM_SSI_SLAVE() macro with QOM casts Date: Sun, 28 Jun 2020 15:24:29 +0100 Message-Id: <20200628142429.17111-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200628142429.17111-1-peter.maydell@linaro.org> References: <20200628142429.17111-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The FROM_SSI_SLAVE() macro predates QOM and is used as a typesafe way to cast from an SSISlave* to the instance struct of a subtype of TYPE_SSI_SLAVE. Switch to using the QOM cast macros instead, which have the same effect (by writing the QOM macros if the types were previously missing them.) (The FROM_SSI_SLAVE() macro allows the SSISlave member of the subtype's struct to be anywhere as long as it is named "ssidev", whereas a QOM cast macro insists that it is the first thing in the subtype's struct. This is true for all the types we convert here.) This removes all the uses of FROM_SSI_SLAVE() so we can delete the definition. Signed-off-by: Peter Maydell --- include/hw/ssi/ssi.h | 2 -- hw/arm/z2.c | 11 +++++++---- hw/display/ads7846.c | 9 ++++++--- hw/display/ssd0323.c | 10 +++++++--- hw/sd/ssi-sd.c | 4 ++-- 5 files changed, 22 insertions(+), 14 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h index 5fd411f2e4e..eac168aa1db 100644 --- a/include/hw/ssi/ssi.h +++ b/include/hw/ssi/ssi.h @@ -66,8 +66,6 @@ struct SSISlave { bool cs; }; -#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev) - extern const VMStateDescription vmstate_ssi_slave; #define VMSTATE_SSI_SLAVE(_field, _state) { \ diff --git a/hw/arm/z2.c b/hw/arm/z2.c index a0f40959904..e1f22f58681 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -111,9 +111,12 @@ typedef struct { int pos; } ZipitLCD; +#define TYPE_ZIPIT_LCD "zipit-lcd" +#define ZIPIT_LCD(obj) OBJECT_CHECK(ZipitLCD, (obj), TYPE_ZIPIT_LCD) + static uint32_t zipit_lcd_transfer(SSISlave *dev, uint32_t value) { - ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev); + ZipitLCD *z = ZIPIT_LCD(dev); uint16_t val; if (z->selected) { z->buf[z->pos] = value & 0xff; @@ -153,7 +156,7 @@ static void z2_lcd_cs(void *opaque, int line, int level) static void zipit_lcd_realize(SSISlave *dev, Error **errp) { - ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev); + ZipitLCD *z = ZIPIT_LCD(dev); z->selected = 0; z->enabled = 0; z->pos = 0; @@ -185,7 +188,7 @@ static void zipit_lcd_class_init(ObjectClass *klass, void *data) } static const TypeInfo zipit_lcd_info = { - .name = "zipit-lcd", + .name = TYPE_ZIPIT_LCD, .parent = TYPE_SSI_SLAVE, .instance_size = sizeof(ZipitLCD), .class_init = zipit_lcd_class_init, @@ -325,7 +328,7 @@ static void z2_init(MachineState *machine) type_register_static(&zipit_lcd_info); type_register_static(&aer915_info); - z2_lcd = ssi_create_slave(mpu->ssp[1], "zipit-lcd"); + z2_lcd = ssi_create_slave(mpu->ssp[1], TYPE_ZIPIT_LCD); bus = pxa2xx_i2c_bus(mpu->i2c[0]); i2c_create_slave(bus, TYPE_AER915, 0x55); wm = i2c_create_slave(bus, TYPE_WM8750, 0x1b); diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c index 9228b40b1af..56bf82fe079 100644 --- a/hw/display/ads7846.c +++ b/hw/display/ads7846.c @@ -29,6 +29,9 @@ typedef struct { int output; } ADS7846State; +#define TYPE_ADS7846 "ads7846" +#define ADS7846(obj) OBJECT_CHECK(ADS7846State, (obj), TYPE_ADS7846) + /* Control-byte bitfields */ #define CB_PD0 (1 << 0) #define CB_PD1 (1 << 1) @@ -61,7 +64,7 @@ static void ads7846_int_update(ADS7846State *s) static uint32_t ads7846_transfer(SSISlave *dev, uint32_t value) { - ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, dev); + ADS7846State *s = ADS7846(dev); switch (s->cycle ++) { case 0: @@ -139,7 +142,7 @@ static const VMStateDescription vmstate_ads7846 = { static void ads7846_realize(SSISlave *d, Error **errp) { DeviceState *dev = DEVICE(d); - ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, d); + ADS7846State *s = ADS7846(d); qdev_init_gpio_out(dev, &s->interrupt, 1); @@ -166,7 +169,7 @@ static void ads7846_class_init(ObjectClass *klass, void *data) } static const TypeInfo ads7846_info = { - .name = "ads7846", + .name = TYPE_ADS7846, .parent = TYPE_SSI_SLAVE, .instance_size = sizeof(ADS7846State), .class_init = ads7846_class_init, diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c index c3bdb18742c..32d27f008ae 100644 --- a/hw/display/ssd0323.c +++ b/hw/display/ssd0323.c @@ -66,9 +66,13 @@ typedef struct { uint8_t framebuffer[128 * 80 / 2]; } ssd0323_state; +#define TYPE_SSD0323 "ssd0323" +#define SSD0323(obj) OBJECT_CHECK(ssd0323_state, (obj), TYPE_SSD0323) + + static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data) { - ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev); + ssd0323_state *s = SSD0323(dev); switch (s->mode) { case SSD0323_DATA: @@ -346,7 +350,7 @@ static const GraphicHwOps ssd0323_ops = { static void ssd0323_realize(SSISlave *d, Error **errp) { DeviceState *dev = DEVICE(d); - ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, d); + ssd0323_state *s = SSD0323(d); s->col_end = 63; s->row_end = 79; @@ -368,7 +372,7 @@ static void ssd0323_class_init(ObjectClass *klass, void *data) } static const TypeInfo ssd0323_info = { - .name = "ssd0323", + .name = TYPE_SSD0323, .parent = TYPE_SSI_SLAVE, .instance_size = sizeof(ssd0323_state), .class_init = ssd0323_class_init, diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index 25cec2ddeaa..25cdf4c966d 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -74,7 +74,7 @@ typedef struct { static uint32_t ssi_sd_transfer(SSISlave *dev, uint32_t val) { - ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, dev); + ssi_sd_state *s = SSI_SD(dev); /* Special case: allow CMD12 (STOP TRANSMISSION) while reading data. */ if (s->mode == SSI_SD_DATA_READ && val == 0x4d) { @@ -241,7 +241,7 @@ static const VMStateDescription vmstate_ssi_sd = { static void ssi_sd_realize(SSISlave *d, Error **errp) { - ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, d); + ssi_sd_state *s = SSI_SD(d); DeviceState *carddev; DriveInfo *dinfo; Error *err = NULL;