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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id u15sm1538776iog.18.2020.06.30.06.33.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jun 2020 06:33:08 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 1/5] net: ipa: head-of-line block registers are RX only Date: Tue, 30 Jun 2020 08:33:00 -0500 Message-Id: <20200630133304.1331058-2-elder@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200630133304.1331058-1-elder@linaro.org> References: <20200630133304.1331058-1-elder@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The INIT_HOL_BLOCK_EN and INIT_HOL_BLOCK_TIMER endpoint registers are only valid for RX endpoints. Have ipa_endpoint_modem_hol_block_clear_all() skip writing these registers for TX endpoints. Signed-off-by: Alex Elder --- v2: The commented calls to assert() that were added are now gone. drivers/net/ipa/ipa_endpoint.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 9f50d0d11704..31afe282f347 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -683,7 +683,7 @@ void ipa_endpoint_modem_hol_block_clear_all(struct ipa *ipa) for (i = 0; i < IPA_ENDPOINT_MAX; i++) { struct ipa_endpoint *endpoint = &ipa->endpoint[i]; - if (endpoint->ee_id != GSI_EE_MODEM) + if (endpoint->toward_ipa || endpoint->ee_id != GSI_EE_MODEM) continue; (void)ipa_endpoint_init_hol_block_timer(endpoint, 0); From patchwork Tue Jun 30 13:33:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 192078 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp3821673ilg; Tue, 30 Jun 2020 06:33:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2qq2+LV/1APZfsT/VB/AXcUToInR5lRbj6rsSUXlw1XIW340jtiTL50BI3dGE8hbd91yr X-Received: by 2002:aa7:c808:: with SMTP id a8mr20606689edt.259.1593523994973; Tue, 30 Jun 2020 06:33:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593523994; cv=none; d=google.com; s=arc-20160816; b=CJN4vtAiMJUdgpoNNwcYNyubzrvCNZIpHeVf2IKRBeZPNHZM3yxU6do1XaU0BTeme5 0yRszbVpptRkWiVj7hSw98e+73f8PM6H45ZtjtXSDwQYfRvOpKqwi56sblUIK5eI8M1n +HHmMGaPlT+Wyx6Rem8hr6hqZ2Uq6mTWpAKa0KLkB1sIhtzMPMoFNPuZK+JYHsFf+gOR +1pCw9uxigDi+/BUi5Yqvt5OGGvgMUJFqEu75dr77O7GpGzs5wAysBAvgFiiDjCxyKCO rFctm27FhQ+NAb9mWhtXZ73jbRZPeLL3iUexWXGKF5pra7jeIBnszp3TyXejh1zIJ5hM /41A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=riisFCPpfIy+ddIeKemrrsU0BmBozz0Ml8rD1KyP5/o=; b=lf1KoA2c5kNlxy4qxi3fBt7mVd32rkg11Nv7dvzFbvqq+AE87dthcReXbgAorZjI7R xcXu0PGlagsT1EyJLIM6U96BUGRBZnjB06s3WBzXwDJCtC6lsvjzpaY8U/LFw0z0zMM4 AQCs0T6fN09ro7lkTvq1K5Bgo5FnkSt8EaYZlHc0zDj69NVTywUfki+GxGO5zJmgKcUC FVHi3MWVNLmBFnGosOfgstBuhmKuJLQWxdJrDIr7u54sD+NllnO3RrH+LMYfSa8J4GD3 5AlPB27t2/C3TFM7OheTS/0Iq9tRYZHU1X8ME/1KnLsopBUlHX84C7U3Fs7jEvTuvmyP OUUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ktsLrCTc; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id u15sm1538776iog.18.2020.06.30.06.33.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jun 2020 06:33:09 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 2/5] net: ipa: metadata_mask register is RX only Date: Tue, 30 Jun 2020 08:33:01 -0500 Message-Id: <20200630133304.1331058-3-elder@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200630133304.1331058-1-elder@linaro.org> References: <20200630133304.1331058-1-elder@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The INIT_HDR_METADATA_MASK endpoint configuration register is only valid for RX endpoints. Rather than writing a zero to that register for TX endpoints, avoid writing the register at all. Signed-off-by: Alex Elder --- v2: The commented call to assert() that was added is now gone. drivers/net/ipa/ipa_endpoint.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 31afe282f347..1babcfc79360 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -530,7 +530,7 @@ static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint) offset = IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(endpoint_id); /* Note that HDR_ENDIANNESS indicates big endian header fields */ - if (!endpoint->toward_ipa && endpoint->data->qmap) + if (endpoint->data->qmap) val = cpu_to_be32(IPA_ENDPOINT_QMAP_METADATA_MASK); iowrite32(val, endpoint->ipa->reg_virt + offset); @@ -1302,10 +1302,10 @@ static void ipa_endpoint_program(struct ipa_endpoint *endpoint) (void)ipa_endpoint_program_suspend(endpoint, false); ipa_endpoint_init_hdr_ext(endpoint); ipa_endpoint_init_aggr(endpoint); + ipa_endpoint_init_hdr_metadata_mask(endpoint); } ipa_endpoint_init_cfg(endpoint); ipa_endpoint_init_hdr(endpoint); - ipa_endpoint_init_hdr_metadata_mask(endpoint); ipa_endpoint_init_mode(endpoint); ipa_endpoint_status(endpoint); } From patchwork Tue Jun 30 13:33:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 192079 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp3821781ilg; Tue, 30 Jun 2020 06:33:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw//V1jCwRURfR5BUEmXD4mmZKumihXfLgkgI19F+LtxR845/hTI0doR6MSKjGEpmsX55m5 X-Received: by 2002:a17:906:7247:: with SMTP id n7mr18437831ejk.105.1593524002666; Tue, 30 Jun 2020 06:33:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593524002; cv=none; d=google.com; s=arc-20160816; b=t7ZhjrAkhVot0Pmkqj+iW1KlDuaKLOdYv7QqPUOPwTMWaIkP6t/n4uxoNA2b4+unWu 2/RBqu1wGuC7wOP2VwJFl+xMNiAc9zZ6tw5yTgQVtyKo+eY4uwe0MpRXxbNMpBRmXxdx W9LcQWRGxs39AK7JVF90eSb4PYOLmqCbP+WWfqAdKPOmlp4GaN3oParVcdyftDQgk0Yj Zddt8NiJoHjdqfg8uG/HdAC4ZDASsiQoajmCLszTAsjc5Ly/UceT3+tiDDMj37GllIvB Fh8C4KbmN9i2CtSUIInjVwJkejM97malykuVHJ6RyJnzcjO7JJ9LJZtw3xARrkf8vQCs 9s3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=r5aSRp59jKO5d55dBFG61qZSPf1iY4fVxx3iYfquSAE=; b=mL3bU3VWHrlGcoh6TTVKS1D8GFWRBFSfParyFXVXhJlK2AOmPndOiK193uWnZrQqfS AuLBZcgyIIlcnsT2Xey33FSoqbJA1F1UVEaE4m4CzOl7G+8w2HOuvqJhLbdbXkUqCnRY IVwrpeAUWmUNguTQNFwK16NTL6fAepp6gRR+40T40tNP+cO2MjnSn28GMsKmXMiY5kIl +zNKBIwL/c7RHfdnY0GnF3ozfYTxbY8ELyFG7Hc5i+Chsj8nf2ID44Bn2Yq7wuq9FAx8 M5kauLQyHiyhXa2JRnm0SdeEcAqQKuy3x2oqfAvpq18td+c31N3UQGqFcywlddufNDw5 CtXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UQnfJJ9g; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id u15sm1538776iog.18.2020.06.30.06.33.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jun 2020 06:33:10 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 3/5] net: ipa: mode register is TX only Date: Tue, 30 Jun 2020 08:33:02 -0500 Message-Id: <20200630133304.1331058-4-elder@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200630133304.1331058-1-elder@linaro.org> References: <20200630133304.1331058-1-elder@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The INIT_MODE endpoint configuration register is only valid for TX endpoints. Rather than writing a zero to that register for RX endpoints, avoid writing the register at all. Signed-off-by: Alex Elder --- v2: The commented calls to assert() that were added are now gone. drivers/net/ipa/ipa_endpoint.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 1babcfc79360..566ff6a09e65 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -541,7 +541,7 @@ static void ipa_endpoint_init_mode(struct ipa_endpoint *endpoint) u32 offset = IPA_REG_ENDP_INIT_MODE_N_OFFSET(endpoint->endpoint_id); u32 val; - if (endpoint->toward_ipa && endpoint->data->dma_mode) { + if (endpoint->data->dma_mode) { enum ipa_endpoint_name name = endpoint->data->dma_endpoint; u32 dma_endpoint_id; @@ -552,7 +552,7 @@ static void ipa_endpoint_init_mode(struct ipa_endpoint *endpoint) } else { val = u32_encode_bits(IPA_BASIC, MODE_FMASK); } - /* Other bitfields unspecified (and 0) */ + /* All other bits unspecified (and 0) */ iowrite32(val, endpoint->ipa->reg_virt + offset); } @@ -1297,6 +1297,7 @@ static void ipa_endpoint_program(struct ipa_endpoint *endpoint) ipa_endpoint_init_aggr(endpoint); ipa_endpoint_init_deaggr(endpoint); ipa_endpoint_init_seq(endpoint); + ipa_endpoint_init_mode(endpoint); } else { if (endpoint->ipa->version == IPA_VERSION_3_5_1) (void)ipa_endpoint_program_suspend(endpoint, false); @@ -1306,7 +1307,6 @@ static void ipa_endpoint_program(struct ipa_endpoint *endpoint) } ipa_endpoint_init_cfg(endpoint); ipa_endpoint_init_hdr(endpoint); - ipa_endpoint_init_mode(endpoint); ipa_endpoint_status(endpoint); } From patchwork Tue Jun 30 13:33:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 192080 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp3821946ilg; Tue, 30 Jun 2020 06:33:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJywgFiHkGFqwSzFJQwgVpRlFN6Ib1+ysW+f+Fc66e3G1lxEolLKheet8qOmRgnkzBnO5ZbI X-Received: by 2002:a50:a1e7:: with SMTP id 94mr22497492edk.165.1593524012657; Tue, 30 Jun 2020 06:33:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593524012; cv=none; d=google.com; s=arc-20160816; b=FBbX+nGVJy250QNHm46ihHD3LAVDeu+CvNx9ZIEhw3MaZiwlTySx47X8JqxxW5Vo+j 2DUrmFW08uslYY5/mzyRtsGFn99q8foLnZ1Ahd3dBAV019eaJZOyrO/qXHPaKq1//YbY fAcdD/V1X06iQucoSnRQatOAFh6f4rQv3rqKlVbv3WZM+li2ezGzXss8xC8iTxPurkzm mqpRxfmsQoC1vzV9NhtT7NegfsPFTdP9Utfqk95rl+X12Z+qwdj/HYyoLy2Nu+uLJ9xq X8ZCzmnBll6uQOz8U9B1PxK+mBP49CBrm9xzYaMAKde5oCjYCVbUxfKyqf0L3Z1jXfaJ qtQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VivmetwM/ISybdgajhPoVZntM81ebOCgMDarkRt8jT4=; b=Aad97Oy470CaQZl6qI2+7vPMRyN67t8jMobNV8O48Mo2NfNydvyDlfR5KdDtH+WW14 E2A+MqZ3KqLr5qoTVAvSHF0q8s5a7nWfi8WCbdcvLEu6GevYOuTG3cD6xhgdFdz/NJdv thtiC/m6L+K0Ic9uasisQejt4oAJCMfIdIa4/6DxMHaNgYXcAAO3cO2HUtjaFAh7dGMh XTzQiRvOgcF7WPM0XEoVVbzgmmdxGiiAibzxYhHkhbF3NQO1shBUlMm0Vj78ddKnc9nT Lqa125zNFsujoxmlLwJEhC/ZvvmBDWIUI+qiDIONczHwBr+oK5caUFtvoR91q4xrBRAm hF7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DaBoNegh; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id u15sm1538776iog.18.2020.06.30.06.33.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jun 2020 06:33:11 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 4/5] net: ipa: clarify endpoint register macro constraints Date: Tue, 30 Jun 2020 08:33:03 -0500 Message-Id: <20200630133304.1331058-5-elder@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200630133304.1331058-1-elder@linaro.org> References: <20200630133304.1331058-1-elder@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org A handful of registers are valid only for RX endpoints, and some others are valid only for TX endpoints. For these endpoints, add a comment above their defined offset macro that indicates the endpoints to which they apply. Extend the endpoint parameter naming convention as well, to make these constraints more explicit. Signed-off-by: Alex Elder --- v2: No change from version 1. drivers/net/ipa/ipa_reg.h | 43 +++++++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 18 deletions(-) -- 2.25.1 diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index 0a688d8c1d7c..10e4ac9ead68 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -32,10 +32,12 @@ struct ipa; * parameter is supplied to the offset macro. The "ee" value is a member of * the gsi_ee enumerated type. * - * The offset of a register dependent on endpoint id is computed by a macro - * that is supplied a parameter "ep". The "ep" value is assumed to be less - * than the maximum endpoint value for the current hardware, and that will - * not exceed IPA_ENDPOINT_MAX. + * The offset of a register dependent on endpoint ID is computed by a macro + * that is supplied a parameter "ep", "txep", or "rxep". A register with an + * "ep" parameter is valid for any endpoint; a register with a "txep" or + * "rxep" parameter is valid only for TX or RX endpoints, respectively. The + * "*ep" value is assumed to be less than the maximum valid endpoint ID + * for the current hardware, and that will not exceed IPA_ENDPOINT_MAX. * * The offset of registers related to filter and route tables is computed * by a macro that is supplied a parameter "er". The "er" represents an @@ -293,11 +295,13 @@ static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) #define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4) #define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10) -#define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(ep) \ - (0x00000818 + 0x0070 * (ep)) +/* Valid only for RX (IPA producer) endpoints */ +#define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(rxep) \ + (0x00000818 + 0x0070 * (rxep)) -#define IPA_REG_ENDP_INIT_MODE_N_OFFSET(ep) \ - (0x00000820 + 0x0070 * (ep)) +/* Valid only for TX (IPA consumer) endpoints */ +#define IPA_REG_ENDP_INIT_MODE_N_OFFSET(txep) \ + (0x00000820 + 0x0070 * (txep)) #define MODE_FMASK GENMASK(2, 0) #define DEST_PIPE_INDEX_FMASK GENMASK(8, 4) #define BYTE_THRESHOLD_FMASK GENMASK(27, 12) @@ -316,19 +320,21 @@ static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) #define AGGR_FORCE_CLOSE_FMASK GENMASK(22, 22) #define AGGR_HARD_BYTE_LIMIT_ENABLE_FMASK GENMASK(24, 24) -#define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(ep) \ - (0x0000082c + 0x0070 * (ep)) +/* Valid only for RX (IPA producer) endpoints */ +#define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \ + (0x0000082c + 0x0070 * (rxep)) #define HOL_BLOCK_EN_FMASK GENMASK(0, 0) -/* The next register is valid only for RX (IPA producer) endpoints */ -#define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(ep) \ - (0x00000830 + 0x0070 * (ep)) +/* Valid only for RX (IPA producer) endpoints */ +#define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \ + (0x00000830 + 0x0070 * (rxep)) /* The next fields are present for IPA v4.2 only */ #define BASE_VALUE_FMASK GENMASK(4, 0) #define SCALE_FMASK GENMASK(12, 8) -#define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(ep) \ - (0x00000834 + 0x0070 * (ep)) +/* Valid only for TX (IPA consumer) endpoints */ +#define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \ + (0x00000834 + 0x0070 * (txep)) #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) @@ -338,8 +344,9 @@ static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) (0x00000838 + 0x0070 * (ep)) #define RSRC_GRP_FMASK GENMASK(1, 0) -#define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(ep) \ - (0x0000083c + 0x0070 * (ep)) +/* Valid only for TX (IPA consumer) endpoints */ +#define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \ + (0x0000083c + 0x0070 * (txep)) #define HPS_SEQ_TYPE_FMASK GENMASK(3, 0) #define DPS_SEQ_TYPE_FMASK GENMASK(7, 4) #define HPS_REP_SEQ_TYPE_FMASK GENMASK(11, 8) @@ -353,7 +360,7 @@ static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) /* The next field is present for IPA v4.0 and above */ #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) -/* "er" is either an endpoint id (for filters) or a route id (for routes) */ +/* "er" is either an endpoint ID (for filters) or a route ID (for routes) */ #define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \ (0x0000085c + 0x0070 * (er)) #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) From patchwork Tue Jun 30 13:33:04 2020 Content-Type: text/plain; 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id u15sm1538776iog.18.2020.06.30.06.33.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jun 2020 06:33:12 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 5/5] net: ipa: HOL_BLOCK_EN_FMASK is a 1-bit mask Date: Tue, 30 Jun 2020 08:33:04 -0500 Message-Id: <20200630133304.1331058-6-elder@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200630133304.1331058-1-elder@linaro.org> References: <20200630133304.1331058-1-elder@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The convention throughout the IPA driver is to directly use single-bit field mask values, rather than using (for example) u32_encode_bits() to set or clear them. Fix the one place that doesn't follow that convention, which sets HOL_BLOCK_EN_FMASK in ipa_endpoint_init_hol_block_enable(). Signed-off-by: Alex Elder --- v2: No change from version 1. drivers/net/ipa/ipa_endpoint.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 566ff6a09e65..0332dcbcaaae 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -671,7 +671,7 @@ ipa_endpoint_init_hol_block_enable(struct ipa_endpoint *endpoint, bool enable) u32 offset; u32 val; - val = u32_encode_bits(enable ? 1 : 0, HOL_BLOCK_EN_FMASK); + val = enable ? HOL_BLOCK_EN_FMASK : 0; offset = IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(endpoint_id); iowrite32(val, endpoint->ipa->reg_virt + offset); }