From patchwork Tue Jul 18 16:58:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108141 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6148128obm; Tue, 18 Jul 2017 09:59:44 -0700 (PDT) X-Received: by 10.98.73.205 with SMTP id r74mr2684777pfi.166.1500397184620; Tue, 18 Jul 2017 09:59:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397184; cv=none; d=google.com; s=arc-20160816; b=vs5PtAvaWeCGk1rwlxdnKsMicVXH2yRAaZCcfcaBY8YYkmI5blWf2jNvrxZ7MconJR SZ1RZDOogadMUCSppQhvfiZ2xF9dytB6TgzXMFune/1GIBYpDtN7hMlTySVfLWLOyuYT w0aQBUoiQ3z5rayz5J8fItvgWA2n4WfeEU1crIvWWqX0OuhtS1FvxanugxGbfU7aTUpn X0iOq9gpDBf7xdTk+fL0/3OYTJ8ohFJZKTHxB+PBX69X/3F8UKW8IoBOiYxsaSxfJFr5 8EibFhRgoJY3qXKdJwaVl5gpruMQJuPZKo5MwGSs0VTRQm45m6RgU2lqnv5bAulXRCoZ 7Tgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=T0v9utudyF81U6j+p85lLGe3ajEusd68NHDmkB9JO6g=; b=o97M76m0FzOcjbK1t1h8Iw1BWx60QQv4EzK0Vw6LJEJG7xtjpFtuUVhSKkMpACDU4t 1QCBjtSxkKfEbHaW/RdUVW8M8fWw35XX0GWC/eeMVQOUTMRmrW3qGSTCIVsRcfVU2Wsb AmsZhhtsBP4HfSoFfPIEkDsNYHmRMHcjYPQm8oMhfznQ338R3RpD6Op6ZRnGUuflvvTk bvVPbCCVKgRLBLRiPuFIO8dTat8V590KfeAtc5OdEEYs44SGkQwZiF2OI1LzDWca19xg Dk6csTo+qI/7gQ5hUAuCnLoMIoMGc13MWz/mkS1IMadHNqyR1EXNaCfRm7F28mWf0LK+ gzAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=fiRQYEdg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m17si2157454pge.71.2017.07.18.09.59.44; Tue, 18 Jul 2017 09:59:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=fiRQYEdg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751824AbdGRQ7j (ORCPT + 25 others); Tue, 18 Jul 2017 12:59:39 -0400 Received: from mail-it0-f46.google.com ([209.85.214.46]:38034 "EHLO mail-it0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751557AbdGRQ7g (ORCPT ); Tue, 18 Jul 2017 12:59:36 -0400 Received: by mail-it0-f46.google.com with SMTP id h199so16515824ith.1 for ; Tue, 18 Jul 2017 09:59:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=T0v9utudyF81U6j+p85lLGe3ajEusd68NHDmkB9JO6g=; b=fiRQYEdgocQaqisVGAAxv20lAHwVNOf08vMV4RP0FVm2f3SH/suTDyIRrYRiaVIoPY cCC6ZUqZkwxhijwLnhDm/5Pd89ZauwRJAt3nZ07HCSA8Is96PPTRX80lHYmBviTNlbLz WkE4F1xEVD5fbU5+vI3+HQ3z3+1TsaiuwNIhQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=T0v9utudyF81U6j+p85lLGe3ajEusd68NHDmkB9JO6g=; b=oqmRLTCPZg/UoQmlVZoBUQvx8y1hNfdgeAJjy/ulHQMeJ5TH/Jyegs1DeJnMqkkIzw f5uUYJXoMdEwHoNh21rzcw3GO4JLLXVZ38LCUE1493WlfAML0KL4O+wWFA3y8y1PBJVb t9U6D9HcM5HizsCBy1UG0Rgr3p/ns4lVDC9e85a7wFwlmfqL0YlzJrKYY9EChwxmpC3k AryYw0YdSXYbQJrxG8FMJw7qMPWm7KJNigE8Wy0cCZm6nswtXYl1AQeiVzEAFaoUS9w4 6SS+bc/wKsRWglUS1dyTzwntbQdrYCrjDIPNzR9uOIpFblKgqhoNfs+JNsAaUPO1zAyy uNuQ== X-Gm-Message-State: AIVw110yFNaTcFG+U+K05j7FQ2D+SQdVisDIA6jdFh+rfGsQdaEXJxGx 0743Qn72D0Kh7kGM X-Received: by 10.36.16.144 with SMTP id 138mr3744466ity.64.1500397175871; Tue, 18 Jul 2017 09:59:35 -0700 (PDT) Received: from node.jintackl-qv26972.kvmarm-pg0.wisc.cloudlab.us (c220g1-030822.wisc.cloudlab.us. [128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.09.59.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 09:59:35 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 01/38] arm64: Add ARM64_HAS_NESTED_VIRT feature Date: Tue, 18 Jul 2017 11:58:27 -0500 Message-Id: <1500397144-16232-2-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a new ARM64_HAS_NESTED_VIRT feature to indicate that the CPU has the ARMv8.3 nested virtualization capability. This will be used to support nested virtualization in KVM. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/asm/sysreg.h | 1 + arch/arm64/kernel/cpufeature.c | 11 +++++++++++ 3 files changed, 14 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 8d2272c..64df263 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -39,7 +39,8 @@ #define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18 #define ARM64_WORKAROUND_858921 19 #define ARM64_WORKAROUND_CAVIUM_30115 20 +#define ARM64_HAS_NESTED_VIRT 21 -#define ARM64_NCAPS 21 +#define ARM64_NCAPS 22 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 16e44fa..737ca30 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -376,6 +376,7 @@ #define ID_AA64MMFR1_VMIDBITS_16 2 /* id_aa64mmfr2 */ +#define ID_AA64MMFR2_NV_SHIFT 24 #define ID_AA64MMFR2_LVA_SHIFT 16 #define ID_AA64MMFR2_IESB_SHIFT 12 #define ID_AA64MMFR2_LSM_SHIFT 8 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 94b8f7f..523f998 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -144,6 +144,7 @@ }; static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_NV_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0), @@ -867,6 +868,16 @@ static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unus .min_field_value = 0, .matches = has_no_fpsimd, }, + { + .desc = "Nested Virtualization Support", + .capability = ARM64_HAS_NESTED_VIRT, + .def_scope = SCOPE_SYSTEM, + .matches = has_cpuid_feature, + .sys_reg = SYS_ID_AA64MMFR2_EL1, + .sign = FTR_UNSIGNED, + .field_pos = ID_AA64MMFR2_NV_SHIFT, + .min_field_value = 1, + }, {}, }; From patchwork Tue Jul 18 16:58:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108181 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp6194419qge; Tue, 18 Jul 2017 10:13:24 -0700 (PDT) X-Received: by 10.84.229.75 with SMTP id d11mr2808353pln.207.1500398003987; Tue, 18 Jul 2017 10:13:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500398003; cv=none; d=google.com; s=arc-20160816; b=Btpk/YCT45dGXKi8qb9gt/2OC/ZRbRjhDyJCtfoUwo6xxaNLGGjNFBSsmRSf0IgBcW 6D/Ueg7DQWj/AFF7aGnYdE4p/BvZblAOB68/y7VC+dhBO6bTwuCBJ43kBYxntkwwDRh2 BSR48aXPm/BZ7Fb6jMJ36KKBP1zII24XbqXm7r6gX3h1iU8gOKHGJ30wPJtkWFYx6v+E EeMuaXg+Y1z0zuliPYdUykk4X2HyR5tXKyzHMJMfsHczTyu1cQZ6yW10+9CoMG5C92/B CoK2CWZPvFFALdElvDnYLK7GlRa8HJsDjnlcjFI8gYHpXuZLg9ihGwkjc8yBL3M0VfbB mVnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=gS4ttO5+VUU0HPCLsGuyaKUxGqZs9JmugC2RyJAHZ70=; b=r7QpJAGWYUR0WU6ZggWVT00TrVnZFiHyO4SHi6Vm0SWDbMcuY1Z6lH5ShIUMCmvR1C 6EtiyH7LV+VSbhl98JQ4DIsIFu8YtPreNRzf97VdmXgiP3ma/okk++f/q91MzElQc/QE 7zcx3Wib3YoA8Vtp9mOxNHTkQHqgGbtAAzvDKDjBky5yqOhJexuzsbcTba0qvbsEkqXL 15ggeu5UBqYwv+AiB4VJ5pD/Gs01zyBdShs9os9EyO76PNYYv/iAPB+zWXUkqxjtnKp2 XMEBG2bLHPxR36soDbngMm7UYDSFoQ21d9fNNknG+AsGJChCTi7e7X6Y89kVAUX4pvLh 1ivA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=JuHNthdA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.09.59.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 09:59:36 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 02/38] KVM: arm/arm64: Enable nested virtualization via command-line Date: Tue, 18 Jul 2017 11:58:28 -0500 Message-Id: <1500397144-16232-3-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a new kernel parameter(kvm-arm.nested) to enable KVM/ARM nested virtualization support. This kernel parameter on arm architecture is ignored since nested virtualization is not supported on arm. Note that this kernel parameter will not have any impact until nested virtualization support is completed. Just add this parameter first to use it when implementing nested virtualization support. Signed-off-by: Jintack Lim --- Documentation/admin-guide/kernel-parameters.txt | 4 ++++ arch/arm/include/asm/kvm_host.h | 4 ++++ arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/kvm/Makefile | 2 ++ arch/arm64/kvm/nested.c | 26 +++++++++++++++++++++++++ virt/kvm/arm/arm.c | 2 ++ 6 files changed, 40 insertions(+) create mode 100644 arch/arm64/kvm/nested.c -- 1.9.1 diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index aa8341e..8fb152d 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1841,6 +1841,10 @@ [KVM,ARM] Trap guest accesses to GICv3 common system registers + kvm-arm.nested= + [KVM,ARM] Allow nested virtualization in KVM/ARM. + Default is 0 (disabled) + kvm-intel.ept= [KVM,Intel] Disable extended page tables (virtualized MMU) support on capable Intel chips. Default is 1 (enabled) diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h index 127e2dd..00b0f97 100644 --- a/arch/arm/include/asm/kvm_host.h +++ b/arch/arm/include/asm/kvm_host.h @@ -299,4 +299,8 @@ int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); +static inline int __init kvmarm_nested_cfg(char *buf) +{ + return 0; +} #endif /* __ARM_KVM_HOST_H__ */ diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 0c4fd1f..dcc4df8 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -386,4 +386,6 @@ static inline void __cpu_init_stage2(void) "PARange is %d bits, unsupported configuration!", parange); } +int __init kvmarm_nested_cfg(char *buf); + #endif /* __ARM64_KVM_HOST_H__ */ diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile index 5d98100..f513047 100644 --- a/arch/arm64/kvm/Makefile +++ b/arch/arm64/kvm/Makefile @@ -35,3 +35,5 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-debug.o kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/irqchip.o kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arch_timer.o kvm-$(CONFIG_KVM_ARM_PMU) += $(KVM)/arm/pmu.o + +kvm-$(CONFIG_KVM_ARM_HOST) += nested.o diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c new file mode 100644 index 0000000..79f38da --- /dev/null +++ b/arch/arm64/kvm/nested.c @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2017 - Columbia University and Linaro Ltd. + * Author: Jintack Lim + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +static bool nested_param; + +int __init kvmarm_nested_cfg(char *buf) +{ + return strtobool(buf, &nested_param); +} diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index a39a1e1..1c1c772 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -67,6 +67,8 @@ static DEFINE_PER_CPU(unsigned char, kvm_arm_hardware_enabled); +early_param("kvm-arm.nested", kvmarm_nested_cfg); + static void kvm_arm_set_running_vcpu(struct kvm_vcpu *vcpu) { BUG_ON(preemptible()); From patchwork Tue Jul 18 16:58:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108142 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6148156obm; Tue, 18 Jul 2017 09:59:46 -0700 (PDT) X-Received: by 10.99.52.72 with SMTP id b69mr2735329pga.240.1500397186071; Tue, 18 Jul 2017 09:59:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397186; cv=none; d=google.com; s=arc-20160816; b=ntci4HpRg87A/7flkqQYHNhmn1RHjtz0OANhlN2Pu3VbkclbAr3SQwOsGeMexewOrd EVhS9serObBx00ohUNZcuxCvETaEJXcCSJXI6hYmat6B0kczyVBHHSYOn1RRxTBN+jm6 n4M4HuGesZ2drib4WZqxA3GAjqu7TWDl9n3FPzAFWuOIizrVubi6+tLE0b19ze99YCKY hXACzgTofgGTOJ12caFgLTKePRrYGOF1jEFcBnuA/jdERt9ZG4ZpyDSU+WkTtPNh6kw5 yrzY0c36Lk5qGdfukFmq8h6h0aAU1A225qJTPQifPdm1/ydOFfDreegtqYHgocfC/cuu 90Mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=NHh5RazUl2Nkio6vZFiVbdU8c6ChO4/5Unh/TqNnEvc=; b=u/4aG6bC23l0WuMrsjYk5+WVLIVqPYQ390uRDIN1cVgKcvS0f9TrTqmoGXsHpKBQ9d vQSgZ2Dn2tXemeacCOfWFkmdrzJBvlZggwQvV4XAsHEuNCK5BxAkSjWvsGK81DD83r46 1rQAk4rz6MYi6JOsksAkZzkXcSYQ0iisya+PpXGv8zmq1PVbTSQnauPK4dbZTQXxkkN/ gfwcvOTRmctAZaCEu1vDJrecWRsga8+5qYGz5gGPtIolsgQYQvY5mHGMx96y8jHRbvuy RZVSObYTdu6ROPjhbvd6p15FsyqEz8wmBcbKhudD9s7l9+8OMO/hr70LpHd2G1o1ICLw 8BSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=Lijnh/uv; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.09.59.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 09:59:38 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 03/38] KVM: arm64: Add KVM nesting feature Date: Tue, 18 Jul 2017 11:58:29 -0500 Message-Id: <1500397144-16232-4-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Christoffer Dall Set the initial exception level of the guest to EL2 if nested virtualization feature is enabled. Signed-off-by: Christoffer Dall Signed-off-by: Jintack Lim --- arch/arm64/include/asm/kvm_host.h | 2 +- arch/arm64/include/uapi/asm/kvm.h | 1 + arch/arm64/kvm/reset.c | 8 ++++++++ 3 files changed, 10 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index dcc4df8..6df0c7c 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -39,7 +39,7 @@ #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS -#define KVM_VCPU_MAX_FEATURES 4 +#define KVM_VCPU_MAX_FEATURES 5 #define KVM_REQ_SLEEP \ KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index 9f3ca24..4a71a72 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -99,6 +99,7 @@ struct kvm_regs { #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ #define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */ +#define KVM_ARM_VCPU_NESTED_VIRT 4 /* Support nested virtualization */ struct kvm_vcpu_init { __u32 target; diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 3256b92..1353516 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -41,6 +41,11 @@ PSR_F_BIT | PSR_D_BIT), }; +static const struct kvm_regs default_regs_reset_el2 = { + .regs.pstate = (PSR_MODE_EL2h | PSR_A_BIT | PSR_I_BIT | + PSR_F_BIT | PSR_D_BIT), +}; + static const struct kvm_regs default_regs_reset32 = { .regs.pstate = (COMPAT_PSR_MODE_SVC | COMPAT_PSR_A_BIT | COMPAT_PSR_I_BIT | COMPAT_PSR_F_BIT), @@ -106,6 +111,9 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) if (!cpu_has_32bit_el1()) return -EINVAL; cpu_reset = &default_regs_reset32; + } else if (test_bit(KVM_ARM_VCPU_NESTED_VIRT, + vcpu->arch.features)) { + cpu_reset = &default_regs_reset_el2; } else { cpu_reset = &default_regs_reset; } From patchwork Tue Jul 18 16:58:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108180 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp6193664qge; Tue, 18 Jul 2017 10:12:49 -0700 (PDT) X-Received: by 10.98.67.82 with SMTP id q79mr2745768pfa.121.1500397969388; Tue, 18 Jul 2017 10:12:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397969; cv=none; d=google.com; s=arc-20160816; b=BO8Rq4OVjhdREt4d1BVwFf6tkwJvamUTeLAywz4M2/9g5soi8SdBorhb3R+QaRzx06 vHKRZBcFtBrMbqRswdoZXkoXw6ZY1RnZOY44EXGUlQnQcCW7alXegGP91j1Y8m5NfMuE v3oOuS0/8KQdS9FmGgjkb54MnVXUqJG1IBPCRQX1XRWRLC8PTFJ/RGiNg52vyp3LJAgw P+F5Kg7IevDY/FN4m5gZvV/6E880UAij4Q/bUSJ2VR5cue4dttvMkNJL6b5wfiP2a4AS j5Lx4mJSdnvRkDaiS/YjUOAJyebJG9RsfOZ+Jm0fUnugyJMsFMZ5wfvxVvFaHz4G8OL+ ldXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=xzZF34TOJYqmhTjpA6ipdsQmbyVV8Q6Nja1JgJcypaI=; b=LseAOgXMVccocmrKfmuPmXuWG7XCa0D8zwcm7oefC2jnRwJafL+DW9nUW4Y2duBwwK E1OBG3olGiuAnZ5pyjb9d6OpR2bg5XivaRxhKgn7Zzc610ZJHNMT6KHng1EQsKtIteaL 7A/44x5t4zjgPu5OsdKAYNzU2w9KzRiWgfFeixnXpR1gtXQaxwHcI5Oa58I0u4ykbuqJ DxuuUU8i5PcKI8mjaQ/bdU5FgjJe3+qRaDyHPMqyIwkFVxC6JYabNoLV8z3HkUXcsMrd jSWLDsaMh20QGxHiriPl2Y6f2Q2ansD3JVxTdi/WbiuwM0WLrHUpd0xaB1eNIa9eolIO PAug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=UgKXjw5F; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.09.59.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 09:59:40 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 04/38] KVM: arm/arm64: Check if nested virtualization is in use Date: Tue, 18 Jul 2017 11:58:30 -0500 Message-Id: <1500397144-16232-5-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Nested virtualizaion is in use only if all three conditions are met: - The architecture supports nested virtualization. - The kernel parameter is set. - The userspace uses nested virtualiztion feature. Signed-off-by: Jintack Lim --- arch/arm/include/asm/kvm_host.h | 11 +++++++++++ arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/kvm/nested.c | 17 +++++++++++++++++ virt/kvm/arm/arm.c | 4 ++++ 4 files changed, 34 insertions(+) -- 1.9.1 diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h index 00b0f97..7e9e6c8 100644 --- a/arch/arm/include/asm/kvm_host.h +++ b/arch/arm/include/asm/kvm_host.h @@ -303,4 +303,15 @@ static inline int __init kvmarm_nested_cfg(char *buf) { return 0; } + +static inline int init_nested_virt(void) +{ + return 0; +} + +static inline bool nested_virt_in_use(struct kvm_vcpu *vcpu) +{ + return false; +} + #endif /* __ARM_KVM_HOST_H__ */ diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 6df0c7c..86d4b6c 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -387,5 +387,7 @@ static inline void __cpu_init_stage2(void) } int __init kvmarm_nested_cfg(char *buf); +int init_nested_virt(void); +bool nested_virt_in_use(struct kvm_vcpu *vcpu); #endif /* __ARM64_KVM_HOST_H__ */ diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index 79f38da..9a05c76 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -24,3 +24,20 @@ int __init kvmarm_nested_cfg(char *buf) { return strtobool(buf, &nested_param); } + +int init_nested_virt(void) +{ + if (nested_param && cpus_have_const_cap(ARM64_HAS_NESTED_VIRT)) + kvm_info("Nested virtualization is supported\n"); + + return 0; +} + +bool nested_virt_in_use(struct kvm_vcpu *vcpu) +{ + if (nested_param && cpus_have_const_cap(ARM64_HAS_NESTED_VIRT) + && test_bit(KVM_ARM_VCPU_NESTED_VIRT, vcpu->arch.features)) + return true; + + return false; +} diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index 1c1c772..36aae3a 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -1478,6 +1478,10 @@ int kvm_arch_init(void *opaque) if (err) goto out_err; + err = init_nested_virt(); + if (err) + return err; + err = init_subsystems(); if (err) goto out_hyp; From patchwork Tue Jul 18 16:58:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108143 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6148296obm; Tue, 18 Jul 2017 09:59:54 -0700 (PDT) X-Received: by 10.84.209.205 with SMTP id y71mr2709315plh.85.1500397194384; Tue, 18 Jul 2017 09:59:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397194; cv=none; d=google.com; s=arc-20160816; b=Qg4zclvDw08rkRnvvtdJn6T+O9kaktmwI88RAtIevH9zSziyjMz+bRbmsZaS5H5jyg /FauR9jwLF93bJ/lwVSLRVq+HYMcr7Ib0SFqtVraNr4CYdmqWHdISuogFEMIbCjvReTB bR+NaSTneSCVTKTnrJwHJz8mYw37imkFW3vV34bU3nuDY217mYEhaTFSYcqyL3K0EvEF L3aQJcX0dKQP+GkxoMRBj5gkISZHpJOZv+CBLhwFhz24ffGrSjqLoPAUWaKYRj3FPwpz zS/7MuzOxXaJiVes2WgeLfy7tjQpQw8aXgySuBjnBAMQn0bQV4MmWbrmToE4t+PduRif 9oTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=+m5y/Wd5Rco9GT4iaOG3yHTn/eMhdoJikTUfbpTHXHo=; b=RP7ZogRefEW4F/IBWvIeQqVqfNxplNOA/lLmXFslXwWi728Ji/Zh8EJtxICULHrJW2 NJAY/0sPdrEwUxsFFOlgEwk33dylI1lV9r1JXEX5G1I1/5w2A9S7QvFT66joXc27bRSU KjsnbOfGeiCeZ8FxGM2IsiJeZYWXvqw5d4LvbDW2wz4d0GXfpInvHnWvPEHMyWKhE0uC UGB3jg+dgCFjJ5SL43L+L02+xAgSQA2qdwcOb6LIYFIRO2hup/j2P1eZutU5VLg0AnRh NY/fChlnRztn/4lR2ov/5pF4qluQw5PAd3J1E5sQbnEgCQpEzpFMrDjURn5rPsSNg402 93Tw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=HuTsSxhG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.09.59.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 09:59:42 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH v2 05/38] KVM: arm64: Allow userspace to set PSR_MODE_EL2x Date: Tue, 18 Jul 2017 11:58:31 -0500 Message-Id: <1500397144-16232-6-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Christoffer Dall We were not allowing userspace to set a more privileged mode for the VCPU than EL1, but now that we support nesting with a virtual EL2 mode, do allow this! Signed-off-by: Christoffer Dall --- arch/arm64/kvm/guest.c | 2 ++ 1 file changed, 2 insertions(+) -- 1.9.1 diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 5c7f657..5e673ae 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -117,6 +117,8 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) case PSR_MODE_EL0t: case PSR_MODE_EL1t: case PSR_MODE_EL1h: + case PSR_MODE_EL2h: + case PSR_MODE_EL2t: break; default: err = -EINVAL; From patchwork Tue Jul 18 16:58:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108179 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp6193047qge; Tue, 18 Jul 2017 10:12:22 -0700 (PDT) X-Received: by 10.98.102.85 with SMTP id a82mr2820680pfc.82.1500397942375; Tue, 18 Jul 2017 10:12:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397942; cv=none; d=google.com; s=arc-20160816; b=bPFvmrTVuDtc4ufvO5Nq3rLN21BkmDxX458laNvV+HsDKdm9wCXWelbAoxjqqyyV3F E0s8xsb6SWA4XeuBuG251yoDGw7eUtu8wJthUnR8YGq4+TnCdBGYDsGdqRmZiclzufQH xyLhWHzAM155uLMoVK8xNLPpuyXicTCKNE09fWtbWD+MefuGv7NeEW3NtMT0V5ZrMm4K bu5HxoIFJ3OBy0T0T1peMt3wPmjln2fWVcss09st2MxpRMXyRO91wNSJj/R5eaYPKo8C fWBD1qZzKmS0tzFiVSkAVw+IeAanVOzQ52bysta34D+1GhNUFeiT23jXd6Vtosqjyiz5 70JQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=/mtq4MWeiH7riv+htGWNDtS6ajNnnh73naJGKoVzYsg=; b=CT/bFoJUlL6Gz4wGYXn2gJWuCfqPVap59BEk/bOFPWsOWnE1jaK1lS8Vat2d/9biBL LH22BAoYE5xgEHtWjmJib4Z+SgJNPWN8/Fz5fgmB7FwqyNnuEMalarUQinKCXXwtJih2 zqEQJvTzNCROajml029L3D34KA1ixrjl+ahXurlQ+bDueqqXG1IGKwMyEWjgZBjEz8a4 LUsnx/0hAM/Knzb0JzrCtlTQXWCCJXeY7pqbbC76e2TtzCg5Lko6R5F9iPpzPHg/xwWI XYRLnGf61/43NQyiw5tgUeC6v6zZqbYtZ0jQCDEv5uefiZaVoMyBeycGJfnRR1ll+bm/ Xnjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=gNE+vTeA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.09.59.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 09:59:43 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH v2 06/38] KVM: arm64: Add vcpu_mode_el2 primitive to support nesting Date: Tue, 18 Jul 2017 11:58:32 -0500 Message-Id: <1500397144-16232-7-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Christoffer Dall When running a nested hypervisor we occasionally have to figure out if the mode we are switching into is the virtual EL2 mode or a regular EL0/1 mode. Signed-off-by: Christoffer Dall --- arch/arm/include/asm/kvm_emulate.h | 6 ++++++ arch/arm64/include/asm/kvm_emulate.h | 12 ++++++++++++ 2 files changed, 18 insertions(+) -- 1.9.1 diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h index 9a8a45a..399cd75e 100644 --- a/arch/arm/include/asm/kvm_emulate.h +++ b/arch/arm/include/asm/kvm_emulate.h @@ -77,6 +77,12 @@ static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu) return 1; } +/* We don't support nesting on arm */ +static inline bool vcpu_mode_el2(const struct kvm_vcpu *vcpu) +{ + return false; +} + static inline unsigned long *vcpu_pc(struct kvm_vcpu *vcpu) { return &vcpu->arch.ctxt.gp_regs.usr_regs.ARM_pc; diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index fe39e68..5d6f3d0 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -143,6 +143,18 @@ static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) return mode != PSR_MODE_EL0t; } +static inline bool vcpu_mode_el2(const struct kvm_vcpu *vcpu) +{ + u32 mode; + + if (vcpu_mode_is_32bit(vcpu)) + return false; + + mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK; + + return mode == PSR_MODE_EL2h || mode == PSR_MODE_EL2t; +} + static inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu) { return vcpu->arch.fault.esr_el2; From patchwork Tue Jul 18 16:58:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108178 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp6192511qge; Tue, 18 Jul 2017 10:12:00 -0700 (PDT) X-Received: by 10.98.131.143 with SMTP id h137mr2732581pfe.132.1500397920011; Tue, 18 Jul 2017 10:12:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397920; cv=none; d=google.com; s=arc-20160816; b=NoiUwg9idumLRV0cZjnxHH9goFvmKJWmaILmIZTqpnrVzcFfibqk/MuiWfQkjyug+W wiyVEuuv4Z5X75rl5H+catN/igCkHt2A2MytyI7TRJK/GPFTLMo+ey7qkNPC2OvxApcj xC2yuV586bhV+oUYFEeDbE8RR/HCntrO//RP1XASezDf1psyEJNMRz06/DgTouGHW0Lw lgcaAFAGhe5zdamkE4VfhzsIzk/9iI3f1Mp+dFPLfHY18FB/EsVNQYNywMVd1dMpdSaY MmNccNgIH8PPtS4qeT2+bnID0Em3RNHiNyHM3aT9owwG+gMU+K1nn1DI4umVDDvc8DAG 2VWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=8Gbw2wwJ1dAVk5oSh2Xat+r2c3s06aQBQPctLxCA/24=; b=aCdOYAnmNEpdiAuU/EjnyMNO4PlpqxGqTgGG6oLRfRdSkq3bqytNOcP4+z1laDPHWN 15JX2ar32dE0b5tjl/0XjvLYxfT+AiYp3KXzd5UbbB7hnqxoyvZLJ4KVyfYHjK4Gafm0 jAecA0vkAx02ZMXYe4gj+7FuUjcprba+mje65I1KKGMbwkCnel3uY+y5O7KmyIAbggC6 AnH8uOhGMXSG2zjXeyGe4HZaBAzrnPZ0Tvp5qXF49zic5kJxE9UPaHxU3wSoDHWQpS2F qeyE4FhTyhS/BuXyZ2cYPe1rxIAbscfh0pZi2f5HieJtQZhG4VgZhmbk5myi3ae2lZb+ F97g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=gGkcHH2a; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.09.59.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 09:59:45 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 07/38] KVM: arm64: Add EL2 system registers to vcpu context Date: Tue, 18 Jul 2017 11:58:33 -0500 Message-Id: <1500397144-16232-8-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ARM v8.3 introduces a new bit in the HCR_EL2, which is the NV bit. When this bit is set, accessing EL2 registers in EL1 traps to EL2. In addition, executing the following instructions in EL1 will trap to EL2: tlbi, at, eret, and msr/mrs instructions to access SP_EL1. Most of the instructions that trap to EL2 with the NV bit were undef at EL1 prior to ARM v8.3. The only instruction that was not undef is eret. This patch sets up a handler for EL2 registers and SP_EL1 register accesses at EL1. The host hypervisor keeps those register values in memory, and will emulate their behavior. This patch doesn't set the NV bit yet. It will be set in a later patch once nested virtualization support is completed. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/kvm_host.h | 30 +++++++++++++++++++- arch/arm64/include/asm/sysreg.h | 37 +++++++++++++++++++++++++ arch/arm64/kvm/sys_regs.c | 58 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 124 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 86d4b6c..1dc4ed6 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -134,12 +134,40 @@ enum vcpu_sysreg { PMSWINC_EL0, /* Software Increment Register */ PMUSERENR_EL0, /* User Enable Register */ - /* 32bit specific registers. Keep them at the end of the range */ + /* 32bit specific registers. */ DACR32_EL2, /* Domain Access Control Register */ IFSR32_EL2, /* Instruction Fault Status Register */ FPEXC32_EL2, /* Floating-Point Exception Control Register */ DBGVCR32_EL2, /* Debug Vector Catch Register */ + /* EL2 registers sorted ascending by Op0, Op1, CRn, CRm, Op2 */ + VPIDR_EL2, /* Virtualization Processor ID Register */ + VMPIDR_EL2, /* Virtualization Multiprocessor ID Register */ + SCTLR_EL2, /* System Control Register (EL2) */ + ACTLR_EL2, /* Auxiliary Control Register (EL2) */ + HCR_EL2, /* Hypervisor Configuration Register */ + MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ + CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ + HSTR_EL2, /* Hypervisor System Trap Register */ + HACR_EL2, /* Hypervisor Auxiliary Control Register */ + TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ + TCR_EL2, /* Translation Control Register (EL2) */ + VTTBR_EL2, /* Virtualization Translation Table Base Register */ + VTCR_EL2, /* Virtualization Translation Control Register */ + AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ + AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */ + ESR_EL2, /* Exception Syndrome Register (EL2) */ + FAR_EL2, /* Hypervisor IPA Fault Address Register */ + HPFAR_EL2, /* Hypervisor IPA Fault Address Register */ + MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */ + AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */ + VBAR_EL2, /* Vector Base Address Register (EL2) */ + RVBAR_EL2, /* Reset Vector Base Address Register */ + RMR_EL2, /* Reset Management Register */ + TPIDR_EL2, /* EL2 Software Thread ID Register */ + CNTVOFF_EL2, /* Counter-timer Virtual Offset register */ + CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ + NR_SYS_REGS /* Nothing after this line! */ }; diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 737ca30..9277c4a 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -250,10 +250,42 @@ #define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7) +#define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0) +#define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5) + +#define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) +#define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1) +#define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0) +#define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1) +#define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2) +#define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3) +#define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7) + +#define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0) +#define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2) +#define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) +#define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) + #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) + +#define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0) + #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) +#define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0) +#define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1) +#define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0) #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) +#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0) +#define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4) + +#define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0) +#define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0) + +#define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0) +#define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1) +#define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2) + #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) @@ -295,6 +327,11 @@ #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) +#define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2) + +#define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3) +#define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0) + /* Common SCTLR_ELx flags. */ #define SCTLR_ELx_EE (1 << 25) #define SCTLR_ELx_I (1 << 12) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 7786288..1568f8b 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -892,6 +892,27 @@ static bool access_cntp_cval(struct kvm_vcpu *vcpu, return true; } +static inline void access_rw(struct sys_reg_params *p, u64 *sysreg) +{ + if (!p->is_write) + p->regval = *sysreg; + else + *sysreg = p->regval; +} + +static bool trap_el2_regs(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + /* SP_EL1 is NOT maintained in sys_regs array */ + if (sys_reg(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2) == SYS_SP_EL1) + access_rw(p, &vcpu->arch.ctxt.gp_regs.sp_el1); + else + access_rw(p, &vcpu_sys_reg(vcpu, r->reg)); + + return true; +} + /* * Architected system registers. * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 @@ -1077,9 +1098,46 @@ static bool access_cntp_cval(struct kvm_vcpu *vcpu, */ { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 }, + { SYS_DESC(SYS_VPIDR_EL2), trap_el2_regs, reset_val, VPIDR_EL2, 0 }, + { SYS_DESC(SYS_VMPIDR_EL2), trap_el2_regs, reset_val, VMPIDR_EL2, 0 }, + + { SYS_DESC(SYS_SCTLR_EL2), trap_el2_regs, reset_val, SCTLR_EL2, 0 }, + { SYS_DESC(SYS_ACTLR_EL2), trap_el2_regs, reset_val, ACTLR_EL2, 0 }, + { SYS_DESC(SYS_HCR_EL2), trap_el2_regs, reset_val, HCR_EL2, 0 }, + { SYS_DESC(SYS_MDCR_EL2), trap_el2_regs, reset_val, MDCR_EL2, 0 }, + { SYS_DESC(SYS_CPTR_EL2), trap_el2_regs, reset_val, CPTR_EL2, 0 }, + { SYS_DESC(SYS_HSTR_EL2), trap_el2_regs, reset_val, HSTR_EL2, 0 }, + { SYS_DESC(SYS_HACR_EL2), trap_el2_regs, reset_val, HACR_EL2, 0 }, + + { SYS_DESC(SYS_TTBR0_EL2), trap_el2_regs, reset_val, TTBR0_EL2, 0 }, + { SYS_DESC(SYS_TCR_EL2), trap_el2_regs, reset_val, TCR_EL2, 0 }, + { SYS_DESC(SYS_VTTBR_EL2), trap_el2_regs, reset_val, VTTBR_EL2, 0 }, + { SYS_DESC(SYS_VTCR_EL2), trap_el2_regs, reset_val, VTCR_EL2, 0 }, + { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, + + { SYS_DESC(SYS_SP_EL1), trap_el2_regs }, + { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, + { SYS_DESC(SYS_AFSR0_EL2), trap_el2_regs, reset_val, AFSR0_EL2, 0 }, + { SYS_DESC(SYS_AFSR1_EL2), trap_el2_regs, reset_val, AFSR1_EL2, 0 }, + { SYS_DESC(SYS_ESR_EL2), trap_el2_regs, reset_val, ESR_EL2, 0 }, { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x70 }, + + { SYS_DESC(SYS_FAR_EL2), trap_el2_regs, reset_val, FAR_EL2, 0 }, + { SYS_DESC(SYS_HPFAR_EL2), trap_el2_regs, reset_val, HPFAR_EL2, 0 }, + + { SYS_DESC(SYS_MAIR_EL2), trap_el2_regs, reset_val, MAIR_EL2, 0 }, + { SYS_DESC(SYS_AMAIR_EL2), trap_el2_regs, reset_val, AMAIR_EL2, 0 }, + + { SYS_DESC(SYS_VBAR_EL2), trap_el2_regs, reset_val, VBAR_EL2, 0 }, + { SYS_DESC(SYS_RVBAR_EL2), trap_el2_regs, reset_val, RVBAR_EL2, 0 }, + { SYS_DESC(SYS_RMR_EL2), trap_el2_regs, reset_val, RMR_EL2, 0 }, + + { SYS_DESC(SYS_TPIDR_EL2), trap_el2_regs, reset_val, TPIDR_EL2, 0 }, + + { SYS_DESC(SYS_CNTVOFF_EL2), trap_el2_regs, reset_val, CNTVOFF_EL2, 0 }, + { SYS_DESC(SYS_CNTHCTL_EL2), trap_el2_regs, reset_val, CNTHCTL_EL2, 0 }, }; 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.09.59.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 09:59:47 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 08/38] KVM: arm64: Add EL2 special registers to vcpu context Date: Tue, 18 Jul 2017 11:58:34 -0500 Message-Id: <1500397144-16232-9-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To support the virtual EL2 execution, we need to maintain the EL2 special registers such as SPSR_EL2, ELR_EL2 and SP_EL2 in vcpu context. Note that SP_EL2 is not accessible in EL2, so we don't need a trap handler for this register. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/kvm_host.h | 12 ++++++++++++ arch/arm64/include/asm/sysreg.h | 4 ++++ arch/arm64/kvm/sys_regs.c | 38 +++++++++++++++++++++++++++++++++----- arch/arm64/kvm/sys_regs.h | 8 ++++++++ 4 files changed, 57 insertions(+), 5 deletions(-) -- 1.9.1 diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 1dc4ed6..57dccde 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -171,6 +171,15 @@ enum vcpu_sysreg { NR_SYS_REGS /* Nothing after this line! */ }; +enum el2_special_regs { + __INVALID_EL2_SPECIAL_REG__, + SPSR_EL2, /* Saved Program Status Register (EL2) */ + ELR_EL2, /* Exception Link Register (EL2) */ + SP_EL2, /* Stack Pointer (EL2) */ + + NR_EL2_SPECIAL_REGS +}; + /* 32bit mapping */ #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ @@ -218,6 +227,8 @@ struct kvm_cpu_context { u64 sys_regs[NR_SYS_REGS]; u32 copro[NR_COPRO_REGS]; }; + + u64 el2_special_regs[NR_EL2_SPECIAL_REGS]; }; typedef struct kvm_cpu_context kvm_cpu_context_t; @@ -307,6 +318,7 @@ struct kvm_vcpu_arch { #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs) #define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)]) +#define vcpu_el2_sreg(v,r) ((v)->arch.ctxt.el2_special_regs[(r)]) /* * CP14 and CP15 live in the same array, as they are backed by the * same system registers. diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9277c4a..98c32ef 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -268,6 +268,8 @@ #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) +#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) +#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0) #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) @@ -332,6 +334,8 @@ #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3) #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0) +#define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0) + /* Common SCTLR_ELx flags. */ #define SCTLR_ELx_EE (1 << 25) #define SCTLR_ELx_I (1 << 12) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 1568f8b..2b3ed70 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -900,15 +900,33 @@ static inline void access_rw(struct sys_reg_params *p, u64 *sysreg) *sysreg = p->regval; } +static u64 *get_special_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p) +{ + u64 reg = sys_reg(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); + + switch (reg) { + case SYS_SP_EL1: + return &vcpu->arch.ctxt.gp_regs.sp_el1; + case SYS_ELR_EL2: + return &vcpu_el2_sreg(vcpu, ELR_EL2); + case SYS_SPSR_EL2: + return &vcpu_el2_sreg(vcpu, SPSR_EL2); + default: + return NULL; + }; +} + static bool trap_el2_regs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - /* SP_EL1 is NOT maintained in sys_regs array */ - if (sys_reg(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2) == SYS_SP_EL1) - access_rw(p, &vcpu->arch.ctxt.gp_regs.sp_el1); - else - access_rw(p, &vcpu_sys_reg(vcpu, r->reg)); + u64 *sys_reg; + + sys_reg = get_special_reg(vcpu, p); + if (!sys_reg) + sys_reg = &vcpu_sys_reg(vcpu, r->reg); + + access_rw(p, sys_reg); return true; } @@ -1116,6 +1134,8 @@ static bool trap_el2_regs(struct kvm_vcpu *vcpu, { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, + { SYS_DESC(SYS_SPSR_EL2), trap_el2_regs, reset_special, SPSR_EL2, 0 }, + { SYS_DESC(SYS_ELR_EL2), trap_el2_regs, reset_special, ELR_EL2, 0 }, { SYS_DESC(SYS_SP_EL1), trap_el2_regs }, { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, @@ -1138,6 +1158,8 @@ static bool trap_el2_regs(struct kvm_vcpu *vcpu, { SYS_DESC(SYS_CNTVOFF_EL2), trap_el2_regs, reset_val, CNTVOFF_EL2, 0 }, { SYS_DESC(SYS_CNTHCTL_EL2), trap_el2_regs, reset_val, CNTHCTL_EL2, 0 }, + + { SYS_DESC(SYS_SP_EL2), NULL, reset_special, SP_EL2, 0}, }; static bool trap_dbgidr(struct kvm_vcpu *vcpu, @@ -2271,6 +2293,8 @@ void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) /* Catch someone adding a register without putting in reset entry. */ memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs)); + memset(&vcpu->arch.ctxt.el2_special_regs, 0x42, + sizeof(vcpu->arch.ctxt.el2_special_regs)); /* Generic chip reset first (so target could override). */ reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); @@ -2281,4 +2305,8 @@ void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) for (num = 1; num < NR_SYS_REGS; num++) if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242) panic("Didn't reset vcpu_sys_reg(%zi)", num); + + for (num = 1; num < NR_EL2_SPECIAL_REGS; num++) + if (vcpu_el2_sreg(vcpu, num) == 0x4242424242424242) + panic("Didn't reset vcpu_el2_sreg(%zi)", num); } diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h index 060f534..827717b 100644 --- a/arch/arm64/kvm/sys_regs.h +++ b/arch/arm64/kvm/sys_regs.h @@ -99,6 +99,14 @@ static inline void reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r vcpu_sys_reg(vcpu, r->reg) = r->val; } +static inline void reset_special(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *r) +{ + BUG_ON(!r->reg); + BUG_ON(r->reg >= NR_EL2_SPECIAL_REGS); + vcpu_el2_sreg(vcpu, r->reg) = r->val; +} + static inline int cmp_sys_reg(const struct sys_reg_desc *i1, const struct sys_reg_desc *i2) { From patchwork Tue Jul 18 16:58:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108174 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp6190472qge; Tue, 18 Jul 2017 10:10:24 -0700 (PDT) X-Received: by 10.84.232.8 with SMTP id h8mr2882871plk.252.1500397824459; Tue, 18 Jul 2017 10:10:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397824; cv=none; d=google.com; s=arc-20160816; b=fx/T0zpDqwmHSfiHXudwIjB8e6wJ92SRr4gMg6kuNMxlVWlHt46rUlN3wCyN/xkNEg OxWLxmydwGy3jzPS1RJhnKLdiOkEMXSgMzfHZJtj4pjB7ZBYnDBdgSFWtyuczDiOTF2q mck5jxk+GexKDEnqau+k2b4f/7fycSp6+8qlx2V7lK9ONNNnBbg6erZmNyFfxlgNmARW klZFwAblvBDVBhWlqS/lXkwst4YOiO7BErHEmFnOhO1sgvRQ2/bJWLcIvP158j2wA0MA /lgOuejU+cqKATv2WLE3DhhbTArnrayuegc2DYgNy12QEF6m41KRRdcXoNwBfd/WT4Tc ofaA== ARC-Message-Signature: i=1; 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.09.59.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 09:59:48 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 09/38] KVM: arm64: Add the shadow context for virtual EL2 execution Date: Tue, 18 Jul 2017 11:58:35 -0500 Message-Id: <1500397144-16232-10-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org With the nested virtualization support, a hypervisor running inside a VM (i.e. a guest hypervisor) is now deprivilaged and runs in EL1 instead of EL2. So, the host hypervisor manages the shadow context for the virtual EL2 execution. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/kvm_host.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 1.9.1 diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 57dccde..46880c3 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -229,6 +229,19 @@ struct kvm_cpu_context { }; u64 el2_special_regs[NR_EL2_SPECIAL_REGS]; + + u64 shadow_sys_regs[NR_SYS_REGS]; /* only used for virtual EL2 */ + + /* + * hw_* will be written to the hardware when entering to a VM. + * They have either the virtual EL2 or EL1/EL0 context depending + * on the vcpu mode. + */ + u64 *hw_sys_regs; + u64 hw_sp_el1; + u64 hw_pstate; + u64 hw_elr_el1; + u64 hw_spsr_el1; }; typedef struct kvm_cpu_context kvm_cpu_context_t; From patchwork Tue Jul 18 16:58:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108176 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp6191766qge; Tue, 18 Jul 2017 10:11:21 -0700 (PDT) X-Received: by 10.98.35.214 with SMTP id q83mr2782423pfj.101.1500397881082; Tue, 18 Jul 2017 10:11:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397881; cv=none; d=google.com; s=arc-20160816; b=fZa4hTLGPchCIPnLe2JQ1lvvWB6hAc6oe7JTSGdlnN6Nz5M639MpUUz95cAVDr/RaC cRQN9Qhc4wYpvlSX/UZeaQ3KpcNv9TidK+5uKdBiZtBpQaZ2ac3Z9uGobDJtIYzvnZdI qKjY6CEE96OLiQo6wUFgMIJUuJ3/BpPk9fjCc3AS7mtHUEzUdvAc2qlQ8+0pzLJbITMU jtKDqG1JEkb3vwexo1ouoLJHN2E7os1LnAJc5nNqJBPZXZVnntfugDTFMWk6tFs5LJlF mk+L/BGA6ciND2IWaf0hzo3gRU5cWjm2lOpyCZqOHVZZjoukb63I+me8NZ8mHjwgSK1V gXLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=QjqGXKCkj7cTvfCR2elOA4s+vn/8R8M9iajH1+uBZDk=; b=s7GXptRE5cLGymM7rleYCvYd7eFLwir39+EtHQdhY/us5ezWEw5JwgTKr4CfpNASuf u0Er51wOIkukzCPpHhLYxaA1jvscDQKDleDXo/wg72yG7Hs6YHf91Y0Bdiab4u7J+8K9 ktX7Tj6WpYGMfV37EZK82M9kSWyHs9ZKuSd0ItOcud9WoUXniIKj0bZ2LNpLQdzdNiL+ b/xlDdDfyMucO0+PkzvosN2xTA2/DzOF/7knLlabqJ776Tbn2j1cdHP1omGgzTG+Q9jd MB7gr6gzK1VqwitADac50Y+7xt0I7Ermro1bNCLUz9VCJV9DFNH85zFXk3GgMSUCELA7 aVPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=eMwFnOyN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.09.59.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 09:59:50 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 10/38] KVM: arm/arm64: Add a framework to prepare virtual EL2 execution Date: Tue, 18 Jul 2017 11:58:36 -0500 Message-Id: <1500397144-16232-11-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Christoffer Dall Add functions setting up and restoring the guest's context on each entry and exit. These functions will come in handy when we want to use different context for normal EL0/EL1 and virtual EL2 execution. No functional change yet. Signed-off-by: Christoffer Dall Signed-off-by: Jintack Lim --- arch/arm/include/asm/kvm_emulate.h | 4 ++ arch/arm64/include/asm/kvm_emulate.h | 4 ++ arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/context.c | 54 ++++++++++++++++ arch/arm64/kvm/hyp/sysreg-sr.c | 117 +++++++++++++++++++---------------- virt/kvm/arm/arm.c | 14 +++++ 6 files changed, 140 insertions(+), 55 deletions(-) create mode 100644 arch/arm64/kvm/context.c -- 1.9.1 diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h index 399cd75e..0a03b7d 100644 --- a/arch/arm/include/asm/kvm_emulate.h +++ b/arch/arm/include/asm/kvm_emulate.h @@ -47,6 +47,10 @@ static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num, void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr); void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr); +static inline void kvm_arm_setup_shadow_state(struct kvm_vcpu *vcpu) { }; +static inline void kvm_arm_restore_shadow_state(struct kvm_vcpu *vcpu) { }; +static inline void kvm_arm_init_cpu_context(kvm_cpu_context_t *cpu_ctxt) { }; + static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu) { return kvm_condition_valid32(vcpu); diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index 5d6f3d0..14c4ce9 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -42,6 +42,10 @@ void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr); void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr); +void kvm_arm_setup_shadow_state(struct kvm_vcpu *vcpu); +void kvm_arm_restore_shadow_state(struct kvm_vcpu *vcpu); +void kvm_arm_init_cpu_context(kvm_cpu_context_t *cpu_ctxt); + static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) { vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS; diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile index f513047..5762337 100644 --- a/arch/arm64/kvm/Makefile +++ b/arch/arm64/kvm/Makefile @@ -15,7 +15,7 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o $(KVM)/e kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arm.o $(KVM)/arm/mmu.o $(KVM)/arm/mmio.o kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/psci.o $(KVM)/arm/perf.o -kvm-$(CONFIG_KVM_ARM_HOST) += inject_fault.o regmap.o +kvm-$(CONFIG_KVM_ARM_HOST) += inject_fault.o regmap.o context.o kvm-$(CONFIG_KVM_ARM_HOST) += hyp.o hyp-init.o handle_exit.o kvm-$(CONFIG_KVM_ARM_HOST) += guest.o debug.o reset.o sys_regs.o sys_regs_generic_v8.o kvm-$(CONFIG_KVM_ARM_HOST) += vgic-sys-reg-v3.o diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c new file mode 100644 index 0000000..bc43e66 --- /dev/null +++ b/arch/arm64/kvm/context.c @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2016 - Linaro Ltd. + * Author: Christoffer Dall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +/** + * kvm_arm_setup_shadow_state -- prepare shadow state based on emulated mode + * @vcpu: The VCPU pointer + */ +void kvm_arm_setup_shadow_state(struct kvm_vcpu *vcpu) +{ + struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; + + ctxt->hw_pstate = *vcpu_cpsr(vcpu); + ctxt->hw_sys_regs = ctxt->sys_regs; + ctxt->hw_sp_el1 = ctxt->gp_regs.sp_el1; + ctxt->hw_elr_el1 = ctxt->gp_regs.elr_el1; + ctxt->hw_spsr_el1 = ctxt->gp_regs.spsr[KVM_SPSR_EL1]; +} + +/** + * kvm_arm_restore_shadow_state -- write back shadow state from guest + * @vcpu: The VCPU pointer + */ +void kvm_arm_restore_shadow_state(struct kvm_vcpu *vcpu) +{ + struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; + + *vcpu_cpsr(vcpu) = ctxt->hw_pstate; + ctxt->gp_regs.sp_el1 = ctxt->hw_sp_el1; + ctxt->gp_regs.elr_el1 = ctxt->hw_elr_el1; + ctxt->gp_regs.spsr[KVM_SPSR_EL1] = ctxt->hw_spsr_el1; +} + +void kvm_arm_init_cpu_context(kvm_cpu_context_t *cpu_ctxt) +{ + /* This is to set hw_sys_regs of host_cpu_context */ + cpu_ctxt->hw_sys_regs = cpu_ctxt->sys_regs; +} diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c index 9341376..b7a67b1 100644 --- a/arch/arm64/kvm/hyp/sysreg-sr.c +++ b/arch/arm64/kvm/hyp/sysreg-sr.c @@ -19,6 +19,7 @@ #include #include +#include #include /* Yes, this does nothing, on purpose */ @@ -33,39 +34,43 @@ static void __hyp_text __sysreg_do_nothing(struct kvm_cpu_context *ctxt) { } static void __hyp_text __sysreg_save_common_state(struct kvm_cpu_context *ctxt) { - ctxt->sys_regs[ACTLR_EL1] = read_sysreg(actlr_el1); - ctxt->sys_regs[TPIDR_EL0] = read_sysreg(tpidr_el0); - ctxt->sys_regs[TPIDRRO_EL0] = read_sysreg(tpidrro_el0); - ctxt->sys_regs[TPIDR_EL1] = read_sysreg(tpidr_el1); - ctxt->sys_regs[MDSCR_EL1] = read_sysreg(mdscr_el1); + u64 *sys_regs = kern_hyp_va(ctxt->hw_sys_regs); + + sys_regs[ACTLR_EL1] = read_sysreg(actlr_el1); + sys_regs[TPIDR_EL0] = read_sysreg(tpidr_el0); + sys_regs[TPIDRRO_EL0] = read_sysreg(tpidrro_el0); + sys_regs[TPIDR_EL1] = read_sysreg(tpidr_el1); + sys_regs[MDSCR_EL1] = read_sysreg(mdscr_el1); ctxt->gp_regs.regs.sp = read_sysreg(sp_el0); ctxt->gp_regs.regs.pc = read_sysreg_el2(elr); - ctxt->gp_regs.regs.pstate = read_sysreg_el2(spsr); + ctxt->hw_pstate = read_sysreg_el2(spsr); } static void __hyp_text __sysreg_save_state(struct kvm_cpu_context *ctxt) { - ctxt->sys_regs[MPIDR_EL1] = read_sysreg(vmpidr_el2); - ctxt->sys_regs[CSSELR_EL1] = read_sysreg(csselr_el1); - ctxt->sys_regs[SCTLR_EL1] = read_sysreg_el1(sctlr); - ctxt->sys_regs[CPACR_EL1] = read_sysreg_el1(cpacr); - ctxt->sys_regs[TTBR0_EL1] = read_sysreg_el1(ttbr0); - ctxt->sys_regs[TTBR1_EL1] = read_sysreg_el1(ttbr1); - ctxt->sys_regs[TCR_EL1] = read_sysreg_el1(tcr); - ctxt->sys_regs[ESR_EL1] = read_sysreg_el1(esr); - ctxt->sys_regs[AFSR0_EL1] = read_sysreg_el1(afsr0); - ctxt->sys_regs[AFSR1_EL1] = read_sysreg_el1(afsr1); - ctxt->sys_regs[FAR_EL1] = read_sysreg_el1(far); - ctxt->sys_regs[MAIR_EL1] = read_sysreg_el1(mair); - ctxt->sys_regs[VBAR_EL1] = read_sysreg_el1(vbar); - ctxt->sys_regs[CONTEXTIDR_EL1] = read_sysreg_el1(contextidr); - ctxt->sys_regs[AMAIR_EL1] = read_sysreg_el1(amair); - ctxt->sys_regs[CNTKCTL_EL1] = read_sysreg_el1(cntkctl); - ctxt->sys_regs[PAR_EL1] = read_sysreg(par_el1); - - ctxt->gp_regs.sp_el1 = read_sysreg(sp_el1); - ctxt->gp_regs.elr_el1 = read_sysreg_el1(elr); - ctxt->gp_regs.spsr[KVM_SPSR_EL1]= read_sysreg_el1(spsr); + u64 *sys_regs = kern_hyp_va(ctxt->hw_sys_regs); + + sys_regs[MPIDR_EL1] = read_sysreg(vmpidr_el2); + sys_regs[CSSELR_EL1] = read_sysreg(csselr_el1); + sys_regs[SCTLR_EL1] = read_sysreg_el1(sctlr); + sys_regs[CPACR_EL1] = read_sysreg_el1(cpacr); + sys_regs[TTBR0_EL1] = read_sysreg_el1(ttbr0); + sys_regs[TTBR1_EL1] = read_sysreg_el1(ttbr1); + sys_regs[TCR_EL1] = read_sysreg_el1(tcr); + sys_regs[ESR_EL1] = read_sysreg_el1(esr); + sys_regs[AFSR0_EL1] = read_sysreg_el1(afsr0); + sys_regs[AFSR1_EL1] = read_sysreg_el1(afsr1); + sys_regs[FAR_EL1] = read_sysreg_el1(far); + sys_regs[MAIR_EL1] = read_sysreg_el1(mair); + sys_regs[VBAR_EL1] = read_sysreg_el1(vbar); + sys_regs[CONTEXTIDR_EL1] = read_sysreg_el1(contextidr); + sys_regs[AMAIR_EL1] = read_sysreg_el1(amair); + sys_regs[CNTKCTL_EL1] = read_sysreg_el1(cntkctl); + sys_regs[PAR_EL1] = read_sysreg(par_el1); + + ctxt->hw_sp_el1 = read_sysreg(sp_el1); + ctxt->hw_elr_el1 = read_sysreg_el1(elr); + ctxt->hw_spsr_el1 = read_sysreg_el1(spsr); } static hyp_alternate_select(__sysreg_call_save_host_state, @@ -86,39 +91,43 @@ void __hyp_text __sysreg_save_guest_state(struct kvm_cpu_context *ctxt) static void __hyp_text __sysreg_restore_common_state(struct kvm_cpu_context *ctxt) { - write_sysreg(ctxt->sys_regs[ACTLR_EL1], actlr_el1); - write_sysreg(ctxt->sys_regs[TPIDR_EL0], tpidr_el0); - write_sysreg(ctxt->sys_regs[TPIDRRO_EL0], tpidrro_el0); - write_sysreg(ctxt->sys_regs[TPIDR_EL1], tpidr_el1); - write_sysreg(ctxt->sys_regs[MDSCR_EL1], mdscr_el1); + u64 *sys_regs = kern_hyp_va(ctxt->hw_sys_regs); + + write_sysreg(sys_regs[ACTLR_EL1], actlr_el1); + write_sysreg(sys_regs[TPIDR_EL0], tpidr_el0); + write_sysreg(sys_regs[TPIDRRO_EL0], tpidrro_el0); + write_sysreg(sys_regs[TPIDR_EL1], tpidr_el1); + write_sysreg(sys_regs[MDSCR_EL1], mdscr_el1); write_sysreg(ctxt->gp_regs.regs.sp, sp_el0); write_sysreg_el2(ctxt->gp_regs.regs.pc, elr); - write_sysreg_el2(ctxt->gp_regs.regs.pstate, spsr); + write_sysreg_el2(ctxt->hw_pstate, spsr); } static void __hyp_text __sysreg_restore_state(struct kvm_cpu_context *ctxt) { - write_sysreg(ctxt->sys_regs[MPIDR_EL1], vmpidr_el2); - write_sysreg(ctxt->sys_regs[CSSELR_EL1], csselr_el1); - write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], sctlr); - write_sysreg_el1(ctxt->sys_regs[CPACR_EL1], cpacr); - write_sysreg_el1(ctxt->sys_regs[TTBR0_EL1], ttbr0); - write_sysreg_el1(ctxt->sys_regs[TTBR1_EL1], ttbr1); - write_sysreg_el1(ctxt->sys_regs[TCR_EL1], tcr); - write_sysreg_el1(ctxt->sys_regs[ESR_EL1], esr); - write_sysreg_el1(ctxt->sys_regs[AFSR0_EL1], afsr0); - write_sysreg_el1(ctxt->sys_regs[AFSR1_EL1], afsr1); - write_sysreg_el1(ctxt->sys_regs[FAR_EL1], far); - write_sysreg_el1(ctxt->sys_regs[MAIR_EL1], mair); - write_sysreg_el1(ctxt->sys_regs[VBAR_EL1], vbar); - write_sysreg_el1(ctxt->sys_regs[CONTEXTIDR_EL1],contextidr); - write_sysreg_el1(ctxt->sys_regs[AMAIR_EL1], amair); - write_sysreg_el1(ctxt->sys_regs[CNTKCTL_EL1], cntkctl); - write_sysreg(ctxt->sys_regs[PAR_EL1], par_el1); - - write_sysreg(ctxt->gp_regs.sp_el1, sp_el1); - write_sysreg_el1(ctxt->gp_regs.elr_el1, elr); - write_sysreg_el1(ctxt->gp_regs.spsr[KVM_SPSR_EL1],spsr); + u64 *sys_regs = kern_hyp_va(ctxt->hw_sys_regs); + + write_sysreg(sys_regs[MPIDR_EL1], vmpidr_el2); + write_sysreg(sys_regs[CSSELR_EL1], csselr_el1); + write_sysreg_el1(sys_regs[SCTLR_EL1], sctlr); + write_sysreg_el1(sys_regs[CPACR_EL1], cpacr); + write_sysreg_el1(sys_regs[TTBR0_EL1], ttbr0); + write_sysreg_el1(sys_regs[TTBR1_EL1], ttbr1); + write_sysreg_el1(sys_regs[TCR_EL1], tcr); + write_sysreg_el1(sys_regs[ESR_EL1], esr); + write_sysreg_el1(sys_regs[AFSR0_EL1], afsr0); + write_sysreg_el1(sys_regs[AFSR1_EL1], afsr1); + write_sysreg_el1(sys_regs[FAR_EL1], far); + write_sysreg_el1(sys_regs[MAIR_EL1], mair); + write_sysreg_el1(sys_regs[VBAR_EL1], vbar); + write_sysreg_el1(sys_regs[CONTEXTIDR_EL1], contextidr); + write_sysreg_el1(sys_regs[AMAIR_EL1], amair); + write_sysreg_el1(sys_regs[CNTKCTL_EL1], cntkctl); + write_sysreg(sys_regs[PAR_EL1], par_el1); + + write_sysreg(ctxt->hw_sp_el1, sp_el1); + write_sysreg_el1(ctxt->hw_elr_el1, elr); + write_sysreg_el1(ctxt->hw_spsr_el1, spsr); } static hyp_alternate_select(__sysreg_call_restore_host_state, diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index 36aae3a..0ff2997 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -689,6 +689,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) } kvm_arm_setup_debug(vcpu); + kvm_arm_setup_shadow_state(vcpu); /************************************************************** * Enter the guest @@ -704,6 +705,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) * Back from guest *************************************************************/ + kvm_arm_restore_shadow_state(vcpu); kvm_arm_clear_debug(vcpu); /* @@ -1334,6 +1336,16 @@ static void teardown_hyp_mode(void) static int init_vhe_mode(void) { + int cpu; + + for_each_possible_cpu(cpu) { + kvm_cpu_context_t *cpu_ctxt; + + cpu_ctxt = per_cpu_ptr(kvm_host_cpu_state, cpu); + + kvm_arm_init_cpu_context(cpu_ctxt); + } + kvm_info("VHE mode initialized successfully\n"); return 0; } @@ -1416,6 +1428,8 @@ static int init_hyp_mode(void) kvm_err("Cannot map host CPU state: %d\n", err); goto out_err; } + + kvm_arm_init_cpu_context(cpu_ctxt); } kvm_info("Hyp mode initialized successfully\n"); From patchwork Tue Jul 18 16:58:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108177 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp6192045qge; Tue, 18 Jul 2017 10:11:34 -0700 (PDT) X-Received: by 10.98.93.21 with SMTP id r21mr2689550pfb.201.1500397894707; Tue, 18 Jul 2017 10:11:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397894; 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.09.59.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 09:59:52 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 11/38] KVM: arm64: Set vcpu context depending on the guest exception level Date: Tue, 18 Jul 2017 11:58:37 -0500 Message-Id: <1500397144-16232-12-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org If the guest exception level is EL2, then set up the shadow context of the virtual EL2 to hardware. Otherwise, set the regular EL0/EL1 context. Note that the shadow context content will be prepared in subsequent patches. Signed-off-by: Jintack Lim --- arch/arm64/kvm/context.c | 74 +++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 64 insertions(+), 10 deletions(-) -- 1.9.1 diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c index bc43e66..2645787 100644 --- a/arch/arm64/kvm/context.c +++ b/arch/arm64/kvm/context.c @@ -18,11 +18,29 @@ #include #include -/** - * kvm_arm_setup_shadow_state -- prepare shadow state based on emulated mode - * @vcpu: The VCPU pointer - */ -void kvm_arm_setup_shadow_state(struct kvm_vcpu *vcpu) +static void flush_shadow_special_regs(struct kvm_vcpu *vcpu) +{ + struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; + + ctxt->hw_pstate = *vcpu_cpsr(vcpu) & ~PSR_MODE_MASK; + /* + * We can emulate the guest's configuration of which + * stack pointer to use when executing in virtual EL2 by + * using the equivalent feature in EL1 to point to + * either the EL1 or EL0 stack pointer. + */ + if ((*vcpu_cpsr(vcpu) & PSR_MODE_MASK) == PSR_MODE_EL2h) + ctxt->hw_pstate |= PSR_MODE_EL1h; + else + ctxt->hw_pstate |= PSR_MODE_EL1t; + + ctxt->hw_sys_regs = ctxt->shadow_sys_regs; + ctxt->hw_sp_el1 = vcpu_el2_sreg(vcpu, SP_EL2); + ctxt->hw_elr_el1 = vcpu_el2_sreg(vcpu, ELR_EL2); + ctxt->hw_spsr_el1 = vcpu_el2_sreg(vcpu, SPSR_EL2); +} + +static void flush_special_regs(struct kvm_vcpu *vcpu) { struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; @@ -33,11 +51,18 @@ void kvm_arm_setup_shadow_state(struct kvm_vcpu *vcpu) ctxt->hw_spsr_el1 = ctxt->gp_regs.spsr[KVM_SPSR_EL1]; } -/** - * kvm_arm_restore_shadow_state -- write back shadow state from guest - * @vcpu: The VCPU pointer - */ -void kvm_arm_restore_shadow_state(struct kvm_vcpu *vcpu) +static void sync_shadow_special_regs(struct kvm_vcpu *vcpu) +{ + struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; + + *vcpu_cpsr(vcpu) &= PSR_MODE_MASK; + *vcpu_cpsr(vcpu) |= ctxt->hw_pstate & ~PSR_MODE_MASK; + vcpu_el2_sreg(vcpu, SP_EL2) = ctxt->hw_sp_el1; + vcpu_el2_sreg(vcpu, ELR_EL2) = ctxt->hw_elr_el1; + vcpu_el2_sreg(vcpu, SPSR_EL2) = ctxt->hw_spsr_el1; +} + +static void sync_special_regs(struct kvm_vcpu *vcpu) { struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; @@ -47,6 +72,35 @@ void kvm_arm_restore_shadow_state(struct kvm_vcpu *vcpu) ctxt->gp_regs.spsr[KVM_SPSR_EL1] = ctxt->hw_spsr_el1; } +/** + * kvm_arm_setup_shadow_state -- prepare shadow state based on emulated mode + * @vcpu: The VCPU pointer + */ +void kvm_arm_setup_shadow_state(struct kvm_vcpu *vcpu) +{ + struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; + + if (unlikely(vcpu_mode_el2(vcpu))) { + flush_shadow_special_regs(vcpu); + ctxt->hw_sys_regs = ctxt->shadow_sys_regs; + } else { + flush_special_regs(vcpu); + ctxt->hw_sys_regs = ctxt->sys_regs; + } +} + +/** + * kvm_arm_restore_shadow_state -- write back shadow state from guest + * @vcpu: The VCPU pointer + */ +void kvm_arm_restore_shadow_state(struct kvm_vcpu *vcpu) +{ + if (unlikely(vcpu_mode_el2(vcpu))) + sync_shadow_special_regs(vcpu); + else + sync_special_regs(vcpu); +} + void kvm_arm_init_cpu_context(kvm_cpu_context_t *cpu_ctxt) { /* This is to set hw_sys_regs of host_cpu_context */ From patchwork Tue Jul 18 16:58:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108175 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp6190725qge; Tue, 18 Jul 2017 10:10:36 -0700 (PDT) X-Received: by 10.84.238.1 with SMTP id u1mr2714682plk.187.1500397836061; Tue, 18 Jul 2017 10:10:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397836; cv=none; d=google.com; s=arc-20160816; b=pSacMi7Sd2DtF6OyCRVXC/rV0M80+wpa5aXwMLxHZV2B3yCv+DYe5Tyaj1zyt8tbbE K9g92MOU4eoaNHktrimqQfnTMQlFoJW0WVO85qZb91intMNu+P6/LheI2MJxDge+njfh S8JYd6B58N0qp+g/KdL2t3PovIvWVuMWP0DdDWN/DZFfucUMpkRZySvAlCoiL6eCuwYx wcAffrWRKw++xzhEjPrlzvENnplUh4v1EHclvH/pmJkcgFhXdCMPoCG3ZMtmfxqiSxrv SiYMV4rPaI89B9aSRsS8+XYujzvmLMEf0EsOT52NtzqYA/aih0EduE0j4d2GvAVzERPH loSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=qFO2nYoh8D4OMIvdEfNQNJxTIMOtELHgPWAZPezcI9A=; b=upstLJCCnvX/Ls9kNyw7bo5nLNvUpctPF/fLZ2Q5fEOzhcmjYYUMSHC46eOSjKomoz 6w5KN3S+YLyEChmnjsLabiqpShq6wZ60xBuw2yjXJhoNCAzvMDnAf9e1KgSBnMk4E8Qj p0okM+S+9sceW0m1Mv2aWT6i3NaECpUB2XobZ9FkaxHgygSN5WkNT+C5A39JQWOWIps1 AUiJGWyGl2cfeXR/mAlGmYyEyrDhYPPYuIS5bxJJH1luw0qBR50V3kkUwzB1ZwSumrEb ixTYefthXBdTvLMEqw14TyCQuaU9IqfR32H23m75gF7mUlcdh2CcuKfZSU6mUfg3dh+o M3jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=Xyi/zhHy; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.09.59.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 09:59:54 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH v2 12/38] arm64: Add missing TCR hw defines Date: Tue, 18 Jul 2017 11:58:38 -0500 Message-Id: <1500397144-16232-13-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Christoffer Dall Some bits of the TCR weren't defined and since we're about to use these in KVM, add these defines. Signed-off-by: Christoffer Dall --- arch/arm64/include/asm/pgtable-hwdef.h | 6 ++++++ 1 file changed, 6 insertions(+) -- 1.9.1 diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index eb0c2bd..d26cab7 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -272,9 +272,15 @@ #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) +#define TCR_IPS_SHIFT 32 +#define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT) + #define TCR_ASID16 (UL(1) << 36) #define TCR_TBI0 (UL(1) << 37) #define TCR_HA (UL(1) << 39) #define TCR_HD (UL(1) << 40) +#define TCR_EPD1 (UL(1) << 23) +#define TCR_EPD0 (UL(1) << 7) + #endif From patchwork Tue Jul 18 16:58:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108173 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp6190058qge; Tue, 18 Jul 2017 10:10:06 -0700 (PDT) X-Received: by 10.99.113.77 with SMTP id b13mr2688569pgn.11.1500397806780; Tue, 18 Jul 2017 10:10:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397806; cv=none; d=google.com; s=arc-20160816; b=KUAKwH3Wgr/XFLT8c5C8JrLqq7BCCSTZliyWA9Fnp0IPr7eMawIkR2coG0alolTC9G QMNv3OJuRhHR/nOqkaHrNoOwSBpw/OHH9TgQ8T17vJhO+JWrOMFLs+jyzvd9jGUyxgMl yBaggv53K42yIrEg1CuMJYv8iLMJ3fSt3q/GvNLEtOHHLs86fyGgmfUOC9gD+F/uet6s iYCBy+F5NIsmHeATxafoBaCUKVQZ2SmCPluvi+L6b7qk3GvMVIT4Jutn5BlsPj2vfC2L XhSAtZFv3lcadzgHaThVBnvN6QJ5Gnl1QmaBcAtqVnGMcgvyej1PZmmdolpFVhbAidaW Vq7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Dzi5ftaJYrZCPDUJeVqmPGV6OrJXqoJ0k10UZczbrnA=; b=vdOmnkIZVefdhCS3qZfB6pADaKvNawcxIP3aWPupnVEeJyL5cU2IpGpoGktihOfgjw rtFtz5bw312KTLZXYTg/nQ6JHF6xhZ5vU0NYsSKHSAGBzwU3kYpg14WIv85crT09pDJ2 CvTesXS4v3AzMAiLv/2awLa1PMdl2OikQ/vCVxNnMsZ3oKNmDf8//X50zLfA6ab/SBEc NkKTaGpMyHhV545e+CLPcBhDyoHonkdQtB9kY2larveeNztj3D3i2+EAFjKRjmoBWPw0 c6na3t46dcK5GoL8lsAih4FqdMRw8i+lAA4pkbSbVKvQIM2oEMU/+CHWt7wabm0wv6Kc mAng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=ii5BTruz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.09.59.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 09:59:55 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 13/38] KVM: arm64: Create shadow EL1 registers Date: Tue, 18 Jul 2017 11:58:39 -0500 Message-Id: <1500397144-16232-14-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Christoffer Dall When entering virtual EL2, we need to reflect virtual EL2 register states to corresponding shadow EL1 registers. We can simply copy them if their formats are identical. Otherwise, we need to convert EL2 register state to EL1 register state. When entering EL1/EL0, we need a special care for MPIDR_EL1. Read of this register returns the value of VMPIDR_EL2, so when a VM has the virtual EL2, the value of MPIDR_EL1 should come from the virtual VMPIDR_EL2. Signed-off-by: Christoffer Dall Signed-off-by: Jintack Lim --- arch/arm64/kvm/context.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) -- 1.9.1 diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c index 2645787..e965049 100644 --- a/arch/arm64/kvm/context.c +++ b/arch/arm64/kvm/context.c @@ -17,6 +17,74 @@ #include #include +#include + +struct el1_el2_map { + enum vcpu_sysreg el1; + enum vcpu_sysreg el2; +}; + +/* + * List of EL2 registers which can be directly applied to EL1 registers to + * emulate running EL2 in EL1. + */ +static const struct el1_el2_map el1_el2_map[] = { + { AMAIR_EL1, AMAIR_EL2 }, + { MAIR_EL1, MAIR_EL2 }, + { TTBR0_EL1, TTBR0_EL2 }, + { ACTLR_EL1, ACTLR_EL2 }, + { AFSR0_EL1, AFSR0_EL2 }, + { AFSR1_EL1, AFSR1_EL2 }, + { SCTLR_EL1, SCTLR_EL2 }, + { VBAR_EL1, VBAR_EL2 }, +}; + +static inline u64 tcr_el2_ips_to_tcr_el1_ps(u64 tcr_el2) +{ + return ((tcr_el2 & TCR_EL2_PS_MASK) >> TCR_EL2_PS_SHIFT) + << TCR_IPS_SHIFT; +} + +static inline u64 cptr_to_cpacr(u64 cptr_el2) +{ + u64 cpacr_el1 = 0; + + if (!(cptr_el2 & CPTR_EL2_TFP)) + cpacr_el1 |= CPACR_EL1_FPEN; + if (cptr_el2 & CPTR_EL2_TTA) + cpacr_el1 |= CPACR_EL1_TTA; + + return cpacr_el1; +} + +static void flush_shadow_el1_sysregs(struct kvm_vcpu *vcpu) +{ + u64 *s_sys_regs = vcpu->arch.ctxt.shadow_sys_regs; + u64 tcr_el2; + int i; + + for (i = 0; i < ARRAY_SIZE(el1_el2_map); i++) { + const struct el1_el2_map *map = &el1_el2_map[i]; + + s_sys_regs[map->el1] = vcpu_sys_reg(vcpu, map->el2); + } + + tcr_el2 = vcpu_sys_reg(vcpu, TCR_EL2); + s_sys_regs[TCR_EL1] = + TCR_EPD1 | /* disable TTBR1_EL1 */ + ((tcr_el2 & TCR_EL2_TBI) ? TCR_TBI0 : 0) | + tcr_el2_ips_to_tcr_el1_ps(tcr_el2) | + (tcr_el2 & TCR_EL2_TG0_MASK) | + (tcr_el2 & TCR_EL2_ORGN0_MASK) | + (tcr_el2 & TCR_EL2_IRGN0_MASK) | + (tcr_el2 & TCR_EL2_T0SZ_MASK); + + /* Rely on separate VMID for VA context, always use ASID 0 */ + s_sys_regs[TTBR0_EL1] &= ~GENMASK_ULL(63, 48); + s_sys_regs[TTBR1_EL1] = 0; + + s_sys_regs[CPACR_EL1] = cptr_to_cpacr(vcpu_sys_reg(vcpu, CPTR_EL2)); +} static void flush_shadow_special_regs(struct kvm_vcpu *vcpu) { @@ -72,6 +140,17 @@ static void sync_special_regs(struct kvm_vcpu *vcpu) ctxt->gp_regs.spsr[KVM_SPSR_EL1] = ctxt->hw_spsr_el1; } +static void setup_mpidr_el1(struct kvm_vcpu *vcpu) +{ + /* + * A non-secure EL0 or EL1 read of MPIDR_EL1 returns + * the value of VMPIDR_EL2. For nested virtualization, + * it comes from the virtual VMPIDR_EL2. + */ + if (nested_virt_in_use(vcpu)) + vcpu_sys_reg(vcpu, MPIDR_EL1) = vcpu_sys_reg(vcpu, VMPIDR_EL2); +} + /** * kvm_arm_setup_shadow_state -- prepare shadow state based on emulated mode * @vcpu: The VCPU pointer @@ -82,9 +161,11 @@ void kvm_arm_setup_shadow_state(struct kvm_vcpu *vcpu) if (unlikely(vcpu_mode_el2(vcpu))) { flush_shadow_special_regs(vcpu); + flush_shadow_el1_sysregs(vcpu); ctxt->hw_sys_regs = ctxt->shadow_sys_regs; } else { flush_special_regs(vcpu); + setup_mpidr_el1(vcpu); ctxt->hw_sys_regs = ctxt->sys_regs; } } From patchwork Tue Jul 18 16:58:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108145 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6148618obm; Tue, 18 Jul 2017 10:00:13 -0700 (PDT) X-Received: by 10.84.169.36 with SMTP id g33mr2936825plb.52.1500397213235; Tue, 18 Jul 2017 10:00:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397213; cv=none; d=google.com; s=arc-20160816; b=zM972WMStH0d/aVXw/IT/29L8Zeb0A7E4YZgJOP2/I3wYrvsmOJc3JJwkTv78At/1v AstW2bkp2cTYwInTcSRPc6PKxk0Dd6Txqgc2QlAMSQGJChcD71NfTMSmbWnuC6CmsLVO 9UTImtAhBSj9MBIDRLVzKbYmsRHTKV11YgVX0AmhhgVmsNpuOmW0FrV+SORwVZSdyYWT /0OZuOgMfH3D9NGT59sQsE7QdXWdTR5eTcvq3hJeYV7nmV4Nc0+m2VX9aRBHM7CzcjsD d2eeejuVIFy8VRRTAbg/EBJ8XtFGv66uA+btj0fbcRrRIp6qIB7SMOUo2v3uffSWmvxS zF3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=FRi4V9u1gbS0dP/ydCmVVbCmWKtSV9AdAFrgkp+PwsQ=; b=EctBMRV1oqiy0r5QboIJLXTu7vmgRoyhpFQrhmTkUO5SabvlSf7fklMzVJa+H9ZTtE ANSyKNnxge7h7TmnE2QqhareQw+kmAElAiy7KaIZMUB/HAHN6SJ5AgnvDdy1wgrqzyMa XKRX/bSr0vz+Qz7O7EgpWlTOU3h/AlHJrYd0ZKB5HES5T3G4i74I/HP9lZo5ns5SY3Si NP+7MbotlArBLt0Etjn3DI1Fb0n+0yANcrEd55eYRwcEcEranYbu7u5DXtSMI51XiUBx QZGNpj3NdKLyZoFHl7316ZnwSi701uLBYRo3Mqa3BDq4/haVt5uLkJiLc59WnQyYKEz5 CxVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=biDmBbyP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.09.59.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 09:59:57 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 14/38] KVM: arm64: Synchronize EL1 system registers on virtual EL2 entry and exit Date: Tue, 18 Jul 2017 11:58:40 -0500 Message-Id: <1500397144-16232-15-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When running in virtual EL2 we use the shadow EL1 systerm register array for the save/restore process, so that hardware and especially the memory subsystem behaves as code written for EL2 expects while really running in EL1. This works great for EL1 system register accesses that we trap, because these accesses will be written into the virtual state for the EL1 system registers used when eventually switching the VCPU mode to EL1. However, there was a collection of EL1 system registers which we do not trap, and as a consequence all save/restore operations of these registers were happening locally in the shadow array, with no benefit to software actually running in virtual EL1 at all. To fix this, simply synchronize the shadow and real EL1 state for these registers on entry/exit to/from virtual EL2 state. Signed-off-by: Christoffer Dall Signed-off-by: Jintack Lim --- arch/arm64/kvm/context.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 56 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c index e965049..e1bc753 100644 --- a/arch/arm64/kvm/context.c +++ b/arch/arm64/kvm/context.c @@ -86,6 +86,58 @@ static void flush_shadow_el1_sysregs(struct kvm_vcpu *vcpu) s_sys_regs[CPACR_EL1] = cptr_to_cpacr(vcpu_sys_reg(vcpu, CPTR_EL2)); } + +/* + * List of EL0 and EL1 registers which we allow the virtual EL2 mode to access + * directly without trapping. This is possible because the impact of + * accessing those registers are the same regardless of the exception + * levels that are allowed. + */ +static const int el1_non_trap_regs[] = { + CNTKCTL_EL1, + CSSELR_EL1, + PAR_EL1, + TPIDR_EL0, + TPIDR_EL1, + TPIDRRO_EL0 +}; + +/** + * copy_shadow_non_trap_el1_state + * @vcpu: The VCPU pointer + * @setup: True, if on the way to the guest (called from setup) + * False, if returning form the guet (calld from restore) + * + * Some EL1 registers are accessed directly by the virtual EL2 mode because + * they in no way affect execution state in virtual EL2. However, we must + * still ensure that virtual EL2 observes the same state of the EL1 registers + * as the normal VM's EL1 mode, so copy this state as needed on setup/restore. + */ +static void copy_shadow_non_trap_el1_state(struct kvm_vcpu *vcpu, bool setup) +{ + u64 *s_sys_regs = vcpu->arch.ctxt.shadow_sys_regs; + int i; + + for (i = 0; i < ARRAY_SIZE(el1_non_trap_regs); i++) { + const int sr = el1_non_trap_regs[i]; + + if (setup) + s_sys_regs[sr] = vcpu_sys_reg(vcpu, sr); + else + vcpu_sys_reg(vcpu, sr) = s_sys_regs[sr]; + } +} + +static void sync_shadow_non_trap_el1_state(struct kvm_vcpu *vcpu) +{ + copy_shadow_non_trap_el1_state(vcpu, false); +} + +static void flush_shadow_non_trap_el1_state(struct kvm_vcpu *vcpu) +{ + copy_shadow_non_trap_el1_state(vcpu, true); +} + static void flush_shadow_special_regs(struct kvm_vcpu *vcpu) { struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; @@ -162,6 +214,7 @@ void kvm_arm_setup_shadow_state(struct kvm_vcpu *vcpu) if (unlikely(vcpu_mode_el2(vcpu))) { flush_shadow_special_regs(vcpu); flush_shadow_el1_sysregs(vcpu); + flush_shadow_non_trap_el1_state(vcpu); ctxt->hw_sys_regs = ctxt->shadow_sys_regs; } else { flush_special_regs(vcpu); @@ -176,9 +229,10 @@ void kvm_arm_setup_shadow_state(struct kvm_vcpu *vcpu) */ void kvm_arm_restore_shadow_state(struct kvm_vcpu *vcpu) { - if (unlikely(vcpu_mode_el2(vcpu))) + if (unlikely(vcpu_mode_el2(vcpu))) { sync_shadow_special_regs(vcpu); - else + sync_shadow_non_trap_el1_state(vcpu); + } else sync_special_regs(vcpu); } From patchwork Tue Jul 18 16:58:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108172 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp6188501qge; Tue, 18 Jul 2017 10:08:57 -0700 (PDT) X-Received: by 10.98.95.67 with SMTP id t64mr2712315pfb.127.1500397737631; Tue, 18 Jul 2017 10:08:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397737; cv=none; d=google.com; s=arc-20160816; b=EdsHYUEg9kiNJnDqfNUKIjrnRGapKTCv6r3tU2Vhm8HWnw3s8ssMXTXwpjI8QAAcSf FESEVXhuIieArUDTx/Zr/ByTvVW/iZ9/J74wicdD2y9MlIWnGZcdsSCFKgcEwrJUM0MX vKC2D2coWnIU8xqe4+U6CDTHkzGTFhZQmyMqZ3B+278ka3HQHt/aFvKwsWo7bU8InlKy 4NL44Whbv4KkfnYIqdmB92FwUfYcN9H/oZ0oF+XIF996M3rrBqkdXsyyEwZhIiU0cBuz Y9X7SkS7PvOu1cHbBaNpnTeLPNtwyOQFJvn50m/XuD04I5ULJ+/+5g6CxXXBX61hKEtn u34Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=OPr+27sfCY8QxeijpDIPuXpRRNcpRZOCse2LXlKzKMg=; b=nyjD2ShYMqSXUeBTgZV+dblxtcwQjJ1n+5gRiWWAWjmfyzxAAaG5DxGmThGOZSTwWR htu0hAVR2NzeyUwqVc032tYXw4MrA2YcsZWWjfqtdYzlA2F6428wR/PocUiaIxUjmKgE sXwf/eqbIkr+VS8zx+UX8d3J+kSL9WIIIsqb2FEXATP05sG0uk+9uIGViR+EjbdlcovV duVvSmkZ3KdLBjbZ0ewTjy3qpv+WDj2MDcMmknic/FrniCE9F6oqrYdaAqtcdjiaR4rj MKv/zqgfGOnJHNESnyBME+oZ9qVTQ3JP7oCZc+kYUNAuiu0ievtkY7cY0cU45TPlORIV FVQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=M8LvUZ14; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.09.59.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 09:59:59 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 15/38] KVM: arm64: Move exception macros and enums to a common file Date: Tue, 18 Jul 2017 11:58:41 -0500 Message-Id: <1500397144-16232-16-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These macros and enums can be reused to inject exceptions for nested virtualization. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/kvm_emulate.h | 12 ++++++++++++ arch/arm64/kvm/inject_fault.c | 12 ------------ 2 files changed, 12 insertions(+), 12 deletions(-) -- 1.9.1 diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index 14c4ce9..94f98cc 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -31,6 +31,18 @@ #include #include +#define CURRENT_EL_SP_EL0_VECTOR 0x0 +#define CURRENT_EL_SP_ELx_VECTOR 0x200 +#define LOWER_EL_AArch64_VECTOR 0x400 +#define LOWER_EL_AArch32_VECTOR 0x600 + +enum exception_type { + except_type_sync = 0, + except_type_irq = 0x80, + except_type_fiq = 0x100, + except_type_serror = 0x180, +}; + unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num); unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c index da6a8cf..94679fb 100644 --- a/arch/arm64/kvm/inject_fault.c +++ b/arch/arm64/kvm/inject_fault.c @@ -28,11 +28,6 @@ #define PSTATE_FAULT_BITS_64 (PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | \ PSR_I_BIT | PSR_D_BIT) -#define CURRENT_EL_SP_EL0_VECTOR 0x0 -#define CURRENT_EL_SP_ELx_VECTOR 0x200 -#define LOWER_EL_AArch64_VECTOR 0x400 -#define LOWER_EL_AArch32_VECTOR 0x600 - static void prepare_fault32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset) { unsigned long cpsr; @@ -101,13 +96,6 @@ static void inject_abt32(struct kvm_vcpu *vcpu, bool is_pabt, *fsr = 0x14; } -enum exception_type { - except_type_sync = 0, - except_type_irq = 0x80, - except_type_fiq = 0x100, - except_type_serror = 0x180, -}; - static u64 get_except_vector(struct kvm_vcpu *vcpu, enum exception_type type) { u64 exc_offset; From patchwork Tue Jul 18 16:58:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108171 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp6188460qge; Tue, 18 Jul 2017 10:08:55 -0700 (PDT) X-Received: by 10.99.121.133 with SMTP id u127mr2821937pgc.31.1500397735766; Tue, 18 Jul 2017 10:08:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397735; cv=none; d=google.com; s=arc-20160816; b=VCPIBlH99QhqyNuSOcOdxXKt/1rDAU4/ueC2LmRfgW9MgaZYqRPxS4+8X6QA6lo5Fx w8/MiwRjGxPcMv8aPHiA/smZ/fH8PAlflNwN/jvp7G57dbsGLTDcReaeG39CSnowqebX lGf3nYdoZ4QlTNbfR5leneOfoly1BBF4r8oKsOhU1dU5iTZ2bM7j6OZL20z4yy9AcoEQ UgFopobXzWWLp9CoueTNB5kWJ2somVHc/XtJkuU8Oo6Go4/r/1VE/Qo3ClzKTjbMkYwo QLoveQvTYszvkMbV5pJfP3M8xaV4pJYObiPGNaPAwlYWCZ8xKIFs+3QsKFmt7gQgBHhO Z1fQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=OP7AoCD6KD7pkUCxrsUGkVgKCpdo//1VjbXMdmfYWlk=; b=t9z7kalWar3Lu4eSR0C5qVn2nCIS4Rie3pqtU8EVJjglPMHyRyaUbwynvdosWk2InP 1QMXJZIWF+er+7RLNM0mlU0AlEhBZluHE2u+CWWbwJJIns3vKecZxJ8Rt9VceF1zfl6q TrYUm0V8m7sJLzzcYm4FN+uMQRJmdPgjElTqYd/uOu89dPoC16NmLebYO/SobJ0aIfB0 rt/I5U6kGhVqMZQ7M6g6Iy8i3oFq8GjPJ3i2iFUCHSqVUoKvfO471TA9kPQ/wYnpKhAm NML9TO6ns6Zp2XYVZbsEReg7wP7uXvbdeW9pXzfow8BUu0yzwYBxump4L/7LqRf20wuS hItg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=DCgW4zXp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:01 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 16/38] KVM: arm64: Support to inject exceptions to the virtual EL2 Date: Tue, 18 Jul 2017 11:58:42 -0500 Message-Id: <1500397144-16232-17-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Support inject synchronous exceptions to the virtual EL2 as described in ARM ARM AArch64.TakeException(). This can be easily extended to support to inject asynchronous exceptions to the virtual EL2, but it will be added in a later patch when appropriate. Signed-off-by: Jintack Lim --- arch/arm/include/asm/kvm_emulate.h | 7 +++ arch/arm64/include/asm/kvm_emulate.h | 2 + arch/arm64/kvm/Makefile | 1 + arch/arm64/kvm/emulate-nested.c | 83 ++++++++++++++++++++++++++++++++++++ arch/arm64/kvm/trace.h | 20 +++++++++ 5 files changed, 113 insertions(+) create mode 100644 arch/arm64/kvm/emulate-nested.c -- 1.9.1 diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h index 0a03b7d..29a4dec 100644 --- a/arch/arm/include/asm/kvm_emulate.h +++ b/arch/arm/include/asm/kvm_emulate.h @@ -47,6 +47,13 @@ static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num, void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr); void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr); +static inline int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2) +{ + kvm_err("Unexpected call to %s for the non-nesting configuration\n", + __func__); + return -EINVAL; +} + static inline void kvm_arm_setup_shadow_state(struct kvm_vcpu *vcpu) { }; static inline void kvm_arm_restore_shadow_state(struct kvm_vcpu *vcpu) { }; static inline void kvm_arm_init_cpu_context(kvm_cpu_context_t *cpu_ctxt) { }; diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index 94f98cc..3017234 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -54,6 +54,8 @@ enum exception_type { void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr); void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr); +int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2); + void kvm_arm_setup_shadow_state(struct kvm_vcpu *vcpu); void kvm_arm_restore_shadow_state(struct kvm_vcpu *vcpu); void kvm_arm_init_cpu_context(kvm_cpu_context_t *cpu_ctxt); diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile index 5762337..0263ef0 100644 --- a/arch/arm64/kvm/Makefile +++ b/arch/arm64/kvm/Makefile @@ -37,3 +37,4 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arch_timer.o kvm-$(CONFIG_KVM_ARM_PMU) += $(KVM)/arm/pmu.o kvm-$(CONFIG_KVM_ARM_HOST) += nested.o +kvm-$(CONFIG_KVM_ARM_HOST) += emulate-nested.o diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c new file mode 100644 index 0000000..48b84cc --- /dev/null +++ b/arch/arm64/kvm/emulate-nested.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2016 - Linaro and Columbia University + * Author: Jintack Lim + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +#include + +#include "trace.h" + +/* This is borrowed from get_except_vector in inject_fault.c */ +static u64 get_el2_except_vector(struct kvm_vcpu *vcpu, + enum exception_type type) +{ + u64 exc_offset; + + switch (*vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT)) { + case PSR_MODE_EL2t: + exc_offset = CURRENT_EL_SP_EL0_VECTOR; + break; + case PSR_MODE_EL2h: + exc_offset = CURRENT_EL_SP_ELx_VECTOR; + break; + case PSR_MODE_EL1t: + case PSR_MODE_EL1h: + case PSR_MODE_EL0t: + exc_offset = LOWER_EL_AArch64_VECTOR; + break; + default: + kvm_err("Unexpected previous exception level: aarch32\n"); + exc_offset = LOWER_EL_AArch32_VECTOR; + } + + return vcpu_sys_reg(vcpu, VBAR_EL2) + exc_offset + type; +} + +/* + * Emulate taking an exception to EL2. + * See ARM ARM J8.1.2 AArch64.TakeException() + */ +static int kvm_inject_nested(struct kvm_vcpu *vcpu, u64 esr_el2, + enum exception_type type) +{ + int ret = 1; + + if (!nested_virt_in_use(vcpu)) { + kvm_err("Unexpected call to %s for the non-nesting configuration\n", + __func__); + return -EINVAL; + } + + vcpu_el2_sreg(vcpu, SPSR_EL2) = *vcpu_cpsr(vcpu); + vcpu_el2_sreg(vcpu, ELR_EL2) = *vcpu_pc(vcpu); + vcpu_sys_reg(vcpu, ESR_EL2) = esr_el2; + + *vcpu_pc(vcpu) = get_el2_except_vector(vcpu, type); + /* On an exception, PSTATE.SP becomes 1 */ + *vcpu_cpsr(vcpu) = PSR_MODE_EL2h; + *vcpu_cpsr(vcpu) |= (PSR_A_BIT | PSR_F_BIT | PSR_I_BIT | PSR_D_BIT); + + trace_kvm_inject_nested_exception(vcpu, esr_el2, *vcpu_pc(vcpu)); + + return ret; +} + +int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2) +{ + return kvm_inject_nested(vcpu, esr_el2, except_type_sync); +} diff --git a/arch/arm64/kvm/trace.h b/arch/arm64/kvm/trace.h index 7fb0008..7c86cfb 100644 --- a/arch/arm64/kvm/trace.h +++ b/arch/arm64/kvm/trace.h @@ -167,6 +167,26 @@ ); +TRACE_EVENT(kvm_inject_nested_exception, + TP_PROTO(struct kvm_vcpu *vcpu, unsigned long esr_el2, + unsigned long pc), + TP_ARGS(vcpu, esr_el2, pc), + + TP_STRUCT__entry( + __field(struct kvm_vcpu *, vcpu) + __field(unsigned long, esr_el2) + __field(unsigned long, pc) + ), + + TP_fast_assign( + __entry->vcpu = vcpu; + __entry->esr_el2 = esr_el2; + __entry->pc = pc; + ), + + TP_printk("vcpu: %p, inject exception to vEL2: ESR_EL2 0x%lx, vector: 0x%016lx", + __entry->vcpu, __entry->esr_el2, __entry->pc) +); #endif /* _TRACE_ARM64_KVM_H */ #undef TRACE_INCLUDE_PATH From patchwork Tue Jul 18 16:58:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108170 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp6188384qge; Tue, 18 Jul 2017 10:08:53 -0700 (PDT) X-Received: by 10.98.197.130 with SMTP id j124mr2653484pfg.117.1500397733157; Tue, 18 Jul 2017 10:08:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397733; cv=none; d=google.com; s=arc-20160816; b=SmiA1yI0EwuA0+MkD6l9eY4BgXMaFaPQidsNKLbDDzEVdogRsROxJYPkdxqAv6J/q3 F57WG4DuWiJbwpq4MUlNwYe10G5R4BGDDaIkvfhaOK36C4evD+7meTkp+/lVyczxYvIy PVgNhy2Ra16pTw/kKx0wkXSYJIkAReezXz/3iSkdvoZztKFZvSdNBbgaZJDzzEk5Ep5O UMIrkZyqpxxVyfTVYz3yE/wx2p3SnSrCYAxe0G4PkvV2Lg6Bi49dxV3C/8PK0CiU6jZj Lm78zzJYAGRe0V6HfGyqDwK46TsaWWxd/SwMg8CRoNxumCUaiXgaEpKg0NZoktSU8RID C3lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=SDxDsiNRGBAtNxVsRG2mqOMWzuz/FgyKHCtIVSKW+ks=; b=qeo7LuVqj3XrTjIRoKtzDo9ucjYYs45yf2E5SY/2Zfre4DGH+NMYrHX5O9VuyMkOlO 3OfLghdFPtwQDvsU6Guqz/KPLf261/zpqWhn/VS3c/AhBdHjlGbjhwZ80diFQC6PgoW8 HbGW9hsrhRaTv7xBdpfRrnVGcipNYDIWuC75/tRr1cEbymNBP+BAdZCm348JiJyHbKDT kEjj3ONS8Wj1tmts9u9mwtfiAIUPSqomiJzN2hbV6M7I9NpFtgUD1RZTEP4VYPEYQPZn pU/pfDGzR0opgHhJNR36rMXVRgknTfalXt1V3lEvhTMgT/1qErLFjrekRAjESwyX08JF vZzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=jNB88igg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:03 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH v2 17/38] KVM: arm64: Trap EL1 VM register accesses in virtual EL2 Date: Tue, 18 Jul 2017 11:58:43 -0500 Message-Id: <1500397144-16232-18-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Christoffer Dall When running in virtual EL2 mode, we actually run the hardware in EL1 and therefore have to use the EL1 registers to ensure correct operation. By setting the HCR.TVM and HCR.TVRM we ensure that the virtual EL2 mode doesn't shoot itself in the foot when setting up what it believes to be a different mode's system register state (for example when preparing to switch to a VM). We can leverage the existing sysregs infrastructure to support trapped accesses to these registers. Signed-off-by: Christoffer Dall --- arch/arm64/kvm/hyp/switch.c | 2 ++ arch/arm64/kvm/sys_regs.c | 7 ++++++- 2 files changed, 8 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 945e79c..ec91cd08 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -85,6 +85,8 @@ static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu) write_sysreg(1 << 30, fpexc32_el2); isb(); } + if (vcpu_mode_el2(vcpu)) + val |= HCR_TVM | HCR_TRVM; write_sysreg(val, hcr_el2); /* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */ write_sysreg(1 << 15, hstr_el2); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 2b3ed70..d8b1d4b 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -121,7 +121,12 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu, { bool was_enabled = vcpu_has_cache_enabled(vcpu); - BUG_ON(!p->is_write); + BUG_ON(!vcpu_mode_el2(vcpu) && !p->is_write); + + if (!p->is_write) { + p->regval = vcpu_sys_reg(vcpu, r->reg); + return true; + } if (!p->is_aarch32) { vcpu_sys_reg(vcpu, r->reg) = p->regval; From patchwork Tue Jul 18 16:58:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108169 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp6187877qge; Tue, 18 Jul 2017 10:08:26 -0700 (PDT) X-Received: by 10.84.174.131 with SMTP id r3mr2853817plb.37.1500397706605; Tue, 18 Jul 2017 10:08:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397706; cv=none; d=google.com; s=arc-20160816; b=HZ7i66/T3mPrrQ690FMvtibJ0zdSfZiQnn+YPtjk5kLkw5pnXxdX5QM6HzVNLsF7Ns ygygSUtp74a9GEX7CBtDugU28Z4xREN0PPx2XZOjPpIZ4/c0VwEVLbw6BDvXwPd0liwa +STqasUeoZMEhT6n2uXnErY5SmWAASANJAWd1WiGLSxdeaQ3jvk66QuBk0IIuIT/tlpV yijJ8h94EOhGYZLxqTRqjHMz6DM8VOiGFMMqkPzsAZkQeF5M156d3YPg6B+vBzN3Q/ht sxCZOszS5Emwm0T/89U+di2B92+M+beCLB5FDMNwBsdk0iV3BPwM1TwrY9onk2qpHAe3 k8Bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=oaAuvYAVsNU1+HbJI/0ovsAvScBgSob+BXXlaYcRmN4=; b=KayhkLVK0RYzowOFi1j+zMA9D2uAH8+6toZeR+bgq+FA8sBTyLrPatxRqG8lh9TznA tbYVc/Gg8hUXi/tMw9D+scGJGqpiV92MdyVx5uLbkq3jCtEqNe+UAnVM2zbme1MFl8Xn EsPKDsSS16uvFwNREfRw7hfr2O1srojm4draPts7MrCeXPmEJcarmQ5FQSsY1jp7K5yI YX6qvCSk039xVt4Af15zK8l44i07v22o20VFRLhsHzIMHkh/WXU+ztCUuPaL0YFzHx7d 8YV2rEuqQ94LjrCDCH23TKiNrokyH/wtYrcN4R530VeDutlcb0P/12gy/doKZpV7LWoD HzMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=kBid3ANM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:05 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 18/38] KVM: arm64: Trap SPSR_EL1, ELR_EL1 and VBAR_EL1 from virtual EL2 Date: Tue, 18 Jul 2017 11:58:44 -0500 Message-Id: <1500397144-16232-19-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For the same reason we trap virtual memory register accesses at virtual EL2, we need to trap SPSR_EL1, ELR_EL1 and VBAR_EL1 accesses. ARM v8.3 introduces the HCR_EL2.NV1 bit to be able to trap on those register accesses in EL1. Do not set this bit until the whole nesting support is completed. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/sysreg.h | 2 ++ arch/arm64/kvm/sys_regs.c | 29 ++++++++++++++++++++++++++++- 2 files changed, 30 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 98c32ef..6373d3d 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -164,6 +164,8 @@ #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) +#define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) +#define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d8b1d4b..b83fef2 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -936,6 +936,30 @@ static bool trap_el2_regs(struct kvm_vcpu *vcpu, return true; } +static bool access_elr(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + access_rw(p, &vcpu->arch.ctxt.gp_regs.elr_el1); + return true; +} + +static bool access_spsr(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + access_rw(p, &vcpu->arch.ctxt.gp_regs.spsr[KVM_SPSR_EL1]); + return true; +} + +static bool access_vbar(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + access_rw(p, &vcpu_sys_reg(vcpu, r->reg)); + return true; +} + /* * Architected system registers. * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 @@ -994,6 +1018,9 @@ static bool trap_el2_regs(struct kvm_vcpu *vcpu, { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, + { SYS_DESC(SYS_SPSR_EL1), access_spsr}, + { SYS_DESC(SYS_ELR_EL1), access_elr}, + { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, @@ -1006,7 +1033,7 @@ static bool trap_el2_regs(struct kvm_vcpu *vcpu, { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, - { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 }, + { SYS_DESC(SYS_VBAR_EL1), access_vbar, reset_val, VBAR_EL1, 0 }, { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, From patchwork Tue Jul 18 16:58:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108146 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6148741obm; Tue, 18 Jul 2017 10:00:19 -0700 (PDT) X-Received: by 10.84.169.67 with SMTP id g61mr2694643plb.155.1500397219527; Tue, 18 Jul 2017 10:00:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397219; cv=none; d=google.com; s=arc-20160816; b=zAfDnSiQFa4OhiXfNROa7DiaV8+9SBNoRwWM2ygoC1ozv+AQFKZhNjg7g6O++xsdxx KQ7tblA5DGEDYo7pPt8Jqq1Mwerqp1LnwV6pMJwxPM8brslVXWP8FSbDK2w1e+FoqE5B P5CjliugkRs38giSv3VzHivuWX5MFvDngdUop6+FLteJ/jGm1DflXsWK2stKk0hkcnG2 VEivcDHoqGUzR0DOw74P/RNyfF8iKjWHcvaiJehfQX2fdyJB3JQsdklp/xswawZqG1HS lye/KoCd8bzvz6V0tqP2gIZm6ov15uQdmlnmWfJX5J4g+GYDd844H0uZQ97ApLAxRoMM W/+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=sXk26+440EKMeJd7u3TuCLY1cuh9Kulm5tVEytfrl8A=; b=doBruWVtQY6UlizFy/N1koT/SYfnZuW8P5SA8MKao1qIppGec1iZzIuLKBde7fvYBL T3dqO8uBDsvN6CJsNS2hCd7OnMg8LmF9JXk2s1RET7mu8isLb5Lm2TrotkjJJrIv3SS8 UROdSEaKu+fs5GzgegrPxrNVKTFX9mdSE2CtFIb0Axcik3GbqJNPXkcCkJFPLU89bCFO DstHwnvCNnRNnzLuSTb2H/mY3e7hiq7D6uvSzMbTKUtleZMMgGRINkEQNGq8EK0lFsZq BEjHhgjSQvj7R+M+eouwpcf9oyBIOInEA4w5wPW8xEaQdkJyncDs3+qQgKPg9WuCa57u GghA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=UqcJcYaB; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:07 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 19/38] KVM: arm64: Trap CPACR_EL1 access in virtual EL2 Date: Tue, 18 Jul 2017 11:58:45 -0500 Message-Id: <1500397144-16232-20-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For the same reason we trap virtual memory register accesses in virtual EL2, we trap CPACR_EL1 access too; We allow the virtual EL2 mode to access EL1 system register state instead of the virtual EL2 one. Signed-off-by: Jintack Lim --- arch/arm64/kvm/hyp/switch.c | 10 +++++++--- arch/arm64/kvm/sys_regs.c | 10 +++++++++- 2 files changed, 16 insertions(+), 4 deletions(-) -- 1.9.1 diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index ec91cd08..d513da9 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -42,7 +42,8 @@ bool __hyp_text __fpsimd_enabled(void) return __fpsimd_is_enabled()(); } -static void __hyp_text __activate_traps_vhe(void) +static void __hyp_text __activate_traps_vhe(struct kvm_vcpu *vcpu) + { u64 val; @@ -54,12 +55,15 @@ static void __hyp_text __activate_traps_vhe(void) write_sysreg(__kvm_hyp_vector, vbar_el1); } -static void __hyp_text __activate_traps_nvhe(void) +static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu) + { u64 val; val = CPTR_EL2_DEFAULT; val |= CPTR_EL2_TTA | CPTR_EL2_TFP; + if (vcpu_mode_el2(vcpu)) + val |= CPTR_EL2_TCPAC; write_sysreg(val, cptr_el2); } @@ -99,7 +103,7 @@ static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu) write_sysreg(0, pmselr_el0); write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0); write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2); - __activate_traps_arch()(); + __activate_traps_arch()(vcpu); } static void __hyp_text __deactivate_traps_vhe(void) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index b83fef2..7062645 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -960,6 +960,14 @@ static bool access_vbar(struct kvm_vcpu *vcpu, return true; } +static bool access_cpacr(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + access_rw(p, &vcpu_sys_reg(vcpu, r->reg)); + return true; +} + /* * Architected system registers. * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 @@ -1013,7 +1021,7 @@ static bool access_vbar(struct kvm_vcpu *vcpu, { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, - { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, + { SYS_DESC(SYS_CPACR_EL1), access_cpacr, reset_val, CPACR_EL1, 0 }, { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, From patchwork Tue Jul 18 16:58:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108167 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp6186704qge; Tue, 18 Jul 2017 10:07:33 -0700 (PDT) X-Received: by 10.98.76.145 with SMTP id e17mr2798176pfj.78.1500397653793; Tue, 18 Jul 2017 10:07:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397653; cv=none; d=google.com; s=arc-20160816; b=dFtF7aHwPrl98hzBZLuQxMtyiipXpHHbNbLXol74646P/4l1F/eqJKw+gwRgrlVWKi XRLIcgWtYNrXA3J7ElFIwVTGr5jVDfMyUeplt9lBgRpnd2486/iYhsZpho9PhNDdBi/m gSOn4Zs5lyap7YFjd2Oh8kj1P6jJS8IYtP6kxqBXWSEd0IfVZZtnvN0oMi/AR6ld38DL KHh63uK/2ndvLyicBJHcye1+/UNbuXl9eImSv3E4W3TmczICm99UCcf1Hbp1k2V3X45f vAVUsD/JUXGiS1GcamCEtAfIXZ6orgWE6DIC8KTWhaBC5xKC6bva1wSRawVt+5b5TDH9 KDjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=VpYnMlglPnVCmfktOSAHTQch804MdYvz/n57z6rGkQE=; b=Nr1Z4CqAR0aOhnp+pgKKL4IfA/PtUH0HkBaZULA9kPBwFNOM3qKoIjp3uORQzysGEm n3pz/pR5iSBlRMpBoMMnEbZrPuOxY1aDreqxgBGpZcwaIWgQP906C7L3/GJia+ABf5Ym F1YQWxsyRFjRvKnmPcseDlk+e4Jh1zR14xX7I7kvPpBFr9EqA2YvoF0nAyHhdMDDAelo r8qXfnu2CAV/XjWgpoqTHDo539VyR/Px6GVRjnnSxOjKlBfpPZQSRGfWYt371uGElh3c cagPUSdug5ZbXPBS5i4S7Rlx6uAcbqhjPedyirWbsGNkP5ClO02yK9es9akHhsuWRb6X S8OA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=dAY2OlDt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:08 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 20/38] KVM: arm64: Handle eret instruction traps Date: Tue, 18 Jul 2017 11:58:46 -0500 Message-Id: <1500397144-16232-21-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When HCR.NV bit is set, eret instructions trap to EL2 with EC code 0x1A. Emulate eret instructions by setting pc and pstate. Note that the current exception level is always the virtual EL2, since we set HCR_EL2.NV bit only when entering the virtual EL2. So, we take spsr and elr states from the virtual _EL2 registers. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/esr.h | 1 + arch/arm64/kvm/handle_exit.c | 16 ++++++++++++++++ arch/arm64/kvm/trace.h | 21 +++++++++++++++++++++ 3 files changed, 38 insertions(+) -- 1.9.1 diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index e7d8e28..210fde6 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -43,6 +43,7 @@ #define ESR_ELx_EC_HVC64 (0x16) #define ESR_ELx_EC_SMC64 (0x17) #define ESR_ELx_EC_SYS64 (0x18) +#define ESR_ELx_EC_ERET (0x1A) /* Unallocated EC: 0x19 - 0x1E */ #define ESR_ELx_EC_IMP_DEF (0x1f) #define ESR_ELx_EC_IABT_LOW (0x20) diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 17d8a16..9259881 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -147,6 +147,21 @@ static int kvm_handle_unknown_ec(struct kvm_vcpu *vcpu, struct kvm_run *run) return 1; } +static int kvm_handle_eret(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + trace_kvm_nested_eret(vcpu, vcpu_el2_sreg(vcpu, ELR_EL2), + vcpu_el2_sreg(vcpu, SPSR_EL2)); + + /* + * Note that the current exception level is always the virtual EL2, + * since we set HCR_EL2.NV bit only when entering the virtual EL2. + */ + *vcpu_pc(vcpu) = vcpu_el2_sreg(vcpu, ELR_EL2); + *vcpu_cpsr(vcpu) = vcpu_el2_sreg(vcpu, SPSR_EL2); + + return 1; +} + static exit_handle_fn arm_exit_handlers[] = { [0 ... ESR_ELx_EC_MAX] = kvm_handle_unknown_ec, [ESR_ELx_EC_WFx] = kvm_handle_wfx, @@ -160,6 +175,7 @@ static int kvm_handle_unknown_ec(struct kvm_vcpu *vcpu, struct kvm_run *run) [ESR_ELx_EC_HVC64] = handle_hvc, [ESR_ELx_EC_SMC64] = handle_smc, [ESR_ELx_EC_SYS64] = kvm_handle_sys_reg, + [ESR_ELx_EC_ERET] = kvm_handle_eret, [ESR_ELx_EC_IABT_LOW] = kvm_handle_guest_abort, [ESR_ELx_EC_DABT_LOW] = kvm_handle_guest_abort, [ESR_ELx_EC_SOFTSTP_LOW]= kvm_handle_guest_debug, diff --git a/arch/arm64/kvm/trace.h b/arch/arm64/kvm/trace.h index 7c86cfb..5f40987 100644 --- a/arch/arm64/kvm/trace.h +++ b/arch/arm64/kvm/trace.h @@ -187,6 +187,27 @@ TP_printk("vcpu: %p, inject exception to vEL2: ESR_EL2 0x%lx, vector: 0x%016lx", __entry->vcpu, __entry->esr_el2, __entry->pc) ); + +TRACE_EVENT(kvm_nested_eret, + TP_PROTO(struct kvm_vcpu *vcpu, unsigned long elr_el2, + unsigned long spsr_el2), + TP_ARGS(vcpu, elr_el2, spsr_el2), + + TP_STRUCT__entry( + __field(struct kvm_vcpu *, vcpu) + __field(unsigned long, elr_el2) + __field(unsigned long, spsr_el2) + ), + + TP_fast_assign( + __entry->vcpu = vcpu; + __entry->elr_el2 = elr_el2; + __entry->spsr_el2 = spsr_el2; + ), + + TP_printk("vcpu: %p, eret to elr_el2: 0x%016lx, with spsr_el2: 0x%08lx", + __entry->vcpu, __entry->elr_el2, __entry->spsr_el2) +); #endif /* _TRACE_ARM64_KVM_H */ #undef TRACE_INCLUDE_PATH From patchwork Tue Jul 18 16:58:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108166 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp6186676qge; Tue, 18 Jul 2017 10:07:32 -0700 (PDT) X-Received: by 10.101.77.69 with SMTP id j5mr2644357pgt.133.1500397652228; Tue, 18 Jul 2017 10:07:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397652; cv=none; d=google.com; s=arc-20160816; b=A+tLjWpC6FUnuGBT8XuXWAddAKwDyUzQfNIFg/CB3mNIr7GIcv//YynoifzCG7DlBY 6ilESsD4s/TtakHKJeqMl6Sy4luUoD5tHVWmeHx82yEOa82NiqWXVWOX6IjRH/Q48Oyt 50GePqdbcz0o1PiEm12fSz3dJOkoDX6/noDohnOSqIHfx84Ox1OiQJU0TA/Wy4AfjYfL 5igSeDKaBHOnkvSS07/t0MUWXVCHweYX+T/TbiLsGt651w5zhy8/P6DIBITjKegFCFPl eF6kmgiOB7vwFQCDo2Mdc4z4hmtX4C3QAEJqllpPz73KLkdfS75WxIs5cLihta8GtPHu Jvbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=v9ng7JXoZifgJ+iFBzrQ0taJ1+uyo+wn3PxM7RUYQAk=; b=ypOT8ogW3r1uOLTzSTKcKMaiSOmCEziCzh0XMG+oP6l2gGH/Z1LNEkRDREARbri7Cw 8ezd4kDGA8jxbLac01Et4eJ+PNWyL1CGLW2S10nIEQgDwynpuSa28bUNa+FLML7zm5ov FDXVdKAhR9op0cVXFsMLg5lTJ93A8LO7E8mY8AbUzAh/gCwXp+4u+XzmAZ5XZ6UnRmi/ Z0YJLPuUk+uuiYyADN3EKyO1xR3AsnEPb9MDW9C2jKob2yRxMn7CaY2L4wQ3rpD+0uTQ 3NFUYSDurE49BLTqFwAlwN/d1w+zRpVtkf3mbdcGGA/ONrCL8oDGBLMCgcb1FmsAzy/t MMLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=S8voPEXT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:10 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 21/38] KVM: arm64: Set a handler for the system instruction traps Date: Tue, 18 Jul 2017 11:58:47 -0500 Message-Id: <1500397144-16232-22-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When HCR.NV bit is set, execution of the EL2 translation regime address aranslation instructions and TLB maintenance instructions are trapped to EL2. In addition, execution of the EL1 translation regime address aranslation instructions and TLB maintenance instructions that are only accessible from EL2 and above are trapped to EL2. In these cases, ESR_EL2.EC will be set to 0x18. Change the existing handler to handle those system instructions as well as MRS/MSR instructions. Emulation of each system instructions will be done in separate patches. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/kvm_coproc.h | 2 +- arch/arm64/kvm/handle_exit.c | 2 +- arch/arm64/kvm/sys_regs.c | 53 ++++++++++++++++++++++++++++++++----- arch/arm64/kvm/trace.h | 2 +- 4 files changed, 50 insertions(+), 9 deletions(-) -- 1.9.1 diff --git a/arch/arm64/include/asm/kvm_coproc.h b/arch/arm64/include/asm/kvm_coproc.h index 0b52377..1b3d21b 100644 --- a/arch/arm64/include/asm/kvm_coproc.h +++ b/arch/arm64/include/asm/kvm_coproc.h @@ -43,7 +43,7 @@ void kvm_register_target_sys_reg_table(unsigned int target, int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run); int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run); int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run); -int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run); +int kvm_handle_sys(struct kvm_vcpu *vcpu, struct kvm_run *run); #define kvm_coproc_table_init kvm_sys_reg_table_init void kvm_sys_reg_table_init(void); diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 9259881..d19e253 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -174,7 +174,7 @@ static int kvm_handle_eret(struct kvm_vcpu *vcpu, struct kvm_run *run) [ESR_ELx_EC_SMC32] = handle_smc, [ESR_ELx_EC_HVC64] = handle_hvc, [ESR_ELx_EC_SMC64] = handle_smc, - [ESR_ELx_EC_SYS64] = kvm_handle_sys_reg, + [ESR_ELx_EC_SYS64] = kvm_handle_sys, [ESR_ELx_EC_ERET] = kvm_handle_eret, [ESR_ELx_EC_IABT_LOW] = kvm_handle_guest_abort, [ESR_ELx_EC_DABT_LOW] = kvm_handle_guest_abort, diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 7062645..dbf5022 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1808,6 +1808,40 @@ static int emulate_sys_reg(struct kvm_vcpu *vcpu, return 1; } +static int emulate_tlbi(struct kvm_vcpu *vcpu, + struct sys_reg_params *params) +{ + /* TODO: support tlbi instruction emulation*/ + kvm_inject_undefined(vcpu); + return 1; +} + +static int emulate_at(struct kvm_vcpu *vcpu, + struct sys_reg_params *params) +{ + /* TODO: support address translation instruction emulation */ + kvm_inject_undefined(vcpu); + return 1; +} + +static int emulate_sys_instr(struct kvm_vcpu *vcpu, + struct sys_reg_params *params) +{ + int ret = 0; + + /* TLB maintenance instructions*/ + if (params->CRn == 0b1000) + ret = emulate_tlbi(vcpu, params); + /* Address Translation instructions */ + else if (params->CRn == 0b0111 && params->CRm == 0b1000) + ret = emulate_at(vcpu, params); + + if (ret) + kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); + + return ret; +} + static void reset_sys_reg_descs(struct kvm_vcpu *vcpu, const struct sys_reg_desc *table, size_t num) { @@ -1819,18 +1853,19 @@ static void reset_sys_reg_descs(struct kvm_vcpu *vcpu, } /** - * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access + * kvm_handle_sys-- handles a system instruction or mrs/msr instruction trap + on a guest execution * @vcpu: The VCPU pointer * @run: The kvm_run struct */ -int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run) +int kvm_handle_sys(struct kvm_vcpu *vcpu, struct kvm_run *run) { struct sys_reg_params params; unsigned long esr = kvm_vcpu_get_hsr(vcpu); int Rt = kvm_vcpu_sys_get_rt(vcpu); int ret; - trace_kvm_handle_sys_reg(esr); + trace_kvm_handle_sys(esr); params.is_aarch32 = false; params.is_32bit = false; @@ -1842,10 +1877,16 @@ int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run) params.regval = vcpu_get_reg(vcpu, Rt); params.is_write = !(esr & 1); - ret = emulate_sys_reg(vcpu, ¶ms); + if (params.Op0 == 1) { + /* System instructions */ + ret = emulate_sys_instr(vcpu, ¶ms); + } else { + /* MRS/MSR instructions */ + ret = emulate_sys_reg(vcpu, ¶ms); + if (!params.is_write) + vcpu_set_reg(vcpu, Rt, params.regval); + } - if (!params.is_write) - vcpu_set_reg(vcpu, Rt, params.regval); return ret; } diff --git a/arch/arm64/kvm/trace.h b/arch/arm64/kvm/trace.h index 5f40987..192708e 100644 --- a/arch/arm64/kvm/trace.h +++ b/arch/arm64/kvm/trace.h @@ -134,7 +134,7 @@ TP_printk("%s %s reg %d (0x%08llx)", __entry->fn, __entry->is_write?"write to":"read from", __entry->reg, __entry->write_value) ); -TRACE_EVENT(kvm_handle_sys_reg, +TRACE_EVENT(kvm_handle_sys, TP_PROTO(unsigned long hsr), TP_ARGS(hsr), From patchwork Tue Jul 18 16:58:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108168 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp6187330qge; Tue, 18 Jul 2017 10:08:02 -0700 (PDT) X-Received: by 10.84.137.1 with SMTP id 1mr2726910plm.75.1500397682500; Tue, 18 Jul 2017 10:08:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397682; cv=none; d=google.com; s=arc-20160816; b=vfzWLDid1hFBePC9wQlpYgst2P6061A2q06cvRaHpd23NNlb4caTbPHjH8TNBYlBNk oRbb+vkSFiCPR146JNsfg+Bcu/N2zfKWEyo95Ijmi45onKLsF6/ODWIRoIVNTj9KqdDF nSjBBfc2sH0UoIhOETTNV1v+wGQCRwVinr0c0i74UK+U/NrFet1mVY/W7JXlopG2V3Kf rNxeR8rA8wfyKDRKWIPwtu2yHfKpb/zPznKk31xZqd3DpKbpxK0CtsSqDS7Oy8nAWGQX t9d35o2Dsz+CmZDju4XI8X5CsU7UkAB2V3exr3HaBqoIoj4UjXQBSqoBxFOuTvY/SbrI V3iQ== ARC-Message-Signature: i=1; a=rsa-sha256; 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:12 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 22/38] KVM: arm64: Handle PSCI call via smc from the guest Date: Tue, 18 Jul 2017 11:58:48 -0500 Message-Id: <1500397144-16232-23-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org VMs used to execute hvc #0 for the psci call if EL3 is not implemented. However, when we come to provide the virtual EL2 mode to the VM, the host OS inside the VM calls kvm_call_hyp() which is also hvc #0. So, it's hard to differentiate between them from the host hypervisor's point of view. So, let the VM execute smc instruction for the psci call. On ARMv8.3, even if EL3 is not implemented, a smc instruction executed at non-secure EL1 is trapped to EL2 if HCR_EL2.TSC==1, rather than being treated as UNDEFINED. So, the host hypervisor can handle this psci call without any confusion. Signed-off-by: Jintack Lim --- arch/arm64/kvm/handle_exit.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index d19e253..6cf6b93 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -53,8 +53,28 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run) static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run) { - kvm_inject_undefined(vcpu); - return 1; + int ret; + + /* If imm is non-zero, it's not defined */ + if (kvm_vcpu_hvc_get_imm(vcpu)) { + kvm_inject_undefined(vcpu); + return 1; + } + + /* + * If imm is zero, it's a psci call. + * Note that on ARMv8.3, even if EL3 is not implemented, SMC executed + * at Non-secure EL1 is trapped to EL2 if HCR_EL2.TSC==1, rather than + * being treated as UNDEFINED. + */ + ret = kvm_psci_call(vcpu); + if (ret < 0) { + kvm_inject_undefined(vcpu); + return 1; + } + kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); + + return ret; } /* From patchwork Tue Jul 18 16:58:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108165 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6156541obm; Tue, 18 Jul 2017 10:06:43 -0700 (PDT) X-Received: by 10.98.88.66 with SMTP id m63mr2697411pfb.51.1500397603627; Tue, 18 Jul 2017 10:06:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397603; cv=none; d=google.com; s=arc-20160816; b=Nqe9tUKfZOiVV9AWQmOPN9/r7r5Rl9YoYTKOebeUbsZcN1csvMOSojucbJmyYE3Jup U603F7tktZVNYFpgODuAnr36h9G7rvte6y3DeYX+bwciOaKeje/0wLBgKGcQ/yYeNYOV va+UGD2aODqEozl9q352tzLNCZr07zC/mJlI+gCEcE1bpUYBEXWQ4qV8RnfowqcK5F1D ArRLdmeQD9f8epsnr89FtOHv7aOQjL1liETZ8N78P2keqBKMV2yttT2a2NHXimlnDrLb CrZub+tao4Sp0tszCslhcLYKVASqW79geu4uHxi/KE9xm49eLBpfI9Nx+jOB6qHPz1QK R4bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=ZRWx2Swikq8DPW+kJomamLkrE5+EYLN8kUpHckOCxwI=; b=Sve0z7JkqANeIjqssKlL1YbadDc9iEB5WtQ6xt6sF3t/QwNe8DU2q+z2wzXFkCpAGg eCyZFdZyriHsYdBM+IwKuV+kjPhY6FJ4FYkghc0Omc8L7KuwxfQ0IAi7TDmbqcOi0Exv JHDWzOZRZU3X7V3xULrNwc8UiXIp9KBODaHsvC4mIZ6kA493R42ks34JdU1P10HJZOjv f5JnYgTN6Qq5QqBAnEqTdquPDm5I4nKDPTD3KKL92ujIe64BFL939E756qJ332jQNlgd DgsSdaLWjv9jJQG3k4YM8vovFCtstg4dJ3db3PbFxATQw82+2nxOHeS8GPvMfqRSqA1D RXhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=S8KJDMp+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:13 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 23/38] KVM: arm64: Inject HVC exceptions to the virtual EL2 Date: Tue, 18 Jul 2017 11:58:49 -0500 Message-Id: <1500397144-16232-24-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that the psci call is done by the smc instruction when nested virtualization is enabled, it is clear that all hvc instruction from the VM (including from the virtual EL2) are supposed to handled in the virtual EL2. Signed-off-by: Jintack Lim --- arch/arm64/kvm/handle_exit.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 1.9.1 diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 6cf6b93..8b398b2 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -42,6 +42,12 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run) kvm_vcpu_hvc_get_imm(vcpu)); vcpu->stat.hvc_exit_stat++; + /* Forward hvc instructions to the virtual EL2 if the guest has EL2. */ + if (nested_virt_in_use(vcpu)) { + kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + return 1; + } + ret = kvm_psci_call(vcpu); if (ret < 0) { kvm_inject_undefined(vcpu); From patchwork Tue Jul 18 16:58:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108164 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6155627obm; Tue, 18 Jul 2017 10:05:52 -0700 (PDT) X-Received: by 10.99.145.67 with SMTP id l64mr2793267pge.184.1500397552911; Tue, 18 Jul 2017 10:05:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397552; cv=none; d=google.com; s=arc-20160816; b=jbSrr52Fn12KJJWQHt+862EOQZfwXRjtmWkB6pXL4vp4q8B6BKthuvgUalfnI/3N00 ES3v3EUV79UK+mCbVw2UTM2icEbK5/fmnhgCEIaWQO9GxEPgzAXCrTGVEcggh2g1Q5Zf BKLEhN3yZgkdCZMgqhohfK3C4he/DGQ2kJfxmWHgzUaY0iy/OfnnV3A2QZhETIlPTjs1 /JxblY27YuTVHE9TRqq472s1Iuuvi71Dfpe+r0MqVfo6LJHw8emsMiGF9QfzYmvuoxc0 DizMMby3eUoVBaSuznybuKqbOXzpzz0BjbufQHeYcVxY6zGx09S/F2/prfrWyzh0HuSD e+tA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=r0TbfSmYolF1B4i1TJyduZHKE3K6Ho915piO3zAsk4U=; b=CmR3yHsiarhRVPCMMNX3xCjyXtCMS6+hoTnVvnIsc5BuxAx7YV00qdcVSc0i9HBoRM AKbK1MFlFYNQTTiMqvcpdVF+nyndAs6m5EU66Wqi+DCacSHPmRNhKqyxhFz0puHffshA gukPPH5nIJ6nD06HgbY12Z7k0YefNoUyuYsrYGHAo+ruoriicMNqOiS+8jtI5bCeUi6Q qIMlpVtPDgmL4jrzj1BFV4M54yzDov9TE7e39tHwjA6aZgG1waey4oOwvRw4AUbkoy6X ZwHqnsTUwmYbxy0nP6t9x6e/oA/M1i49QCvA4M4MlQMrWtoI29ZDy9lQMz4CySRUO77G 11LA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=UqW2AHGG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:15 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 24/38] KVM: arm64: Respect virtual HCR_EL2.TWX setting Date: Tue, 18 Jul 2017 11:58:50 -0500 Message-Id: <1500397144-16232-25-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Forward exceptions due to WFI or WFE instructions to the virtual EL2 if they are not coming from the virtual EL2 and virtual HCR_EL2.TWX is set. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/handle_exit.c | 13 ++++++++++++- arch/arm64/kvm/nested.c | 20 ++++++++++++++++++++ 3 files changed, 33 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 46880c3..53b0b33 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -442,5 +442,6 @@ static inline void __cpu_init_stage2(void) int __init kvmarm_nested_cfg(char *buf); int init_nested_virt(void); bool nested_virt_in_use(struct kvm_vcpu *vcpu); +int handle_wfx_nested(struct kvm_vcpu *vcpu, bool is_wfe); #endif /* __ARM64_KVM_HOST_H__ */ diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 8b398b2..25ec824 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -107,7 +107,18 @@ static int handle_no_fpsimd(struct kvm_vcpu *vcpu, struct kvm_run *run) */ static int kvm_handle_wfx(struct kvm_vcpu *vcpu, struct kvm_run *run) { - if (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WFx_ISS_WFE) { + bool is_wfe = !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WFx_ISS_WFE); + + if (nested_virt_in_use(vcpu)) { + int ret = handle_wfx_nested(vcpu, is_wfe); + + if (ret < 0 && ret != -EINVAL) + return ret; + else if (ret >= 0) + return ret; + } + + if (is_wfe) { trace_kvm_wfx_arm64(*vcpu_pc(vcpu), true); vcpu->stat.wfe_exit_stat++; kvm_vcpu_on_spin(vcpu); diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index 9a05c76..042d304 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -18,6 +18,8 @@ #include #include +#include + static bool nested_param; int __init kvmarm_nested_cfg(char *buf) @@ -41,3 +43,21 @@ bool nested_virt_in_use(struct kvm_vcpu *vcpu) return false; } + +/* + * Inject wfx to the virtual EL2 if this is not from the virtual EL2 and + * the virtual HCR_EL2.TWX is set. Otherwise, let the host hypervisor + * handle this. + */ +int handle_wfx_nested(struct kvm_vcpu *vcpu, bool is_wfe) +{ + u64 hcr_el2 = vcpu_sys_reg(vcpu, HCR_EL2); + + if (vcpu_mode_el2(vcpu)) + return -EINVAL; + + if ((is_wfe && (hcr_el2 & HCR_TWE)) || (!is_wfe && (hcr_el2 & HCR_TWI))) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + + return -EINVAL; +} From patchwork Tue Jul 18 16:58:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108147 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6148947obm; Tue, 18 Jul 2017 10:00:29 -0700 (PDT) X-Received: by 10.101.89.6 with SMTP id f6mr2748387pgu.270.1500397229360; Tue, 18 Jul 2017 10:00:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397229; cv=none; d=google.com; s=arc-20160816; b=G8DblqX/CNHEe/liuiNY7qfX6V6M+iYM36epKfZKjXnFTSpmTE53/9OR25z0aadhkg p6HbcqsxYX0bPU/5l0v57tLnIMFPuU+FeR0fNFj4yHqz3izEbYUcgEvZ09hD1VxOeOp9 dfd8WjD4xFS4npYJfKSqqTk8ptRVvfusGlhIpwrqH5EccO/VaA22/YE882DZKvpka+ww kjSRtS5YoIpqFbxOQCoXSjQ24AI3PKK+3M4Uj2IMO8cGu75JrVGJW2x1lPDcMOjWIX6D PprncI+3uvYeq5dbEphmiDI6Ihy7k0s1eb6dLhbsvLJFe2tN02uDaC7qebKWX8T15tkU vw8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=HD6tiVnPQXrP5ruY0ol51yXrKvh5Xohm2NIzSxIZQ3Y=; b=cNBfioB0ZRJy4kK98+x/2tNAo3VX7veBzKCTJ9YaPvw799e37dHIm1mBaoc6kHKFH+ AEWYOk/1vUUYjMPPHFafzfHen70C/rUJ9LhMufigLbCgJzN40//6U0Z+IGsRFE9cY0vO UsfqbJ/JcCN/95aUiQdM2jZGLWOPy2miOusgREGCizLWKAQBZYkMFfVXHcyVxMJ9FBok z/QFVLBrc/Yi18dg6SZZhE0srYiYKexztHmWI0AciW2YJUxUFbn6PVklviAvzh7Rw1uR 6YJCs3KKM89v2Ay18noOQ/tsx2awOJxG7BGTr/FJxFqKHc2zYh07M6Ih8Gm8h+pUEtkb e1nQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=jafG7YUK; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:17 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 25/38] KVM: arm64: Respect virtual CPTR_EL2.TFP setting Date: Tue, 18 Jul 2017 11:58:51 -0500 Message-Id: <1500397144-16232-26-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Forward traps due to FP/ASIMD register accesses to the virtual EL2 if virtual CPTR_EL2.TFP is set. Note that if TFP bit is set, then even accesses to FP/ASIMD register from EL2 as well as NS EL0/1 will trap to EL2. So, we don't check the VM's exception level. Signed-off-by: Jintack Lim --- arch/arm64/kernel/asm-offsets.c | 1 + arch/arm64/kvm/handle_exit.c | 15 +++++++++++---- arch/arm64/kvm/hyp/entry.S | 13 +++++++++++++ arch/arm64/kvm/hyp/hyp-entry.S | 2 +- 4 files changed, 26 insertions(+), 5 deletions(-) -- 1.9.1 diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c index b3bb7ef..f5117a3 100644 --- a/arch/arm64/kernel/asm-offsets.c +++ b/arch/arm64/kernel/asm-offsets.c @@ -134,6 +134,7 @@ int main(void) DEFINE(CPU_FP_REGS, offsetof(struct kvm_regs, fp_regs)); DEFINE(VCPU_FPEXC32_EL2, offsetof(struct kvm_vcpu, arch.ctxt.sys_regs[FPEXC32_EL2])); DEFINE(VCPU_HOST_CONTEXT, offsetof(struct kvm_vcpu, arch.host_cpu_context)); + DEFINE(VIRTUAL_CPTR_EL2, offsetof(struct kvm_vcpu, arch.ctxt.sys_regs[CPTR_EL2])); #endif #ifdef CONFIG_CPU_PM DEFINE(CPU_SUSPEND_SZ, sizeof(struct cpu_suspend_ctx)); diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 25ec824..d4e7b2b 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -84,11 +84,18 @@ static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run) } /* - * Guest access to FP/ASIMD registers are routed to this handler only - * when the system doesn't support FP/ASIMD. + * When the system supports FP/ASMID and we are NOT running nested + * virtualization, FP/ASMID traps are handled in EL2 directly. + * This handler handles the cases those are not belong to the above case. */ -static int handle_no_fpsimd(struct kvm_vcpu *vcpu, struct kvm_run *run) +static int kvm_handle_fpasimd(struct kvm_vcpu *vcpu, struct kvm_run *run) { + + /* This is for nested virtualization */ + if (vcpu_sys_reg(vcpu, CPTR_EL2) & CPTR_EL2_TFP) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + + /* This is the case when the system doesn't support FP/ASIMD. */ kvm_inject_undefined(vcpu); return 1; } @@ -220,7 +227,7 @@ static int kvm_handle_eret(struct kvm_vcpu *vcpu, struct kvm_run *run) [ESR_ELx_EC_BREAKPT_LOW]= kvm_handle_guest_debug, [ESR_ELx_EC_BKPT32] = kvm_handle_guest_debug, [ESR_ELx_EC_BRK64] = kvm_handle_guest_debug, - [ESR_ELx_EC_FP_ASIMD] = handle_no_fpsimd, + [ESR_ELx_EC_FP_ASIMD] = kvm_handle_fpasimd, }; static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu) diff --git a/arch/arm64/kvm/hyp/entry.S b/arch/arm64/kvm/hyp/entry.S index 12ee62d..95af673 100644 --- a/arch/arm64/kvm/hyp/entry.S +++ b/arch/arm64/kvm/hyp/entry.S @@ -158,6 +158,19 @@ abort_guest_exit_end: 1: ret ENDPROC(__guest_exit) +ENTRY(__fpsimd_guest_trap) + // If virtual CPTR_EL2.TFP is set, then forward the trap to the + // virtual EL2. For the non-nested case, this bit is always 0. + mrs x1, tpidr_el2 + ldr x0, [x1, #VIRTUAL_CPTR_EL2] + and x0, x0, #CPTR_EL2_TFP + cbnz x0, 1f + b __fpsimd_guest_restore +1: + mov x0, #ARM_EXCEPTION_TRAP + b __guest_exit +ENDPROC(__fpsimd_guest_trap) + ENTRY(__fpsimd_guest_restore) stp x2, x3, [sp, #-16]! stp x4, lr, [sp, #-16]! diff --git a/arch/arm64/kvm/hyp/hyp-entry.S b/arch/arm64/kvm/hyp/hyp-entry.S index 5170ce1..ab169fd 100644 --- a/arch/arm64/kvm/hyp/hyp-entry.S +++ b/arch/arm64/kvm/hyp/hyp-entry.S @@ -113,7 +113,7 @@ el1_trap: */ alternative_if_not ARM64_HAS_NO_FPSIMD cmp x0, #ESR_ELx_EC_FP_ASIMD - b.eq __fpsimd_guest_restore + b.eq __fpsimd_guest_trap alternative_else_nop_endif mrs x1, tpidr_el2 From patchwork Tue Jul 18 16:58:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108161 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6154398obm; Tue, 18 Jul 2017 10:04:46 -0700 (PDT) X-Received: by 10.84.191.131 with SMTP id a3mr2744944pld.279.1500397486008; Tue, 18 Jul 2017 10:04:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397486; cv=none; d=google.com; s=arc-20160816; b=FJTwORNkfNceNHzzEu0O1oiUlmF+onsx9Bi8zAYLOKRXhPXF0UOA6YKePqJ7e+KIO5 zdK3l0FAB0nAd01ca8HCoA+25bveY/Rgfu7OQrzx9Y9G9lnNJGM6DJVOO0C8mAEsw9gY TTHvXGunV9wuJGqg37BD+JaHOhJFOm82p7EDCRwmSP6+e1n42vo6pJNqPYIdfd1UPFU3 fMzhKdvZd7i/IUuBl+lNh3vxsVaNGXJ/6eTkn+pQfwYJnzEC68XWmvWDLkrr0TCbD+EV eBA1dGlvIrwOzv2l/57ThecsdGc3oLXaThibu6vpLZANe7g1jaeOaOoyTw195iESk6Ub 5nxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=wzOSyQMrKTDK4dX0Too1hK5ddjKST2O3EkJkca+aWQM=; b=filx9kqaJ7eFE7+ltfOsMSUskqv8zoP/VtLhnbfv9ci7FLnOdz7YocUSnUOLfLaU6t 37k8azF2gAad423DzLRwdzIJ0nYKxSiRUYALLA9fQ4p48iYFSEiziKDM60Mqfd9YgB03 q4lpaPuFYoZdPO/opm8r2vhAkbT6zoh9sh3bP5ttzOrK1qTLK3koW+StqFqoVkKnJkMd 65/TQiiMk8ze3jC0tV76ZkCB9r/eDLeKUcEVbqTLcld+6dhMWLH9n4krnfO0Blutc6Nf eIB7GhnalZSVJd/crdQroxwPQUcbuCNoO2t1XlrFc5EG0E4LoCSHUn0G0l0ZevFpWarI X+Zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=fUKpFGRD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:19 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 26/38] KVM: arm64: Add macros to support the virtual EL2 with VHE Date: Tue, 18 Jul 2017 11:58:52 -0500 Message-Id: <1500397144-16232-27-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These macros will be used to support the virtual EL2 with VHE. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/kvm_emulate.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) -- 1.9.1 diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index 3017234..68aafbd 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -173,6 +173,30 @@ static inline bool vcpu_mode_el2(const struct kvm_vcpu *vcpu) return mode == PSR_MODE_EL2h || mode == PSR_MODE_EL2t; } +static inline bool vcpu_el2_e2h_is_set(const struct kvm_vcpu *vcpu) +{ + return (vcpu_sys_reg(vcpu, HCR_EL2) & HCR_E2H); +} + +static inline bool vcpu_el2_tge_is_set(const struct kvm_vcpu *vcpu) +{ + return (vcpu_sys_reg(vcpu, HCR_EL2) & HCR_TGE); +} + +static inline bool is_hyp_ctxt(const struct kvm_vcpu *vcpu) +{ + /* + * We are in a hypervisor context if the vcpu mode is EL2 or + * E2H and TGE bits are set. The latter means we are in the user space + * of the VHE kernel. ARMv8.1 ARM describes this as 'InHost' + */ + if (vcpu_mode_el2(vcpu) || + (vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu))) + return true; + + return false; +} + static inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu) { return vcpu->arch.fault.esr_el2; From patchwork Tue Jul 18 16:58:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108159 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6153732obm; Tue, 18 Jul 2017 10:04:08 -0700 (PDT) X-Received: by 10.99.122.94 with SMTP id j30mr1462187pgn.188.1500397448753; Tue, 18 Jul 2017 10:04:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397448; cv=none; d=google.com; s=arc-20160816; b=MoFtZfv0PYvzBPCOEUnaYkjzkLRFziLFdz6vo4Q6wXTlmWo1cIUws/etR69RwJX3AL 9MUeBwatgg1OqHtRLg4sIZczfA6BKo58m7hAy98EXzEY1ZMTuayNXJRewp1cojn2NH7Z pLr+QbCEj2/7yLL+JhOqE5Nsqu+tAqYfXnYfWtU68VB4faQCgbRcvpACKDTkZ3Jk9FI4 5PuGSvFFmglzWAOZp2Ih1CHjvTFJl26576oYKoY8UZzOXc/EZ+1G42LSZjeZir4GY0ml jaUOEy3FzkATsZqIQg2amLAGzuKXheTmfWoqQI2Bi5k09LCd3FvBIteMqsPimn7d+gxy fFvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=47yD867015Kg5okFVWRS+yIC3oPkfSt7gdaFVyNuIxo=; b=g7x0G0t4gojioZS7ouKW7SxHvsIzZ2V5Q67vIp1ZeA8oQ7UWh9hXrw3A9spQJWQu3l hlWQZ+c0KlIy/uApU3kUaC2uIRVcHZ6orunlWewnBUeskDMT5fm4p682nVfF4ib8H/EP pYGb0Uh+2WbDEFtODpzktQXy1iUQVJLz/nRrZNrQ0Bj4SpO6hzpQw/B0h8CvkHmAZDMG QYBnzwNbDtMZVZ+i6yzOlcUM5z4+sFNMFaHKRvm9E+jZkCa8kr7tEhr4aiKdcQx13haH a8dADKYOhjSjfYhjaHgJ0soK2eayGQd589C15FVgMasSxNPj2K9xWFFRhGZmGJRuoEuR hXSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=h2kjlpO2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:21 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 27/38] KVM: arm64: Add EL2 registers defined in ARMv8.1 to vcpu context Date: Tue, 18 Jul 2017 11:58:53 -0500 Message-Id: <1500397144-16232-28-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ARMv8.1 added more EL2 registers: TTBR1_EL2, CONTEXTIDR_EL2, and three EL2 virtual timer registers. Add the first two registers to vcpu context and set their handlers. The timer registers and their handlers will be added in a separate patch. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/include/asm/sysreg.h | 2 ++ arch/arm64/kvm/sys_regs.c | 2 ++ 3 files changed, 6 insertions(+) -- 1.9.1 diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 53b0b33..373235c 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -151,6 +151,7 @@ enum vcpu_sysreg { HSTR_EL2, /* Hypervisor System Trap Register */ HACR_EL2, /* Hypervisor Auxiliary Control Register */ TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ + TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ TCR_EL2, /* Translation Control Register (EL2) */ VTTBR_EL2, /* Virtualization Translation Table Base Register */ VTCR_EL2, /* Virtualization Translation Control Register */ @@ -164,6 +165,7 @@ enum vcpu_sysreg { VBAR_EL2, /* Vector Base Address Register (EL2) */ RVBAR_EL2, /* Reset Vector Base Address Register */ RMR_EL2, /* Reset Management Register */ + CONTEXTIDR_EL2, /* Context ID Register (EL2) */ TPIDR_EL2, /* EL2 Software Thread ID Register */ CNTVOFF_EL2, /* Counter-timer Virtual Offset register */ CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 6373d3d..b01c608 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -264,6 +264,7 @@ #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7) #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0) +#define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1) #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2) #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) @@ -331,6 +332,7 @@ #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) +#define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1) #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2) #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index dbf5022..b3e0cb8 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1168,6 +1168,7 @@ static bool access_cpacr(struct kvm_vcpu *vcpu, { SYS_DESC(SYS_HACR_EL2), trap_el2_regs, reset_val, HACR_EL2, 0 }, { SYS_DESC(SYS_TTBR0_EL2), trap_el2_regs, reset_val, TTBR0_EL2, 0 }, + { SYS_DESC(SYS_TTBR1_EL2), trap_el2_regs, reset_val, TTBR1_EL2, 0 }, { SYS_DESC(SYS_TCR_EL2), trap_el2_regs, reset_val, TCR_EL2, 0 }, { SYS_DESC(SYS_VTTBR_EL2), trap_el2_regs, reset_val, VTTBR_EL2, 0 }, { SYS_DESC(SYS_VTCR_EL2), trap_el2_regs, reset_val, VTCR_EL2, 0 }, @@ -1194,6 +1195,7 @@ static bool access_cpacr(struct kvm_vcpu *vcpu, { SYS_DESC(SYS_RVBAR_EL2), trap_el2_regs, reset_val, RVBAR_EL2, 0 }, { SYS_DESC(SYS_RMR_EL2), trap_el2_regs, reset_val, RMR_EL2, 0 }, + { SYS_DESC(SYS_CONTEXTIDR_EL2), trap_el2_regs, reset_val, CONTEXTIDR_EL2, 0 }, { SYS_DESC(SYS_TPIDR_EL2), trap_el2_regs, reset_val, TPIDR_EL2, 0 }, { SYS_DESC(SYS_CNTVOFF_EL2), trap_el2_regs, reset_val, CNTVOFF_EL2, 0 }, From patchwork Tue Jul 18 16:58:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108148 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6149145obm; Tue, 18 Jul 2017 10:00:39 -0700 (PDT) X-Received: by 10.84.179.36 with SMTP id a33mr2827523plc.144.1500397239778; Tue, 18 Jul 2017 10:00:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397239; cv=none; d=google.com; s=arc-20160816; b=HiUCpk7G+YMI4YCyiPPvJMItAhQritY+jxdWxQUJ6yO+GAXQWAkWs6IDSahLLPdn1x 8NsfEHxhTnDJGFcd4kP4XoLMUcq9PEFuSTyzoQUNEOzIbZlOviGNm8TBeyzrzOaWT9ax 1YxXzHSFu8I/IO/V8+xZHtxTTP8J+2opee4nVO2e9pLGUuy3Y2HPu6TFNzX7ltykwy/I t3AzPHnuMqMTIvhNSr8u0vfEsZE5+fKYk/tciLLOdFkZDLnxw7yXpe/vmxfUTs+VHGss 3c8nrxahp3SEUXoSVz4m9YgTvwWOWjuYOGzZ8nHpSPFtydcaM6nI2A/qK0sObtUkjhLy zgwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=gALCH1ZoFT3Icy79Atjbl956taiIBSgeUK/1cf1kfjk=; b=MUWo7FLiAA26xXtnxUPo1KtqynfpjyFj6qViIPck66RS9z6/BFzyuhnwlQL4pKlc3t oZN8MR4zHrB9TNA4GVc2pz8YNORvCi4lhB4A7Res5Cuf/PxUKfj/ax8Y1+xXkiQv93HS 3LkowiWMiNE68qmfUgQrLOWLTJT8QnHWlGSfzi824t/TVXzwrdC5dODSgLXDCsE07N9D tKD0aG0nd9xqfX7BoRnl0yBABRzim01zAYGy1jh6nH86t3e3fNnZ0AGtesfrLV3ns1yz fRV0LCGdX60xCOAM01BmC1RdhAD1QGyQjlYKapPpFVDJ98/ZQtbhoIJS46kQorM39WLB ANNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=AzC5Ax6b; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:23 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 28/38] KVM: arm64: Emulate EL12 register accesses from the virtual EL2 Date: Tue, 18 Jul 2017 11:58:54 -0500 Message-Id: <1500397144-16232-29-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org With HCR_EL2.NV bit set, accesses to EL12 registers in the virtual EL2 trap to EL2. Handle those traps just like we do for EL1 registers. One exception is CNTKCTL_EL12. We don't trap on CNTKCTL_EL1 for non-VHE virtual EL2 because we don't have to. However, accessing CNTKCTL_EL12 will trap since it's one of the EL12 registers controlled by HCR_EL2.NV bit. Therefore, add a handler for it and don't treat it as a non-trap-registers when preparing a shadow context. Move EL12 system register macros to a common place to reuse them. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/kvm_hyp.h | 24 ------------------------ arch/arm64/include/asm/sysreg.h | 24 ++++++++++++++++++++++++ arch/arm64/kvm/context.c | 7 +++++++ arch/arm64/kvm/sys_regs.c | 25 +++++++++++++++++++++++++ 4 files changed, 56 insertions(+), 24 deletions(-) -- 1.9.1 diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h index 4572a9b..353b895 100644 --- a/arch/arm64/include/asm/kvm_hyp.h +++ b/arch/arm64/include/asm/kvm_hyp.h @@ -73,30 +73,6 @@ #define read_sysreg_el1(r) read_sysreg_elx(r, _EL1, _EL12) #define write_sysreg_el1(v,r) write_sysreg_elx(v, r, _EL1, _EL12) -/* The VHE specific system registers and their encoding */ -#define sctlr_EL12 sys_reg(3, 5, 1, 0, 0) -#define cpacr_EL12 sys_reg(3, 5, 1, 0, 2) -#define ttbr0_EL12 sys_reg(3, 5, 2, 0, 0) -#define ttbr1_EL12 sys_reg(3, 5, 2, 0, 1) -#define tcr_EL12 sys_reg(3, 5, 2, 0, 2) -#define afsr0_EL12 sys_reg(3, 5, 5, 1, 0) -#define afsr1_EL12 sys_reg(3, 5, 5, 1, 1) -#define esr_EL12 sys_reg(3, 5, 5, 2, 0) -#define far_EL12 sys_reg(3, 5, 6, 0, 0) -#define mair_EL12 sys_reg(3, 5, 10, 2, 0) -#define amair_EL12 sys_reg(3, 5, 10, 3, 0) -#define vbar_EL12 sys_reg(3, 5, 12, 0, 0) -#define contextidr_EL12 sys_reg(3, 5, 13, 0, 1) -#define cntkctl_EL12 sys_reg(3, 5, 14, 1, 0) -#define cntp_tval_EL02 sys_reg(3, 5, 14, 2, 0) -#define cntp_ctl_EL02 sys_reg(3, 5, 14, 2, 1) -#define cntp_cval_EL02 sys_reg(3, 5, 14, 2, 2) -#define cntv_tval_EL02 sys_reg(3, 5, 14, 3, 0) -#define cntv_ctl_EL02 sys_reg(3, 5, 14, 3, 1) -#define cntv_cval_EL02 sys_reg(3, 5, 14, 3, 2) -#define spsr_EL12 sys_reg(3, 5, 4, 0, 0) -#define elr_EL12 sys_reg(3, 5, 4, 0, 1) - /** * hyp_alternate_select - Generates patchable code sequences that are * used to switch between two implementations of a function, depending diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index b01c608..b8d4d0c 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -338,6 +338,30 @@ #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3) #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0) +/* The VHE specific system registers and their encoding */ +#define sctlr_EL12 sys_reg(3, 5, 1, 0, 0) +#define cpacr_EL12 sys_reg(3, 5, 1, 0, 2) +#define ttbr0_EL12 sys_reg(3, 5, 2, 0, 0) +#define ttbr1_EL12 sys_reg(3, 5, 2, 0, 1) +#define tcr_EL12 sys_reg(3, 5, 2, 0, 2) +#define afsr0_EL12 sys_reg(3, 5, 5, 1, 0) +#define afsr1_EL12 sys_reg(3, 5, 5, 1, 1) +#define esr_EL12 sys_reg(3, 5, 5, 2, 0) +#define far_EL12 sys_reg(3, 5, 6, 0, 0) +#define mair_EL12 sys_reg(3, 5, 10, 2, 0) +#define amair_EL12 sys_reg(3, 5, 10, 3, 0) +#define vbar_EL12 sys_reg(3, 5, 12, 0, 0) +#define contextidr_EL12 sys_reg(3, 5, 13, 0, 1) +#define cntkctl_EL12 sys_reg(3, 5, 14, 1, 0) +#define cntp_tval_EL02 sys_reg(3, 5, 14, 2, 0) +#define cntp_ctl_EL02 sys_reg(3, 5, 14, 2, 1) +#define cntp_cval_EL02 sys_reg(3, 5, 14, 2, 2) +#define cntv_tval_EL02 sys_reg(3, 5, 14, 3, 0) +#define cntv_ctl_EL02 sys_reg(3, 5, 14, 3, 1) +#define cntv_cval_EL02 sys_reg(3, 5, 14, 3, 2) +#define spsr_EL12 sys_reg(3, 5, 4, 0, 0) +#define elr_EL12 sys_reg(3, 5, 4, 0, 1) + #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0) /* Common SCTLR_ELx flags. */ diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c index e1bc753..f3d3398 100644 --- a/arch/arm64/kvm/context.c +++ b/arch/arm64/kvm/context.c @@ -121,6 +121,13 @@ static void copy_shadow_non_trap_el1_state(struct kvm_vcpu *vcpu, bool setup) for (i = 0; i < ARRAY_SIZE(el1_non_trap_regs); i++) { const int sr = el1_non_trap_regs[i]; + /* + * We trap on cntkctl_el12 accesses from virtual EL2 as suppose + * to not trapping on cntlctl_el1 accesses. + */ + if (vcpu_el2_e2h_is_set(vcpu) && sr == CNTKCTL_EL1) + continue; + if (setup) s_sys_regs[sr] = vcpu_sys_reg(vcpu, sr); else diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index b3e0cb8..2aa922c 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -905,6 +905,14 @@ static inline void access_rw(struct sys_reg_params *p, u64 *sysreg) *sysreg = p->regval; } +static bool access_cntkctl_el12(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + access_rw(p, &vcpu_sys_reg(vcpu, r->reg)); + return true; +} + static u64 *get_special_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p) { u64 reg = sys_reg(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); @@ -1201,6 +1209,23 @@ static bool access_cpacr(struct kvm_vcpu *vcpu, { SYS_DESC(SYS_CNTVOFF_EL2), trap_el2_regs, reset_val, CNTVOFF_EL2, 0 }, { SYS_DESC(SYS_CNTHCTL_EL2), trap_el2_regs, reset_val, CNTHCTL_EL2, 0 }, + { SYS_DESC(sctlr_EL12), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, + { SYS_DESC(cpacr_EL12), access_cpacr, reset_val, CPACR_EL1, 0 }, + { SYS_DESC(ttbr0_EL12), access_vm_reg, reset_unknown, TTBR0_EL1 }, + { SYS_DESC(ttbr1_EL12), access_vm_reg, reset_unknown, TTBR1_EL1 }, + { SYS_DESC(tcr_EL12), access_vm_reg, reset_val, TCR_EL1, 0 }, + { SYS_DESC(spsr_EL12), access_spsr}, + { SYS_DESC(elr_EL12), access_elr}, + { SYS_DESC(afsr0_EL12), access_vm_reg, reset_unknown, AFSR0_EL1 }, + { SYS_DESC(afsr1_EL12), access_vm_reg, reset_unknown, AFSR1_EL1 }, + { SYS_DESC(esr_EL12), access_vm_reg, reset_unknown, ESR_EL1 }, + { SYS_DESC(far_EL12), access_vm_reg, reset_unknown, FAR_EL1 }, + { SYS_DESC(mair_EL12), access_vm_reg, reset_unknown, MAIR_EL1 }, + { SYS_DESC(amair_EL12), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, + { SYS_DESC(vbar_EL12), access_vbar, reset_val, VBAR_EL1, 0 }, + { SYS_DESC(contextidr_EL12), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, + { SYS_DESC(cntkctl_EL12), access_cntkctl_el12, reset_val, CNTKCTL_EL1, 0 }, + { SYS_DESC(SYS_SP_EL2), NULL, reset_special, SP_EL2, 0}, }; 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:24 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 29/38] KVM: arm64: Support a VM with VHE considering EL0 of the VHE host Date: Tue, 18 Jul 2017 11:58:55 -0500 Message-Id: <1500397144-16232-30-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On VHE systems, EL0 of the host kernel is considered as a part of 'VHE host'; The execution of EL0 is affected by system registers set by the VHE kernel including the hypervisor. To emulate this for a VM, we use the same set of system registers (i.e. shadow registers) for the virtual EL2 and EL0 execution. Note that the assumption so far is that a hypervisor in a VM always runs in the virtual EL2, and the exception level change from/to the virtual EL2 always goes through the host hypervisor. With VHE support for a VM, however, the exception level can be changed from EL0 to virtual EL2 without trapping to the host hypervisor. So, when returning from the VHE host mode, set the vcpu mode depending on the physical exception level. Signed-off-by: Jintack Lim --- arch/arm64/kvm/context.c | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) -- 1.9.1 diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c index f3d3398..39bd92d 100644 --- a/arch/arm64/kvm/context.c +++ b/arch/arm64/kvm/context.c @@ -150,16 +150,18 @@ static void flush_shadow_special_regs(struct kvm_vcpu *vcpu) struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; ctxt->hw_pstate = *vcpu_cpsr(vcpu) & ~PSR_MODE_MASK; - /* - * We can emulate the guest's configuration of which - * stack pointer to use when executing in virtual EL2 by - * using the equivalent feature in EL1 to point to - * either the EL1 or EL0 stack pointer. - */ - if ((*vcpu_cpsr(vcpu) & PSR_MODE_MASK) == PSR_MODE_EL2h) - ctxt->hw_pstate |= PSR_MODE_EL1h; - else - ctxt->hw_pstate |= PSR_MODE_EL1t; + if (vcpu_mode_el2(vcpu)) { + /* + * We can emulate the guest's configuration of which + * stack pointer to use when executing in virtual EL2 by + * using the equivalent feature in EL1 to point to + * either the EL1 or EL0 stack pointer. + */ + if ((*vcpu_cpsr(vcpu) & PSR_MODE_MASK) == PSR_MODE_EL2h) + ctxt->hw_pstate |= PSR_MODE_EL1h; + else + ctxt->hw_pstate |= PSR_MODE_EL1t; + } ctxt->hw_sys_regs = ctxt->shadow_sys_regs; ctxt->hw_sp_el1 = vcpu_el2_sreg(vcpu, SP_EL2); @@ -182,8 +184,14 @@ static void sync_shadow_special_regs(struct kvm_vcpu *vcpu) { struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; - *vcpu_cpsr(vcpu) &= PSR_MODE_MASK; - *vcpu_cpsr(vcpu) |= ctxt->hw_pstate & ~PSR_MODE_MASK; + *vcpu_cpsr(vcpu) = ctxt->hw_pstate; + *vcpu_cpsr(vcpu) &= ~PSR_MODE_MASK; + /* Set vcpu exception level depending on the physical EL */ + if ((ctxt->hw_pstate & PSR_MODE_MASK) == PSR_MODE_EL0t) + *vcpu_cpsr(vcpu) |= PSR_MODE_EL0t; + else + *vcpu_cpsr(vcpu) |= PSR_MODE_EL2h; + vcpu_el2_sreg(vcpu, SP_EL2) = ctxt->hw_sp_el1; vcpu_el2_sreg(vcpu, ELR_EL2) = ctxt->hw_elr_el1; vcpu_el2_sreg(vcpu, SPSR_EL2) = ctxt->hw_spsr_el1; @@ -218,7 +226,7 @@ void kvm_arm_setup_shadow_state(struct kvm_vcpu *vcpu) { struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; - if (unlikely(vcpu_mode_el2(vcpu))) { + if (unlikely(is_hyp_ctxt(vcpu))) { flush_shadow_special_regs(vcpu); flush_shadow_el1_sysregs(vcpu); flush_shadow_non_trap_el1_state(vcpu); @@ -236,7 +244,7 @@ void kvm_arm_setup_shadow_state(struct kvm_vcpu *vcpu) */ void kvm_arm_restore_shadow_state(struct kvm_vcpu *vcpu) { - if (unlikely(vcpu_mode_el2(vcpu))) { + if (unlikely(is_hyp_ctxt(vcpu))) { sync_shadow_special_regs(vcpu); sync_shadow_non_trap_el1_state(vcpu); } else From patchwork Tue Jul 18 16:58:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108149 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6149220obm; Tue, 18 Jul 2017 10:00:45 -0700 (PDT) X-Received: by 10.84.232.133 with SMTP id i5mr2808305plk.240.1500397244993; Tue, 18 Jul 2017 10:00:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397244; cv=none; d=google.com; s=arc-20160816; b=yWppAC3Eu/4967OEY63TUpeHI8GAGPzXc3O5BNv8wqw4GegPhhsiX/AfUGOz2x+UnN 8W+ZvahHKVOgoVqILaQeijtECpAZsFzbfQa0TMvaSDTV+ZmqDbG1/IxIlk1E0nuv7Dlg KO0FDgG4CFnkAUgKUhiXKYlI/diM2Duh97Y7bdCLkIsQt8oKYGB5PXCF9fIurLNwvZzp ynHIA5D22VJL6F3H9yb+n3ma8I4feEV3hwA07qe6gIhuBFazfj14pqXjvyjYBh7WOzdv VjacJNCbpDSWE4731D5PlWXahHoMhVq0N/1Sx3fko9Pg0JvQf/EvRI8ImaycX1oUqUcX /C7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=A5YKrD4BtfvlL3J+aGGhT8lU0VAdDRDlOkZU8kaE8W0=; b=Ua2bJ4c0yRdsqeVs6TWocZgJmDfL/tZF1Y1l9i+MhqLzdEsummnsLsVpvb6ZKQJx+1 +0CXywntxDkK59mDQIuSlC77Z5ffgXBsqliIfoZz7jYQ5hzXfOnKlgKPFaLjrz2TtfUn N1kkq2AxqnvDV5SOwasCEXfWefStbNopZ731AM5DjYcvg7C8ZaNCaWoRCygjUXemF2PT z7JNawEX4XiaXJA6OneuTKMFLpFhpZPUajxLRpw9MKCKdopKT6WLmvJrTpKecxSzsH8Q T32vAc1oT8mwtGRWLYU/PLdvOWcZx68hiWfAh4zuYoMNsIHwijzmuAAj17iNLsRnLl1p eRfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=RRIsYyXZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:26 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 30/38] KVM: arm64: Allow the virtual EL2 to access EL2 states without trap Date: Tue, 18 Jul 2017 11:58:56 -0500 Message-Id: <1500397144-16232-31-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When the virtual E2H bit is set, we can support EL2 register accesses via EL1 registers from the virtual EL2 by doing trap-and-emulate. A better alternative, however, is to allow the virtual EL2 to access EL2 register states without trap. This can be easily achieved by not traping EL1 registers since those registers already have EL2 register states. Signed-off-by: Jintack Lim --- arch/arm64/kvm/hyp/switch.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index d513da9..fffd0c7 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -74,6 +74,7 @@ static hyp_alternate_select(__activate_traps_arch, static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu) { u64 val; + u64 vhcr_el2; /* * We are about to set CPTR_EL2.TFP to trap all floating point @@ -89,8 +90,26 @@ static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu) write_sysreg(1 << 30, fpexc32_el2); isb(); } - if (vcpu_mode_el2(vcpu)) - val |= HCR_TVM | HCR_TRVM; + + if (is_hyp_ctxt(vcpu)) { + /* + * For a guest hypervisor on v8.0, trap and emulate the EL1 + * virtual memory control register accesses. + */ + if (!vcpu_el2_e2h_is_set(vcpu)) + val |= HCR_TVM | HCR_TRVM; + /* + * For a guest hypervisor on v8.1 (VHE), allow to access the + * EL1 virtual memory control registers natively. These accesses + * are to access EL2 register states. + * Note that we stil need to respect the virtual HCR_EL2 state. + */ + else { + vhcr_el2 = vcpu_sys_reg(vcpu, HCR_EL2); + val |= vhcr_el2 & (HCR_TVM | HCR_TRVM); + } + } + write_sysreg(val, hcr_el2); /* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */ write_sysreg(1 << 15, hstr_el2); From patchwork Tue Jul 18 16:58:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108158 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6152552obm; Tue, 18 Jul 2017 10:03:15 -0700 (PDT) X-Received: by 10.99.96.85 with SMTP id u82mr2763573pgb.214.1500397395432; Tue, 18 Jul 2017 10:03:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397395; cv=none; d=google.com; s=arc-20160816; b=ELSO2LgPQ1q2m87o2nwzgcEddF6U1sIK7/gnTNMp1zB1BSkZau/LzNWX1dqb/1O+7H mJylOGiABlzbAu+kdKtl+X/HAqM8O6dfz/bM/heeZT4v+YL4Ao9YmVfpl7U8Wqxr4ALR 3dUNssccfS72lc/6TA7tGo/ECc9rLECTYE5iZOA8OlrtM+BAXnOXvPLRD6vYyfRmiUNN BfVkszXsoyJkqt5BcCQ4joW+SPbGU5iW4JuVajmySnneLhjmAHPhYTfF9b5S8DzHCRBE TSOvVx/KpZRLAbolGOWhU2iMT4atXE0EeU5pwiB2rCAV1sgHuSaSe7Fv28MFAapo5dQh Xffg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=8KjAYZtqpeRGUcb4yBOwVe+PFyl5oXGPrMjlOuomUUE=; b=Bp4CikBwfHH0RsnChBO0LS0GG7zHukD4DPrkCXrlJuCbnDkjZ0OsVgybx9LI1Kqoek WBt7uM5ughOwtkTTIxYTqpWE+VUjbJNTbDmMrHdOQisyyAD78BU+Im1QeGFXjgJrCAl1 boD66UB26RX/jtWPZ8wYiAXsrPIKXCEjUQMnM43SFeM4fkDRUNAYO13JFWd7bvYMemmW MBfY3iYNDxpJfnJy//dZ7ciw+Z3Rr4SxFG/byi1ATIXBT2zLg2jUEUV/QboP/kBeDqy8 dqdUiTpk0gAs2lkkBXCE09o+ayI/e8Hn7mqfu2JV/ajD2TVgLTKAgXI24dg8BG/GX1nH CgbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=BCv7S676; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:29 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 31/38] KVM: arm64: Manage the shadow states when virtual E2H bit enabled Date: Tue, 18 Jul 2017 11:58:57 -0500 Message-Id: <1500397144-16232-32-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When creating the shadow context for the virtual EL2 execution, we can directly copy the EL2 register states to the shadow EL1 register states if the virtual HCR_EL2.E2H bit is set. This is because EL1 and EL2 system register formats compatible with E2H=1. Now that we allow the virtual EL2 modify its EL2 registers without trap via the physical EL1 system register accesses, we need to reflect the changes made to the EL1 system registers to the virtual EL2 register states. This is not required to the virtual EL2 without VHE, since the virtual EL2 should always use _EL2 accessors, which traps to EL2. Signed-off-by: Jintack Lim --- arch/arm64/kvm/context.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 66 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c index 39bd92d..9947bc8 100644 --- a/arch/arm64/kvm/context.c +++ b/arch/arm64/kvm/context.c @@ -39,6 +39,27 @@ struct el1_el2_map { { VBAR_EL1, VBAR_EL2 }, }; +/* + * List of pair of EL1/EL2 registers which are used to access real EL2 + * registers in EL2 with E2H bit set. + */ +static const struct el1_el2_map vhe_map[] = { + { SCTLR_EL1, SCTLR_EL2 }, + { CPACR_EL1, CPTR_EL2 }, + { TTBR0_EL1, TTBR0_EL2 }, + { TTBR1_EL1, TTBR1_EL2 }, + { TCR_EL1, TCR_EL2}, + { AFSR0_EL1, AFSR0_EL2 }, + { AFSR1_EL1, AFSR1_EL2 }, + { ESR_EL1, ESR_EL2}, + { FAR_EL1, FAR_EL2}, + { MAIR_EL1, MAIR_EL2 }, + { AMAIR_EL1, AMAIR_EL2 }, + { VBAR_EL1, VBAR_EL2 }, + { CONTEXTIDR_EL1, CONTEXTIDR_EL2 }, + { CNTKCTL_EL1, CNTHCTL_EL2 }, +}; + static inline u64 tcr_el2_ips_to_tcr_el1_ps(u64 tcr_el2) { return ((tcr_el2 & TCR_EL2_PS_MASK) >> TCR_EL2_PS_SHIFT) @@ -57,7 +78,27 @@ static inline u64 cptr_to_cpacr(u64 cptr_el2) return cpacr_el1; } -static void flush_shadow_el1_sysregs(struct kvm_vcpu *vcpu) +static void sync_shadow_el1_sysregs(struct kvm_vcpu *vcpu) +{ + u64 *s_sys_regs = vcpu->arch.ctxt.shadow_sys_regs; + int i; + + /* + * In the virtual EL2 without VHE no EL1 system registers can't be + * changed without trap except el1_non_trap_regs[]. So we have nothing + * to sync on exit from a guest. + */ + if (!vcpu_el2_e2h_is_set(vcpu)) + return; + + for (i = 0; i < ARRAY_SIZE(vhe_map); i++) { + const struct el1_el2_map *map = &vhe_map[i]; + + vcpu_sys_reg(vcpu, map->el2) = s_sys_regs[map->el1]; + } +} + +static void flush_shadow_el1_sysregs_nvhe(struct kvm_vcpu *vcpu) { u64 *s_sys_regs = vcpu->arch.ctxt.shadow_sys_regs; u64 tcr_el2; @@ -86,6 +127,29 @@ static void flush_shadow_el1_sysregs(struct kvm_vcpu *vcpu) s_sys_regs[CPACR_EL1] = cptr_to_cpacr(vcpu_sys_reg(vcpu, CPTR_EL2)); } +static void flush_shadow_el1_sysregs_vhe(struct kvm_vcpu *vcpu) +{ + u64 *s_sys_regs = vcpu->arch.ctxt.shadow_sys_regs; + int i; + + /* + * When e2h bit is set, EL2 registers becomes compatible + * with corrensponding EL1 registers. So, no conversion required. + */ + for (i = 0; i < ARRAY_SIZE(vhe_map); i++) { + const struct el1_el2_map *map = &vhe_map[i]; + + s_sys_regs[map->el1] = vcpu_sys_reg(vcpu, map->el2); + } +} + +static void flush_shadow_el1_sysregs(struct kvm_vcpu *vcpu) +{ + if (vcpu_el2_e2h_is_set(vcpu)) + flush_shadow_el1_sysregs_vhe(vcpu); + else + flush_shadow_el1_sysregs_nvhe(vcpu); +} /* * List of EL0 and EL1 registers which we allow the virtual EL2 mode to access @@ -247,6 +311,7 @@ void kvm_arm_restore_shadow_state(struct kvm_vcpu *vcpu) if (unlikely(is_hyp_ctxt(vcpu))) { sync_shadow_special_regs(vcpu); sync_shadow_non_trap_el1_state(vcpu); + sync_shadow_el1_sysregs(vcpu); } else sync_special_regs(vcpu); } From patchwork Tue Jul 18 16:58:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108157 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6152049obm; Tue, 18 Jul 2017 10:02:51 -0700 (PDT) X-Received: by 10.84.210.140 with SMTP id a12mr2710247pli.281.1500397371554; Tue, 18 Jul 2017 10:02:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397371; cv=none; d=google.com; s=arc-20160816; b=LXuHUhQOCsVSLw5OzjzW047cUDfGu6iL63JblRu5FcJ4e2RTKNUOASISLLIkjoCa6u Wo6yleZDtCbP1YWWXjefOfngd8tCfA0hofrRvmVEjHncqn8jAeTqvx5CJYzwHAoze7uT rVs/s7is6rRSqcb0SpFR76vmU9LM3aeyfCfbTSxnVim+6UoNZhBXcXDayCnsxNiQcs1d vifoqGczGT9DVHU48H/efebodgg2vkLjHJWD1dU16ef/vMmQANKyc0U3saXGa1yt2LCI vcpIu0bhwvdetfZe21z5K5HWCRoceiPHX9JQy2h3oyXjOiYhtacD9apdw9NkdsiGOVvB 4MDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=RTOCeD9C0Q0Zk3vCwtWb/h9OY7AIslrucChSVac3rQY=; b=hDMUi4e1jfpmT7mZKcXCl70XqcG6UbeEuI4pIQmAuKuoHu2ZXMBLjbdpjKbMbs4dlX lICoI4HjSjtpCOsbMPJ6yHrwVvya5h5RRGcM38IKOtXCEdg19yTUzUa0KY2GuZFqFGXO cXYVJrBM9RAUu0D78K1NjapFXPyTw5wxz9RlAx8W0oZW//ESqDjHdtP287o04clXZjad /VSfYG8Vpf+uUvTQPvycWcriA+E8tNg5b5paTHZpOCDRm+S9YXtT3xrYGlZb1vAbSpoR LwrqdTuyXhfEByoi11o6txrt9SwaQa0LBYFJOcppznADQnJ8RMiZRl4d9YDUDvuVOGTU lTzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=cBu/xqGO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:31 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 32/38] KVM: arm64: Trap and emulate CPTR_EL2 accesses via CPACR_EL1 from the virtual EL2 with VHE Date: Tue, 18 Jul 2017 11:58:58 -0500 Message-Id: <1500397144-16232-33-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org While the EL1 virtual memory control registers can be accessed in the virtual EL2 with VHE without trap to manuplate the virtual EL2 states, we can't do that for CPTR_EL2 for an unfortunate reason. This is because the top bit of CPTR_EL2, which is TCPAC, will be ignored if it is accessed via CPACR_EL1 in the virtual EL2 without trap since the top bot of cpacr_el1 is RES0. Therefore we need to trap CPACR_EL1 accesses from the virtual EL2 to emulate this bit correctly. Set CPTR_EL2.TCPAC bit to trap CPACR_EL1 accesses and handle them in the existing handler considering that they could be meant to access CPTR_EL2 instead in the virtual EL2 with VHE. Note that CPTR_EL2 format depends on HCR_EL2.E2H bit. We always keep it in v8.0 format for the convenience. Otherwise, we need to check E2H bit and use different bit masks in the entry.S, and we also check E2H bit in all places we access virtual CPTR_EL2. The downside of using v8.0 format is to convert the format when copying states between CPTR_EL2 and CPACR_EL1 to support the virtual EL2 with VHE. The decision is subject to change depending on the future discussion. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/kvm_emulate.h | 2 ++ arch/arm64/kvm/context.c | 29 ++++++++++++++++++++++++++--- arch/arm64/kvm/hyp/switch.c | 2 ++ arch/arm64/kvm/sys_regs.c | 18 +++++++++++++++++- 4 files changed, 47 insertions(+), 4 deletions(-) -- 1.9.1 diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index 68aafbd..4776bfc 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -59,6 +59,8 @@ enum exception_type { void kvm_arm_setup_shadow_state(struct kvm_vcpu *vcpu); void kvm_arm_restore_shadow_state(struct kvm_vcpu *vcpu); void kvm_arm_init_cpu_context(kvm_cpu_context_t *cpu_ctxt); +u64 cptr_to_cpacr(u64 cptr_el2); +u64 cpacr_to_cptr(u64 cpacr_el1); static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) { diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c index 9947bc8..a7811e1 100644 --- a/arch/arm64/kvm/context.c +++ b/arch/arm64/kvm/context.c @@ -66,7 +66,7 @@ static inline u64 tcr_el2_ips_to_tcr_el1_ps(u64 tcr_el2) << TCR_IPS_SHIFT; } -static inline u64 cptr_to_cpacr(u64 cptr_el2) +u64 cptr_to_cpacr(u64 cptr_el2) { u64 cpacr_el1 = 0; @@ -78,6 +78,21 @@ static inline u64 cptr_to_cpacr(u64 cptr_el2) return cpacr_el1; } +u64 cpacr_to_cptr(u64 cpacr_el1) +{ + u64 cptr_el2; + + cptr_el2 = CPTR_EL2_DEFAULT; + if (!(cpacr_el1 & CPACR_EL1_FPEN)) + cptr_el2 |= CPTR_EL2_TFP; + if (cpacr_el1 & CPACR_EL1_TTA) + cptr_el2 |= CPTR_EL2_TTA; + if (cpacr_el1 & CPTR_EL2_TCPAC) + cptr_el2 |= CPTR_EL2_TCPAC; + + return cptr_el2; +} + static void sync_shadow_el1_sysregs(struct kvm_vcpu *vcpu) { u64 *s_sys_regs = vcpu->arch.ctxt.shadow_sys_regs; @@ -93,8 +108,12 @@ static void sync_shadow_el1_sysregs(struct kvm_vcpu *vcpu) for (i = 0; i < ARRAY_SIZE(vhe_map); i++) { const struct el1_el2_map *map = &vhe_map[i]; + u64 *el2_reg = &vcpu_sys_reg(vcpu, map->el2); - vcpu_sys_reg(vcpu, map->el2) = s_sys_regs[map->el1]; + /* We do trap-and-emulate CPACR_EL1 accesses. So, don't sync */ + if (map->el2 == CPTR_EL2) + continue; + *el2_reg = s_sys_regs[map->el1]; } } @@ -138,8 +157,12 @@ static void flush_shadow_el1_sysregs_vhe(struct kvm_vcpu *vcpu) */ for (i = 0; i < ARRAY_SIZE(vhe_map); i++) { const struct el1_el2_map *map = &vhe_map[i]; + u64 *el1_reg = &s_sys_regs[map->el1]; - s_sys_regs[map->el1] = vcpu_sys_reg(vcpu, map->el2); + if (map->el2 == CPTR_EL2) + *el1_reg = cptr_to_cpacr(vcpu_sys_reg(vcpu, map->el2)); + else + *el1_reg = vcpu_sys_reg(vcpu, map->el2); } } diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index fffd0c7..50c90f2 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -50,6 +50,8 @@ static void __hyp_text __activate_traps_vhe(struct kvm_vcpu *vcpu) val = read_sysreg(cpacr_el1); val |= CPACR_EL1_TTA; val &= ~CPACR_EL1_FPEN; + if (is_hyp_ctxt(vcpu)) + val |= CPTR_EL2_TCPAC; write_sysreg(val, cpacr_el1); write_sysreg(__kvm_hyp_vector, vbar_el1); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 2aa922c..79980be 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -972,7 +972,23 @@ static bool access_cpacr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - access_rw(p, &vcpu_sys_reg(vcpu, r->reg)); + u64 reg = sys_reg(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); + + /* + * When the virtual HCR_EL2.E2H == 1, an access to CPACR_EL1 + * in the virtual EL2 is to access CPTR_EL2. + */ + if (vcpu_el2_e2h_is_set(vcpu) && (reg == SYS_CPACR_EL1)) { + u64 *sysreg = &vcpu_sys_reg(vcpu, CPTR_EL2); + + /* We keep the value in ARMv8.0 CPTR_EL2 format. */ + if (!p->is_write) + p->regval = cptr_to_cpacr(*sysreg); + else + *sysreg = cpacr_to_cptr(p->regval); + } else /* CPACR_EL1 access with E2H == 0 or CPACR_EL12 access */ + access_rw(p, &vcpu_sys_reg(vcpu, r->reg)); + return true; } From patchwork Tue Jul 18 16:58:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108155 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6151512obm; Tue, 18 Jul 2017 10:02:30 -0700 (PDT) X-Received: by 10.98.160.28 with SMTP id r28mr2686080pfe.86.1500397350131; Tue, 18 Jul 2017 10:02:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397350; cv=none; d=google.com; s=arc-20160816; b=Xh///nDR701YUzqyXFazW1en3IGhLIrrTSekcTf2q+AXPcYwfjhChJ6CAFob8WtH8N HxJHI5kwNFePx91aFclK2TRTNy6UcFeCwsENca4D2Q3GetxAylYrGj+M8QadE7MjkvbH T/NDbjMoj4yJD7CgbzmPqinCPmtXTiWl42kiJsRty8RzHzunnkuy6P8fKGuY/KzB50Cv gvfs5gZnXLZ6WTBTrVL2VNuI2zWbV9BwvwCMAA0QebOW2BP2wK4eMXGPWqU3jduVHZA/ pJfwqbNoJeoRSuGa1xw/nO84Gm7plHi9yhmE3A+LYGWj7HJE1w4Tt36rjVqh4X0UpKQG iqGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=sPeP/zP2VGDW9U2/yC+cePJT9VhyHR9hmPpj6cVo+1s=; b=wFyqfUDn05x7K4WURKqPHCPj53kgA2aaHrHlzRau69d24XcAl3G2An7y3mlf1fqTj0 VAemKiE8dfMxykOFpvhGhtYwxLO0W1SX73MF7fqKQiSM1m9IfhJA98k9+XZrY4FhZhFE w+euPgELvSLevDw1Q3kI0iuOJEplDqpB+ZvKbS8TB4+ElK7vQdltZQa+ervb700nFMGR uxamQVlzGsxXm/B0UhoOW1ElT96uKxa0/8vIH8+c9DMlsJkOO6TAHmYi7dGotOX6r8en RPt+3cGHxHWsGiYrQLweitBqveHBn4OVyRHGhOeyfldrIy9H9bEl6h5IzLgLEWbAkGF+ Lpzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=kLEJXSSP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:33 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 33/38] KVM: arm64: Emulate appropriate VM control system registers Date: Tue, 18 Jul 2017 11:58:59 -0500 Message-Id: <1500397144-16232-34-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that the virtual EL2 can access EL2 register states via EL1 registers, we need to consider it when selecting the register to emulate. Signed-off-by: Jintack Lim --- arch/arm64/kvm/sys_regs.c | 46 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 79980be..910b50d 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -110,6 +110,31 @@ static bool access_dcsw(struct kvm_vcpu *vcpu, return true; } +struct el1_el2_map { + int el1; + int el2; +}; + +static const struct el1_el2_map vm_map[] = { + {SCTLR_EL1, SCTLR_EL2}, + {TTBR0_EL1, TTBR0_EL2}, + {TTBR1_EL1, TTBR1_EL2}, + {TCR_EL1, TCR_EL2}, + {ESR_EL1, ESR_EL2}, + {FAR_EL1, FAR_EL2}, + {AFSR0_EL1, AFSR0_EL2}, + {AFSR1_EL1, AFSR1_EL2}, + {MAIR_EL1, MAIR_EL2}, + {AMAIR_EL1, AMAIR_EL2}, + {CONTEXTIDR_EL1, CONTEXTIDR_EL2}, +}; + +static inline bool el12_reg(struct sys_reg_params *p) +{ + /* All *_EL12 registers have Op1=5. */ + return (p->Op1 == 5); +} + /* * Generic accessor for VM registers. Only called as long as HCR_TVM * is set. If the guest enables the MMU, we stop trapping the VM @@ -120,16 +145,33 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { bool was_enabled = vcpu_has_cache_enabled(vcpu); + u64 *sysreg = &vcpu_sys_reg(vcpu, r->reg); + int i; + const struct el1_el2_map *map; + + /* + * Redirect EL1 register accesses to the corresponding EL2 registers if + * they are meant to access EL2 registers. + */ + if (vcpu_el2_e2h_is_set(vcpu) && !el12_reg(p)) { + for (i = 0; i < ARRAY_SIZE(vm_map); i++) { + map = &vm_map[i]; + if (map->el1 == r->reg) { + sysreg = &vcpu_sys_reg(vcpu, map->el2); + break; + } + } + } BUG_ON(!vcpu_mode_el2(vcpu) && !p->is_write); if (!p->is_write) { - p->regval = vcpu_sys_reg(vcpu, r->reg); + p->regval = *sysreg; return true; } if (!p->is_aarch32) { - vcpu_sys_reg(vcpu, r->reg) = p->regval; + *sysreg = p->regval; } else { if (!p->is_32bit) vcpu_cp15_64_high(vcpu, r->reg) = upper_32_bits(p->regval); From patchwork Tue Jul 18 16:59:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108151 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6149572obm; Tue, 18 Jul 2017 10:01:02 -0700 (PDT) X-Received: by 10.84.163.75 with SMTP id n11mr2805755plg.186.1500397262019; Tue, 18 Jul 2017 10:01:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397262; cv=none; d=google.com; s=arc-20160816; b=ttbW28R9oemoY7hfJUEfxANo+2SxI27WbQyqVI8HZ6HFujf3iumnxQCHKuzhfPLAaz vwRBklVgUpgOZiB+F7OkgANCU4WQ+5vObiB0X4x+n+4oSLmlSS92PlidQiw6rKXaqyI2 6zx09NbjDT09LOVw3oZobP8zjEIIec+uGAMlkzDbT4GwSXj3lcih8DJciT/OjgsxBEl6 fNHdfyR3j8dq4xkK7A1u/qUH2pT1GbU9lYIlIzyH2NiVqVoOOOU2QZ/4O9k5GGUG0ung us6q5tJSiK5UXOX0fvNLCClvA6WeCITBYb+XJnVWl6oVj/5SYZY94avqJi1zHA+H7RFv +gEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=G5Qtvk8sUMgkpfcgAgzvw9AkE1w5H7uqMAoeWmMPdMY=; b=jvnvm2b13bex3hJ2UbWMEsW+CE/wytU6vCgR0XH9jC8kIPR1gCR9y3tmYE3rc7Q6vO LJ0UjRjQ1qOC1cS2QQJLM5ZwjekceuS6iGuAiR0EfVVyEPn5cKeT0J+zwBbZ3UT3yL2+ Ce1jBPb1TZhma+fSQD5O7bOEHT1Z2a3WgqBUQXQggZQvb129/VN5FjywAf5p/l807gKH RUqDbDqkJPIJ7q1H2ADc7FILME9s4oRRp18xoP7ZXkwRTLar8quM+HuY1SAP5sbSVp1m uBC276zrOj7OvQkQuMS4T3SS/tAdyK+nA96lDGLsx8E6rrCx8fLmAj/JXXk0mMIUwIxx imeg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=VHEnrJLE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:35 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 34/38] KVM: arm64: Respect the virtual HCR_EL2.NV bit setting Date: Tue, 18 Jul 2017 11:59:00 -0500 Message-Id: <1500397144-16232-35-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Forward traps due to HCR_EL2.NV bit to the virtual EL2 if they are not coming from the virtual EL2 and the virtual HCR_EL2.NV bit is set. This is for recursive nested virtualization. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/kvm_arm.h | 1 + arch/arm64/include/asm/kvm_coproc.h | 1 + arch/arm64/kvm/handle_exit.c | 13 +++++++++++++ arch/arm64/kvm/sys_regs.c | 22 ++++++++++++++++++++++ 4 files changed, 37 insertions(+) -- 1.9.1 diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 6e99978..aeaac4e 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -23,6 +23,7 @@ #include /* Hyp Configuration Register (HCR) bits */ +#define HCR_NV (UL(1) << 42) #define HCR_E2H (UL(1) << 34) #define HCR_ID (UL(1) << 33) #define HCR_CD (UL(1) << 32) diff --git a/arch/arm64/include/asm/kvm_coproc.h b/arch/arm64/include/asm/kvm_coproc.h index 1b3d21b..6223df6 100644 --- a/arch/arm64/include/asm/kvm_coproc.h +++ b/arch/arm64/include/asm/kvm_coproc.h @@ -44,6 +44,7 @@ void kvm_register_target_sys_reg_table(unsigned int target, int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run); int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run); int kvm_handle_sys(struct kvm_vcpu *vcpu, struct kvm_run *run); +bool forward_nv_traps(struct kvm_vcpu *vcpu); #define kvm_coproc_table_init kvm_sys_reg_table_init void kvm_sys_reg_table_init(void); diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index d4e7b2b..fccd9d6 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -61,6 +61,12 @@ static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run) { int ret; + /* + * Forward this trapped smc instruction to the virtual EL2. + */ + if (forward_nv_traps(vcpu) && (vcpu_sys_reg(vcpu, HCR_EL2) & HCR_TSC)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + /* If imm is non-zero, it's not defined */ if (kvm_vcpu_hvc_get_imm(vcpu)) { kvm_inject_undefined(vcpu); @@ -197,6 +203,13 @@ static int kvm_handle_eret(struct kvm_vcpu *vcpu, struct kvm_run *run) vcpu_el2_sreg(vcpu, SPSR_EL2)); /* + * Forward this trap to the virtual EL2 if the virtual HCR_EL2.NV + * bit is set. + */ + if (forward_nv_traps(vcpu)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + + /* * Note that the current exception level is always the virtual EL2, * since we set HCR_EL2.NV bit only when entering the virtual EL2. */ diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 910b50d..4fd7090 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -939,6 +939,14 @@ static bool access_cntp_cval(struct kvm_vcpu *vcpu, return true; } +/* This function is to support the recursive nested virtualization */ +bool forward_nv_traps(struct kvm_vcpu *vcpu) +{ + if (!vcpu_mode_el2(vcpu) && (vcpu_sys_reg(vcpu, HCR_EL2) & HCR_NV)) + return true; + return false; +} + static inline void access_rw(struct sys_reg_params *p, u64 *sysreg) { if (!p->is_write) @@ -977,6 +985,13 @@ static bool trap_el2_regs(struct kvm_vcpu *vcpu, { u64 *sys_reg; + /* + * Forward this trap to the virtual EL2 if the virtual HCR_EL2.NV + * bit is set. + */ + if (forward_nv_traps(vcpu)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + sys_reg = get_special_reg(vcpu, p); if (!sys_reg) sys_reg = &vcpu_sys_reg(vcpu, r->reg); @@ -1914,6 +1929,13 @@ static int emulate_sys_instr(struct kvm_vcpu *vcpu, { int ret = 0; + /* + * Forward this trap to the virtual EL2 if the virtual HCR_EL2.NV + * bit is set. + */ + if (forward_nv_traps(vcpu)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + /* TLB maintenance instructions*/ if (params->CRn == 0b1000) ret = emulate_tlbi(vcpu, params); From patchwork Tue Jul 18 16:59:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108154 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6150813obm; Tue, 18 Jul 2017 10:01:56 -0700 (PDT) X-Received: by 10.84.174.131 with SMTP id r3mr2821278plb.37.1500397316334; Tue, 18 Jul 2017 10:01:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397316; cv=none; d=google.com; s=arc-20160816; b=Xq6eKnkIncjvyJD/x9j0j3f5bM+AZ0de7s67G8nUkTaRCk1LA1jM6aq2X+C8pPO2aC 2bnDTZbehpSVaz6Q9yjikB5Xi6ZiTcEPq8I4gwzPuNbfgwu9Fm8SuaMDSMr9WPEVzGin +QWEHw5rwHNKUr29Kav2scdNYyM5qpzIORFGZJ2rEVhkdumw6uL6C6bWuiyLdTsJSMFn Zgh8JigtoHK7+sYGae7uAMhISn+vpv5jZlT3KYIILlvRjbMbbxe/P6XAZiaQxmcgHsTY lC2O7AulEAERUCEefjFvq+5NPZbNK1C2gWdl7uipNeznOdY0HA0oZpgRASvxLGvbAlJ7 ZCOg== ARC-Message-Signature: i=1; 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:36 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 35/38] KVM: arm64: Respect the virtual HCR_EL2.NV bit setting for EL12 register traps Date: Tue, 18 Jul 2017 11:59:01 -0500 Message-Id: <1500397144-16232-36-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In addition to EL2 register accesses, setting NV bit will also make EL12 register accesses trap to EL2. To emulate this for the virtual EL2, forword traps due to EL12 register accessses to the virtual EL2 if the virtual HCR_EL2.NV bit is set. This is for recursive nested virtualization. Signed-off-by: Jintack Lim --- arch/arm64/kvm/sys_regs.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) -- 1.9.1 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 4fd7090..3559cf7 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -149,6 +149,9 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu, int i; const struct el1_el2_map *map; + if (el12_reg(p) && forward_nv_traps(vcpu)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + /* * Redirect EL1 register accesses to the corresponding EL2 registers if * they are meant to access EL2 registers. @@ -959,6 +962,9 @@ static bool access_cntkctl_el12(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { + if (forward_nv_traps(vcpu)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + access_rw(p, &vcpu_sys_reg(vcpu, r->reg)); return true; } @@ -1005,6 +1011,9 @@ static bool access_elr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { + if (el12_reg(p) && forward_nv_traps(vcpu)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + access_rw(p, &vcpu->arch.ctxt.gp_regs.elr_el1); return true; } @@ -1013,6 +1022,9 @@ static bool access_spsr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { + if (el12_reg(p) && forward_nv_traps(vcpu)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + access_rw(p, &vcpu->arch.ctxt.gp_regs.spsr[KVM_SPSR_EL1]); return true; } @@ -1021,6 +1033,9 @@ static bool access_vbar(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { + if (el12_reg(p) && forward_nv_traps(vcpu)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + access_rw(p, &vcpu_sys_reg(vcpu, r->reg)); return true; } @@ -1031,6 +1046,9 @@ static bool access_cpacr(struct kvm_vcpu *vcpu, { u64 reg = sys_reg(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); + if (el12_reg(p) && forward_nv_traps(vcpu)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + /* * When the virtual HCR_EL2.E2H == 1, an access to CPACR_EL1 * in the virtual EL2 is to access CPTR_EL2. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:38 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 36/38] KVM: arm64: Respect virtual HCR_EL2.TVM and TRVM settings Date: Tue, 18 Jul 2017 11:59:02 -0500 Message-Id: <1500397144-16232-37-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Forward the EL1 virtual memory register traps to the virtual EL2 if they are not coming from the virtual EL2 and the virtual HCR_EL2.TVM or TRVM bit is set. This is for recursive nested virtualization. Signed-off-by: Jintack Lim --- arch/arm64/kvm/sys_regs.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) -- 1.9.1 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 3559cf7..3e4ec5e 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -135,6 +135,27 @@ static inline bool el12_reg(struct sys_reg_params *p) return (p->Op1 == 5); } +/* This function is to support the recursive nested virtualization */ +static bool forward_vm_traps(struct kvm_vcpu *vcpu, struct sys_reg_params *p) +{ + u64 hcr_el2 = vcpu_sys_reg(vcpu, HCR_EL2); + + /* If a trap comes from the virtual EL2, the host hypervisor handles. */ + if (vcpu_mode_el2(vcpu)) + return false; + + /* + * If the virtual HCR_EL2.TVM or TRVM bit is set, we need to foward + * this trap to the virtual EL2. + */ + if ((hcr_el2 & HCR_TVM) && p->is_write) + return true; + else if ((hcr_el2 & HCR_TRVM) && !p->is_write) + return true; + + return false; +} + /* * Generic accessor for VM registers. Only called as long as HCR_TVM * is set. If the guest enables the MMU, we stop trapping the VM @@ -152,6 +173,9 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu, if (el12_reg(p) && forward_nv_traps(vcpu)) return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + if (!el12_reg(p) && forward_vm_traps(vcpu, p)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + /* * Redirect EL1 register accesses to the corresponding EL2 registers if * they are meant to access EL2 registers. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:40 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim , Jintack Lim Subject: [RFC PATCH v2 37/38] KVM: arm64: Respect the virtual HCR_EL2.NV1 bit setting Date: Tue, 18 Jul 2017 11:59:03 -0500 Message-Id: <1500397144-16232-38-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Forward ELR_EL1, SPSR_EL1 and VBAR_EL1 traps to the virtual EL2 if the virtual HCR_EL2.NV bit is set. This is for recursive nested virtualization. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/kvm_arm.h | 1 + arch/arm64/kvm/sys_regs.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) -- 1.9.1 diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index aeaac4e..a1274b7 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -23,6 +23,7 @@ #include /* Hyp Configuration Register (HCR) bits */ +#define HCR_NV1 (UL(1) << 43) #define HCR_NV (UL(1) << 42) #define HCR_E2H (UL(1) << 34) #define HCR_ID (UL(1) << 33) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 3e4ec5e..6f67666 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1031,6 +1031,15 @@ static bool trap_el2_regs(struct kvm_vcpu *vcpu, return true; } +/* This function is to support the recursive nested virtualization */ +static bool forward_nv1_traps(struct kvm_vcpu *vcpu, struct sys_reg_params *p) +{ + if (!vcpu_mode_el2(vcpu) && (vcpu_sys_reg(vcpu, HCR_EL2) & HCR_NV1)) + return true; + + return false; +} + static bool access_elr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -1038,6 +1047,9 @@ static bool access_elr(struct kvm_vcpu *vcpu, if (el12_reg(p) && forward_nv_traps(vcpu)) return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + if (!el12_reg(p) && forward_nv1_traps(vcpu, p)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + access_rw(p, &vcpu->arch.ctxt.gp_regs.elr_el1); return true; } @@ -1049,6 +1061,9 @@ static bool access_spsr(struct kvm_vcpu *vcpu, if (el12_reg(p) && forward_nv_traps(vcpu)) return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + if (!el12_reg(p) && forward_nv1_traps(vcpu, p)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + access_rw(p, &vcpu->arch.ctxt.gp_regs.spsr[KVM_SPSR_EL1]); return true; } @@ -1060,6 +1075,9 @@ static bool access_vbar(struct kvm_vcpu *vcpu, if (el12_reg(p) && forward_nv_traps(vcpu)) return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + if (!el12_reg(p) && forward_nv1_traps(vcpu, p)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + access_rw(p, &vcpu_sys_reg(vcpu, r->reg)); return true; } From patchwork Tue Jul 18 16:59:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108153 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6149974obm; Tue, 18 Jul 2017 10:01:20 -0700 (PDT) X-Received: by 10.84.128.9 with SMTP id 9mr2701454pla.61.1500397280215; Tue, 18 Jul 2017 10:01:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397280; cv=none; d=google.com; s=arc-20160816; b=b4puTSQ9J9XDJUePBSa9Q0Ayv/rTF9fw21jyR0xBfozMihEgY/0autAdFPGEMyrQBJ 3kH1Oee0ok6v9FB4OUnV6nrqfkbURuJ209buAmwi37h/wpNss5ILIHQ9tWurGj4ph6Al AiozAaPtw8oAeqZLYtnoM2xWg1mrS7m8QUIUQYKVhyQNciyo0eVhDUDcW3rB4knjMeQL JyHPO3FC49BLX6E50oVY0KaKDOwPHnURXf7PLUyype15mjc4u7wmtIHG/r1foBaIADk2 hI4ks2AK/EFDXd8zURtjz/TQ4u2s+iR0vEIK7i4SwTInsBC8QvL7kiLiqAsXQJiB7xY4 bWdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=L9cgc0L6RjcLZisZBC8Z3TKkptdPzDjn9YtsY+MrqEY=; b=OFPMof+1SQQh5pUTltk6zKeoCS/jUlkTN2AtjDIe8gJh4NPnW5smCA4yEH+SQ9gBQ+ 6nR4P+mX9mnZiTz19fGDzXko14OGqbS2zb9ohifZD2qSK9SXtaubKh4f0fWgmUp3xoJx zLlEUmOFFlCDIwvpytsc9/eF9B/kaKdvEbElOdxEKrIK0rct2Mq2KkfOEeR2+0Xh3RK1 3fDDVSb4eCJPWjiKqrmFFnroGzIQQRUQXeI5e1YBTEYZwR85eIa+ADtBPQ1JWJ6YEwzs sRJVVajpwsQhI5VlHcqywRhzy79F1N/0Pp09SE3F7Ut+C15QdFbt9QQSdkByI2648AN8 u1xA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=A8xGIR8c; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:42 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 38/38] KVM: arm64: Respect the virtual CPTR_EL2.TCPAC setting Date: Tue, 18 Jul 2017 11:59:04 -0500 Message-Id: <1500397144-16232-39-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Forward CPACR_EL1 traps to the virtual EL2 if virtual CPTR_EL2 is configured to trap CPACR_EL1 accesses from EL1. This is for recursive nested virtualization. Signed-off-by: Jintack Lim --- arch/arm64/kvm/sys_regs.c | 5 +++++ 1 file changed, 5 insertions(+) -- 1.9.1 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 6f67666..ba2966d 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1091,6 +1091,11 @@ static bool access_cpacr(struct kvm_vcpu *vcpu, if (el12_reg(p) && forward_nv_traps(vcpu)) return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + /* Forward this trap to the virtual EL2 if CPTR_EL2.TCPAC is set*/ + if (!el12_reg(p) && !vcpu_mode_el2(vcpu) && + (vcpu_sys_reg(vcpu, CPTR_EL2) & CPTR_EL2_TCPAC)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + /* * When the virtual HCR_EL2.E2H == 1, an access to CPACR_EL1 * in the virtual EL2 is to access CPTR_EL2.