From patchwork Mon Jul 31 12:22:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109013 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp3585109obm; Mon, 31 Jul 2017 05:24:06 -0700 (PDT) X-Received: by 10.200.57.81 with SMTP id t17mr15679041qtb.45.1501503846254; Mon, 31 Jul 2017 05:24:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501503846; cv=none; d=google.com; s=arc-20160816; b=r879hAScN3h2IiHu/u7M5kv4YzMDqspIbgS9EcX8SQQFoipgTV1+u+Q/GAUMD0HDrn rsQA4LYR0Lz7bQCEWAbTKKebZaSceS2NDfijSTiNmplLxOqRYrK8IGjz1pwO5qTcUYW4 AT7S518OShzmFPmtl2iCL+sRKVtkW91QJ6ZZkYKq++Iaw8VFsGeCxj8/NSZLpqoa7YXz nM/EgdTLrcyR2gQ0MT2Tt96yaoLKHToLlTs+nC0gPxOO8nQARHJLdrC6xqiqTFdKAXtq ZDy9Ih/LsNAR44Y7wFrsVNWTmHTZ3zJ5b7TOTon1GFCbLfXw4ERkTcZXz/NeuqYhAs7f jeyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=tlM2FcSoblkzq6xAEo5gDGTj9OcWxEgRk3+zSAUO6fo=; b=u/LM9j8gO66KtPzD8qw+FHdT9Bylqt+a+lJuAOt7P45YyQLFYyGxb2CbPtFDD/clME FVcvKKaOWVglpraw7pV/1IG9Sks6h+DpABXHrWGAWCZxMLDjODfl/ZX7i6yTwR7juj7e nbvuBFpoW5WfEDJWmWQxxnSImkRYZp+eimxnqXle/eqL08DurZHjhzZVfrmNVMq72pRM HNzr4JPPEdAGN6m1uSJiXP00myDdMi2cekJLhVLynedxLuTRZqRD2FyzBmdoG9rEwuTt Mqb8wZea+jrThBd148bHFG6qy595NDkMrd1CiN3ofOuma6PwQXRDtDk+n5z8UUq+kG83 nv1A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id m2si24430002qtd.445.2017.07.31.05.24.05 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 31 Jul 2017 05:24:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59292 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9jv-0002HY-JI for patch@linaro.org; Mon, 31 Jul 2017 08:24:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56039) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9iu-0001fI-0Q for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:23:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dc9ip-0003g8-9k for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:23:00 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37752) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dc9ip-0003ax-2i for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:22:55 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dc9ig-0000s6-FD for qemu-devel@nongnu.org; Mon, 31 Jul 2017 13:22:46 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 31 Jul 2017 13:22:39 +0100 Message-Id: <1501503765-15639-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> References: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 1/7] target/arm: Correct MPU trace handling of write vs execute X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Correct off-by-one bug in the PSMAv7 MPU tracing where it would print a write access as "reading", an insn fetch as "writing", and a read access as "execute". Since we have an MMUAccessType enum now, we can make the code clearer in the process by using that rather than the raw 0/1/2 values. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 1500906792-18010-1-git-send-email-peter.maydell@linaro.org --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 4ed32c5..9ed5096 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8558,8 +8558,8 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, phys_ptr, prot, fsr); qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", - access_type == 1 ? "reading" : - (access_type == 2 ? "writing" : "execute"), + access_type == MMU_DATA_LOAD ? "reading" : + (access_type == MMU_DATA_STORE ? "writing" : "execute"), (uint32_t)address, mmu_idx, ret ? "Miss" : "Hit", *prot & PAGE_READ ? 'r' : '-', From patchwork Mon Jul 31 12:22:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109018 Delivered-To: patch@linaro.org Received: by 10.140.101.6 with SMTP id t6csp163344qge; Mon, 31 Jul 2017 05:28:56 -0700 (PDT) X-Received: by 10.200.42.4 with SMTP id k4mr22258607qtk.253.1501504136613; Mon, 31 Jul 2017 05:28:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501504136; cv=none; d=google.com; s=arc-20160816; b=veAnQuKOckJWFCvDAGEtzzrsb1HU2PBisz7iKvGFvK2kJryXEnoXHnoYcll80FIE+T h8WWxbJvjXVB3jGms/ViT4Kdx9bkOCo9WDZcR6TA81dDGzZoZk8sSOfgzAiC/BhjpKez 5p/eiyG6nBu4yPtQFESh37nhY7fOxi42Mwv7WT93TUMUEgwUkT++MJiiwfngleWqZoiK p6PVudk2qtAd2GstEZfx6M4YK/kNgU996q6fnd42SSMujuUzSkO0emCyc41UadYnxZmV aRoCBVq4P4tW+Xd8GKRc112TaOFQEW4Qnz3kr1Ty+M6VHLWy0Jss8hTuD56dsSfq2wIn Z8cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=NvahIgmuFaFzUwSUsNFuuXWVFQPv37Rf/t2DPgL4H0I=; b=O6cWTIJNFCTOsN71a1XM6Lcax7QBHVJIwgHAQ/3lHpxK2sUeWblBqycxMTDu+tBQJB sxTHLxaSZfRlZfWRyTIL8w+KQ5xHrBUSEpXD6zsMDn5gxSjeT5Ts+2Vmc0l/b4OnPc2Z E0GReF5MOAjWtHZwM15XYo80mtQMFQkvOi0pq1fhWEjO4WDptEWuuGOjojPYFu7XdJVH 9gO/Xj/5S/CuXd2Jc681vIL7o985FSMZHOKc0r+6UUcjNRr/MhmnyiOWDUupdGlc0Kxo s3q2bVdVkpnWUSLphrMQLqRH6YnCDB/4AyAiGkrd/9poL4l9Hklc8cylvRXvtsUaOkVF rgSg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id y25si8853706qty.347.2017.07.31.05.28.56 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 31 Jul 2017 05:28:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59315 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9oc-0006Rp-46 for patch@linaro.org; Mon, 31 Jul 2017 08:28:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56061) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9iv-0001ge-6N for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:23:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dc9iu-0003kG-5h for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:23:01 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37752) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dc9it-0003ax-VB for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:23:00 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dc9ig-0000sH-Ta for qemu-devel@nongnu.org; Mon, 31 Jul 2017 13:22:46 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 31 Jul 2017 13:22:40 +0100 Message-Id: <1501503765-15639-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> References: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 2/7] target/arm: Don't do MPU lookups for addresses in M profile PPB region X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The M profile PMSAv7 specification says that if the address being looked up is in the PPB region (0xe0000000 - 0xe00fffff) then we do not use the MPU regions but always use the default memory map. Implement this (we were previously behaving like an R profile PMSAv7, which does not special case this). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 1501153150-19984-2-git-send-email-peter.maydell@linaro.org --- target/arm/helper.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 9ed5096..3d60575 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8244,6 +8244,13 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, } } +static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address) +{ + /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */ + return arm_feature(env, ARM_FEATURE_M) && + extract32(address, 20, 12) == 0xe00; +} + static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, int access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, uint32_t *fsr) @@ -8255,7 +8262,15 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, *phys_ptr = address; *prot = 0; - if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ + if (regime_translation_disabled(env, mmu_idx) || + m_is_ppb_region(env, address)) { + /* MPU disabled or M profile PPB access: use default memory map. + * The other case which uses the default memory map in the + * v7M ARM ARM pseudocode is exception vector reads from the vector + * table. In QEMU those accesses are done in arm_v7m_load_vector(), + * which always does a direct read using address_space_ldl(), rather + * than going via this function, so we don't need to check that here. + */ get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); } else { /* MPU enabled */ for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { From patchwork Mon Jul 31 12:22:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109017 Delivered-To: patch@linaro.org Received: by 10.140.101.6 with SMTP id t6csp162152qge; Mon, 31 Jul 2017 05:27:28 -0700 (PDT) X-Received: by 10.237.38.71 with SMTP id z65mr20034706qtc.21.1501504048517; Mon, 31 Jul 2017 05:27:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501504048; cv=none; d=google.com; s=arc-20160816; b=qJmQdcpipbrLnvZ47Frv8yE3m6VcsjyuMaRgue3Iu9vGsAzqg4+n9VpzXiprEtvABf E8pkIRn/XdyrkwQYB4Rkb4Z28Fv001Yqdcnlt5TzSaa/Uiy+bsqLnfaeJPvbVL8X+D0Q bFWLLAUUYIa7jXzvU8uOVeLShTigXBm12C0lKgEhwGcUKcuzF9AL/fNI9oJghiIjQjQL wgqo0TNjVVT+VXYUg+pzfVwgzJNjMZvfHQfS9dpBkzGufUfP+ynVWksqdlIL+cV5keLv 8UvFToF5X+YS/fQa+5JBWH+/3OniOhARQw6g0udDOYyBwnjT5ICB30oRVcfKUOxtbPOc 5obg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=qIpHrgXwg6xjnpjYsJ3nfq4g7hGb+yUlWi/Hk2XThzo=; b=QaxedtrzYLJ9iFG4Jl90QatMZmqIpaCqP907PI/gaF26nUrCLzRZRLtpqhnVJ2EKUa 0Uzf+ATOMJQCnfpSaCwlZLUxqawIu1/Cr79MZvBkPiRm7wqBBLzkieA0lecX7sbBtBSe 8MFRLhKhSX0Tt8e47zH0SVr9rWkT4aHXSttaaHCDruEP3HExa7EHgvoGb+7LrcjeAOtx w1V2ZCxuLhY0XVQM9TOKG0nY0EreNVJXSFU/VjUqXK14uJpRpRB7ezl4slHP+lQB8pEf 893hAcpyv6DqK8afokub6J2XpCBgjcLAQCl8aUOlcvF+y0MeIdwwvW+eU3d1bDy9VJH3 UyVQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id q34si17475915qtd.284.2017.07.31.05.27.28 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 31 Jul 2017 05:27:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59311 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9nC-0005H4-1i for patch@linaro.org; Mon, 31 Jul 2017 08:27:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56045) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9iu-0001fb-8C for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:23:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dc9it-0003jh-Cd for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:23:00 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37752) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dc9it-0003ax-4y for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:22:59 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dc9ih-0000ss-Ct for qemu-devel@nongnu.org; Mon, 31 Jul 2017 13:22:47 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 31 Jul 2017 13:22:41 +0100 Message-Id: <1501503765-15639-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> References: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 3/7] target/arm: Don't allow guest to make System space executable for M profile X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For an M profile v7PMSA, the system space (0xe0000000 - 0xffffffff) can never be executable, even if the guest tries to set the MPU registers up that way. Enforce this restriction. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 1501153150-19984-3-git-send-email-peter.maydell@linaro.org --- target/arm/helper.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 3d60575..f0299c5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8251,6 +8251,14 @@ static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address) extract32(address, 20, 12) == 0xe00; } +static inline bool m_is_system_region(CPUARMState *env, uint32_t address) +{ + /* True if address is in the M profile system region + * 0xe0000000 - 0xffffffff + */ + return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7; +} + static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, int access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, uint32_t *fsr) @@ -8354,6 +8362,12 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); } else { /* a MPU hit! */ uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); + uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1); + + if (m_is_system_region(env, address)) { + /* System space is always execute never */ + xn = 1; + } if (is_user) { /* User mode AP bit decoding */ switch (ap) { @@ -8394,7 +8408,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, } /* execute never */ - if (env->pmsav7.dracr[n] & (1 << 12)) { + if (xn) { *prot &= ~PAGE_EXEC; } } From patchwork Mon Jul 31 12:22:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109014 Delivered-To: patch@linaro.org Received: by 10.140.101.6 with SMTP id t6csp161308qge; Mon, 31 Jul 2017 05:26:29 -0700 (PDT) X-Received: by 10.200.38.155 with SMTP id 27mr3812932qto.228.1501503989232; Mon, 31 Jul 2017 05:26:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501503989; cv=none; d=google.com; s=arc-20160816; b=Z70Gw7iquWUXMo7ozbBHLdyJmW+dyqcmTtzzImn4OmC5V7QhwbqTMTkYfIhSCj56vs oqQOGFzZkVz/DUKjxi0a1Bfaw6ZB8rPwM0RxGTyKWbxj5wZ9y1kYaEmkgEVg7dgClXiH xVTcXGGO56hHYawQTJAV2Zy7uFQc+nOR1pdHseq/4zhrcuGQRpTkj8wtbMF8Wv86Dg5X Y20Crls4+IUzl835mjKJyPSs2fAEN3VpylHADp9rKe/QmNmVu6A2WHzXkSdzNorEPPcV sBx8X5IT1tILiOmHomRY6EeiGGfkFZ7IUX5WVf3VhlACXwlytAjYOTr4aHDIGGSeO52r gJEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=jANKvQrDiDiToOE2vtwHmAwDdJzYXvNiioBwUDYpAss=; b=breQsZJOPK1HUzu0DGf/AiOrVUNI01/XjzLg8gAymcft8cj6Q+N8HTMeVJu8tf8kHp U8R7CwJxVYLW7xVSAK6kHSApBGHEzHSKs97S464cbmyLwpyBsO9Dweu6c8BTs9VSoWgr bC7jJugKwPluw3GMQWLA83fCVe2pzTyOHS3Ad8TQD0sE36AEYm3E/sKFlscZUNfW6w+d m8H7X/+mjZuk2UqIt8lxmlIP0cxRLvKX2TZ0/b4g0Ndrs5sPsG6nB+VlHzATtcaN+zUo ftbcKKBLyr1npVbY8dt0ZbZIo/62fytr82aY6nlgvCLCtrnxQeIS1tCqcsFGMdfZlJp0 KUCw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id p66si23275471qka.162.2017.07.31.05.26.28 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 31 Jul 2017 05:26:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59308 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9mE-0004Um-Qi for patch@linaro.org; Mon, 31 Jul 2017 08:26:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56031) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9it-0001ew-Ia for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:23:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dc9is-0003jA-HP for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:22:59 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37752) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dc9is-0003ax-AB for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:22:58 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dc9ih-0000tF-Rr for qemu-devel@nongnu.org; Mon, 31 Jul 2017 13:22:47 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 31 Jul 2017 13:22:42 +0100 Message-Id: <1501503765-15639-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> References: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 4/7] target/arm: Rename cp15.c6_rgnr to pmsav7.rnr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Almost all of the PMSAv7 state is in the pmsav7 substruct of the ARM CPU state structure. The exception is the region number register, which is in cp15.c6_rgnr. This exception is a bit odd for M profile, which otherwise generally does not store state in the cp15 substruct. Rename cp15.c6_rgnr to pmsav7.rnr accordingly. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 1501153150-19984-4-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 3 +-- hw/intc/armv7m_nvic.c | 14 +++++++------- target/arm/helper.c | 6 +++--- target/arm/machine.c | 2 +- 4 files changed, 12 insertions(+), 13 deletions(-) -- 2.7.4 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 102c58a..b39d64a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -305,8 +305,6 @@ typedef struct CPUARMState { uint64_t par_el[4]; }; - uint32_t c6_rgnr; - uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; uint64_t c9_pmcr; /* performance monitor control register */ @@ -519,6 +517,7 @@ typedef struct CPUARMState { uint32_t *drbar; uint32_t *drsr; uint32_t *dracr; + uint32_t rnr; } pmsav7; void *nvic; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 26a4b2d..323e2d4 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -536,13 +536,13 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset) case 0xd94: /* MPU_CTRL */ return cpu->env.v7m.mpu_ctrl; case 0xd98: /* MPU_RNR */ - return cpu->env.cp15.c6_rgnr; + return cpu->env.pmsav7.rnr; case 0xd9c: /* MPU_RBAR */ case 0xda4: /* MPU_RBAR_A1 */ case 0xdac: /* MPU_RBAR_A2 */ case 0xdb4: /* MPU_RBAR_A3 */ { - int region = cpu->env.cp15.c6_rgnr; + int region = cpu->env.pmsav7.rnr; if (region >= cpu->pmsav7_dregion) { return 0; @@ -554,7 +554,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset) case 0xdb0: /* MPU_RASR_A2 */ case 0xdb8: /* MPU_RASR_A3 */ { - int region = cpu->env.cp15.c6_rgnr; + int region = cpu->env.pmsav7.rnr; if (region >= cpu->pmsav7_dregion) { return 0; @@ -681,7 +681,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) PRIu32 "/%" PRIu32 "\n", value, cpu->pmsav7_dregion); } else { - cpu->env.cp15.c6_rgnr = value; + cpu->env.pmsav7.rnr = value; } break; case 0xd9c: /* MPU_RBAR */ @@ -702,9 +702,9 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) region, cpu->pmsav7_dregion); return; } - cpu->env.cp15.c6_rgnr = region; + cpu->env.pmsav7.rnr = region; } else { - region = cpu->env.cp15.c6_rgnr; + region = cpu->env.pmsav7.rnr; } if (region >= cpu->pmsav7_dregion) { @@ -720,7 +720,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) case 0xdb0: /* MPU_RASR_A2 */ case 0xdb8: /* MPU_RASR_A3 */ { - int region = cpu->env.cp15.c6_rgnr; + int region = cpu->env.pmsav7.rnr; if (region >= cpu->pmsav7_dregion) { return; diff --git a/target/arm/helper.c b/target/arm/helper.c index f0299c5..0f79b25 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2385,7 +2385,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) return 0; } - u32p += env->cp15.c6_rgnr; + u32p += env->pmsav7.rnr; return *u32p; } @@ -2399,7 +2399,7 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, return; } - u32p += env->cp15.c6_rgnr; + u32p += env->pmsav7.rnr; tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ *u32p = value; } @@ -2447,7 +2447,7 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = { .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr), + .fieldoffset = offsetof(CPUARMState, pmsav7.rnr), .writefn = pmsav7_rgnr_write }, REGINFO_SENTINEL }; diff --git a/target/arm/machine.c b/target/arm/machine.c index 1a40469..93c1a78 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -151,7 +151,7 @@ static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) { ARMCPU *cpu = opaque; - return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion; + return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion; } static const VMStateDescription vmstate_pmsav7 = { From patchwork Mon Jul 31 12:22:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109015 Delivered-To: patch@linaro.org Received: by 10.140.101.6 with SMTP id t6csp161645qge; Mon, 31 Jul 2017 05:26:52 -0700 (PDT) X-Received: by 10.55.20.25 with SMTP id e25mr21323240qkh.75.1501504012593; Mon, 31 Jul 2017 05:26:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501504012; cv=none; d=google.com; s=arc-20160816; b=Vt/Bdg2aJq9Axf/CqC65QYPz2d6+0l3K7HrLp4XuFiq2MU7vQgyHj9spB0Z/vHkLmt gTlUpzK44p9kDoB+XpQf5t5VBERGyT68iAzLr2iwKEj6gau7VUtOxlbv5okLIhQd7KPU Wq0xMqlgNSAM650ml+/yF9ZElvIV5vkToTd1ZyTA4Lqqxwd4ql0TTVcvx6oSWD+Q4ohj YMbn3AcmCHRP+KPxRsVCvZJaoGKJ0pqCB/Wrv3Aw2tRCLc/LdW9XP9bJlJ0b1zUGn3hD MoMgYehJaKXvHOADTOH6tNIQ4doSNIFTmUv6jkIPCsDt7ADHF88yekmtoy2iK4H6qWZw FQdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=VzMcgylyAuy3u9DdXNX78CGMlpH4Zi4oJRDI/tmlSOw=; b=LLbF7Knv9upvEehM1Uq4b+8l48Ziiw9LfIhkGbieheyifMh8IQOy59+0qkPKxra+cC 83Nts0tnyPX9FuLBYjvV0Ut5JOoeWMuBHlzpEevUQ1ttzvhqmwrpfx3nfFUMUpAEz5q+ xI1J6aw1noIGXfidWwllALu7DfzQK8xh6UOyoZ2Buro2vxd6ABGZ5B9oG3koQSPQn6N+ KmujaZN935nLx4iEnUkzy5Ei57DcEToDaOPODGYLUE4JjpajVHNmJ8C1iFjPcH6C9nSV R+08fjLSC5gBaWrFzcm7/oioSg3lf+6aUyEYl2eTkdX5xa1QHaeTe24HcMhBps8L5JFX uFAg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f31si23612833qtb.496.2017.07.31.05.26.52 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 31 Jul 2017 05:26:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59309 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9mb-0004m0-V5 for patch@linaro.org; Mon, 31 Jul 2017 08:26:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56021) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9is-0001e8-R0 for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:22:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dc9ir-0003iF-OV for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:22:58 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37752) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dc9ir-0003ax-Gd for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:22:57 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dc9ii-0000tc-BA for qemu-devel@nongnu.org; Mon, 31 Jul 2017 13:22:48 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 31 Jul 2017 13:22:43 +0100 Message-Id: <1501503765-15639-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> References: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 5/7] target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When the PMSAv7 implementation was originally added it was for R profile CPUs only, and reset was handled using the cpreg .resetfn hooks. Unfortunately for M profile cores this doesn't work, because they do not register any cpregs. Move the reset handling into arm_cpu_reset(), where it will work for both R profile and M profile cores. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 1501153150-19984-5-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.c | 14 ++++++++++++++ target/arm/helper.c | 28 ++++++++++++---------------- 2 files changed, 26 insertions(+), 16 deletions(-) -- 2.7.4 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 96d1f84..05c038b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -232,6 +232,20 @@ static void arm_cpu_reset(CPUState *s) env->vfp.xregs[ARM_VFP_FPEXC] = 0; #endif + + if (arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V7)) { + if (cpu->pmsav7_dregion > 0) { + memset(env->pmsav7.drbar, 0, + sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); + memset(env->pmsav7.drsr, 0, + sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); + memset(env->pmsav7.dracr, 0, + sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); + } + env->pmsav7.rnr = 0; + } + set_flush_to_zero(1, &env->vfp.standard_fp_status); set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); set_default_nan_mode(1, &env->vfp.standard_fp_status); diff --git a/target/arm/helper.c b/target/arm/helper.c index 0f79b25..fa60040 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2404,18 +2404,6 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, *u32p = value; } -static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - ARMCPU *cpu = arm_env_get_cpu(env); - uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); - - if (!u32p) { - return; - } - - memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion); -} - static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2433,22 +2421,30 @@ static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, } static const ARMCPRegInfo pmsav7_cp_reginfo[] = { + /* Reset for all these registers is handled in arm_cpu_reset(), + * because the PMSAv7 is also used by M-profile CPUs, which do + * not register cpregs but still need the state to be reset. + */ { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NO_RAW, .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), - .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, + .readfn = pmsav7_read, .writefn = pmsav7_write, + .resetfn = arm_cp_reset_ignore }, { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, .access = PL1_RW, .type = ARM_CP_NO_RAW, .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), - .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, + .readfn = pmsav7_read, .writefn = pmsav7_write, + .resetfn = arm_cp_reset_ignore }, { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, .access = PL1_RW, .type = ARM_CP_NO_RAW, .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), - .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, + .readfn = pmsav7_read, .writefn = pmsav7_write, + .resetfn = arm_cp_reset_ignore }, { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, pmsav7.rnr), - .writefn = pmsav7_rgnr_write }, + .writefn = pmsav7_rgnr_write, + .resetfn = arm_cp_reset_ignore }, REGINFO_SENTINEL }; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id o6si23019801qkb.55.2017.07.31.05.23.25 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 31 Jul 2017 05:23:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59288 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9jH-0001ga-6R for patch@linaro.org; Mon, 31 Jul 2017 08:23:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56004) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9ir-0001dV-Rl for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:22:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dc9iq-0003hW-UJ for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:22:57 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37752) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dc9iq-0003ax-MY for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:22:56 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dc9ii-0000tz-QN for qemu-devel@nongnu.org; Mon, 31 Jul 2017 13:22:48 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 31 Jul 2017 13:22:44 +0100 Message-Id: <1501503765-15639-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> References: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 6/7] target/arm: Migrate MPU_RNR register state for M profile cores X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The PMSAv7 region number register is migrated for R profile cores using the cpreg scheme, but M profile doesn't use cpregs, and so we weren't migrating the MPU_RNR register state at all. Fix that by adding a migration subsection for the M profile case. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 1501153150-19984-6-git-send-email-peter.maydell@linaro.org --- target/arm/machine.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) -- 2.7.4 diff --git a/target/arm/machine.c b/target/arm/machine.c index 93c1a78..1f66da4 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -171,6 +171,29 @@ static const VMStateDescription vmstate_pmsav7 = { } }; +static bool pmsav7_rnr_needed(void *opaque) +{ + ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; + + /* For R profile cores pmsav7.rnr is migrated via the cpreg + * "RGNR" definition in helper.h. For M profile we have to + * migrate it separately. + */ + return arm_feature(env, ARM_FEATURE_M); +} + +static const VMStateDescription vmstate_pmsav7_rnr = { + .name = "cpu/pmsav7-rnr", + .version_id = 1, + .minimum_version_id = 1, + .needed = pmsav7_rnr_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static int get_cpsr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) { @@ -377,6 +400,11 @@ const VMStateDescription vmstate_arm_cpu = { &vmstate_iwmmxt, &vmstate_m, &vmstate_thumb2ee, + /* pmsav7_rnr must come before pmsav7 so that we have the + * region number before we test it in the VMSTATE_VALIDATE + * in vmstate_pmsav7. + */ + &vmstate_pmsav7_rnr, &vmstate_pmsav7, NULL } From patchwork Mon Jul 31 12:22:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109011 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp3584363obm; Mon, 31 Jul 2017 05:23:23 -0700 (PDT) X-Received: by 10.55.55.7 with SMTP id e7mr20238055qka.294.1501503803088; Mon, 31 Jul 2017 05:23:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501503803; cv=none; d=google.com; s=arc-20160816; b=DIlY1GulQDDuyiQQzJohkhyA/Fx4wM0sdDPQAxT92gQhKHpU8hoiJgjRWTkfihQXcx SwXf3EgHlysd4lqD7u5IqFd7MFvH3oStvEj9wCK7VuhzsBE9OEqV3Q7rmt5hOPchM8vK 1tYCS2rXF8DVtZEMMzX6TL/qFJ3id+5lh3soITDD2pcJMWFD/NtX7PEqkRakFLcPU5Qf unGwkIxWXTorrXpFkB74+6YoVuo5Ci3ANlqkTvXqGqOM0wHlwQejui5btaz/1QET8Kfp 048boIYs5vTCZtrvYtIMgaLkI4VJzhewwSzR/tU96Ynyk3mGBevli8d0RO9Uk1mlZT8f X+Lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=swBR9ElAWfuGhnlahczzN+xFMM4lodjiweKY4FYYGUo=; b=udV8KzVVt10FW4JWUjq3EdjnQmQjMVi+hUK6xegeWnxKtJJti7boHpSxg2umUVL5LC SPFV++tKIm5umGnTV9XuGmbH4vICcry2mU51UdomV8Ma+A9GDS1j2TfEY9lD9kRfO3xv CNgtP8BseIaMeKWCqStbXWIzMDVAXCPpKgF5rC/eov1cnOGNK8r1p1VzTlo95VKVuYKq XqFd2YkCZU/oqa+GhZxHD2ElE6vLvcA86iS4JDjClL5IwgQrAC3gSF0yLrbdaTK3rFxs 7lIDHfd1LzziQYqw1XaZxledUUfYuU7j9DXQ5DfvOxUsGLmbnGMUvf7xPuBpS4yRdjvt jezA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f92si12586665qtd.528.2017.07.31.05.23.22 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 31 Jul 2017 05:23:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59287 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9jE-0001eS-FK for patch@linaro.org; Mon, 31 Jul 2017 08:23:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55988) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9iq-0001cn-Rc for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:22:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dc9iq-0003gr-3t for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:22:56 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37752) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dc9ip-0003ax-TB for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:22:56 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dc9ij-0000uM-9b for qemu-devel@nongnu.org; Mon, 31 Jul 2017 13:22:49 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 31 Jul 2017 13:22:45 +0100 Message-Id: <1501503765-15639-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> References: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 7/7] hw/mps2_scc: fix incorrect properties X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Message-id: 20170729234930.725-1-f4bug@amsat.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/mps2-scc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index cc58d26..32be2a9 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -270,9 +270,9 @@ static Property mps2_scc_properties[] = { /* Values for various read-only ID registers (which are specific * to the board model or FPGA image) */ - DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, aid, 0), + DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0), DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0), - DEFINE_PROP_UINT32("scc-id", MPS2SCC, aid, 0), + DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0), /* These are the initial settings for the source clocks on the board. * In hardware they can be configured via a config file read by the * motherboard configuration controller to suit the FPGA image.