From patchwork Tue Aug 1 10:49:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 109136 Delivered-To: patch@linaro.org Received: by 10.140.101.6 with SMTP id t6csp1341562qge; Tue, 1 Aug 2017 03:54:47 -0700 (PDT) X-Received: by 10.99.106.201 with SMTP id f192mr18470956pgc.124.1501584887414; Tue, 01 Aug 2017 03:54:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501584887; cv=none; d=google.com; s=arc-20160816; b=MI+fJHVPCM3jMdiVnl8NRcLI0FICpKlWS9y01bUWy6G2hsu/oWdNTW2trsKfkHMka1 wszsLL7iv0/kCe9gNEQwJlV/Ez1vsWma2I0uAy+kuF+1iMd5CG02ythL9oxMx54jg5zq UGYvvLX+rojjkWrKZX6uWQGrsLyka/NfgIzt+xM75OqYT634Bb3Oqqe0p91wuG2p3+fC RSj+v1x8Ff0UrOpoCPdo+LGjsMR4ziCXFyWfcJ98swAAcIMtPpH/zodrgWMd73LYG5Pl u3bxLGs++F96OKQgNxPy9kOo+41yNQWaGBb73MYtdLQ1d2bTxF8LvDQxbU1SJpXrcEZZ lF0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=5vnWk1Emw+HXcoY4a/ALHLSuDuKSdTt9/jzQc2G36TM=; b=GPBYTAa+IXcQms8t8RJDwfc/A75v0UH8c4cClkUd7Yl0/wRumFZhuFiYH6FVn0I8pT 3d7Ry77KNN+AV8EsCwcxvs0IAVSHSTOUpWh+AZBDE2NHnmcpyqz5ssqjmvOvwKJwvkfZ 7rx2T/zQqx7CoQnGE3UxaEJMQbG+7GerdNwvxWpAgcWWpYEUkZEEwyH2U+mwIo+inNBA GFGqPjehbNcvecIEyIpF0otMRmbfB1iM/2atfRx2nw6IVtDut6ynm3nkFDb7dV58mTIN T+2nLyEUV3EA5RqOnZNcq/OTmYJEVFXs1A/ICpumSNZx6+XAKDZ3jteTzpUgHLYItBxq hVqg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 92si18838459plw.105.2017.08.01.03.54.47; Tue, 01 Aug 2017 03:54:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751878AbdHAKwz (ORCPT + 7 others); Tue, 1 Aug 2017 06:52:55 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:10743 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751533AbdHAKvp (ORCPT ); Tue, 1 Aug 2017 06:51:45 -0400 Received: from 172.30.72.53 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.53]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ATO11013; Tue, 01 Aug 2017 18:51:44 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Tue, 1 Aug 2017 18:51:35 +0800 From: Shameer Kolothum To: , , , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v5 1/2] ACPI/IORT: Add ITS address regions reservation helper Date: Tue, 1 Aug 2017 11:49:12 +0100 Message-ID: <20170801104913.71912-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170801104913.71912-1-shameerali.kolothum.thodi@huawei.com> References: <20170801104913.71912-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.59805D40.01FB, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 95c1c65355f1635928aa3ce50a7d7d43 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On some platforms ITS address regions have to be excluded from normal IOVA allocation in that they are detected and decoded in a HW specific way by system components and so they cannot be considered normal IOVA address space. Add an helper function that retrieves ITS address regions through IORT device <-> ITS mappings and reserves it so that these regions will not be translated by IOMMU and will be excluded from IOVA allocations. Signed-off-by: Shameer Kolothum [lorenzo.pieralisi@arm.com: updated commit log/added comments] Signed-off-by: Lorenzo Pieralisi --- drivers/acpi/arm64/iort.c | 95 ++++++++++++++++++++++++++++++++++++++-- drivers/irqchip/irq-gic-v3-its.c | 3 +- include/linux/acpi_iort.h | 7 ++- 3 files changed, 100 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index a3215ee..86b5a51 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -39,6 +39,7 @@ struct iort_its_msi_chip { struct list_head list; struct fwnode_handle *fw_node; + phys_addr_t base_addr; u32 translation_id; }; @@ -136,14 +137,16 @@ typedef acpi_status (*iort_find_node_callback) static DEFINE_SPINLOCK(iort_msi_chip_lock); /** - * iort_register_domain_token() - register domain token and related ITS ID - * to the list from where we can get it back later on. + * iort_register_domain_token() - register domain token along with related + * ITS ID and base address to the list from where we can get it back later on. * @trans_id: ITS ID. + * @base: ITS base address. * @fw_node: Domain token. * * Returns: 0 on success, -ENOMEM if no memory when allocating list element */ -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) +int iort_register_domain_token(int trans_id, phys_addr_t base, + struct fwnode_handle *fw_node) { struct iort_its_msi_chip *its_msi_chip; @@ -153,6 +156,7 @@ int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) its_msi_chip->fw_node = fw_node; its_msi_chip->translation_id = trans_id; + its_msi_chip->base_addr = base; spin_lock(&iort_msi_chip_lock); list_add(&its_msi_chip->list, &iort_msi_chip_list); @@ -481,6 +485,24 @@ int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id) return -ENODEV; } +static int __maybe_unused iort_find_its_base(u32 its_id, phys_addr_t *base) +{ + struct iort_its_msi_chip *its_msi_chip; + bool match = false; + + spin_lock(&iort_msi_chip_lock); + list_for_each_entry(its_msi_chip, &iort_msi_chip_list, list) { + if (its_msi_chip->translation_id == its_id) { + *base = its_msi_chip->base_addr; + match = true; + break; + } + } + spin_unlock(&iort_msi_chip_lock); + + return match ? 0 : -ENODEV; +} + /** * iort_dev_find_its_id() - Find the ITS identifier for a device * @dev: The device. @@ -639,6 +661,71 @@ int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev) return err; } + +/** + * iort_iommu_its_get_resv_regions - Reserved region driver helper + * @dev: Device from iommu_get_resv_regions() + * @list: Reserved region list from iommu_get_resv_regions() + * + * Returns: Number of reserved regions on success(0 if no associated ITS), + * appropriate error value otherwise. + */ +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head) +{ + struct acpi_iort_its_group *its; + struct acpi_iort_node *node, *its_node = NULL; + int i, resv = 0; + + node = iort_find_dev_node(dev); + if (!node) + return -ENODEV; + + /* + * Current logic to reserve ITS regions relies on HW topologies + * where a given PCI or named component maps its IDs to only one + * ITS group; if a PCI or named component can map its IDs to + * different ITS groups through IORT mappings this function has + * to be reworked to ensure we reserve regions for all ITS groups + * a given PCI or named component may map IDs to. + */ + if (dev_is_pci(dev)) { + u32 rid; + + pci_for_each_dma_alias(to_pci_dev(dev), __get_pci_rid, &rid); + its_node = iort_node_map_id(node, rid, NULL, IORT_MSI_TYPE); + } else { + for (i = 0; i < node->mapping_count; i++) { + its_node = iort_node_map_platform_id(node, NULL, + IORT_MSI_TYPE, i); + if (its_node) + break; + } + } + + if (!its_node) + return 0; + + /* Move to ITS specific data */ + its = (struct acpi_iort_its_group *)its_node->node_data; + + for (i = 0; i < its->its_count; i++) { + phys_addr_t base; + + if (!iort_find_its_base(its->identifiers[i], &base)) { + int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + struct iommu_resv_region *region; + + region = iommu_alloc_resv_region(base, SZ_128K, prot, + IOMMU_RESV_MSI); + if (region) { + list_add_tail(®ion->list, head); + resv++; + } + } + } + + return (resv == its->its_count) ? resv : -ENODEV; +} #else static inline const struct iommu_ops *iort_fwspec_iommu_ops(struct iommu_fwspec *fwspec) @@ -646,6 +733,8 @@ const struct iommu_ops *iort_fwspec_iommu_ops(struct iommu_fwspec *fwspec) static inline int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev) { return 0; } +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head) +{ return -ENODEV; } #endif static const struct iommu_ops *iort_iommu_xlate(struct device *dev, diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 6893287..77322b3 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1928,7 +1928,8 @@ static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, return -ENOMEM; } - err = iort_register_domain_token(its_entry->translation_id, dom_handle); + err = iort_register_domain_token(its_entry->translation_id, res.start, + dom_handle); if (err) { pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", &res.start, its_entry->translation_id); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 8379d40..d7ed49c 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -26,7 +26,8 @@ #define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL) #define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL) -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node); +int iort_register_domain_token(int trans_id, phys_addr_t base, + struct fwnode_handle *fw_node); void iort_deregister_domain_token(int trans_id); struct fwnode_handle *iort_find_domain_token(int trans_id); #ifdef CONFIG_ACPI_IORT @@ -38,6 +39,7 @@ /* IOMMU interface */ void iort_set_dma_mask(struct device *dev); const struct iommu_ops *iort_iommu_configure(struct device *dev); +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head); #else static inline void acpi_iort_init(void) { } static inline u32 iort_msi_map_rid(struct device *dev, u32 req_id) @@ -51,6 +53,9 @@ static inline void iort_set_dma_mask(struct device *dev) { } static inline const struct iommu_ops *iort_iommu_configure(struct device *dev) { return NULL; } +static inline +int iort_iommu_its_get_resv_regions(struct device *dev, struct list_head *head) +{ return -ENODEV; } #endif #endif /* __ACPI_IORT_H__ */ From patchwork Tue Aug 1 10:49:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 109135 Delivered-To: patch@linaro.org Received: by 10.140.101.6 with SMTP id t6csp1341382qge; Tue, 1 Aug 2017 03:54:34 -0700 (PDT) X-Received: by 10.101.69.142 with SMTP id o14mr18511578pgq.242.1501584874433; Tue, 01 Aug 2017 03:54:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501584874; cv=none; d=google.com; s=arc-20160816; b=JlF9uyM2zsPqBjvpCjRxTAzCZnA7Zb3fbVqsEpeviForGrXSz9ACWcbUN2ao4oN9n5 2W2qeSHCh9XVqM6j8tWUGfEMfHUwNzRH/A5OZ4nwq5X9IThM4TZUUozVoM1IEq/oVVWx MTxyC7eD/SVfyxbEdSTLNzl1pzAUvNM+brIlB2Cat869anvh/ISqToOdW/mm6CRganAz YDFqrrMqsAl0NcjPPXS3mKE9ixlyqsdWrDFn4sZEdhXrvTEeWuJw7B7wnv/PfOhFFbfH UhsBKKKimUKPfSscGmyz6zAb+gTls3e36WLvKd+x5uYRdf8aPnCYbfoVmxyXmcJXuoFb GqFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=KFoZB0Nspn3c5Q5ff4VBn83o2bG1EY8By3iXN/FgypE=; b=JdVuxRApk6UWIfAVPco4up7ufhUtN6ouGXZcRolXtpV3TputFbN1yzjSl9NMLOyJQv uEyus0BAL1nzuoZBpL5czwM3M3D4Nxqvq2O0z99ZT3ZHVQWFcv6n5+JPZ+N2qRY293mN ewzeIigahYEjpuIOYutis5RWWY2PP7zYQBLgTpNK/DE8JZtIVAQWIW85j1H81dNPcO9e t7PlqStgTvpAjamLSVifaV/D+G+PJGmj7slEJ/ilPNjo9YU4NN5ozbN/EhjoXYqoaqiD iuQmStH7+GldTbCuFpBVdqfhaIxTgzJNFVyTOwqGnZYL7NPN7BA3F70d+o7WYXHrT0d5 YvCw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i26si12961076pfi.264.2017.08.01.03.54.34; Tue, 01 Aug 2017 03:54:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751008AbdHAKwz (ORCPT + 7 others); Tue, 1 Aug 2017 06:52:55 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:10809 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751535AbdHAKvu (ORCPT ); Tue, 1 Aug 2017 06:51:50 -0400 Received: from 172.30.72.56 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.56]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ASO11134; Tue, 01 Aug 2017 18:51:49 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Tue, 1 Aug 2017 18:51:40 +0800 From: Shameer Kolothum To: , , , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v5 2/2] iommu/dma: Add HW MSI address regions reservation Date: Tue, 1 Aug 2017 11:49:13 +0100 Message-ID: <20170801104913.71912-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170801104913.71912-1-shameerali.kolothum.thodi@huawei.com> References: <20170801104913.71912-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.59805D45.0156, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 1fcf839a1d2ac9029d2e0539db5ec465 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org Modified iommu_dma_get_resv_regions() to include HW MSI (ARM GICv3 ITS MSI) specific reservations if available. Suggested-by: Robin Murphy Signed-off-by: Shameer Kolothum --- drivers/iommu/dma-iommu.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 9d1cebe..44eca1e 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -19,6 +19,7 @@ * along with this program. If not, see . */ +#include #include #include #include @@ -167,13 +168,18 @@ void iommu_put_dma_cookie(struct iommu_domain *domain) * * IOMMU drivers can use this to implement their .get_resv_regions callback * for general non-IOMMU-specific reservations. Currently, this covers host - * bridge windows for PCI devices. + * bridge windows for PCI devices and HW MSI(ARM GICv3 ITS MSI) region + * reservations if available. */ void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) { struct pci_host_bridge *bridge; struct resource_entry *window; + if (!is_of_node(dev->iommu_fwspec->iommu_fwnode) && + iort_iommu_its_get_resv_regions(dev, list) < 0) + return; + if (!dev_is_pci(dev)) return;