From patchwork Wed Aug 2 16:43:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109248 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003331qge; Wed, 2 Aug 2017 09:44:04 -0700 (PDT) X-Received: by 10.25.17.158 with SMTP id 30mr8319433lfr.187.1501692244180; Wed, 02 Aug 2017 09:44:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692244; cv=none; d=google.com; s=arc-20160816; b=tkifwtHeQkvV5jZqwbzeSurOnOhFEDOn2kMd8KIzrfrZmfcWTjdpj4yMHMrB+cJ4jR TnUR8dlpZ+qwdxzPLMF78FN7iGqSOhjjcbJOu/EjR1X5rzCp6Dj+OWwr4XVE3LpwKDvt 1tD/n0rkuP7sZI7WYJkIZkNcMeJ+ghUcdiyUDV7pcc+WtgJGtxlIXhmL09G90fNj3w6F dDxLJSEm7mYCMsZOSSiuenWYmw5E0OLpzTLM0s83PZ0qt52M4zxP2xkeKRDAa5ZgGEke PwT4cYPxXZ77OcRu5H3uVp4yV1p6EkNvtYem+SbL0SlXN+emtnQepgAb5lhcXSadfybT j1Cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=CQdlDl5aBe8iqU3gOzUqL5ebvEfFMPwSAjNBCTRywp8=; b=wUjW00G7lk2cEhVwR6FW7UIl7tuntjdZomheALi3bcgl6sKeTvlRxXd2C77LZDl1Yi 6LqAjHR6RBA4Sg+XTHHhpRjacVDmPmMk7lagJM22i6mZ+cnDiQYeOwUduZPv94Kxx7TF /MWyBgcXMsBYz2GQFvItA27DwNHKTM+yR8Q2QjH5pkKvYHgoJU1TE7uBNjs5UMcMYoAt Eb9je1ArZre30JQGtmKmO02iXLwsloxvkcA8dGLOVALLTB+HY1nimsmbdIYpDSJ7HsPq mOW1MQ2pWeY5OxMOZK/DHiAy9ztB8oL9D87BvZQfdP3Dcx135H6cBZpSvSwnNzAOlbUt JyVw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 7si3159118lfz.644.2017.08.02.09.44.03 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkc-0003wC-QZ; Wed, 02 Aug 2017 17:44:02 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 01/15] target/arm: Use MMUAccessType enum rather than int Date: Wed, 2 Aug 2017 17:43:47 +0100 Message-Id: <1501692241-23310-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> In the ARM get_phys_addr() code, switch to using the MMUAccessType enum and its MMU_* values rather than int and literal 0/1/2. Signed-off-by: Peter Maydell --- target/arm/helper.c | 30 +++++++++++++++--------------- target/arm/internals.h | 3 ++- 2 files changed, 17 insertions(+), 16 deletions(-) -- 2.7.4 Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index fa60040..b78d277 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -20,13 +20,13 @@ #ifndef CONFIG_USER_ONLY static bool get_phys_addr(CPUARMState *env, target_ulong address, - int access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, target_ulong *page_size, uint32_t *fsr, ARMMMUFaultInfo *fi); static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, - int access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, target_ulong *page_size_ptr, uint32_t *fsr, ARMMMUFaultInfo *fi); @@ -2135,7 +2135,7 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, } static uint64_t do_ats_write(CPUARMState *env, uint64_t value, - int access_type, ARMMMUIdx mmu_idx) + MMUAccessType access_type, ARMMMUIdx mmu_idx) { hwaddr phys_addr; target_ulong page_size; @@ -2194,7 +2194,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - int access_type = ri->opc2 & 1; + MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; uint64_t par64; ARMMMUIdx mmu_idx; int el = arm_current_el(env); @@ -2253,7 +2253,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - int access_type = ri->opc2 & 1; + MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; uint64_t par64; par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); @@ -2273,7 +2273,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - int access_type = ri->opc2 & 1; + MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; ARMMMUIdx mmu_idx; int secure = arm_is_secure_below_el3(env); @@ -7510,7 +7510,7 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, } static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, - int access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, target_ulong *page_size, uint32_t *fsr, ARMMMUFaultInfo *fi) @@ -7626,7 +7626,7 @@ do_fault: } static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, - int access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, target_ulong *page_size, uint32_t *fsr, ARMMMUFaultInfo *fi) @@ -7733,7 +7733,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, if (pxn && !regime_is_user(env, mmu_idx)) { xn = 1; } - if (xn && access_type == 2) + if (xn && access_type == MMU_INST_FETCH) goto do_fault; if (arm_feature(env, ARM_FEATURE_V6K) && @@ -7848,7 +7848,7 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, } static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, - int access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, target_ulong *page_size_ptr, uint32_t *fsr, ARMMMUFaultInfo *fi) @@ -8256,7 +8256,7 @@ static inline bool m_is_system_region(CPUARMState *env, uint32_t address) } static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, - int access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, uint32_t *fsr) { ARMCPU *cpu = arm_env_get_cpu(env); @@ -8415,7 +8415,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, } static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, - int access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, uint32_t *fsr) { int n; @@ -8442,7 +8442,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, return true; } - if (access_type == 2) { + if (access_type == MMU_INST_FETCH) { mask = env->cp15.pmsav5_insn_ap; } else { mask = env->cp15.pmsav5_data_ap; @@ -8513,7 +8513,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, * @fsr: set to the DFSR/IFSR value on failure */ static bool get_phys_addr(CPUARMState *env, target_ulong address, - int access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, target_ulong *page_size, uint32_t *fsr, ARMMMUFaultInfo *fi) @@ -8626,7 +8626,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, * fsr with ARM DFSR/IFSR fault register format value on failure. */ bool arm_tlb_fill(CPUState *cs, vaddr address, - int access_type, int mmu_idx, uint32_t *fsr, + MMUAccessType access_type, int mmu_idx, uint32_t *fsr, ARMMMUFaultInfo *fi) { ARMCPU *cpu = ARM_CPU(cs); diff --git a/target/arm/internals.h b/target/arm/internals.h index 1f6efef..bb06946 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -457,7 +457,8 @@ struct ARMMMUFaultInfo { }; /* Do a page table walk and add page to TLB if possible */ -bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx, +bool arm_tlb_fill(CPUState *cpu, vaddr address, + MMUAccessType access_type, int mmu_idx, uint32_t *fsr, ARMMMUFaultInfo *fi); /* Return true if the stage 1 translation regime is using LPAE format page From patchwork Wed Aug 2 16:43:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109261 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003390qge; Wed, 2 Aug 2017 09:44:08 -0700 (PDT) X-Received: by 10.99.116.26 with SMTP id p26mr22667499pgc.446.1501692248036; Wed, 02 Aug 2017 09:44:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692248; 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[2001:8b0:1d0::2]) by mx.google.com with ESMTPS id b77si14351739pfb.525.2017.08.02.09.44.07 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkd-0003wR-EG; Wed, 02 Aug 2017 17:44:03 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 02/15] target/arm: Don't trap WFI/WFE for M profile Date: Wed, 2 Aug 2017 17:43:48 +0100 Message-Id: <1501692241-23310-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> M profile cores can never trap on WFI or WFE instructions. Check for M profile in check_wfx_trap() to ensure this. The existing code will do the right thing for v7M cores because the hcr_el2 and scr_el3 registers will be all-zeroes and so we won't attempt to trap, but when we start setting ARM_FEATURE_V8 for v8M cores the v8A handling of SCTLR.nTWE and .nTWI will not give the right results. Signed-off-by: Peter Maydell --- target/arm/op_helper.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.7.4 Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 2a85666..5a94a5f 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -370,6 +370,11 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe) int cur_el = arm_current_el(env); uint64_t mask; + if (arm_feature(env, ARM_FEATURE_M)) { + /* M profile cores can never trap WFI/WFE. */ + return 0; + } + /* If we are currently in EL0 then we need to check if SCTLR is set up for * WFx instructions being trapped to EL1. These trap bits don't exist in v7. */ From patchwork Wed Aug 2 16:43:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109247 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003333qge; Wed, 2 Aug 2017 09:44:04 -0700 (PDT) X-Received: by 10.28.154.211 with SMTP id c202mr4055815wme.91.1501692244417; Wed, 02 Aug 2017 09:44:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692244; cv=none; d=google.com; s=arc-20160816; b=aoFsyYTjU3rzwrCrgN0Mnj5uqtABCqmEUK5Gj/VdWAtZUN6xiBLkLgteqoCAyEhygy CeSCYC3FSu9G12oCvmJrN9u4VfJ6bmkZjaxeHLKOJas1FoH4utztGHiBk8OG9botDi+3 J/SKPIHI2fEYrwK5x3ymKxUaJQJLaIYjquYqxsP+fdyhI+e/d56OawoLeciD++Z6thQx T8XsI8Msi59y5xnEd4oBPBZ7m0qnyiW87OnSvq+dLVIJ5rlurGOtGqKaEOHgh5sWn1fo PJ2BdH7KiStSS4QShNB8Lk1JSM9/HERefXk8nRXnU20GB5O/guGu/LpK7QCLgKAmp09U fJxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=b3ociU29Pzft7LUQDdFeYPohaoeo3n/FbHFN5KRptYc=; b=xIaZqlFqhDUW4gKzwNlV93t5AJTnHUsqV7p7i2u49p7vTzfUAKjHpM80o2v0aXXa2m QG3o6gsf1M/MxzcoQgPT7tLDQnMDTxN9YnybmwFDZyESgv2SiqugSRhdlVOX9w6BBjj+ X/YrXpcYuTuQEv/SURMcrq0Ir8I6oQ1HUyt6ZZfTNvDuc4bIrOCv/TYkNPvICffnqc55 wh0YqVT+gWilqohv8XMGbjGIOKrgfX/IvmUo65DfMDNRPTDJzF3FZkOvMbD3WrttE3ta yE4k/NCDtSTNzJc8amaOXs+kfvxfF92y6xnr0iWCLFQrbPMpCIgP+IoqvCuY6gPjwFMq orJw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id g39si25157255wrd.149.2017.08.02.09.44.04 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkd-0003wq-SX; Wed, 02 Aug 2017 17:44:03 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 03/15] target/arm: Consolidate PMSA handling in get_phys_addr() Date: Wed, 2 Aug 2017 17:43:49 +0100 Message-Id: <1501692241-23310-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> Currently get_phys_addr() has PMSAv7 handling before the "is translation disabled?" check, and then PMSAv5 after it. Tidy this up by making the PMSAv5 code handle the "MPU disabled" case itself, so that we have all the PMSA code in one place. This will make adding the PMSAv8 code slightly cleaner, and also means that pre-v7 PMSA cores benefit from the MPU lookup logging that the PMSAv7 codepath had. Signed-off-by: Peter Maydell --- target/arm/helper.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) -- 2.7.4 Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index b78d277..fd83a21 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8423,6 +8423,13 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, uint32_t base; bool is_user = regime_is_user(env, mmu_idx); + if (regime_translation_disabled(env, mmu_idx)) { + /* MPU disabled. */ + *phys_ptr = address; + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return false; + } + *phys_ptr = address; for (n = 7; n >= 0; n--) { base = env->cp15.c6_region[n]; @@ -8572,16 +8579,20 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, } } - /* pmsav7 has special handling for when MPU is disabled so call it before - * the common MMU/MPU disabled check below. - */ - if (arm_feature(env, ARM_FEATURE_PMSA) && - arm_feature(env, ARM_FEATURE_V7)) { + if (arm_feature(env, ARM_FEATURE_PMSA)) { bool ret; *page_size = TARGET_PAGE_SIZE; - ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, - phys_ptr, prot, fsr); - qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32 + + if (arm_feature(env, ARM_FEATURE_V7)) { + /* PMSAv7 */ + ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, + phys_ptr, prot, fsr); + } else { + /* Pre-v7 MPU */ + ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, + phys_ptr, prot, fsr); + } + qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", access_type == MMU_DATA_LOAD ? "reading" : (access_type == MMU_DATA_STORE ? "writing" : "execute"), @@ -8594,21 +8605,16 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, return ret; } + /* Definitely a real MMU, not an MPU */ + if (regime_translation_disabled(env, mmu_idx)) { - /* MMU/MPU disabled. */ + /* MMU disabled. */ *phys_ptr = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; *page_size = TARGET_PAGE_SIZE; return 0; } - if (arm_feature(env, ARM_FEATURE_PMSA)) { - /* Pre-v7 MPU */ - *page_size = TARGET_PAGE_SIZE; - return get_phys_addr_pmsav5(env, address, access_type, mmu_idx, - phys_ptr, prot, fsr); - } - if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, attrs, prot, page_size, fsr, fi); From patchwork Wed Aug 2 16:43:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109249 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003347qge; Wed, 2 Aug 2017 09:44:05 -0700 (PDT) X-Received: by 10.223.150.10 with SMTP id b10mr16737356wra.85.1501692244997; Wed, 02 Aug 2017 09:44:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692244; cv=none; d=google.com; s=arc-20160816; b=OV1JdcvcdZLaS/0OwU2cqutK1el7oGAr9u51lMvlSipDEZiD48RrCLf/1rLcsTERPD 2PqQ0dlrBoxYt9cfqJRCoCcw/uRgwGr1vg5DHRlL6uu0hV/F/QlxjwcAgrNrIYxZLXHP PuS6qUU6OdMArTqekOamgqAQTJf2OTbqEkAvMkxRMH8G5cMUR1jIhCR4UvvCnjXRB8pm dP7plhnJ1d8TgGII0M009irqZCVuHcOn8/mGCxBGUJ9NAY2Mr6r66DBSGPj8f3qpb2Kp 28qvzbHKLotND0VAdzbzWYkuRuUfdGvAUZcUn7S8M19yXbBX1BJyEWUv+F6b+f6o4vOl d8xA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=xACm1ObE4RWwOUveFdJ0M5TkxnS4WSXWROrEXqq41/Q=; b=YMl5RZJi7lTbP0hVEf18GXe3/srJIoh8PBE6tPpzTDMY6kiddqvc+pWGd7L2mmKPRu aUKtnBkysmpFxGTA56Heb3tNAtEkAofuhE2CUL7bJBnx0uXsAwlLftSj8LDPM+90NF0I 4+EibkeMh4kc50elpBQo1Tfy1Gq88hPqe454JAfP22rFzvD8HKvSF6IUob5ujIXKTHs3 xU3Ud7/us+HDXGSOW6JwAcccxFGFncN6Zvycqjtw3ciSvQtLQwV4vhpmHhwxnuqRAJGp DCzcWnfJEAyrl1MVELlVqmmFFEWjEhqiD/4PcRSYwolsdpwOit3FkCwJ0jttaP45h37h rGKQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id s6si17326465wrg.389.2017.08.02.09.44.04 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwke-0003x6-Ho; Wed, 02 Aug 2017 17:44:04 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 04/15] target/arm: Tighten up Thumb decode where new v8M insns will be Date: Wed, 2 Aug 2017 17:43:50 +0100 Message-Id: <1501692241-23310-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> Tighten up the T32 decoder in the places where new v8M instructions will be: * TT/TTT/TTA/TTAT are in what was nominally LDREX/STREX r15, ... which is UNPREDICTABLE: make the UNPREDICTABLE behaviour be to UNDEF * BXNS/BLXNS are distinguished from BX/BLX via the low 3 bits, which in previous architectural versions are SBZ: enforce the SBZ via UNDEF rather than ignoring it, and move the "ARCH(5)" UNDEF case up so we don't leak a TCG temporary * SG is in the encoding which would be LDRD/STRD with rn = r15; this is UNPREDICTABLE and we currently UNDEF: move this check further up the code so that we don't leak TCG temporaries in the UNDEF case and have a better place to put the SG decode. This means that if a v8M binary is accidentally run on v7M or if a test case hits something that we haven't implemented yet the behaviour will be obvious (UNDEF) rather than obscure (plough on treating it as a different instruction). In the process, add some comments about the instruction patterns at these points in the decode. Our Thumb and ARM decoders are very difficult to understand currently, but gradually adding comments like this should help to clarify what exactly has been decoded when. Signed-off-by: Peter Maydell --- target/arm/translate.c | 48 +++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 39 insertions(+), 9 deletions(-) -- 2.7.4 Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson diff --git a/target/arm/translate.c b/target/arm/translate.c index d1a5f56..3c14cb0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9735,10 +9735,23 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw abort(); case 4: if (insn & (1 << 22)) { - /* Other load/store, table branch. */ + /* 0b1110_100x_x1xx_xxxx_xxxx_xxxx_xxxx_xxxx + * - load/store doubleword, load/store exclusive, ldacq/strel, + * table branch. + */ if (insn & 0x01200000) { - /* Load/store doubleword. */ + /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx + * - load/store dual (post-indexed) + * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx + * - load/store dual (literal and immediate) + * 0b1111_1001_x11x_xxxx_xxxx_xxxx_xxxx_xxxx + * - load/store dual (pre-indexed) + */ if (rn == 15) { + if (insn & (1 << 21)) { + /* UNPREDICTABLE */ + goto illegal_op; + } addr = tcg_temp_new_i32(); tcg_gen_movi_i32(addr, s->pc & ~3); } else { @@ -9772,15 +9785,18 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw } if (insn & (1 << 21)) { /* Base writeback. */ - if (rn == 15) - goto illegal_op; tcg_gen_addi_i32(addr, addr, offset - 4); store_reg(s, rn, addr); } else { tcg_temp_free_i32(addr); } } else if ((insn & (1 << 23)) == 0) { - /* Load/store exclusive word. */ + /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx + * - load/store exclusive word + */ + if (rs == 15) { + goto illegal_op; + } addr = tcg_temp_local_new_i32(); load_reg_var(s, addr, rn); tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2); @@ -11137,7 +11153,9 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) break; } if (insn & (1 << 10)) { - /* data processing extended or blx */ + /* 0b0100_01xx_xxxx_xxxx + * - data processing extended, branch and exchange + */ rd = (insn & 7) | ((insn >> 4) & 8); rm = (insn >> 3) & 0xf; op = (insn >> 8) & 3; @@ -11160,10 +11178,21 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) tmp = load_reg(s, rm); store_reg(s, rd, tmp); break; - case 3:/* branch [and link] exchange thumb register */ - tmp = load_reg(s, rm); - if (insn & (1 << 7)) { + case 3: + { + /* 0b0100_0111_xxxx_xxxx + * - branch [and link] exchange thumb register + */ + bool link = insn & (1 << 7); + + if (insn & 7) { + goto undef; + } + if (link) { ARCH(5); + } + tmp = load_reg(s, rm); + if (link) { val = (uint32_t)s->pc | 1; tmp2 = tcg_temp_new_i32(); tcg_gen_movi_i32(tmp2, val); @@ -11175,6 +11204,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) } break; } + } break; } From patchwork Wed Aug 2 16:43:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109250 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003353qge; Wed, 2 Aug 2017 09:44:05 -0700 (PDT) X-Received: by 10.28.164.66 with SMTP id n63mr2608393wme.82.1501692245471; Wed, 02 Aug 2017 09:44:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692245; cv=none; d=google.com; s=arc-20160816; b=wPQr5keDbmkfBwK6QukurD5XCi9572DlVQR4HkrRdlfy4HfDB85JOJX9i2JdzysrBD 32FmADcXwP9EPoReYgugeRSQuFkUCkjwq8g7UnmK//TJPXE0za9PC5ybJVV3McMlFfeC X1pXss3MCnlGAuFL4h1jBxrcqPcRYJq6cgQDih+/k4b/05X30lMDonkL595K9l2ZeCB1 F8cYzO22hngcyYyQZDzQt4Far1JUANYThe9ULdEt6jgmLW/bgF7QZ9MVQ9sIlvtMyoVs 8LHgvq7PPaBaf8KsR6d176bqESY1qpx4+MJN16IUv1VtXABeTgPkhqroehQOkLCynsUo +0ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=NtaxEGKpc5UeLOSiIMNjB+coLoYkXUj/Nys4qeMJJb4=; b=WNxzRNNkjmWrUGHyDdU3AMDbsCcm9YE1BhamWCzpBNuD7vw9JOcyiDV6wc09VY8wg2 PjjCL3Thm5JP9Hwy79gIsT+w0m3YJdyrf0bCYstCdGRxVrwE885+W+ZrRbIxUFjUCHoX hXalI61OW/mENFsNTfzDwSaFtkz1l7kQDLIP44vnzjXCO+uIor6c+bEoWfgBgNlG35FF AMK2GHPMOLKdH2xiT4mijO6Xh6rQpVh4kRb2tBrBIB4mT/7rmOPJXQ6C+zG64+W1z9jP JSEglv7OazQ0ON+tFeqJy3TXNDj8zVhwd27RmZ+WWAIiBZorqEbZQ7OiYde/Eeo0eiNv S8/Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id j2si26708254wre.433.2017.08.02.09.44.05 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkf-0003xR-14; Wed, 02 Aug 2017 17:44:05 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 05/15] hw/intc/armv7m_nvic.c: Remove out of date comment Date: Wed, 2 Aug 2017 17:43:51 +0100 Message-Id: <1501692241-23310-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> Remove an out of date comment which says there's only one item in the NVIC container region -- we put systick into its own device object a while back and so now there are two things in the container. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 4 ---- 1 file changed, 4 deletions(-) -- 2.7.4 Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 323e2d4..2e8166a 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1036,10 +1036,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) * 0xd00..0xd3c - SCS registers * 0xd40..0xeff - Reserved or Not implemented * 0xf00 - STIR - * - * At the moment there is only one thing in the container region, - * but we leave it in place to allow us to pull systick out into - * its own device object later. */ memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000); /* The system register region goes at the bottom of the priority From patchwork Wed Aug 2 16:43:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109251 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003358qge; Wed, 2 Aug 2017 09:44:06 -0700 (PDT) X-Received: by 10.223.142.68 with SMTP id n62mr20714309wrb.27.1501692245950; Wed, 02 Aug 2017 09:44:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692245; cv=none; d=google.com; s=arc-20160816; b=uduxK+SyAXxEjD1GKnkqRekfXOsySYHCpw/JBhzHo/AsPcKptr9sDIc2kOyCj3A4QW iZVEFhdQU/pXB9YZJDU3LC+MGTuPNoH3MD+SVI9cBBds6ZtsnVqRIEqxfvrWwkt99tUB x7Jg2qEovXyZCApQ59/jWA/zeOthuiOiJosG9RUs2OSD+0oZOn5FCECot0ItIRUgW7v9 5RaAmCAvKQEnovvYPsSG/+gW6yx5fRKAp1/jcuzIzPtbyw+qyq1sPOJXrTbbDesIl3Pm 4uTM32bJ6X5s0nyOe6raGN2c66ZLZSOx1vR4xoxnKeoMnPobV/NutEp/IySpV4xI/iGB nFWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=+6Qar3r5X0EamItaEhpBe7+TPCOvZagGrw0SAlMkkRo=; b=C22BGScKrWvjNii57TvDNXnF024+VI7bNIGTcfpH+enGo/rU2OEElIUZc835oAWCzA 7Kt+G6D6NK5rwy8YWRM1euHjkSHMowRbGftT/P2zoxIHz6nGMrXG1vi/0ZiwT7B1yYwF X7nTwkZyKcIOyply8DffuktEwuIieZE+0V/tHt29N9OXNFAlGECyciia23RNAPsiA7dJ cY7HCSsSr3zzQF81zcZYZsk+SHXKQIBP7ePLZ8ejoR6G0RszEsJ8Xo0F+Bg6YFSFhPlW WBS8wS7YUqoP1CVTUIFnBpmq92Q2Djz6OYsjLmJW+N6yujVUA7RpLq3LYS3BpG/K8a5B kgiw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id w63si17509860wrb.70.2017.08.02.09.44.05 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkf-0003xp-H1; Wed, 02 Aug 2017 17:44:05 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 06/15] target/arm: Remove incorrect comment about MPU_CTRL Date: Wed, 2 Aug 2017 17:43:52 +0100 Message-Id: <1501692241-23310-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> Remove the comment that claims that some MPU_CTRL bits are stored in sctlr_el[1]. This has never been true since MPU_CTRL was added in commit 29c483a50607 -- the comment is a leftover from Michael Davidsaver's original implementation, which I modified not to use sctlr_el[1]; I forgot to delete the comment then. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b39d64a..b64474c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -416,7 +416,7 @@ typedef struct CPUARMState { uint32_t dfsr; /* Debug Fault Status Register */ uint32_t mmfar; /* MemManage Fault Address */ uint32_t bfar; /* BusFault Address */ - unsigned mpu_ctrl; /* MPU_CTRL (some bits kept in sctlr_el[1]) */ + unsigned mpu_ctrl; /* MPU_CTRL */ int exception; } v7m; From patchwork Wed Aug 2 16:43:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109252 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003361qge; Wed, 2 Aug 2017 09:44:06 -0700 (PDT) X-Received: by 10.223.150.200 with SMTP id u66mr21183237wrb.216.1501692246394; Wed, 02 Aug 2017 09:44:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692246; cv=none; d=google.com; s=arc-20160816; b=UyeGrw0IG7TBi+AQC0nYLfPS5X1O9/ZycivgLv7TRecZ/UG+1nScU5hSMHUkjkmQZX rCGaBRa5zGZ+cOj3KwUISDeELvhBkH7OJP56VbOwFRIDkbqI9D5YlDNJjsIfGAXvx8Wa UvoVoBy5/osI7eQB6ZNIE6dZU/v1YO8Ff5rmAKk8OpX9jR6CVgL90HGqSOcILZHB7sG8 B3VhjcZu/o+d1HAqWvcjRWV3wvbHFOXxcskdF8ccLxtMJ56ZIlVWlFw8sj8ApcCnZKYD Q7YBrNca/azYkmVEez+8R9JjEJ4B0MLEpnZmBd3tawEmonP0n0a37QBUpwBBLbGCVwaz Fu1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=M/Ta+5+FLoCioBcaYj4TWwcHbecwb7lppqdwhp0Lp/4=; b=CtkCAl3qbZoUoaUh2NZprGkbqLcJ3YOHyreWF0jPgdelm+gCaKSKV1k862LXA1LldR WzshXTuGSXRH/8pNeD41sMGWce06VSC3YXxpRKElk2fCWpLhBbuwV9bfMBtktz92v8Xz 2fPBkZNkCZ4DnOuqbtrQP3kaYu2CMHVqry/hI1dGW4wZEwwIjQykr4FQ4gDceluF/DCl qb2n+3upoA58RdG6xfgG13GiGn5EB7QF5uKtmDJj4HU63F+IZoCxJcdUhs/FYWZCPjhX 66bLf8tasE+IFAvTKqD/ec5gmMiBU1P5HrHPY6GbGY9k6LIFZvHE7AaeTg7r3mOsMBiH 96Bw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id v23si7112466wrd.388.2017.08.02.09.44.06 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkf-0003yE-Vq; Wed, 02 Aug 2017 17:44:05 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 07/15] target/arm: Fix outdated comment about exception exit Date: Wed, 2 Aug 2017 17:43:53 +0100 Message-Id: <1501692241-23310-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> When we switched our handling of exception exit to detect the magic addresses at translate time rather than via a do_unassigned_access hook, we forgot to update a comment; correct the omission. Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index fd83a21..cb88c66 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6143,7 +6143,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) bool rettobase = false; /* We can only get here from an EXCP_EXCEPTION_EXIT, and - * arm_v7m_do_unassigned_access() enforces the architectural rule + * gen_bx_excret() enforces the architectural rule * that jumps to magic addresses don't have magic behaviour unless * we're in Handler mode (compare pseudocode BXWritePC()). */ From patchwork Wed Aug 2 16:43:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109253 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003369qge; Wed, 2 Aug 2017 09:44:06 -0700 (PDT) X-Received: by 10.28.52.207 with SMTP id b198mr4327648wma.31.1501692246877; Wed, 02 Aug 2017 09:44:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692246; cv=none; d=google.com; s=arc-20160816; b=Scxy28elrYDt+AkLdICNtvCDQ5vTDqVQeC58O8iVlz6JwSjjubvChXAWtISHaXLpDq h9pD4u1aLgxR8t5GjTql+oo6cL0t/DfN1o5dUVqA4sCkF7WQAr/zls+ClOwyrPtSh1Vb BDReyUwtq+3at4C2uMrfOSHn0QqnbkLc0TY2UdJmFeKYMGIJsijDd8nCOWqAeYCzRrd8 Ed5DZbPecLI3f4eTY4FlzFhEYw4h7+KCCsZ5/+GNlhUzo0zzYjnXnw2JLpl7r8eV2vQF pdvpWqFw4U6++voLJhzQXWd/rk8P5zEzmFGHbpPowFRDOnoFkT0Vjz7RU7VG/rXaAq5V 2Nmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=LC5PFc3t5fueI0T8ImT9lfMo7MFqOCvneVZqFLN5bE0=; b=CqbtcXXkzoHBs6ZpmEnRilUgocYV83Cvnqo3h2WawAWliort4Ux6zvQ52A3qWXLddr NWlTUOxph8mZrFZ/K9p3y7UTWoXFjQC8lGARn2lgxDmhdZ22YASS8c9l8fx8R2V1ef8D dZ4q3hH7cX6ks17trcZ/GDkQAvIegnpNIuabPYu4smWDJibl4v/qJZ0PRtfRY24Ar1+q yJqXQvMFes8bkpIetheKHCPxa6O1hmsrReaNTm1/nXQ5NsyEDAcOXLKaKaGYQVfNZ0Eg 7GVPk8xgHPozfTnZiyy9p4vDL8W2ZInKc1SMbCXAP4PGKpxxDsan10apTJJh0E5DPtdm hgaw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id p48si7884746wrc.303.2017.08.02.09.44.06 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkg-0003yc-Do; Wed, 02 Aug 2017 17:44:06 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 08/15] target/arm: Define and use XPSR bit masks Date: Wed, 2 Aug 2017 17:43:54 +0100 Message-Id: <1501692241-23310-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> The M profile XPSR is almost the same format as the A profile CPSR, but not quite. Define some XPSR_* macros and use them where we definitely dealing with an XPSR rather than reusing the CPSR ones. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 38 ++++++++++++++++++++++++++++---------- target/arm/helper.c | 15 ++++++++------- 2 files changed, 36 insertions(+), 17 deletions(-) -- 2.7.4 Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b64474c..1f06de0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -883,6 +883,22 @@ void pmccntr_sync(CPUARMState *env); /* Mask of bits which may be set by exception return copying them from SPSR */ #define CPSR_ERET_MASK (~CPSR_RESERVED) +/* Bit definitions for M profile XPSR. Most are the same as CPSR. */ +#define XPSR_EXCP 0x1ffU +#define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ +#define XPSR_IT_2_7 CPSR_IT_2_7 +#define XPSR_GE CPSR_GE +#define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ +#define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ +#define XPSR_IT_0_1 CPSR_IT_0_1 +#define XPSR_Q CPSR_Q +#define XPSR_V CPSR_V +#define XPSR_C CPSR_C +#define XPSR_Z CPSR_Z +#define XPSR_N CPSR_N +#define XPSR_NZCV CPSR_NZCV +#define XPSR_IT CPSR_IT + #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ #define TTBCR_PD0 (1U << 4) @@ -987,26 +1003,28 @@ static inline uint32_t xpsr_read(CPUARMState *env) /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) { - if (mask & CPSR_NZCV) { - env->ZF = (~val) & CPSR_Z; + if (mask & XPSR_NZCV) { + env->ZF = (~val) & XPSR_Z; env->NF = val; env->CF = (val >> 29) & 1; env->VF = (val << 3) & 0x80000000; } - if (mask & CPSR_Q) - env->QF = ((val & CPSR_Q) != 0); - if (mask & (1 << 24)) - env->thumb = ((val & (1 << 24)) != 0); - if (mask & CPSR_IT_0_1) { + if (mask & XPSR_Q) { + env->QF = ((val & XPSR_Q) != 0); + } + if (mask & XPSR_T) { + env->thumb = ((val & XPSR_T) != 0); + } + if (mask & XPSR_IT_0_1) { env->condexec_bits &= ~3; env->condexec_bits |= (val >> 25) & 3; } - if (mask & CPSR_IT_2_7) { + if (mask & XPSR_IT_2_7) { env->condexec_bits &= 3; env->condexec_bits |= (val >> 8) & 0xfc; } - if (mask & 0x1ff) { - env->v7m.exception = val & 0x1ff; + if (mask & XPSR_EXCP) { + env->v7m.exception = val & XPSR_EXCP; } } diff --git a/target/arm/helper.c b/target/arm/helper.c index cb88c66..f087d42 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6119,7 +6119,7 @@ static void v7m_push_stack(ARMCPU *cpu) /* Align stack pointer if the guest wants that */ if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) { env->regs[13] -= 4; - xpsr |= 0x200; + xpsr |= XPSR_SPREALIGN; } /* Switch to the handler mode. */ v7m_push(env, xpsr); @@ -6244,10 +6244,11 @@ static void do_v7m_exception_exit(ARMCPU *cpu) env->regs[15] &= ~1U; } xpsr = v7m_pop(env); - xpsr_write(env, xpsr, 0xfffffdff); + xpsr_write(env, xpsr, ~XPSR_SPREALIGN); /* Undo stack alignment. */ - if (xpsr & 0x200) + if (xpsr & XPSR_SPREALIGN) { env->regs[13] |= 4; + } /* The restored xPSR exception field will be zero if we're * resuming in Thread mode. If that doesn't match what the @@ -8693,10 +8694,10 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) case 0 ... 7: /* xPSR sub-fields */ mask = 0; if ((reg & 1) && el) { - mask |= 0x000001ff; /* IPSR (unpriv. reads as zero) */ + mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */ } if (!(reg & 4)) { - mask |= 0xf8000000; /* APSR */ + mask |= XPSR_NZCV | XPSR_Q; /* APSR */ } /* EPSR reads as zero */ return xpsr_read(env) & mask; @@ -8754,10 +8755,10 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) uint32_t apsrmask = 0; if (mask & 8) { - apsrmask |= 0xf8000000; /* APSR NZCVQ */ + apsrmask |= XPSR_NZCV | XPSR_Q; } if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { - apsrmask |= 0x000f0000; /* APSR GE[3:0] */ + apsrmask |= XPSR_GE; } xpsr_write(env, val, apsrmask); } From patchwork Wed Aug 2 16:43:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109254 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003378qge; Wed, 2 Aug 2017 09:44:07 -0700 (PDT) X-Received: by 10.28.212.147 with SMTP id l141mr4381325wmg.13.1501692247414; Wed, 02 Aug 2017 09:44:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692247; cv=none; d=google.com; s=arc-20160816; b=JH3DKAT7fkW5CO2tEjGCRsKDdVc04Z1eq0KuKLoJGOAWci2LKJAI0kefDGjwMrML9P Qkgtdjt9gUMURVLr65hh7PEm79Uq2Qr6RdnQqcCFt0ck8tVK2ipIPtsxXqiL/v/RYD1w Kk4HUDEwqj1chmieB3xlNE/JhEI++XWhEKyamGoqtffIhCWFqpOBYSjDjTXcaW08U3+L kf+5v+O3uW6XgeOL+6KDItFNijmSwWsUDS1/JMnj/4HR0RSsi8LHUL8B1wkcrl4fBXw4 PqZMW0qT5VFrZpoNCbb9lyxu79WKlj81MSXcRF1En0cjoRiYrEueplz3PiAR5rCbt4u/ tysw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=fX0zB3DuXdZABnuwbp0Th9yYnae/271fCQB1YAUMOfs=; b=yvn/OMkBy/2ApCDUKVWBtANKlKmibMUwhGWlm1sqeFmEP5kyZ3XYkFO6YclGwLG2t6 ewyUUIv5TrONbWb2QGAlK2s+QkKmSBaJ5LpYrLrbjneTVWizZPtKhoVIr97eyaUqvxNk zpJq4XjKvPan8i7DKU6Wmd95SI+WZVhioU1SYsiB2TBd3EgTpdIYl8SMh9oGDksQlxfE RjaUPt2GQlrtN7asX24qw64tiUYObQa+mFqSnJ7E8Aa0LkCbeHzskvCqzqNKqMwNplyI rOLkhQK7gjoCWSEI5dH/D0/SMcgw6wXGbBjq6O53MrevmIL0NNDxCDGFQTHHsBlfgpU0 3Ilg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id c29si17905987wrb.318.2017.08.02.09.44.07 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkg-0003z0-U7; Wed, 02 Aug 2017 17:44:06 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 09/15] target/arm: Don't store M profile PRIMASK and FAULTMASK in daif Date: Wed, 2 Aug 2017 17:43:55 +0100 Message-Id: <1501692241-23310-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> We currently store the M profile CPU register state PRIMASK and FAULTMASK in the daif field of the CPU state in its I and F bits. This is a legacy from the original implementation, which tried to share the cpu_exec_interrupt code between A profile and M profile. We've since separated out the two cases because they are significantly different, so now there is no common code between M and A profile which looks at env->daif: all the uses are either in A-only or M-only code paths. Sharing the state fields now is just confusing, and will make things awkward when we implement v8M, where the PRIMASK and FAULTMASK registers are banked between security states. Switch M profile over to using v7m.faultmask and v7m.primask fields for these registers. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 4 ++-- target/arm/cpu.c | 5 ----- target/arm/cpu.h | 4 +++- target/arm/helper.c | 18 +++++------------- target/arm/machine.c | 33 +++++++++++++++++++++++++++++++++ 5 files changed, 43 insertions(+), 21 deletions(-) -- 2.7.4 Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 2e8166a..343bc16 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -167,9 +167,9 @@ static inline int nvic_exec_prio(NVICState *s) CPUARMState *env = &s->cpu->env; int running; - if (env->daif & PSTATE_F) { /* FAULTMASK */ + if (env->v7m.faultmask) { running = -1; - } else if (env->daif & PSTATE_I) { /* PRIMASK */ + } else if (env->v7m.primask) { running = 0; } else if (env->v7m.basepri > 0) { running = env->v7m.basepri & nvic_gprio_mask(s); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 05c038b..b241a63 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -185,11 +185,6 @@ static void arm_cpu_reset(CPUState *s) uint32_t initial_pc; /* Loaded from 0x4 */ uint8_t *rom; - /* For M profile we store FAULTMASK and PRIMASK in the - * PSTATE F and I bits; these are both clear at reset. - */ - env->daif &= ~(PSTATE_I | PSTATE_F); - /* The reset value of this bit is IMPDEF, but ARM recommends * that it resets to 1, so QEMU always does that rather than making * it dependent on CPU model. diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1f06de0..da90b7a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -418,6 +418,8 @@ typedef struct CPUARMState { uint32_t bfar; /* BusFault Address */ unsigned mpu_ctrl; /* MPU_CTRL */ int exception; + uint32_t primask; + uint32_t faultmask; } v7m; /* Information associated with an exception about to be taken: @@ -2179,7 +2181,7 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) * we're in a HardFault or NMI handler. */ if ((env->v7m.exception > 0 && env->v7m.exception <= 3) - || env->daif & PSTATE_F) { + || env->v7m.faultmask) { return arm_to_core_mmu_idx(ARMMMUIdx_MNegPri); } diff --git a/target/arm/helper.c b/target/arm/helper.c index f087d42..b64ddb1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6172,7 +6172,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) if (env->v7m.exception != ARMV7M_EXCP_NMI) { /* Auto-clear FAULTMASK on return from other than NMI */ - env->daif &= ~PSTATE_F; + env->v7m.faultmask = 0; } switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) { @@ -8718,12 +8718,12 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? env->regs[13] : env->v7m.other_sp; case 16: /* PRIMASK */ - return (env->daif & PSTATE_I) != 0; + return env->v7m.primask; case 17: /* BASEPRI */ case 18: /* BASEPRI_MAX */ return env->v7m.basepri; case 19: /* FAULTMASK */ - return (env->daif & PSTATE_F) != 0; + return env->v7m.faultmask; default: qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" " register %d\n", reg); @@ -8778,11 +8778,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) } break; case 16: /* PRIMASK */ - if (val & 1) { - env->daif |= PSTATE_I; - } else { - env->daif &= ~PSTATE_I; - } + env->v7m.primask = val & 1; break; case 17: /* BASEPRI */ env->v7m.basepri = val & 0xff; @@ -8793,11 +8789,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) env->v7m.basepri = val; break; case 19: /* FAULTMASK */ - if (val & 1) { - env->daif |= PSTATE_F; - } else { - env->daif &= ~PSTATE_F; - } + env->v7m.faultmask = val & 1; break; case 20: /* CONTROL */ /* Writing to the SPSEL bit only has an effect if we are in diff --git a/target/arm/machine.c b/target/arm/machine.c index 1f66da4..2fb4b76 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -97,6 +97,17 @@ static bool m_needed(void *opaque) return arm_feature(env, ARM_FEATURE_M); } +static const VMStateDescription vmstate_m_faultmask_primask = { + .name = "cpu/m/faultmask-primask", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(env.v7m.faultmask, ARMCPU), + VMSTATE_UINT32(env.v7m.primask, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_m = { .name = "cpu/m", .version_id = 4, @@ -115,6 +126,10 @@ static const VMStateDescription vmstate_m = { VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU), VMSTATE_INT32(env.v7m.exception, ARMCPU), VMSTATE_END_OF_LIST() + }, + .subsections = (const VMStateDescription*[]) { + &vmstate_m_faultmask_primask, + NULL } }; @@ -201,6 +216,24 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size, CPUARMState *env = &cpu->env; uint32_t val = qemu_get_be32(f); + if (arm_feature(env, ARM_FEATURE_M)) { + /* If the I or F bits are set then this is a migration from + * an old QEMU which still stored the M profile FAULTMASK + * and PRIMASK in env->daif. Set v7m.faultmask and v7m.primask + * accordingly, and then clear the bits so they don't confuse + * cpsr_write(). For a new QEMU, the bits here will always be + * clear, and the data is transferred using the + * vmstate_m_faultmask_primask subsection. + */ + if (val & CPSR_F) { + env->v7m.faultmask = 1; + } + if (val & CPSR_I) { + env->v7m.primask = 1; + } + val &= ~(CPSR_F | CPSR_I); + } + env->aarch64 = ((val & PSTATE_nRW) == 0); if (is_a64(env)) { From patchwork Wed Aug 2 16:43:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109255 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003389qge; Wed, 2 Aug 2017 09:44:07 -0700 (PDT) X-Received: by 10.28.87.193 with SMTP id l184mr4035748wmb.121.1501692247868; Wed, 02 Aug 2017 09:44:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692247; cv=none; d=google.com; s=arc-20160816; b=DjrBKg6ydAZI84X7KnHyLHQa3YvZM48sNNNGz8a5FC+ri9ibdEVypokC6hcrnqfGHa fOJPVRyflFjCgwJY/5QQV5cLk6t/N0Na8DTCSLxpecXMVW+pFWWuh5G8GNVXvQ0qyuun C7Z1aF/F6RvfWBUm4s9qViBMhriac83Wk43dRTimKg1Dd2hweJgFL/XvAW5R7Gr9on48 dW7MFA629Wv88TOXuWA7H05skfCFWdIVXEf5T4VXfJCI0RWzRjmhIt3fHtmuQPPPM1n0 DdlGtM3JyZM1ZuIRrU1THl+BX2s0UUtl8Zm60uDrEC/pB4OCBi0iolBiW73XZPBK3TBY ffBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=bDtLgHuN1uARvu8/XUeKUmQoJ3+0PqDF3HbngR8y97A=; b=0rfVINjUnuWrEHIUQ5pebB+ohNGda5GeJCRNcdt6F4G9CiEpt0IH/3umZD7pGNbbFt K3oARvYtXFknu2E+DJxCidPOCTs/3dfV7SOop4lfrVsVPupFnBS3hZD46NF0bl4t2arA fHNrTla+Lq8SCHkXD2NwxtLzouGaMGhW19R3edHyezH30RPafpMhFnffnUA0XNpTcnkA 1hfM5dXlNDBoLfMHzV9nzad/bhQ9fHFdHsQbJJXslXBUhEnCqRnJUkd4yZu7FRFj39h3 AoyeNf6QLkhB2uBSnJYmNNhwTFrcSTuaGgOm2XC3njcaQlQFcZb2yUTd82Uma76v82US odtg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 199si3647411wmy.108.2017.08.02.09.44.07 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkh-0003zO-EN; Wed, 02 Aug 2017 17:44:07 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 10/15] target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR Date: Wed, 2 Aug 2017 17:43:56 +0100 Message-Id: <1501692241-23310-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> For M profile the XPSR is a similar but not identical format to the A profile CPSR/SPSR. (For instance the Thumb bit is in a different place.) For guest accesses we make the M profile code go through xpsr_read() and xpsr_write() which handle the different layout. However for migration we use cpsr_read() and cpsr_write() to marshal state into and out of the migration data stream. This is pretty confusing and works more by luck than anything else. Make M profile migration use xpsr_read() and xpsr_write() instead. The most complicated part of this is handling the possibility that the migration source is an older QEMU which hands us a CPSR format value; helpfully we can always tell the two apart. Signed-off-by: Peter Maydell --- target/arm/machine.c | 49 ++++++++++++++++++++++++++++++++++--------------- 1 file changed, 34 insertions(+), 15 deletions(-) -- 2.7.4 Reviewed-by: Richard Henderson diff --git a/target/arm/machine.c b/target/arm/machine.c index 2fb4b76..3193b00 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -217,21 +217,37 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size, uint32_t val = qemu_get_be32(f); if (arm_feature(env, ARM_FEATURE_M)) { - /* If the I or F bits are set then this is a migration from - * an old QEMU which still stored the M profile FAULTMASK - * and PRIMASK in env->daif. Set v7m.faultmask and v7m.primask - * accordingly, and then clear the bits so they don't confuse - * cpsr_write(). For a new QEMU, the bits here will always be - * clear, and the data is transferred using the - * vmstate_m_faultmask_primask subsection. - */ - if (val & CPSR_F) { - env->v7m.faultmask = 1; - } - if (val & CPSR_I) { - env->v7m.primask = 1; + if (val & XPSR_EXCP) { + /* This is a CPSR format value from an older QEMU. (We can tell + * because values transferred in XPSR format always have zero + * for the EXCP field, and CPSR format will always have bit 4 + * set in CPSR_M.) Rearrange it into XPSR format. The significant + * differences are that the T bit is not in the same place, the + * primask/faultmask info may be in the CPSR I and F bits, and + * we do not want the mode bits. + */ + uint32_t newval = val; + + newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); + if (val & CPSR_T) { + newval |= XPSR_T; + } + /* If the I or F bits are set then this is a migration from + * an old QEMU which still stored the M profile FAULTMASK + * and PRIMASK in env->daif. For a new QEMU, the data is + * transferred using the vmstate_m_faultmask_primask subsection. + */ + if (val & CPSR_F) { + env->v7m.faultmask = 1; + } + if (val & CPSR_I) { + env->v7m.primask = 1; + } + val = newval; } - val &= ~(CPSR_F | CPSR_I); + /* Ignore the low bits, they are handled by vmstate_m. */ + xpsr_write(env, val, ~XPSR_EXCP); + return 0; } env->aarch64 = ((val & PSTATE_nRW) == 0); @@ -252,7 +268,10 @@ static int put_cpsr(QEMUFile *f, void *opaque, size_t size, CPUARMState *env = &cpu->env; uint32_t val; - if (is_a64(env)) { + if (arm_feature(env, ARM_FEATURE_M)) { + /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */ + val = xpsr_read(env) & ~XPSR_EXCP; + } else if (is_a64(env)) { val = pstate_read(env); } else { val = cpsr_read(env); From patchwork Wed Aug 2 16:43:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109256 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003394qge; Wed, 2 Aug 2017 09:44:08 -0700 (PDT) X-Received: by 10.223.145.163 with SMTP id 32mr20570361wri.224.1501692248368; Wed, 02 Aug 2017 09:44:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692248; cv=none; d=google.com; s=arc-20160816; b=H82geNryMqmlhMSi5TJHHw5yZBz93+39dkXejwUdTWVGAFSd9Ccrn2VBrTstwPkLGs evzR92bwnW3OQFTrhRF9tGbGN7B9t8SUUPgluS25hS9pCkICkCbkmahTmN6dIV4yHlWy VQScVjr9tjjMDw6pfYA++NhgpzLfnzu500RofArrLOCADdEgeWca8CqXasJmlTip+XUS FBRTHx/Mr4iBgpYwaAZWTK/lNdMnU4Unspm6HNxQptTVDmNIJyfJFK2KN2HYRUI6ujqN nXwATJMNvsv2ytAZJUu4Uah6Q37kIIATw+1Jwa6Wcp+b9XtkXjzr1MCJ6eQXEBvHB8Mt bp+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=jdN+bY9wsxrm6bqr7oVJALqDb/w5x64kVPuLVrhkvpI=; b=oy4Y04jx5O4ZzcSw01RyaKS3rxn9vc39PNURaU7nwWatltlCrCQQMgRO7XpqFHLhi2 YLGEPAk/tdR1UxXJ13Tg53xi3TK6liMKC0uBcfOR5dYZPvRTlVE0tJZk0ulGhBIgjzhB fof00/TKklhCusJASHdUS1ABOLz5o0gUP9M4Xcy0XbGtBv9mUUGe6OrgCeXC7PVmp8xI YyaYbRK9NtSfG/0THCu/xAObNalb8NWpPqOhu7Q7Nr96vxM0EwAOCKtaXhQaY7+sQRUi JKJeALSNf0+z8MnyLVXv0HQ6xuVDyk9PMK9jqxt7giclZ4M3KfRHn6vHVCKwGbuPIdnl AA3Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id b4si27150460wrf.401.2017.08.02.09.44.08 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkh-0003zm-U3; Wed, 02 Aug 2017 17:44:07 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 11/15] target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR Date: Wed, 2 Aug 2017 17:43:57 +0100 Message-Id: <1501692241-23310-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> Make the arm_cpu_dump_state() debug logging handle the M-profile XPSR rather than assuming it's an A-profile CPSR. On M profile the PSR line of a register dump will now look like this: XPSR=41000000 -Z-- T priv-thread Signed-off-by: Peter Maydell --- target/arm/translate.c | 58 ++++++++++++++++++++++++++++++++++---------------- 1 file changed, 40 insertions(+), 18 deletions(-) -- 2.7.4 Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson diff --git a/target/arm/translate.c b/target/arm/translate.c index 3c14cb0..e52a6d7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12215,8 +12215,6 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; int i; - uint32_t psr; - const char *ns_status; if (is_a64(env)) { aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags); @@ -12230,24 +12228,48 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, else cpu_fprintf(f, " "); } - psr = cpsr_read(env); - if (arm_feature(env, ARM_FEATURE_EL3) && - (psr & CPSR_M) != ARM_CPU_MODE_MON) { - ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; + if (arm_feature(env, ARM_FEATURE_M)) { + uint32_t xpsr = xpsr_read(env); + const char *mode; + + if (xpsr & XPSR_EXCP) { + mode = "handler"; + } else { + if (env->v7m.control & R_V7M_CONTROL_NPRIV_MASK) { + mode = "unpriv-thread"; + } else { + mode = "priv-thread"; + } + } + + cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s\n", + xpsr, + xpsr & XPSR_N ? 'N' : '-', + xpsr & XPSR_Z ? 'Z' : '-', + xpsr & XPSR_C ? 'C' : '-', + xpsr & XPSR_V ? 'V' : '-', + xpsr & XPSR_T ? 'T' : 'A', + mode); } else { - ns_status = ""; - } - - cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", - psr, - psr & (1 << 31) ? 'N' : '-', - psr & (1 << 30) ? 'Z' : '-', - psr & (1 << 29) ? 'C' : '-', - psr & (1 << 28) ? 'V' : '-', - psr & CPSR_T ? 'T' : 'A', - ns_status, - cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); + uint32_t psr = cpsr_read(env); + const char *ns_status = ""; + + if (arm_feature(env, ARM_FEATURE_EL3) && + (psr & CPSR_M) != ARM_CPU_MODE_MON) { + ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; + } + + cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", + psr, + psr & CPSR_N ? 'N' : '-', + psr & CPSR_Z ? 'Z' : '-', + psr & CPSR_C ? 'C' : '-', + psr & CPSR_V ? 'V' : '-', + psr & CPSR_T ? 'T' : 'A', + ns_status, + cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); + } if (flags & CPU_DUMP_FPU) { int numvfpregs = 0; From patchwork Wed Aug 2 16:43:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109257 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003412qge; Wed, 2 Aug 2017 09:44:08 -0700 (PDT) X-Received: by 10.223.163.158 with SMTP id l30mr20898336wrb.203.1501692248885; Wed, 02 Aug 2017 09:44:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692248; cv=none; d=google.com; s=arc-20160816; b=ubXXNaX0YWv+yOkeKUvoAFSIdFUblW6h6CgQeTbyfOf7hxHI4Unu9LWxMqpEIO0MBg z64OFKJXfIpAZkIbaqviOG7xMLXHm5iMCX4tKSvVlPx04F1gwxVEZbxovuI/J6esEJu1 Ss8Mnoy3G50CheXyDA2yQ5wWebZHEwiyKt/8Jl0aCRq1EXKxsXMXRIhaBT65olK2nsgh j2hTj/Fp6RU4++5CJc57pv3OztWdnr1ZBYH7skZIXHKVIMTEbuo68Ufc6axTyhxQ0w/D tQYdGojVj+8RmDGH1mQmh7/FVUFfSRWfEwQX6/gpaFjWCUb1YUTz4auWd4rdMWB+qOVH vXcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=MFhLl6TJBr4rJacH/vjWxiNoW+ugx7pQnJ7K7jiklSI=; b=MCHDz4aaSLui36qukQ3H0HwK0D25Q9svy7P6bXaz+iyu8YuOi2Q3D4+u7+VUeKPrhR n0ykmx2p4/NugUXdaa5W01m5+sQfQ5JNj9K/uDUZub5hSB+qzgPEbOm95hkOL51Bv3BM O/12XoN0BoWi2U5ew4mZo0bEucHLAcp9itpD+WKnmKjUZ1lDeFUpXRjNjE+fCS2sZv3X 8pDZe47w+G2SwCdoxYw6oUjzCN8UASUb5mQ5LT502Kidvd01j6jZrhzHS64VZNEYatyD VAuxv6DuthkRJLK+Rechjc2j5op1eMVc06wCjbv57CYL9vBt6z3RmgHB3I0RvKS+pZDN cYKg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id y3si11292917wra.421.2017.08.02.09.44.08 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwki-00040L-D5; Wed, 02 Aug 2017 17:44:08 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 12/15] target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed Date: Wed, 2 Aug 2017 17:43:58 +0100 Message-Id: <1501692241-23310-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> Move the code in arm_v7m_cpu_do_interrupt() that calculates the magic LR value down to when we're actually going to use it. Having the calculation and use so far apart makes the code a little harder to understand than it needs to be. Signed-off-by: Peter Maydell --- target/arm/helper.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) -- 2.7.4 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index b64ddb1..0ecc8f1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6311,13 +6311,6 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) arm_log_exception(cs->exception_index); - lr = 0xfffffff1; - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { - lr |= 4; - } - if (env->v7m.exception == 0) - lr |= 8; - /* For exceptions we just mark as pending on the NVIC, and let that handle it. */ switch (cs->exception_index) { @@ -6408,6 +6401,14 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) return; /* Never happens. Keep compiler happy. */ } + lr = 0xfffffff1; + if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { + lr |= 4; + } + if (env->v7m.exception == 0) { + lr |= 8; + } + v7m_push_stack(cpu); v7m_exception_taken(cpu, lr); qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception); From patchwork Wed Aug 2 16:43:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109260 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003480qge; Wed, 2 Aug 2017 09:44:12 -0700 (PDT) X-Received: by 10.98.72.90 with SMTP id v87mr23842812pfa.337.1501692252805; Wed, 02 Aug 2017 09:44:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692252; cv=none; d=google.com; s=arc-20160816; b=0B2Gl2GQM3Mven6Y0YLJl96FPUj2dI1Ew5Hws6Gnxhsgo8e/XbZ8IImXJAwwN5O27R JthRMrYIhuxkPoYD99htLPu3tbNsizd18LCxDN/bF4V4OFe7I5BS0ThJ12HJPcExJfQq 7VO/IYIIHzN8yQgXLDnaajwKcklkI2gkK5UFk743YpWZq7iHuuojmGQxeGYtykpVfqKp IK22iHeG8xxudnYiBzr3hyQFrc6PwQZ/4NDIxJkEoMAr6wVS9OsmQjM7JR9v6NL3tDzz BW62IoJEI5KNKGfjb8YSGZCC8DALRpaCRPYkvgNytspcMRksSTMvjqVJ65q58PjfJNAP FY2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=3ZTuLbp07JH9BmNpmUIy+gxCRsW5I5x6DtvxcxNVH8M=; b=OquIaRi5B0ahO8+p3xhnP1nRm1k5FvqHEgN+au0NRcJDIOuaMSa7lXqjbGCRfVJjH9 bAVZEYFjQcY8Q/6a+b3QK5gwZUksCmLpD4S+u3zJafIDCxk5tpI/3zdSM+bCK1SWBXUC CpXSdaOEVmeUYnlYh4RFgVKPETux7cHxRi2CUEkac2NJYByBeXUXi6UQLSVm7RVoujwQ Aqdg7DCoXz1H7m2PcTGaC6AZLYuKC9lw0xI3xS/0eYWHVXrXm7w28Wm953GJRk2MUoEz rRBPBUqdZ6hque+EL/repjfCmxIgtSbZASouPyOfbdwFfkOHfScpQSvzA83K4zeY7iOy ICMA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id r3si2210601pgf.128.2017.08.02.09.44.12 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwki-00040j-RZ; Wed, 02 Aug 2017 17:44:08 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 13/15] target/arm: Create and use new function arm_v7m_is_handler_mode() Date: Wed, 2 Aug 2017 17:43:59 +0100 Message-Id: <1501692241-23310-14-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> Add a utility function for testing whether the CPU is in Handler mode; this is just a check whether v7m.exception is non-zero, but we do it in several places and it makes the code a bit easier to read to not have to mentally figure out what the test is testing. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 10 ++++++++-- target/arm/helper.c | 8 ++++---- 2 files changed, 12 insertions(+), 6 deletions(-) -- 2.7.4 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index da90b7a..a3b4b78 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1630,13 +1630,19 @@ static inline int arm_highest_el(CPUARMState *env) return 1; } +/* Return true if a v7M CPU is in Handler mode */ +static inline bool arm_v7m_is_handler_mode(CPUARMState *env) +{ + return env->v7m.exception != 0; +} + /* Return the current Exception Level (as per ARMv8; note that this differs * from the ARMv7 Privilege Level). */ static inline int arm_current_el(CPUARMState *env) { if (arm_feature(env, ARM_FEATURE_M)) { - return !((env->v7m.exception == 0) && (env->v7m.control & 1)); + return arm_v7m_is_handler_mode(env) || !(env->v7m.control & 1); } if (is_a64(env)) { @@ -2636,7 +2642,7 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; - if (env->v7m.exception != 0) { + if (arm_v7m_is_handler_mode(env)) { *flags |= ARM_TBFLAG_HANDLER_MASK; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ecc8f1..7920153 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6147,7 +6147,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * that jumps to magic addresses don't have magic behaviour unless * we're in Handler mode (compare pseudocode BXWritePC()). */ - assert(env->v7m.exception != 0); + assert(arm_v7m_is_handler_mode(env)); /* In the spec pseudocode ExceptionReturn() is called directly * from BXWritePC() and gets the full target PC value including @@ -6254,7 +6254,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * resuming in Thread mode. If that doesn't match what the * exception return type specified then this is a UsageFault. */ - if (return_to_handler == (env->v7m.exception == 0)) { + if (return_to_handler != arm_v7m_is_handler_mode(env)) { /* Take an INVPC UsageFault by pushing the stack again. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK; @@ -6405,7 +6405,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { lr |= 4; } - if (env->v7m.exception == 0) { + if (!arm_v7m_is_handler_mode(env)) { lr |= 8; } @@ -8798,7 +8798,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) * switch_v7m_sp() deals with updating the SPSEL bit in * env->v7m.control, so we only need update the others. */ - if (env->v7m.exception == 0) { + if (!arm_v7m_is_handler_mode(env)) { switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); } env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK; From patchwork Wed Aug 2 16:44:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109258 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003425qge; Wed, 2 Aug 2017 09:44:09 -0700 (PDT) X-Received: by 10.28.211.193 with SMTP id k184mr4159946wmg.21.1501692249729; Wed, 02 Aug 2017 09:44:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692249; cv=none; d=google.com; s=arc-20160816; b=uy6h46S5ubniXKuA1/p5PBXqRkjDrFfG7v8U+n+i2wTX+QvKbWi1kBp0fnQCezYZ1s VFZdov3MsbqogMjORAeHsxymgARhDQdMBiMN8diec7VJWPRhmlCBF54K3huIYbhKO2Sh RffQwWdIffV8V1bm8/d6aIftM777F2goEBS9ENLvBFvuYlgtbW2Gg0G6BU69OkwI12nU kmsLZcMarSqUgkw6ebLiuBcic5gUkBT0b2HiisngtFoCyiPZzFh6SIr1v5wvt5R3hlWP ICnV+5WWPDWRF5+JWjr4QS/9f3YxooozijVGqMzi0Blr+MBP0INvQx+egFexwTg/Ydc+ q//w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=suVInd7KYDrTK7MIgJprQgQp7uQFFYRMUUDoE1rTEnU=; b=MPyGP7wLwcmwHQCdUqAozibHrT1fWAtTvvXnjnSjlgIq8OQAX9XqPS89sFQBJrmwUh QKBkd8Kup5n6MLVAO+ZhIhjqIIno1IbdfMDxJReVPUDOLYWOvfBjamXydHFHHr6z1/7k wN2VLJgNrLokxmnVvkNLSRB+KgrnFxqoaoQFkl9sZh2UNUrVXo5LXlX6aaSJLJ+g3KHS /6o75y+g+UyLBZhnZZWbkFQWYBBpzO1n0KW/p5rObwd3fmfJF4JgjT+VbFAui5rbwhwv SeMsniAfwiHvpkKfy5UkZIB8yNaGlElpDSukefj9Va/w1sMyvu6555okOcAVgSzekB1b XuKg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id g14si3495077wme.258.2017.08.02.09.44.09 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkj-000417-AT; Wed, 02 Aug 2017 17:44:09 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 14/15] armv7m_nvic.h: Move from include/hw/arm to include/hw/intc Date: Wed, 2 Aug 2017 17:44:00 +0100 Message-Id: <1501692241-23310-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> The armv7m_nvic.h header file was accidentally placed in include/hw/arm; move it to include/hw/intc to match where its corresponding .c file lives. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 2 +- include/hw/arm/armv7m.h | 2 +- include/hw/{arm => intc}/armv7m_nvic.h | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename include/hw/{arm => intc}/armv7m_nvic.h (100%) -- 2.7.4 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 343bc16..5a18025 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -17,7 +17,7 @@ #include "hw/sysbus.h" #include "qemu/timer.h" #include "hw/arm/arm.h" -#include "hw/arm/armv7m_nvic.h" +#include "hw/intc/armv7m_nvic.h" #include "target/arm/cpu.h" #include "exec/exec-all.h" #include "qemu/log.h" diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index a9b3f2a..10eb058 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -11,7 +11,7 @@ #define HW_ARM_ARMV7M_H #include "hw/sysbus.h" -#include "hw/arm/armv7m_nvic.h" +#include "hw/intc/armv7m_nvic.h" #define TYPE_BITBAND "ARM,bitband-memory" #define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND) diff --git a/include/hw/arm/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h similarity index 100% rename from include/hw/arm/armv7m_nvic.h rename to include/hw/intc/armv7m_nvic.h From patchwork Wed Aug 2 16:44:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 109259 Delivered-To: patches@linaro.org Received: by 10.140.101.6 with SMTP id t6csp3003433qge; Wed, 2 Aug 2017 09:44:10 -0700 (PDT) X-Received: by 10.223.134.213 with SMTP id 21mr3353351wry.104.1501692250236; Wed, 02 Aug 2017 09:44:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501692250; cv=none; d=google.com; s=arc-20160816; b=GJ+zK/8/T0FrgHuQdUTqc4pHmViZ0RhvAGtDHdgTq5Ccr8RKUeQNhoV+/7wNhL6g0L Wxi1iYbn/T5PSWdrFUXugFON9xJHMmRdD6oYkZPXDddAklyEggaoYN6yn80ch7fpLeUu Lzls21kYiodu8+HQljJGYOJdWOpvseNoVbTGmTaHgpTHxsTtk5hcVFSEbcgeBCRQVPuF 3e6EO9HcwQKRxvHGiGMe7iLoKlMcOfOKgwXHN+km5lPgBWQlXTay/Thi8p5hhCXRymml pw1lil39uQ6xBu82oV3McIvJAyV7zFyMjSqkUkNe3lApsmZ+cBgBvH+2G0yUvrc8w28Z tXdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=qZSSs+hqqz022T2ZJ22GWesj3VpaTdtIyweROquVPrg=; b=BtxafXanpvTWBBt7TPmcvX+zCBCOiJThBxodNlm7DcUrbJl4RB6+DJ8Ye3/rheF87c rlRMdOxKTU27VSoDPMrJnQ2m1v2h6ti3xzQYrgHnzkIhzHqIBVsHfWvlSd70zE+WNAlz jm8fjfQYEnfRDRGZYxN6kYn4i17ZpEy7NfXOkJ7bySGsdeX5bJAyr/IqK6WbFKWKww8b n5wWmfIrvHbrRYpjxhE89iiLt9w7T7NKqq7zccS0Cye9uAhchndtLa5xJbHPtPLRjy+z nhvCTZSIuFzrKc5yBgZBIGMgJ0CwMmSaAfUmjK+Phiemo5AV0+Y0P0PJuHD0mhSpkI6s 88/A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id j11si21891257wrb.98.2017.08.02.09.44.10 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Aug 2017 09:44:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkj-00041K-Op; Wed, 02 Aug 2017 17:44:09 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 15/15] nvic: Implement "user accesses BusFault" SCS region behaviour Date: Wed, 2 Aug 2017 17:44:01 +0100 Message-Id: <1501692241-23310-16-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> The ARMv7M architecture specifies that most of the addresses in the PPB region (which includes the NVIC, systick and system registers) are not accessible to unprivileged accesses, which should BusFault with a few exceptions: * the STIR is configurably user-accessible * the ITM (which we don't implement at all) is always user-accessible Implement this by switching the register access functions to the _with_attrs scheme that lets us distinguish user mode accesses. This allows us to pull the handling of the CCR.USERSETMPEND flag up to the level where we can make it generate a BusFault as it should for non-permitted accesses. Note that until the core ARM CPU code implements turning MEMTX_ERROR into a BusFault the registers will continue to act as RAZ/WI to user accesses. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 58 ++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 41 insertions(+), 17 deletions(-) -- 2.7.4 Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 5a18025..bbfe2d5 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -733,11 +733,8 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) } case 0xf00: /* Software Triggered Interrupt Register */ { - /* user mode can only write to STIR if CCR.USERSETMPEND permits it */ int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ; - if (excnum < s->num_irq && - (arm_current_el(&cpu->env) || - (cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK))) { + if (excnum < s->num_irq) { armv7m_nvic_set_pending(s, excnum); } break; @@ -748,14 +745,32 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) } } -static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr, - unsigned size) +static bool nvic_user_access_ok(NVICState *s, hwaddr offset) +{ + /* Return true if unprivileged access to this register is permitted. */ + switch (offset) { + case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */ + return s->cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK; + default: + /* All other user accesses cause a BusFault unconditionally */ + return false; + } +} + +static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) { NVICState *s = (NVICState *)opaque; uint32_t offset = addr; unsigned i, startvec, end; uint32_t val; + if (attrs.user && !nvic_user_access_ok(s, addr)) { + /* Generate BusFault for unprivileged accesses */ + return MEMTX_ERROR; + } + switch (offset) { /* reads of set and clear both return the status */ case 0x100 ... 0x13f: /* NVIC Set enable */ @@ -826,11 +841,13 @@ static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr, } trace_nvic_sysreg_read(addr, val, size); - return val; + *data = val; + return MEMTX_OK; } -static void nvic_sysreg_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) +static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) { NVICState *s = (NVICState *)opaque; uint32_t offset = addr; @@ -839,6 +856,11 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr, trace_nvic_sysreg_write(addr, value, size); + if (attrs.user && !nvic_user_access_ok(s, addr)) { + /* Generate BusFault for unprivileged accesses */ + return MEMTX_ERROR; + } + switch (offset) { case 0x100 ... 0x13f: /* NVIC Set enable */ offset += 0x80; @@ -853,7 +875,7 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr, } } nvic_irq_update(s); - return; + return MEMTX_OK; case 0x200 ... 0x23f: /* NVIC Set pend */ /* the special logic in armv7m_nvic_set_pending() * is not needed since IRQs are never escalated @@ -870,9 +892,9 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr, } } nvic_irq_update(s); - return; + return MEMTX_OK; case 0x300 ... 0x33f: /* NVIC Active */ - return; /* R/O */ + return MEMTX_OK; /* R/O */ case 0x400 ... 0x5ef: /* NVIC Priority */ startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ @@ -880,26 +902,28 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr, set_prio(s, startvec + i, (value >> (i * 8)) & 0xff); } nvic_irq_update(s); - return; + return MEMTX_OK; case 0xd18 ... 0xd23: /* System Handler Priority. */ for (i = 0; i < size; i++) { unsigned hdlidx = (offset - 0xd14) + i; set_prio(s, hdlidx, (value >> (i * 8)) & 0xff); } nvic_irq_update(s); - return; + return MEMTX_OK; } if (size == 4) { nvic_writel(s, offset, value); - return; + return MEMTX_OK; } qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad write of size %d at offset 0x%x\n", size, offset); + /* This is UNPREDICTABLE; treat as RAZ/WI */ + return MEMTX_OK; } static const MemoryRegionOps nvic_sysreg_ops = { - .read = nvic_sysreg_read, - .write = nvic_sysreg_write, + .read_with_attrs = nvic_sysreg_read, + .write_with_attrs = nvic_sysreg_write, .endianness = DEVICE_NATIVE_ENDIAN, };