From patchwork Fri Aug 11 18:02:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 109907 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1250081qge; Fri, 11 Aug 2017 11:05:23 -0700 (PDT) X-Received: by 10.36.138.196 with SMTP id v187mr11450224itd.12.1502474723191; Fri, 11 Aug 2017 11:05:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502474723; cv=none; d=google.com; s=arc-20160816; b=QLlrwTLv3CGFrb2RdnoC1GbStlAx1YXTiZfS4/UFDHaWNztgD38D1Ce7W/Kfl0aYK/ 1ogpE7DSguVZfdXFWBoAlaSmD/QWLaHrBFP9fNi4k1MzwT1iWQDwe1Z3ZySmQuRN/Yim G9zns2bFintqU3EKpTnzAGiDwgXrqpt92wBtGZ+Hg8hqyRFf5GyKi7AGX9I0nKbXMvXp vlyLNwluvI5TGDYZ1Fvdw/WGDEeYDtTdp1fffIXXY897+8iMvuY6xqLbUnzQL8wdXTar NXe5hf+Oeg/ohR31lq2TDFotDMhhVy+h2jorFChXbHwmzdK5/BQpsLIMxE8SeZLdEJSA P9FQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-unsubscribe:list-id:precedence:subject:cc :mime-version:references:in-reply-to:message-id:date:to:from :arc-authentication-results; bh=9UhDBwfUgNQRtBmXsOrxiuRFFJ7sRYM9m4QgIzpPc5c=; b=0QT10oGUuYpZUZjsA27rEOj0VafZS7ykCV0H0qy6di8LUDwo6ZWP6bvvdTtC1yzZaQ G2+WFR4eeIMgk3n9hSFLsqw+RXKSHOUrvMON5h2XIw/BApQW0Odft04Ovg9BIsSTt1v/ WCdsJV2c1ZxdEOJ/QJKi4+cfkD3H38buZ09nX8YCnLhCsZO+J+6wpxViRyZavtdPqiZr Jdvg1XfNY7kJV+XqeEfPLFbr/EixDpGtZNYt9HSLU1bQkvQDuyYVqMg+d05OuYOIk21k PdooRk3a6BQ06heIyNFyq1OWttVLpOVa0o9x2QrKo+KBA+tDm9/0ZPLQ3g+G2qVSUPtT RZMQ== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id d125si1719066itg.94.2017.08.11.11.05.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Aug 2017 11:05:23 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dgEH8-0002Y9-JP; Fri, 11 Aug 2017 18:03:10 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dgEH6-0002Xm-ST for xen-devel@lists.xen.org; Fri, 11 Aug 2017 18:03:08 +0000 Received: from [85.158.137.68] by server-3.bemta-3.messagelabs.com id D6/C9-01987-C51FD895; Fri, 11 Aug 2017 18:03:08 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRWlGSWpSXmKPExsVysyfVTTf6Y2+ kwdmnMhZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa0bXpnmsBXc4K7Zv+cPYwDiTo4uRi0NIYDOj xIWe7UxdjJxAzmlGic9b2UFsNgFNiTufP4HFRQSkJa59vswI0sAs8IFJYuGTJ2AJYQFPibn9L WA2i4CqxMNfnaxdjBwcvAIWEisn+4CEJQTkJXa1XQQLcwpYSsy5LAuxykJi+791bCA2r4CgxM mZT1hASpgF1CXWzxMCCTMDdTZvnc08gZFvFpKqWQhVs5BULWBkXsWoUZxaVJZapGtoopdUlJm eUZKbmJmja2hgrJebWlycmJ6ak5hUrJecn7uJERhoDECwg3HFds9DjJIcTEqivAk+vZFCfEn5 KZUZicUZ8UWlOanFhxhlODiUJHifvAfKCRalpqdWpGXmAEMeJi3BwaMkwivxASjNW1yQmFucm Q6ROsWoy/Fqwv9vTEIsefl5qVLivDNBZgiAFGWU5sGNgMXfJUZZKWFeRqCjhHgKUotyM0tQ5V 8xinMwKgnz3gaZwpOZVwK36RXQEUxAR/T5gB1RkoiQkmpg3Gty0sLizpbGd+IXNQ0WX4tYyLu R55NLv/zWtUr77e4lPWBo1vm6be6hf/f2z5pZZO24zleXf2/V3e/ms7sNPG/lzT6+zfaAxt+E nf5bC72T/0049O7BrJLFd36pmazLl/gfvdakuOZUsndQGpezr0Pj6x9CDQFODvohM1hST9lvm t6xfFm5jhJLcUaioRZzUXEiAJ+/0Fe6AgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-10.tower-31.messagelabs.com!1502474586!108955581!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 1652 invoked from network); 11 Aug 2017 18:03:07 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-10.tower-31.messagelabs.com with SMTP; 11 Aug 2017 18:03:07 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A951415AD; Fri, 11 Aug 2017 11:03:06 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AEE3E3F577; Fri, 11 Aug 2017 11:03:04 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 11 Aug 2017 19:02:47 +0100 Message-Id: <20170811180257.5493-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170811180257.5493-1-julien.grall@arm.com> References: <20170811180257.5493-1-julien.grall@arm.com> MIME-Version: 1.0 Cc: sstabellini@kernel.org, Wei Liu , George Dunlap , Andrew Cooper , Ian Jackson , Tim Deegan , Julien Grall , Jan Beulich , bhupinder.thakur@linaro.org Subject: [Xen-devel] [PATCH 01/11] xen/grant_table: Include mm.h in xen/grant_table.h X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" While re-ordering the include alphabetically in arch/arm/domain.c, I got a complitation error because grant_table.h is using gfn_t before been defined: In file included from domain.c:14:0: xen/xen/include/xen/grant_table.h:153:29: error: unknown type name ‘gfn_t’ gfn_t *gfn, uint16_t *status); ^ Fix it by including xen/mm.h in it. Signed-off-by: Julien Grall Acked-by: Jan Beulich Acked-by: Wei Liu --- Cc: Andrew Cooper Cc: George Dunlap Cc: Ian Jackson Cc: Jan Beulich Cc: Konrad Rzeszutek Wilk Cc: Stefano Stabellini Cc: Tim Deegan Cc: Wei Liu --- xen/include/xen/grant_table.h | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/include/xen/grant_table.h b/xen/include/xen/grant_table.h index 4e7789968c..7913facf9f 100644 --- a/xen/include/xen/grant_table.h +++ b/xen/include/xen/grant_table.h @@ -23,6 +23,7 @@ #ifndef __XEN_GRANT_TABLE_H__ #define __XEN_GRANT_TABLE_H__ +#include #include #include #include From patchwork Fri Aug 11 18:02:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 109911 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1250149qge; Fri, 11 Aug 2017 11:05:26 -0700 (PDT) X-Received: by 10.36.149.198 with SMTP id m189mr18254itd.104.1502474726770; Fri, 11 Aug 2017 11:05:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502474726; cv=none; d=google.com; s=arc-20160816; b=FlhwViZ+zeVp2UjEzPqFoyTXfe+Zss/novKqao1CeAm4QA5FNPuGOyvWTOX8zzW6So 7xQyRyEJkZFdX5e0meBRZGC/HvIONcwcW0jMpXoHFvx35zESjSBizOTg5qBzlJNdp4NX S1O5h6FNvQ+IsOdf0HI1PwiGzUIKKXfunsWQun1UI/ombZTzVB4rKyUt290PhQnoCpzO Iw/Vw5wuWa7GyunstEaOo8cEyHSRAqIl6L8K4YbGgMOZK1AsuMVPMusPpEvng+KZcnQh spFFO/Tmvx08+j8q9WescuYNdsRTdeJlw0PdvU7vH7PuMtTm04sAH/Z0iIvIp6uxvMHA d87Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=uu/lahf8rE31lQLgxnVnd/WIiI7NZ2RPocanG4TR2rU=; b=j4BivEf3GSejQztcW+pJ1l00f3eIUynHH01ZHw7AjakJ9uSYDxDNnezv1Olr9Nn/Oc MyMJUN74uDXHt6gL3EDrYmvpeYskjiZpJDFLfWlWl7IpsrnhOERjk1x0bun1d5HJ635I dVrSJ9FZEt7eA/IEj6b66Le1kYvl8eR/0uy3wUYSneb6btebIzhWyxxxftdtpSSWS9MM qU98U2i2yqCzVpCHGmgeMiji8eIYxfS2Um4wMlzEIY9PSmCaAV38XHF6AYgPpEXi9k70 tIovzYX/8W5D65rtiVGCU9ofGTKFg8Le2a73VppZtu1QzUSQ8/BHmOBWwCijtdp5MZNM JmEg== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id p76si1806627itp.183.2017.08.11.11.05.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Aug 2017 11:05:26 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dgEH8-0002YZ-Th; Fri, 11 Aug 2017 18:03:10 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dgEH7-0002Xx-VV for xen-devel@lists.xen.org; Fri, 11 Aug 2017 18:03:10 +0000 Received: from [85.158.137.68] by server-2.bemta-3.messagelabs.com id D5/F9-22472-D51FD895; Fri, 11 Aug 2017 18:03:09 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrALMWRWlGSWpSXmKPExsVysyfVTTfmY2+ kwbfzahZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8bjKWtYCrZyVfzu/crYwDiTs4uRi0NIYDOj xOdLN1i6GDmBnNOMEp+6TUBsNgFNiTufPzGB2CIC0hLXPl9mBLGZBeIk3i9qBKsXFvCRmPGwn b2LkYODRUBVYvOPYJAwr4CFROejM2CtEgLyErvaLrKClHAKWErMuSwLsclCYvu/dWwTGLkXMD KsYtQoTi0qSy3SNTLQSyrKTM8oyU3MzNE1NDDWy00tLk5MT81JTCrWS87P3cQI9G09AwPjDsb mE36HGCU5mJREeRN8eiOF+JLyUyozEosz4otKc1KLDzHKcHAoSfCGfADKCRalpqdWpGXmAIMM Ji3BwaMkwtsHkuYtLkjMLc5Mh0idYtTleDXh/zcmIZa8/LxUKXFeHpAiAZCijNI8uBGwgL/EK CslzMvIwMAgxFOQWpSbWYIq/4pRnINRSZh3AsgUnsy8ErhNr4COYAI5wgfsiJJEhJRUA6P7vM 1/nBapbE/XWqum91nIdP6e69nsLAZeVmase6audJ6koRaw1N3KcscHw1zuJpOaGxWbpZbaSLs ZHLomkqy74PNbJ7PXTcVm6qHPJi9TK+GtP775RdsHpxeFr4uVJdvb8tb8SRdnePdSgHknd+GV LROPta2+c3b/4ajtycrdeUeZX17wv6TEUpyRaKjFXFScCACyYIdkcwIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-13.tower-31.messagelabs.com!1502474588!105078030!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 33523 invoked from network); 11 Aug 2017 18:03:08 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-13.tower-31.messagelabs.com with SMTP; 11 Aug 2017 18:03:08 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D96C7164F; Fri, 11 Aug 2017 11:03:07 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E90C73F577; Fri, 11 Aug 2017 11:03:06 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 11 Aug 2017 19:02:48 +0100 Message-Id: <20170811180257.5493-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170811180257.5493-1-julien.grall@arm.com> References: <20170811180257.5493-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 02/11] xen/arm: domain: Re-order the includes alphabetically X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/domain.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 2dc8b0ab5a..1d835d321d 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -9,6 +9,9 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#include +#include +#include #include #include #include @@ -16,24 +19,21 @@ #include #include #include -#include -#include -#include +#include +#include #include #include +#include #include -#include -#include #include -#include -#include +#include +#include #include -#include - -#include +#include +#include #include -#include + #include "vtimer.h" #include "vuart.h" From patchwork Fri Aug 11 18:02:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 109909 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1250111qge; Fri, 11 Aug 2017 11:05:25 -0700 (PDT) X-Received: by 10.107.185.134 with SMTP id j128mr14243897iof.218.1502474725211; Fri, 11 Aug 2017 11:05:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502474725; cv=none; d=google.com; s=arc-20160816; b=iIX60U0LmO0dk6+jpJWUaKYuzXxs3vWjcoPofzOxGj6/9XQKOP2t1WfTj7sW+SqVtf 8mWMQLSlny7MFoWic4EcUA8xaRVocgxNhyCfYm49YbyQ7rNRaosfv/es/Y1Jbm5+R6qY 6H3giqqrW89CpAOfpbrkx080cg7qv0GAnWjb8xSlqB3N7blS9VzrkEDh3YPpofdGTzdx 6zKRXIR/2wPewMNhrDu/JB6UD9xWPsaeKiAas6S7NUvEByLZxni+CxyhOqUN/bakrOiW 3mCPLARsflCJjezJf0hL8jTgQ971bh/lnjqOQj/5NEVS9oUhhlohOQD6QXi3Ljm7EU2q dg+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=KsznI60fsDoSoBcDlr/9InJOmLWBXxuopLG2Sokua7M=; b=vKQhe8qWbTJ7YnsCzdoDHYPmBpTU6snP1LT0PK5lLzMT4zFnUj4/i0j4NH31Io1waN k6yV8o5tBvDOJnu8qlxsmPW5HGTuTtjduB5UiQ7AYns/s7ekYh9TfUzwkseQr6DrJeAQ /+ZehH31m60ljTlDjx+xFqNuu3ihzmeEmtDrAOYGdwUzWRu2NoLCk4/xSZmS7YXGwgjo zW/gqfaUTe7YIrdCiyTs0Qx4R8id9J9vDyjNVy7C8+ItKDnSoh7B3EmI5onal9H+QM/S dQmJs2jj78ViY/550UYTa6sv4H1WvEn1WoB5Me0IINuC5ew6UZoj+1xRYP3aWQxgrBat DLdw== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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banners=-,-,- X-VirusChecked: Checked Received: (qmail 24802 invoked from network); 11 Aug 2017 18:03:09 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-15.tower-21.messagelabs.com with SMTP; 11 Aug 2017 18:03:09 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1593F1650; Fri, 11 Aug 2017 11:03:09 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 256543F577; Fri, 11 Aug 2017 11:03:08 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 11 Aug 2017 19:02:49 +0100 Message-Id: <20170811180257.5493-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170811180257.5493-1-julien.grall@arm.com> References: <20170811180257.5493-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 03/11] xen/arm: traps: Re-order the includes alphabetically X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Signed-off-by: Julien Grall Acked-by: Bhupinder Thakur --- xen/arch/arm/traps.c | 42 ++++++++++++++++++++++-------------------- 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index c07999b518..ca9bef712c 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -16,41 +16,43 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include -#include +#include +#include +#include #include +#include +#include #include #include +#include #include -#include -#include -#include -#include #include +#include +#include +#include +#include +#include #include -#include -#include + #include #include -#include -#include -#include + +#include #include -#include -#include +#include #include +#include +#include #include +#include +#include #include +#include +#include +#include #include "decode.h" #include "vtimer.h" -#include -#include -#include -#include /* The base of the stack must always be double-word aligned, which means * that both the kernel half of struct cpu_user_regs (which is pushed in From patchwork Fri Aug 11 18:02:50 2017 Content-Type: text/plain; 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banners=-,-,- X-VirusChecked: Checked Received: (qmail 59717 invoked from network); 11 Aug 2017 18:03:10 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-10.tower-206.messagelabs.com with SMTP; 11 Aug 2017 18:03:10 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 45A5E164F; Fri, 11 Aug 2017 11:03:10 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 55A433F577; Fri, 11 Aug 2017 11:03:09 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 11 Aug 2017 19:02:50 +0100 Message-Id: <20170811180257.5493-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170811180257.5493-1-julien.grall@arm.com> References: <20170811180257.5493-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 04/11] xen/arm: vgic-v3: Re-order the includes alphabetically X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/vgic-v3.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 48c7682671..cbeac28b28 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -19,16 +19,17 @@ */ #include -#include #include -#include #include +#include #include +#include #include + #include -#include #include #include +#include #include #include #include From patchwork Fri Aug 11 18:02:51 2017 Content-Type: text/plain; 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banners=-,-,- X-VirusChecked: Checked Received: (qmail 24811 invoked from network); 11 Aug 2017 18:03:12 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-5.tower-31.messagelabs.com with SMTP; 11 Aug 2017 18:03:12 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 75D8C165C; Fri, 11 Aug 2017 11:03:11 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 85CB73F577; Fri, 11 Aug 2017 11:03:10 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 11 Aug 2017 19:02:51 +0100 Message-Id: <20170811180257.5493-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170811180257.5493-1-julien.grall@arm.com> References: <20170811180257.5493-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 05/11] xen/arm: vtimer: Re-order the includes alphabetically X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/vtimer.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index 32ac1279ae..9c7e8f441c 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -18,16 +18,17 @@ */ #include -#include -#include #include +#include +#include + #include +#include #include +#include #include -#include #include #include -#include /* * Check if regs is allowed access, user_gate is tail end of a From patchwork Fri Aug 11 18:02:52 2017 Content-Type: text/plain; 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[192.237.175.120]) by mx.google.com with ESMTPS id 82si1493206iof.271.2017.08.11.11.05.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Aug 2017 11:05:28 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dgEHD-0002a5-OJ; Fri, 11 Aug 2017 18:03:15 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dgEHC-0002ZN-IM for xen-devel@lists.xen.org; Fri, 11 Aug 2017 18:03:14 +0000 Received: from [85.158.139.211] by server-1.bemta-5.messagelabs.com id 14/46-01993-161FD895; Fri, 11 Aug 2017 18:03:13 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrALMWRWlGSWpSXmKPExsVysyfVTTfxY2+ kQUuLjMWSj4tZHBg9ju7+zRTAGMWamZeUX5HAmrHoVm7BK66Khnv3WBoYJ3F2MXJxCAlsZpRo OfiVFcI5zSjx7NRCti5GTg42AU2JO58/MYHYIgLSEtc+X2YEsZkF4iTeL2pkAbGFBYIknl6aD 1bDIqAq0fzvPTuIzStgIXHs80uwGgkBeYldbReBFnBwcApYSsy5LAsSFgIq2f5vHdsERu4FjA yrGNWLU4vKUot0zfWSijLTM0pyEzNzdA0NTPVyU4uLE9NTcxKTivWS83M3MQJ9ywAEOxiPTXY +xCjJwaQkypvg0xspxJeUn1KZkVicEV9UmpNafIhRhoNDSYI35ANQTrAoNT21Ii0zBxhkMGkJ Dh4lEV4JkDRvcUFibnFmOkTqFKMux6sJ/78xCbHk5eelSonz8oAUCYAUZZTmwY2ABfwlRlkpY V5GoKOEeApSi3IzS1DlXzGKczAqCfPefg80hSczrwRu0yugI5iAjujzATuiJBEhJdXA6GDUUL p/kXjtyhsCsnkK647u3yBwxEEyMiPUO/3a3nLeNad+MHc5HF+bb/u25srt9vICh5z+sN3rzL2 PJBz4f+/vPPsJlauupnsfuvJ41/6j/ytvRKZtX9p3KKjiWp5YdTJL+M0lLzTEz98S6Tkg8k6s S04+drrFNqtpEp9iD6YsujBjJnMbgxJLcUaioRZzUXEiAHP8Wz9zAgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-9.tower-206.messagelabs.com!1502474592!107018571!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 28675 invoked from network); 11 Aug 2017 18:03:13 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-9.tower-206.messagelabs.com with SMTP; 11 Aug 2017 18:03:13 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A61681650; Fri, 11 Aug 2017 11:03:12 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B61113F577; Fri, 11 Aug 2017 11:03:11 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 11 Aug 2017 19:02:52 +0100 Message-Id: <20170811180257.5493-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170811180257.5493-1-julien.grall@arm.com> References: <20170811180257.5493-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 06/11] xen/arm: Move arch/arm/vtimer.h to include/asm-arm/vtimer.h X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" It will be necessary to include vtimer.h from subdirectory making the inclusion a bit awkward. Signed-off-by: Julien Grall --- xen/arch/arm/domain.c | 2 +- xen/arch/arm/traps.c | 2 +- xen/{arch/arm => include/asm-arm}/vtimer.h | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename xen/{arch/arm => include/asm-arm}/vtimer.h (100%) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 1d835d321d..355021e452 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -33,8 +33,8 @@ #include #include #include +#include -#include "vtimer.h" #include "vuart.h" DEFINE_PER_CPU(struct vcpu *, curr_vcpu); diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index ca9bef712c..d79e9605b5 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -50,9 +50,9 @@ #include #include #include +#include #include "decode.h" -#include "vtimer.h" /* The base of the stack must always be double-word aligned, which means * that both the kernel half of struct cpu_user_regs (which is pushed in diff --git a/xen/arch/arm/vtimer.h b/xen/include/asm-arm/vtimer.h similarity index 100% rename from xen/arch/arm/vtimer.h rename to xen/include/asm-arm/vtimer.h From patchwork Fri Aug 11 18:02:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 109915 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1250175qge; Fri, 11 Aug 2017 11:05:28 -0700 (PDT) X-Received: by 10.36.184.134 with SMTP id m128mr11837215ite.82.1502474728276; Fri, 11 Aug 2017 11:05:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502474728; cv=none; d=google.com; s=arc-20160816; b=YgxchNnAnPYjkOUi9zvwEeQaf5/Y4w4fUAPZzL8HGkkKKf8htYIVstUNtdZYv9SQhF n4H6bdu4jSkdvMJS5KeBwORqew6qzf+kmYR9SlhD8s44twRX7S62OSyQzEZCQ2xZnbQT 38vTXMQewi5a6iwM0lXDp+u9EXG8dp066J8I4OmO/pbp8ORRdy1rZd3dy9PusU1ljfsP Ec9oBrH6iKDBwgIzwj5J7oO7YOCR1egA9XgknMEn3TBdcNyhVajHRXQahYlhSHzvQLsp K//ea78pEY/3H8s9hkoufNZS2mTwkcRRYvio1PRzeEm1Cc1DvrWvVT6/0Uz+v6D4MnOK Y2nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=2JpH7DrNFzmWNcCFhL8j3zO8UU/rUPseaboU/s5BPiw=; b=NEPNPhjhUs3w3cHKW8nfAa5jfIOjv5uejcu0qw7lKKV7OrD2NAwCO+5QWARX4KeaDY rCkZi4YnlidowrUDApjrNLu+YJpq9bq/rC4F5lWA2X0pXZX0s0Wi1a5tSbvVcmK8Z/vE x4bAnI02ndc1zpRad5xmJxyRrhiCDnNZw+Wt2YCQHpkeJfUFvVA2nE66Ve37Av2MJGmE 2nOrWRGRfaDMGrC8dX8vNcgkpKsOVraaqbc9YI+iVznGuVkP5XzflBlGz+ApkEuRqQkO loShm5Q3/bFYDnkZNBDnzQD/ivrxFBRxLNe9aMO5R7gUA5qBDIp3pUZa6D0oeJS8QXDs ituw== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id n19si1460401ion.8.2017.08.11.11.05.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Aug 2017 11:05:28 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dgEHE-0002ak-VS; Fri, 11 Aug 2017 18:03:16 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dgEHE-0002aA-AQ for xen-devel@lists.xen.org; Fri, 11 Aug 2017 18:03:16 +0000 Received: from [85.158.137.68] by server-2.bemta-3.messagelabs.com id 71/1A-22472-361FD895; Fri, 11 Aug 2017 18:03:15 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrALMWRWlGSWpSXmKPExsVysyfVTTfpY2+ kwes2S4slHxezODB6HN39mymAMYo1My8pvyKBNeP6x3XMBW+MK87v2MfawLhMvYuRi0NIYDOj ROP9GcwQzmlGid+bd7B3MXJysAloStz5/IkJxBYRkJa49vkyI4jNLFAt8X/hSTYQW1ggRGL6i 19AzRwcLAKqEhN+5oGYvAIWEs33fEAqJATkJXa1XWQFCXMKWErMuSwLEhYCqtj+bx3bBEbuBY wMqxg1ilOLylKLdI0M9ZKKMtMzSnITM3N0DQ2M9XJTi4sT01NzEpOK9ZLzczcxAn1bz8DAuIO xZ6/fIUZJDiYlUd4En95IIb6k/JTKjMTijPii0pzU4kOMMhwcShK8IR+AcoJFqempFWmZOcAg g0lLcPAoifD2gaR5iwsSc4sz0yFSpxh1OV5N+P+NSYglLz8vVUqcdwJIkQBIUUZpHtwIWMBfY pSVEuZlZGBgEOIpSC3KzSxBlX/FKM7BqCQMMYUnM68EbtMroCOYQI7wATuiJBEhJdXA6LBgo8 HLXVlRiWuDOtzc8woVpNdW7AjaN//hO4H/wQ4NKpabmJwKIvds/xz9L7pw0tn777fq/npz+YC O0omSL7Kf15zhzdiRKbLwupGAfY52tMI9Y/3pC+u79r3++eBFS1zLqbo++xqnD/cZnfbJPsib xnUgi+m409bmzMtlz9fwSO7u+PiPTYmlOCPRUIu5qDgRANwyHC9zAgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-12.tower-31.messagelabs.com!1502474594!92845740!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 17388 invoked from network); 11 Aug 2017 18:03:14 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-12.tower-31.messagelabs.com with SMTP; 11 Aug 2017 18:03:14 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 06EA7164F; Fri, 11 Aug 2017 11:03:14 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E66973F577; Fri, 11 Aug 2017 11:03:12 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 11 Aug 2017 19:02:53 +0100 Message-Id: <20170811180257.5493-8-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170811180257.5493-1-julien.grall@arm.com> References: <20170811180257.5493-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com Subject: [Xen-devel] [PATCH 07/11] xen/arm: traps: Export a bunch of helpers to handle emulation X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" A follow-up patch will move some parts of traps.c in separate files. The will require to use helpers that are currently statically defined. Export the following helpers: - inject_undef64_exception - inject_undef_exception - check_conditional_instr - advance_pc - handle_raz_wi - handle_wo_wi - handle_ro_raz Note that asm-arm/arm32/traps.h is empty but it is to keep parity with the arm64 counterpart. Signed-off-by: Julien Grall --- Cc: volodymyr_babchuk@epam.com --- xen/arch/arm/traps.c | 43 +++++++++++++++++++-------------------- xen/include/asm-arm/arm32/traps.h | 13 ++++++++++++ xen/include/asm-arm/arm64/traps.h | 15 ++++++++++++++ xen/include/asm-arm/traps.h | 35 +++++++++++++++++++++++++++++++ 4 files changed, 84 insertions(+), 22 deletions(-) create mode 100644 xen/include/asm-arm/arm32/traps.h create mode 100644 xen/include/asm-arm/arm64/traps.h create mode 100644 xen/include/asm-arm/traps.h diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index d79e9605b5..ab56958717 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include @@ -545,7 +546,7 @@ static vaddr_t exception_handler64(struct cpu_user_regs *regs, vaddr_t offset) } /* Inject an undefined exception into a 64 bit guest */ -static void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len) +void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len) { vaddr_t handler; const union hsr esr = { @@ -618,8 +619,7 @@ static void inject_iabt64_exception(struct cpu_user_regs *regs, #endif -static void inject_undef_exception(struct cpu_user_regs *regs, - const union hsr hsr) +void inject_undef_exception(struct cpu_user_regs *regs, const union hsr hsr) { if ( is_32bit_domain(current->domain) ) inject_undef32_exception(regs); @@ -1712,8 +1712,7 @@ static const unsigned short cc_map[16] = { 0 /* NV */ }; -static int check_conditional_instr(struct cpu_user_regs *regs, - const union hsr hsr) +int check_conditional_instr(struct cpu_user_regs *regs, const union hsr hsr) { unsigned long cpsr, cpsr_cond; int cond; @@ -1758,7 +1757,7 @@ static int check_conditional_instr(struct cpu_user_regs *regs, return 1; } -static void advance_pc(struct cpu_user_regs *regs, const union hsr hsr) +void advance_pc(struct cpu_user_regs *regs, const union hsr hsr) { unsigned long itbits, cond, cpsr = regs->cpsr; @@ -1799,11 +1798,11 @@ static void advance_pc(struct cpu_user_regs *regs, const union hsr hsr) } /* Read as zero and write ignore */ -static void handle_raz_wi(struct cpu_user_regs *regs, - int regidx, - bool read, - const union hsr hsr, - int min_el) +void handle_raz_wi(struct cpu_user_regs *regs, + int regidx, + bool read, + const union hsr hsr, + int min_el) { ASSERT((min_el == 0) || (min_el == 1)); @@ -1817,12 +1816,12 @@ static void handle_raz_wi(struct cpu_user_regs *regs, advance_pc(regs, hsr); } -/* Write only as write ignore */ -static void handle_wo_wi(struct cpu_user_regs *regs, - int regidx, - bool read, - const union hsr hsr, - int min_el) +/* write only as write ignore */ +void handle_wo_wi(struct cpu_user_regs *regs, + int regidx, + bool read, + const union hsr hsr, + int min_el) { ASSERT((min_el == 0) || (min_el == 1)); @@ -1837,11 +1836,11 @@ static void handle_wo_wi(struct cpu_user_regs *regs, } /* Read only as read as zero */ -static void handle_ro_raz(struct cpu_user_regs *regs, - int regidx, - bool read, - const union hsr hsr, - int min_el) +void handle_ro_raz(struct cpu_user_regs *regs, + int regidx, + bool read, + const union hsr hsr, + int min_el) { ASSERT((min_el == 0) || (min_el == 1)); diff --git a/xen/include/asm-arm/arm32/traps.h b/xen/include/asm-arm/arm32/traps.h new file mode 100644 index 0000000000..e3c4a8b473 --- /dev/null +++ b/xen/include/asm-arm/arm32/traps.h @@ -0,0 +1,13 @@ +#ifndef __ASM_ARM32_TRAPS__ +#define __ASM_ARM32_TRAPS__ + +#endif /* __ASM_ARM32_TRAPS__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ + diff --git a/xen/include/asm-arm/arm64/traps.h b/xen/include/asm-arm/arm64/traps.h new file mode 100644 index 0000000000..5cb45df6bd --- /dev/null +++ b/xen/include/asm-arm/arm64/traps.h @@ -0,0 +1,15 @@ +#ifndef __ASM_ARM32_TRAPS__ +#define __ASM_ARM32_TRAPS__ + +void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len); + +#endif /* __ASM_ARM32_TRAPS__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ + diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h new file mode 100644 index 0000000000..4e227c4dd2 --- /dev/null +++ b/xen/include/asm-arm/traps.h @@ -0,0 +1,35 @@ +#ifndef __ASM_ARM_TRAPS__ +#define __ASM_ARM_TRAPS__ + +#include + +#if defined(CONFIG_ARM_32) +# include +#elif defined(CONFIG_ARM_64) +# include +#endif + +int check_conditional_instr(struct cpu_user_regs *regs, const union hsr hsr); +void advance_pc(struct cpu_user_regs *regs, const union hsr hsr); + +void inject_undef_exception(struct cpu_user_regs *regs, const union hsr hsr); + +void handle_raz_wi(struct cpu_user_regs *regs, int regidx, bool read, + const union hsr hsr, int min_el); + +void handle_wo_wi(struct cpu_user_regs *regs, int regidx, bool read, + const union hsr hsr, int min_el); + +void handle_ro_raz(struct cpu_user_regs *regs, int regidx, bool read, + const union hsr hsr, int min_el); + +#endif /* __ASM_ARM_TRAPS__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ + From patchwork Fri Aug 11 18:02:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 109916 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1250235qge; Fri, 11 Aug 2017 11:05:30 -0700 (PDT) X-Received: by 10.36.154.3 with SMTP id l3mr34661ite.20.1502474730817; Fri, 11 Aug 2017 11:05:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502474730; cv=none; d=google.com; s=arc-20160816; b=fNcR1hiikKueuWnrdvLxU/CiRGrjemA99gUP4LLojlmihW0GSzSRcptuE2LAQ6/+CL uc/zNAouH9Y+/V13wscIMCoX1ctxacLOTDDYuK5ltiIsDtZEKr5IxFGy92r1UmJTRrUs e5mf2ALWDQ1+Yj6jWOdL8lTnzRdPpGhjHcasTD7EEtPte/GdX1GrOOkTI0bBAzlSQkq+ QyOXCpcvM0ypmiVoWGpf3L/6tWkf2P6YBfhY1/NfikO/XRyOMSsE7mvQLjOGWLdntU07 GP07V2fo8gqErs4+PwKlrYTlU8JcisUcS6Gs2m7hXo/AF9feFC8zVD9ub5CIKjSJXh9w 3FeQ== ARC-Message-Signature: i=1; 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[192.237.175.120]) by mx.google.com with ESMTPS id i75si1133093ioa.235.2017.08.11.11.05.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Aug 2017 11:05:30 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dgEHH-0002bj-9m; Fri, 11 Aug 2017 18:03:19 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dgEHG-0002bO-1D for xen-devel@lists.xen.org; Fri, 11 Aug 2017 18:03:18 +0000 Received: from [193.109.254.147] by server-11.bemta-6.messagelabs.com id 44/CD-03612-561FD895; Fri, 11 Aug 2017 18:03:17 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBLMWRWlGSWpSXmKPExsVysyfVTTflY2+ kwf+VYhZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8aCj68YC7YUVTR8f83WwLgpqIuRi0NIYDOj xMNd61ggnNOMEg2fdzN3MXJysAloStz5/IkJxBYRkJa49vkyI4jNLBAn8X5RIwuILSzgIfHt7 QU2EJtFQFXiwfPN7CA2r4CFRPeJbWC2hIC8xK62i6xdjBwcnAKWEnMuy4KEhYBKtv9bxzaBkX sBI8MqRo3i1KKy1CJdQxO9pKLM9IyS3MTMHF1DAzO93NTi4sT01JzEpGK95PzcTYxA/zIAwQ7 G6xsDDjFKcjApifIm+PRGCvEl5adUZiQWZ8QXleakFh9ilOHgUJLgDfkAlBMsSk1PrUjLzAEG GkxagoNHSYS3DyTNW1yQmFucmQ6ROsVozLFh9fovTByvJvz/xiTEkpeflyolzjsBpFQApDSjN A9uECwCLjHKSgnzMgKdJsRTkFqUm1mCKv+KUZyDUUkYYgpPZl4J3L5XQKcwgZziA3ZKSSJCSq qBscLxufLKELvZdWn9EhtWpv+z2Nqw6Zxt/asdwtqbnucbnM0pa1m5r2+Jhmp5UYLaDMNadya RSi99uQ9X+pZZvzFJXKZx186/8eWv3SoaQQXnV6/qX5VjZy+4pzvmi6oP26WQo+9vXow7taFt 2daKitWz34gJnNd+aGzBuuHAt7tn7+b91XVfosRSnJFoqMVcVJwIAHSk1fJ7AgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-8.tower-27.messagelabs.com!1502474595!100523019!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 37015 invoked from network); 11 Aug 2017 18:03:15 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-8.tower-27.messagelabs.com with SMTP; 11 Aug 2017 18:03:15 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5DBA41650; Fri, 11 Aug 2017 11:03:15 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 46F5F3F577; Fri, 11 Aug 2017 11:03:14 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 11 Aug 2017 19:02:54 +0100 Message-Id: <20170811180257.5493-9-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170811180257.5493-1-julien.grall@arm.com> References: <20170811180257.5493-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 08/11] xen/arm: Move sysreg emulation outside of traps.c X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The sysreg emulation is 64-bit specific and surrounded by #ifdef. Move them in a separate file arm/arm64/vsysreg.c to shrink down a bit traps.c No functional change. Signed-off-by: Julien Grall --- xen/arch/arm/arm64/Makefile | 1 + xen/arch/arm/arm64/vsysreg.c | 229 ++++++++++++++++++++++++++++++++++++++ xen/arch/arm/traps.c | 198 -------------------------------- xen/include/asm-arm/arm64/traps.h | 3 + 4 files changed, 233 insertions(+), 198 deletions(-) create mode 100644 xen/arch/arm/arm64/vsysreg.c diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile index 149b6b3901..718fe44455 100644 --- a/xen/arch/arm/arm64/Makefile +++ b/xen/arch/arm/arm64/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_LIVEPATCH) += livepatch.o obj-y += smpboot.o obj-y += traps.o obj-y += vfp.o +obj-y += vsysreg.o diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c new file mode 100644 index 0000000000..c57ac12503 --- /dev/null +++ b/xen/arch/arm/arm64/vsysreg.c @@ -0,0 +1,229 @@ +/* + * xen/arch/arm/arm64/sysreg.c + * + * Emulate system registers trapped. + * + * Copyright (c) 2011 Citrix Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include +#include +#include +#include + +void do_sysreg(struct cpu_user_regs *regs, + const union hsr hsr) +{ + int regidx = hsr.sysreg.reg; + struct vcpu *v = current; + + switch ( hsr.bits & HSR_SYSREG_REGS_MASK ) + { + /* + * HCR_EL2.TACR + * + * ARMv8 (DDI 0487A.d): D7.2.1 + */ + case HSR_SYSREG_ACTLR_EL1: + if ( psr_mode_is_user(regs) ) + return inject_undef_exception(regs, hsr); + if ( hsr.sysreg.read ) + set_user_reg(regs, regidx, v->arch.actlr); + break; + + /* + * MDCR_EL2.TDRA + * + * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 + */ + case HSR_SYSREG_MDRAR_EL1: + return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* + * MDCR_EL2.TDOSA + * + * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 + * + * Unhandled: + * OSLSR_EL1 + * DBGPRCR_EL1 + */ + case HSR_SYSREG_OSLAR_EL1: + return handle_wo_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + case HSR_SYSREG_OSDLR_EL1: + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* + * MDCR_EL2.TDA + * + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-59 + * + * Unhandled: + * MDCCINT_EL1 + * DBGDTR_EL0 + * DBGDTRRX_EL0 + * DBGDTRTX_EL0 + * OSDTRRX_EL1 + * OSDTRTX_EL1 + * OSECCR_EL1 + * DBGCLAIMSET_EL1 + * DBGCLAIMCLR_EL1 + * DBGAUTHSTATUS_EL1 + */ + case HSR_SYSREG_MDSCR_EL1: + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + case HSR_SYSREG_MDCCSR_EL0: + /* + * Accessible at EL0 only if MDSCR_EL1.TDCC is set to 0. We emulate that + * register as RAZ/WI above. So RO at both EL0 and EL1. + */ + return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); + HSR_SYSREG_DBG_CASES(DBGBVR): + HSR_SYSREG_DBG_CASES(DBGBCR): + HSR_SYSREG_DBG_CASES(DBGWVR): + HSR_SYSREG_DBG_CASES(DBGWCR): + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* + * MDCR_EL2.TPM + * + * ARMv8 (DDI 0487A.d): D1-1511 Table D1-61 + * + * Unhandled: + * PMEVCNTR_EL0 + * PMEVTYPER_EL0 + * PMCCFILTR_EL0 + * MDCR_EL2.TPMCR + * + * ARMv7 (DDI 0406C.b): B1.14.17 + * ARMv8 (DDI 0487A.d): D1-1511 Table D1-62 + * + * NB: Both MDCR_EL2.TPM and MDCR_EL2.TPMCR cause trapping of PMCR. + */ + case HSR_SYSREG_PMINTENSET_EL1: + case HSR_SYSREG_PMINTENCLR_EL1: + /* + * Accessible from EL1 only, but if EL0 trap happens handle as + * undef. + */ + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + case HSR_SYSREG_PMUSERENR_EL0: + /* RO at EL0. RAZ/WI at EL1 */ + if ( psr_mode_is_user(regs) ) + return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); + else + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + case HSR_SYSREG_PMCR_EL0: + case HSR_SYSREG_PMCNTENSET_EL0: + case HSR_SYSREG_PMCNTENCLR_EL0: + case HSR_SYSREG_PMOVSCLR_EL0: + case HSR_SYSREG_PMSWINC_EL0: + case HSR_SYSREG_PMSELR_EL0: + case HSR_SYSREG_PMCEID0_EL0: + case HSR_SYSREG_PMCEID1_EL0: + case HSR_SYSREG_PMCCNTR_EL0: + case HSR_SYSREG_PMXEVTYPER_EL0: + case HSR_SYSREG_PMXEVCNTR_EL0: + case HSR_SYSREG_PMOVSSET_EL0: + /* + * Accessible at EL0 only if PMUSERENR_EL0.EN is set. We + * emulate that register as 0 above. + */ + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* + * !CNTHCTL_EL2.EL1PCEN + * + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 + */ + case HSR_SYSREG_CNTP_CTL_EL0: + case HSR_SYSREG_CNTP_TVAL_EL0: + case HSR_SYSREG_CNTP_CVAL_EL0: + if ( !vtimer_emulate(regs, hsr) ) + return inject_undef_exception(regs, hsr); + break; + + /* + * HCR_EL2.FMO or HCR_EL2.IMO + * + * GIC Architecture Specification (IHI 0069C): Section 4.6.3 + */ + case HSR_SYSREG_ICC_SGI1R_EL1: + case HSR_SYSREG_ICC_ASGI1R_EL1: + case HSR_SYSREG_ICC_SGI0R_EL1: + + if ( !vgic_emulate(regs, hsr) ) + return inject_undef64_exception(regs, hsr.len); + break; + + /* + * ICC_SRE_EL2.Enable = 0 + * + * GIC Architecture Specification (IHI 0069C): Section 8.1.9 + */ + case HSR_SYSREG_ICC_SRE_EL1: + /* + * Trapped when the guest is using GICv2 whilst the platform + * interrupt controller is GICv3. In this case, the register + * should be emulate as RAZ/WI to tell the guest to use the GIC + * memory mapped interface (i.e GICv2 compatibility). + */ + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* + * HCR_EL2.TIDCP + * + * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43 + * + * - Reserved control space for IMPLEMENTATION DEFINED functionality. + * + * CPTR_EL2.TTA + * + * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 + * + * - All implemented trace registers. + * + * And all other unknown registers. + */ + default: + { + const struct hsr_sysreg sysreg = hsr.sysreg; + + gdprintk(XENLOG_ERR, + "%s %d, %d, c%d, c%d, %d %s x%d @ 0x%"PRIregister"\n", + sysreg.read ? "mrs" : "msr", + sysreg.op0, sysreg.op1, + sysreg.crn, sysreg.crm, + sysreg.op2, + sysreg.read ? "=>" : "<=", + sysreg.reg, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 64-bit sysreg access %#x\n", + hsr.bits & HSR_SYSREG_REGS_MASK); + inject_undef_exception(regs, hsr); + return; + } + } + + regs->pc += 4; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index ab56958717..b71354d7ff 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2276,204 +2276,6 @@ static void do_cp(struct cpu_user_regs *regs, const union hsr hsr) inject_undef_exception(regs, hsr); } -#ifdef CONFIG_ARM_64 -static void do_sysreg(struct cpu_user_regs *regs, - const union hsr hsr) -{ - int regidx = hsr.sysreg.reg; - struct vcpu *v = current; - - switch ( hsr.bits & HSR_SYSREG_REGS_MASK ) - { - /* - * HCR_EL2.TACR - * - * ARMv8 (DDI 0487A.d): D7.2.1 - */ - case HSR_SYSREG_ACTLR_EL1: - if ( psr_mode_is_user(regs) ) - return inject_undef_exception(regs, hsr); - if ( hsr.sysreg.read ) - set_user_reg(regs, regidx, v->arch.actlr); - break; - - /* - * MDCR_EL2.TDRA - * - * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 - */ - case HSR_SYSREG_MDRAR_EL1: - return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 1); - - /* - * MDCR_EL2.TDOSA - * - * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 - * - * Unhandled: - * OSLSR_EL1 - * DBGPRCR_EL1 - */ - case HSR_SYSREG_OSLAR_EL1: - return handle_wo_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - case HSR_SYSREG_OSDLR_EL1: - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - - /* - * MDCR_EL2.TDA - * - * ARMv8 (DDI 0487A.d): D1-1510 Table D1-59 - * - * Unhandled: - * MDCCINT_EL1 - * DBGDTR_EL0 - * DBGDTRRX_EL0 - * DBGDTRTX_EL0 - * OSDTRRX_EL1 - * OSDTRTX_EL1 - * OSECCR_EL1 - * DBGCLAIMSET_EL1 - * DBGCLAIMCLR_EL1 - * DBGAUTHSTATUS_EL1 - */ - case HSR_SYSREG_MDSCR_EL1: - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - case HSR_SYSREG_MDCCSR_EL0: - /* - * Accessible at EL0 only if MDSCR_EL1.TDCC is set to 0. We emulate that - * register as RAZ/WI above. So RO at both EL0 and EL1. - */ - return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); - HSR_SYSREG_DBG_CASES(DBGBVR): - HSR_SYSREG_DBG_CASES(DBGBCR): - HSR_SYSREG_DBG_CASES(DBGWVR): - HSR_SYSREG_DBG_CASES(DBGWCR): - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - - /* - * MDCR_EL2.TPM - * - * ARMv8 (DDI 0487A.d): D1-1511 Table D1-61 - * - * Unhandled: - * PMEVCNTR_EL0 - * PMEVTYPER_EL0 - * PMCCFILTR_EL0 - * MDCR_EL2.TPMCR - * - * ARMv7 (DDI 0406C.b): B1.14.17 - * ARMv8 (DDI 0487A.d): D1-1511 Table D1-62 - * - * NB: Both MDCR_EL2.TPM and MDCR_EL2.TPMCR cause trapping of PMCR. - */ - case HSR_SYSREG_PMINTENSET_EL1: - case HSR_SYSREG_PMINTENCLR_EL1: - /* - * Accessible from EL1 only, but if EL0 trap happens handle as - * undef. - */ - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - case HSR_SYSREG_PMUSERENR_EL0: - /* RO at EL0. RAZ/WI at EL1 */ - if ( psr_mode_is_user(regs) ) - return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); - else - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - case HSR_SYSREG_PMCR_EL0: - case HSR_SYSREG_PMCNTENSET_EL0: - case HSR_SYSREG_PMCNTENCLR_EL0: - case HSR_SYSREG_PMOVSCLR_EL0: - case HSR_SYSREG_PMSWINC_EL0: - case HSR_SYSREG_PMSELR_EL0: - case HSR_SYSREG_PMCEID0_EL0: - case HSR_SYSREG_PMCEID1_EL0: - case HSR_SYSREG_PMCCNTR_EL0: - case HSR_SYSREG_PMXEVTYPER_EL0: - case HSR_SYSREG_PMXEVCNTR_EL0: - case HSR_SYSREG_PMOVSSET_EL0: - /* - * Accessible at EL0 only if PMUSERENR_EL0.EN is set. We - * emulate that register as 0 above. - */ - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - - /* - * !CNTHCTL_EL2.EL1PCEN - * - * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 - */ - case HSR_SYSREG_CNTP_CTL_EL0: - case HSR_SYSREG_CNTP_TVAL_EL0: - case HSR_SYSREG_CNTP_CVAL_EL0: - if ( !vtimer_emulate(regs, hsr) ) - return inject_undef_exception(regs, hsr); - break; - - /* - * HCR_EL2.FMO or HCR_EL2.IMO - * - * GIC Architecture Specification (IHI 0069C): Section 4.6.3 - */ - case HSR_SYSREG_ICC_SGI1R_EL1: - case HSR_SYSREG_ICC_ASGI1R_EL1: - case HSR_SYSREG_ICC_SGI0R_EL1: - - if ( !vgic_emulate(regs, hsr) ) - return inject_undef64_exception(regs, hsr.len); - break; - - /* - * ICC_SRE_EL2.Enable = 0 - * - * GIC Architecture Specification (IHI 0069C): Section 8.1.9 - */ - case HSR_SYSREG_ICC_SRE_EL1: - /* - * Trapped when the guest is using GICv2 whilst the platform - * interrupt controller is GICv3. In this case, the register - * should be emulate as RAZ/WI to tell the guest to use the GIC - * memory mapped interface (i.e GICv2 compatibility). - */ - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - - /* - * HCR_EL2.TIDCP - * - * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43 - * - * - Reserved control space for IMPLEMENTATION DEFINED functionality. - * - * CPTR_EL2.TTA - * - * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 - * - * - All implemented trace registers. - * - * And all other unknown registers. - */ - default: - { - const struct hsr_sysreg sysreg = hsr.sysreg; - - gdprintk(XENLOG_ERR, - "%s %d, %d, c%d, c%d, %d %s x%d @ 0x%"PRIregister"\n", - sysreg.read ? "mrs" : "msr", - sysreg.op0, sysreg.op1, - sysreg.crn, sysreg.crm, - sysreg.op2, - sysreg.read ? "=>" : "<=", - sysreg.reg, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit sysreg access %#x\n", - hsr.bits & HSR_SYSREG_REGS_MASK); - inject_undef_exception(regs, hsr); - return; - } - } - - regs->pc += 4; -} -#endif - void dump_guest_s1_walk(struct domain *d, vaddr_t addr) { register_t ttbcr = READ_SYSREG(TCR_EL1); diff --git a/xen/include/asm-arm/arm64/traps.h b/xen/include/asm-arm/arm64/traps.h index 5cb45df6bd..27145d2589 100644 --- a/xen/include/asm-arm/arm64/traps.h +++ b/xen/include/asm-arm/arm64/traps.h @@ -3,6 +3,9 @@ void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len); +void do_sysreg(struct cpu_user_regs *regs, + const union hsr hsr); + #endif /* __ASM_ARM32_TRAPS__ */ /* * Local variables: From patchwork Fri Aug 11 18:02:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 109917 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1250409qge; Fri, 11 Aug 2017 11:05:40 -0700 (PDT) X-Received: by 10.36.163.137 with SMTP id p131mr32642ite.22.1502474740816; Fri, 11 Aug 2017 11:05:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502474740; cv=none; d=google.com; s=arc-20160816; b=VlS96QICrJyLuwetxjUyc6i910CZdUsjl5cRAojxP6V9/ENaDj4kbVbIr1ojqhZNQq uSk9bf59R6E7EOGY46tOfdIZb8nCjs7bRoJbeLYBoFqWuqUp4R9GTpHkudupv5cLmRXM jSQmBpMcO5apD+bN5s7g3YnhSTkWFtSGkXknS9v3IxXbftnNywfzMMs6I7W9QsxxaBKE f4gzuT+MIfzNBfkmw1qOVd4c5A6mK2UuWJ8BdITAL3RGepIK+x96kYYj0aeE5BmMFJFO SLkhtSN7KLXZftcQZrIBvJm2AREXkUaayc3wgjnL0z7lrq5utvuRxKB03caGmrUInvaJ N4MA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=CehDztixPW8D3G/pYyz+O29Y3whCd76RcJo7k0nxC1I=; b=EIVh41AYehEtCaJxKAiF8Ix/SGAsEnesoH6QW0WowFqbcCXS3A4eJuXLa7ywtluv9H ZBNLOMOO9xswlAa50yfpvAUOhpsZsaByY6sL4ZFTtG4c+rPJlHSvg+qERdE0cO4OBOp7 GSG+RjrZ3/X4RV0ZgbFgWSbjts8Q2qBJq5JPd6P7H5tgBg6xRlauoYvmsygP35pxud4v SzI3mp7ced/CcU55QXIGD3dxu3AtbBJp5Obg/oJlprKNLHNppf+E7yfUwrvWt5/Enix5 0splAa2ucZpNG9ncrVNhhg8xN5w01N4CrSJfk9zTev8zcO8xAic0eVuOFJmYWxxfx6On qN0w== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id k184si36809itd.180.2017.08.11.11.05.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Aug 2017 11:05:40 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dgEHI-0002cD-Gy; Fri, 11 Aug 2017 18:03:20 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dgEHH-0002bd-CI for xen-devel@lists.xen.org; Fri, 11 Aug 2017 18:03:19 +0000 Received: from [193.109.254.147] by server-7.bemta-6.messagelabs.com id D5/75-03557-661FD895; Fri, 11 Aug 2017 18:03:18 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMLMWRWlGSWpSXmKPExsVysyfVTTf1Y2+ kwadJRhZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8ahp7cYC65dZ6xYvUCrgXHdTMYuRi4OIYHN jBK73s9ih3BOM0o8O3CVtYuRk4NNQFPizudPTCC2iIC0xLXPlxlBbGaBOIn3ixpZQGxhAT+J9 ytWgtWwCKhKLJt5DizOK2Apcf3sQjBbQkBeYlfbRaCZHBycQPE5l2VBwkICFhLb/61jm8DIvY CRYRWjRnFqUVlqka6xkV5SUWZ6RkluYmaOrqGBmV5uanFxYnpqTmJSsV5yfu4mRqCHGYBgB+P pdYGHGCU5mJREeRN8eiOF+JLyUyozEosz4otKc1KLDzHKcHAoSfCGfADKCRalpqdWpGXmAEMN Ji3BwaMkApHmLS5IzC3OTIdInWLU5Xg14f83JiGWvPy8VClxXh6QIgGQoozSPLgRsLC/xCgrJ czLCHSUEE9BalFuZgmq/CtGcQ5GJWHeGJApPJl5JXCbXgEdwQR0RJ8P2BEliQgpqQbGre4rDu 2qv3Lwu+XNBI2rh25EtfHVlFy8dXFaiJ5Kq+hx/+uS7RnXvsx9mfnHyEn5Yx3zgQs14hPUooM ba30cj1gxyy4WWHjUv49xGvu7yRKHeefpPtdLT+5N2Lv4u43VL/ljX1vd1VfU+l7fXmuZ6+Jz K8T2/6e3B/l97HJztoh72vTq72FXYinOSDTUYi4qTgQAW7dzlnYCAAA= X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-12.tower-27.messagelabs.com!1502474596!109977909!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 14918 invoked from network); 11 Aug 2017 18:03:17 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-12.tower-27.messagelabs.com with SMTP; 11 Aug 2017 18:03:17 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B290B165C; Fri, 11 Aug 2017 11:03:16 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9DBF63F577; Fri, 11 Aug 2017 11:03:15 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 11 Aug 2017 19:02:55 +0100 Message-Id: <20170811180257.5493-10-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170811180257.5493-1-julien.grall@arm.com> References: <20170811180257.5493-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 09/11] xen/arm: Move co-processor emulation outside of traps.c X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The co-processor emulation is quite big and pretty much standalone. Move it in a separate file to shrink down the size of traps.c. At the same time remove unused cpregs.h. No functional change. Signed-off-by: Julien Grall --- xen/arch/arm/Makefile | 1 + xen/arch/arm/traps.c | 421 ----------------------------------------- xen/arch/arm/vcpreg.c | 451 ++++++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/traps.h | 8 + 4 files changed, 460 insertions(+), 421 deletions(-) create mode 100644 xen/arch/arm/vcpreg.c diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 49e1fb2f84..de00c5e339 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -44,6 +44,7 @@ obj-y += smpboot.o obj-y += sysctl.o obj-y += time.o obj-y += traps.o +obj-y += vcpreg.o obj-y += vgic.o obj-y += vgic-v2.o obj-$(CONFIG_HAS_GICV3) += vgic-v3.o diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index b71354d7ff..13efb58e49 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -38,7 +38,6 @@ #include #include -#include #include #include #include @@ -1856,426 +1855,6 @@ void handle_ro_raz(struct cpu_user_regs *regs, advance_pc(regs, hsr); } -static void do_cp15_32(struct cpu_user_regs *regs, - const union hsr hsr) -{ - const struct hsr_cp32 cp32 = hsr.cp32; - int regidx = cp32.reg; - struct vcpu *v = current; - - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - switch ( hsr.bits & HSR_CP32_REGS_MASK ) - { - /* - * !CNTHCTL_EL2.EL1PCEN / !CNTHCTL.PL1PCEN - * - * ARMv7 (DDI 0406C.b): B4.1.22 - * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 - */ - case HSR_CPREG32(CNTP_CTL): - case HSR_CPREG32(CNTP_TVAL): - if ( !vtimer_emulate(regs, hsr) ) - return inject_undef_exception(regs, hsr); - break; - - /* - * HCR_EL2.TACR / HCR.TAC - * - * ARMv7 (DDI 0406C.b): B1.14.6 - * ARMv8 (DDI 0487A.d): G6.2.1 - */ - case HSR_CPREG32(ACTLR): - if ( psr_mode_is_user(regs) ) - return inject_undef_exception(regs, hsr); - if ( cp32.read ) - set_user_reg(regs, regidx, v->arch.actlr); - break; - - /* - * MDCR_EL2.TPM - * - * ARMv7 (DDI 0406C.b): B1.14.17 - * ARMv8 (DDI 0487A.d): D1-1511 Table D1-61 - * - * Unhandled: - * PMEVCNTR - * PMEVTYPER - * PMCCFILTR - * - * MDCR_EL2.TPMCR - * - * ARMv7 (DDI 0406C.b): B1.14.17 - * ARMv8 (DDI 0487A.d): D1-1511 Table D1-62 - * - * NB: Both MDCR_EL2.TPM and MDCR_EL2.TPMCR cause trapping of PMCR. - */ - /* We could trap ID_DFR0 and tell the guest we don't support - * performance monitoring, but Linux doesn't check the ID_DFR0. - * Therefore it will read PMCR. - * - * We tell the guest we have 0 counters. Unfortunately we must - * always support PMCCNTR (the cyle counter): we just RAZ/WI for all - * PM register, which doesn't crash the kernel at least - */ - case HSR_CPREG32(PMUSERENR): - /* RO at EL0. RAZ/WI at EL1 */ - if ( psr_mode_is_user(regs) ) - return handle_ro_raz(regs, regidx, cp32.read, hsr, 0); - else - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - case HSR_CPREG32(PMINTENSET): - case HSR_CPREG32(PMINTENCLR): - /* EL1 only, however MDCR_EL2.TPM==1 means EL0 may trap here also. */ - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - case HSR_CPREG32(PMCR): - case HSR_CPREG32(PMCNTENSET): - case HSR_CPREG32(PMCNTENCLR): - case HSR_CPREG32(PMOVSR): - case HSR_CPREG32(PMSWINC): - case HSR_CPREG32(PMSELR): - case HSR_CPREG32(PMCEID0): - case HSR_CPREG32(PMCEID1): - case HSR_CPREG32(PMCCNTR): - case HSR_CPREG32(PMXEVTYPER): - case HSR_CPREG32(PMXEVCNTR): - case HSR_CPREG32(PMOVSSET): - /* - * Accessible at EL0 only if PMUSERENR_EL0.EN is set. We - * emulate that register as 0 above. - */ - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - - /* - * HCR_EL2.TIDCP - * - * ARMv7 (DDI 0406C.b): B1.14.3 - * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43 - * - * - CRn==c9, opc1=={0-7}, CRm=={c0-c2, c5-c8}, opc2=={0-7} - * (Cache and TCM lockdown registers) - * - CRn==c10, opc1=={0-7}, CRm=={c0, c1, c4, c8}, opc2=={0-7} - * (VMSA CP15 c10 registers) - * - CRn==c11, opc1=={0-7}, CRm=={c0-c8, c15}, opc2=={0-7} - * (VMSA CP15 c11 registers) - * - * CPTR_EL2.T{0..9,12..13} - * - * ARMv7 (DDI 0406C.b): B1.14.12 - * ARMv8 (DDI 0487A.d): N/A - * - * - All accesses to coprocessors 0..9 and 12..13 - * - * HSTR_EL2.T15 - * - * ARMv7 (DDI 0406C.b): B1.14.14 - * ARMv8 (DDI 0487A.d): D1-1507 Table D1-55 - * - * - All accesses to cp15, c15 registers. - * - * And all other unknown registers. - */ - default: - gdprintk(XENLOG_ERR, - "%s p15, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", - cp32.read ? "mrc" : "mcr", - cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 32-bit CP15 access %#x\n", - hsr.bits & HSR_CP32_REGS_MASK); - inject_undef_exception(regs, hsr); - return; - } - advance_pc(regs, hsr); -} - -static void do_cp15_64(struct cpu_user_regs *regs, - const union hsr hsr) -{ - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - switch ( hsr.bits & HSR_CP64_REGS_MASK ) - { - /* - * !CNTHCTL_EL2.EL1PCEN / !CNTHCTL.PL1PCEN - * - * ARMv7 (DDI 0406C.b): B4.1.22 - * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 - */ - case HSR_CPREG64(CNTP_CVAL): - if ( !vtimer_emulate(regs, hsr) ) - return inject_undef_exception(regs, hsr); - break; - - /* - * HCR_EL2.FMO or HCR_EL2.IMO - * - * GIC Architecture Specification (IHI 0069C): Section 4.6.3 - */ - case HSR_CPREG64(ICC_SGI1R): - case HSR_CPREG64(ICC_ASGI1R): - case HSR_CPREG64(ICC_SGI0R): - if ( !vgic_emulate(regs, hsr) ) - return inject_undef_exception(regs, hsr); - break; - - /* - * CPTR_EL2.T{0..9,12..13} - * - * ARMv7 (DDI 0406C.b): B1.14.12 - * ARMv8 (DDI 0487A.d): N/A - * - * - All accesses to coprocessors 0..9 and 12..13 - * - * HSTR_EL2.T15 - * - * ARMv7 (DDI 0406C.b): B1.14.14 - * ARMv8 (DDI 0487A.d): D1-1507 Table D1-55 - * - * - All accesses to cp15, c15 registers. - * - * And all other unknown registers. - */ - default: - { - const struct hsr_cp64 cp64 = hsr.cp64; - - gdprintk(XENLOG_ERR, - "%s p15, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", - cp64.read ? "mrrc" : "mcrr", - cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit CP15 access %#x\n", - hsr.bits & HSR_CP64_REGS_MASK); - inject_undef_exception(regs, hsr); - return; - } - } - advance_pc(regs, hsr); -} - -static void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) -{ - const struct hsr_cp32 cp32 = hsr.cp32; - int regidx = cp32.reg; - struct domain *d = current->domain; - - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - switch ( hsr.bits & HSR_CP32_REGS_MASK ) - { - /* - * MDCR_EL2.TDOSA - * - * ARMv7 (DDI 0406C.b): B1.14.15 - * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 - * - * Unhandled: - * DBGOSLSR - * DBGPRCR - */ - case HSR_CPREG32(DBGOSLAR): - return handle_wo_wi(regs, regidx, cp32.read, hsr, 1); - case HSR_CPREG32(DBGOSDLR): - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - - /* - * MDCR_EL2.TDA - * - * ARMv7 (DDI 0406C.b): B1.14.15 - * ARMv8 (DDI 0487A.d): D1-1510 Table D1-59 - * - * Unhandled: - * DBGDCCINT - * DBGDTRRXint - * DBGDTRTXint - * DBGWFAR - * DBGDTRTXext - * DBGDTRRXext, - * DBGBXVR - * DBGCLAIMSET - * DBGCLAIMCLR - * DBGAUTHSTATUS - * DBGDEVID - * DBGDEVID1 - * DBGDEVID2 - * DBGOSECCR - */ - case HSR_CPREG32(DBGDIDR): - { - uint32_t val; - - /* - * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis - * is set to 0, which we emulated below. - */ - if ( !cp32.read ) - return inject_undef_exception(regs, hsr); - - /* Implement the minimum requirements: - * - Number of watchpoints: 1 - * - Number of breakpoints: 2 - * - Version: ARMv7 v7.1 - * - Variant and Revision bits match MDIR - */ - val = (1 << 24) | (5 << 16); - val |= ((d->arch.vpidr >> 20) & 0xf) | (d->arch.vpidr & 0xf); - set_user_reg(regs, regidx, val); - - break; - } - - case HSR_CPREG32(DBGDSCRINT): - /* - * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis - * is set to 0, which we emulated below. - */ - return handle_ro_raz(regs, regidx, cp32.read, hsr, 1); - - case HSR_CPREG32(DBGDSCREXT): - /* - * Implement debug status and control register as RAZ/WI. - * The OS won't use Hardware debug if MDBGen not set. - */ - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - - case HSR_CPREG32(DBGVCR): - case HSR_CPREG32(DBGBVR0): - case HSR_CPREG32(DBGBCR0): - case HSR_CPREG32(DBGWVR0): - case HSR_CPREG32(DBGWCR0): - case HSR_CPREG32(DBGBVR1): - case HSR_CPREG32(DBGBCR1): - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - - /* - * CPTR_EL2.TTA - * - * ARMv7 (DDI 0406C.b): B1.14.16 - * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 - * - * - All implemented trace registers. - * - * MDCR_EL2.TDRA - * - * ARMv7 (DDI 0406C.b): B1.14.15 - * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 - * - * Unhandled: - * DBGDRAR (32-bit accesses) - * DBGDSAR (32-bit accesses) - * - * And all other unknown registers. - */ - default: - gdprintk(XENLOG_ERR, - "%s p14, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", - cp32.read ? "mrc" : "mcr", - cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#x\n", - hsr.bits & HSR_CP32_REGS_MASK); - inject_undef_exception(regs, hsr); - return; - } - - advance_pc(regs, hsr); -} - -static void do_cp14_64(struct cpu_user_regs *regs, const union hsr hsr) -{ - const struct hsr_cp64 cp64 = hsr.cp64; - - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - /* - * CPTR_EL2.TTA - * - * ARMv7 (DDI 0406C.b): B1.14.16 - * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 - * - * - All implemented trace registers. - * - * MDCR_EL2.TDRA - * - * ARMv7 (DDI 0406C.b): B1.14.15 - * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 - * - * Unhandled: - * DBGDRAR (64-bit accesses) - * DBGDSAR (64-bit accesses) - * - * And all other unknown registers. - */ - gdprintk(XENLOG_ERR, - "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", - cp64.read ? "mrrc" : "mcrr", - cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 access %#x\n", - hsr.bits & HSR_CP64_REGS_MASK); - inject_undef_exception(regs, hsr); -} - -static void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr) -{ - struct hsr_cp64 cp64 = hsr.cp64; - - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - /* - * MDCR_EL2.TDOSA - * - * ARMv7 (DDI 0406C.b): B1.14.15 - * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 - * - * Unhandled: - * DBGDTRTXint - * DBGDTRRXint - * - * And all other unknown registers. - */ - gdprintk(XENLOG_ERR, - "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", - cp64.read ? "mrrc" : "mcrr", - cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 DBG access %#x\n", - hsr.bits & HSR_CP64_REGS_MASK); - - inject_undef_exception(regs, hsr); -} - -static void do_cp(struct cpu_user_regs *regs, const union hsr hsr) -{ - const struct hsr_cp cp = hsr.cp; - - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - ASSERT(!cp.tas); /* We don't trap SIMD instruction */ - gdprintk(XENLOG_ERR, "unhandled CP%d access\n", cp.coproc); - inject_undef_exception(regs, hsr); -} - void dump_guest_s1_walk(struct domain *d, vaddr_t addr) { register_t ttbcr = READ_SYSREG(TCR_EL1); diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c new file mode 100644 index 0000000000..f3b08403fb --- /dev/null +++ b/xen/arch/arm/vcpreg.c @@ -0,0 +1,451 @@ +/* + * xen/arch/arm/arm64/vcpreg.c + * + * Emulate co-processor registers trapped. + * + * Copyright (c) 2011 Citrix Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include +#include +#include +#include + +void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) +{ + const struct hsr_cp32 cp32 = hsr.cp32; + int regidx = cp32.reg; + struct vcpu *v = current; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + switch ( hsr.bits & HSR_CP32_REGS_MASK ) + { + /* + * !CNTHCTL_EL2.EL1PCEN / !CNTHCTL.PL1PCEN + * + * ARMv7 (DDI 0406C.b): B4.1.22 + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 + */ + case HSR_CPREG32(CNTP_CTL): + case HSR_CPREG32(CNTP_TVAL): + if ( !vtimer_emulate(regs, hsr) ) + return inject_undef_exception(regs, hsr); + break; + + /* + * HCR_EL2.TACR / HCR.TAC + * + * ARMv7 (DDI 0406C.b): B1.14.6 + * ARMv8 (DDI 0487A.d): G6.2.1 + */ + case HSR_CPREG32(ACTLR): + if ( psr_mode_is_user(regs) ) + return inject_undef_exception(regs, hsr); + if ( cp32.read ) + set_user_reg(regs, regidx, v->arch.actlr); + break; + + /* + * MDCR_EL2.TPM + * + * ARMv7 (DDI 0406C.b): B1.14.17 + * ARMv8 (DDI 0487A.d): D1-1511 Table D1-61 + * + * Unhandled: + * PMEVCNTR + * PMEVTYPER + * PMCCFILTR + * + * MDCR_EL2.TPMCR + * + * ARMv7 (DDI 0406C.b): B1.14.17 + * ARMv8 (DDI 0487A.d): D1-1511 Table D1-62 + * + * NB: Both MDCR_EL2.TPM and MDCR_EL2.TPMCR cause trapping of PMCR. + */ + /* We could trap ID_DFR0 and tell the guest we don't support + * performance monitoring, but Linux doesn't check the ID_DFR0. + * Therefore it will read PMCR. + * + * We tell the guest we have 0 counters. Unfortunately we must + * always support PMCCNTR (the cyle counter): we just RAZ/WI for all + * PM register, which doesn't crash the kernel at least + */ + case HSR_CPREG32(PMUSERENR): + /* RO at EL0. RAZ/WI at EL1 */ + if ( psr_mode_is_user(regs) ) + return handle_ro_raz(regs, regidx, cp32.read, hsr, 0); + else + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + case HSR_CPREG32(PMINTENSET): + case HSR_CPREG32(PMINTENCLR): + /* EL1 only, however MDCR_EL2.TPM==1 means EL0 may trap here also. */ + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + case HSR_CPREG32(PMCR): + case HSR_CPREG32(PMCNTENSET): + case HSR_CPREG32(PMCNTENCLR): + case HSR_CPREG32(PMOVSR): + case HSR_CPREG32(PMSWINC): + case HSR_CPREG32(PMSELR): + case HSR_CPREG32(PMCEID0): + case HSR_CPREG32(PMCEID1): + case HSR_CPREG32(PMCCNTR): + case HSR_CPREG32(PMXEVTYPER): + case HSR_CPREG32(PMXEVCNTR): + case HSR_CPREG32(PMOVSSET): + /* + * Accessible at EL0 only if PMUSERENR_EL0.EN is set. We + * emulate that register as 0 above. + */ + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + + /* + * HCR_EL2.TIDCP + * + * ARMv7 (DDI 0406C.b): B1.14.3 + * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43 + * + * - CRn==c9, opc1=={0-7}, CRm=={c0-c2, c5-c8}, opc2=={0-7} + * (Cache and TCM lockdown registers) + * - CRn==c10, opc1=={0-7}, CRm=={c0, c1, c4, c8}, opc2=={0-7} + * (VMSA CP15 c10 registers) + * - CRn==c11, opc1=={0-7}, CRm=={c0-c8, c15}, opc2=={0-7} + * (VMSA CP15 c11 registers) + * + * CPTR_EL2.T{0..9,12..13} + * + * ARMv7 (DDI 0406C.b): B1.14.12 + * ARMv8 (DDI 0487A.d): N/A + * + * - All accesses to coprocessors 0..9 and 12..13 + * + * HSTR_EL2.T15 + * + * ARMv7 (DDI 0406C.b): B1.14.14 + * ARMv8 (DDI 0487A.d): D1-1507 Table D1-55 + * + * - All accesses to cp15, c15 registers. + * + * And all other unknown registers. + */ + default: + gdprintk(XENLOG_ERR, + "%s p15, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", + cp32.read ? "mrc" : "mcr", + cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 32-bit CP15 access %#x\n", + hsr.bits & HSR_CP32_REGS_MASK); + inject_undef_exception(regs, hsr); + return; + } + advance_pc(regs, hsr); +} + +void do_cp15_64(struct cpu_user_regs *regs, const union hsr hsr) +{ + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + switch ( hsr.bits & HSR_CP64_REGS_MASK ) + { + /* + * !CNTHCTL_EL2.EL1PCEN / !CNTHCTL.PL1PCEN + * + * ARMv7 (DDI 0406C.b): B4.1.22 + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 + */ + case HSR_CPREG64(CNTP_CVAL): + if ( !vtimer_emulate(regs, hsr) ) + return inject_undef_exception(regs, hsr); + break; + + /* + * HCR_EL2.FMO or HCR_EL2.IMO + * + * GIC Architecture Specification (IHI 0069C): Section 4.6.3 + */ + case HSR_CPREG64(ICC_SGI1R): + case HSR_CPREG64(ICC_ASGI1R): + case HSR_CPREG64(ICC_SGI0R): + if ( !vgic_emulate(regs, hsr) ) + return inject_undef_exception(regs, hsr); + break; + + /* + * CPTR_EL2.T{0..9,12..13} + * + * ARMv7 (DDI 0406C.b): B1.14.12 + * ARMv8 (DDI 0487A.d): N/A + * + * - All accesses to coprocessors 0..9 and 12..13 + * + * HSTR_EL2.T15 + * + * ARMv7 (DDI 0406C.b): B1.14.14 + * ARMv8 (DDI 0487A.d): D1-1507 Table D1-55 + * + * - All accesses to cp15, c15 registers. + * + * And all other unknown registers. + */ + default: + { + const struct hsr_cp64 cp64 = hsr.cp64; + + gdprintk(XENLOG_ERR, + "%s p15, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", + cp64.read ? "mrrc" : "mcrr", + cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 64-bit CP15 access %#x\n", + hsr.bits & HSR_CP64_REGS_MASK); + inject_undef_exception(regs, hsr); + return; + } + } + advance_pc(regs, hsr); +} + +void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) +{ + const struct hsr_cp32 cp32 = hsr.cp32; + int regidx = cp32.reg; + struct domain *d = current->domain; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + switch ( hsr.bits & HSR_CP32_REGS_MASK ) + { + /* + * MDCR_EL2.TDOSA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 + * + * Unhandled: + * DBGOSLSR + * DBGPRCR + */ + case HSR_CPREG32(DBGOSLAR): + return handle_wo_wi(regs, regidx, cp32.read, hsr, 1); + case HSR_CPREG32(DBGOSDLR): + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + + /* + * MDCR_EL2.TDA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-59 + * + * Unhandled: + * DBGDCCINT + * DBGDTRRXint + * DBGDTRTXint + * DBGWFAR + * DBGDTRTXext + * DBGDTRRXext, + * DBGBXVR + * DBGCLAIMSET + * DBGCLAIMCLR + * DBGAUTHSTATUS + * DBGDEVID + * DBGDEVID1 + * DBGDEVID2 + * DBGOSECCR + */ + case HSR_CPREG32(DBGDIDR): + { + uint32_t val; + + /* + * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis + * is set to 0, which we emulated below. + */ + if ( !cp32.read ) + return inject_undef_exception(regs, hsr); + + /* Implement the minimum requirements: + * - Number of watchpoints: 1 + * - Number of breakpoints: 2 + * - Version: ARMv7 v7.1 + * - Variant and Revision bits match MDIR + */ + val = (1 << 24) | (5 << 16); + val |= ((d->arch.vpidr >> 20) & 0xf) | (d->arch.vpidr & 0xf); + set_user_reg(regs, regidx, val); + + break; + } + + case HSR_CPREG32(DBGDSCRINT): + /* + * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis + * is set to 0, which we emulated below. + */ + return handle_ro_raz(regs, regidx, cp32.read, hsr, 1); + + case HSR_CPREG32(DBGDSCREXT): + /* + * Implement debug status and control register as RAZ/WI. + * The OS won't use Hardware debug if MDBGen not set. + */ + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + + case HSR_CPREG32(DBGVCR): + case HSR_CPREG32(DBGBVR0): + case HSR_CPREG32(DBGBCR0): + case HSR_CPREG32(DBGWVR0): + case HSR_CPREG32(DBGWCR0): + case HSR_CPREG32(DBGBVR1): + case HSR_CPREG32(DBGBCR1): + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + + /* + * CPTR_EL2.TTA + * + * ARMv7 (DDI 0406C.b): B1.14.16 + * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 + * + * - All implemented trace registers. + * + * MDCR_EL2.TDRA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 + * + * Unhandled: + * DBGDRAR (32-bit accesses) + * DBGDSAR (32-bit accesses) + * + * And all other unknown registers. + */ + default: + gdprintk(XENLOG_ERR, + "%s p14, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", + cp32.read ? "mrc" : "mcr", + cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#x\n", + hsr.bits & HSR_CP32_REGS_MASK); + inject_undef_exception(regs, hsr); + return; + } + + advance_pc(regs, hsr); +} + +void do_cp14_64(struct cpu_user_regs *regs, const union hsr hsr) +{ + const struct hsr_cp64 cp64 = hsr.cp64; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + /* + * CPTR_EL2.TTA + * + * ARMv7 (DDI 0406C.b): B1.14.16 + * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 + * + * - All implemented trace registers. + * + * MDCR_EL2.TDRA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 + * + * Unhandled: + * DBGDRAR (64-bit accesses) + * DBGDSAR (64-bit accesses) + * + * And all other unknown registers. + */ + gdprintk(XENLOG_ERR, + "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", + cp64.read ? "mrrc" : "mcrr", + cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 access %#x\n", + hsr.bits & HSR_CP64_REGS_MASK); + inject_undef_exception(regs, hsr); +} + +void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr) +{ + struct hsr_cp64 cp64 = hsr.cp64; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + /* + * MDCR_EL2.TDOSA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 + * + * Unhandled: + * DBGDTRTXint + * DBGDTRRXint + * + * And all other unknown registers. + */ + gdprintk(XENLOG_ERR, + "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", + cp64.read ? "mrrc" : "mcrr", + cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 DBG access %#x\n", + hsr.bits & HSR_CP64_REGS_MASK); + + inject_undef_exception(regs, hsr); +} + +void do_cp(struct cpu_user_regs *regs, const union hsr hsr) +{ + const struct hsr_cp cp = hsr.cp; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + ASSERT(!cp.tas); /* We don't trap SIMD instruction */ + gdprintk(XENLOG_ERR, "unhandled CP%d access\n", cp.coproc); + inject_undef_exception(regs, hsr); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h index 4e227c4dd2..f88cbf6ae3 100644 --- a/xen/include/asm-arm/traps.h +++ b/xen/include/asm-arm/traps.h @@ -23,6 +23,14 @@ void handle_wo_wi(struct cpu_user_regs *regs, int regidx, bool read, void handle_ro_raz(struct cpu_user_regs *regs, int regidx, bool read, const union hsr hsr, int min_el); +/* Co-processor registers emulation (see arch/arm/vcpreg.c). */ +void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp15_64(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp14_64(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp(struct cpu_user_regs *regs, const union hsr hsr); + #endif /* __ASM_ARM_TRAPS__ */ /* * Local variables: From patchwork Fri Aug 11 18:02:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 109914 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1250206qge; Fri, 11 Aug 2017 11:05:29 -0700 (PDT) X-Received: by 10.107.3.41 with SMTP id 41mr13820077iod.309.1502474729835; Fri, 11 Aug 2017 11:05:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502474729; cv=none; d=google.com; s=arc-20160816; b=JhB89S2Qe/18stQOXk9IhQ4yQqDUVDXa2jpgr7rjv1jadcmdQlCAoWt/3oBFyDxGPi TS1up5YsSx5d1IeLMuC1k1dXp5wPHYmWtb4uUBLyTLWS5kEIuxu2FQRRwU+bzIpvrss2 dpQY83zGERKUu22IltoRw84OrbZe+EAZ3AMLw+dT0XBuOY7xXdJNC5r3QYhWb31m44X4 ljc0SkS4NZzeRtaRWxUEaPakNkiKlwCDpxKxZAo5G+H6MS7+sZ5bMymUEGliXYx4WxEx tY1FRNh5eIpyBe8gPcwhm47NtgtuOtj1+53E96R+B6bS517Ov9NRRZNQMIJGOukAGw3/ pEWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=7GTu70fg1PgxLGBVvkuQM7da8bHb6cVBgqSUTj6Qovo=; b=Wr51eGGIUsjPxnjHB/wPh0P2/E9sPjRBSUo0fKdLhJ9NWlAdWniv5NXSsVB7HyJrNE fI51uotztDQi/gMluM+tfCZsBDEBIC1bpPiWMYTH12ZZws4PvVBif+RBkgzTLaWTS0Uf vAy86vd3Nvvbv/wLE83pmH5jDCC+thcQkPm0BRB6DUhYLowVv2PFYpzPzU+OK7ecZOaB xyz7zGJDS92j30mdNfM0IagjbhSJ/LNGRJ/uXg6vwlAkWd/y84tCX4Fv56K2+F6DpYh4 4m0YMxmsMDCHBHqAHD5cRX9W7V9FAoJjZ+EGbqaF2k4RSjp5ecK/2rPGOFW9eeBWX4VQ sMQA== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 91si1425396ioi.126.2017.08.11.11.05.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Aug 2017 11:05:29 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dgEHI-0002ct-TR; Fri, 11 Aug 2017 18:03:20 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dgEHH-0002bi-Ow for xen-devel@lists.xen.org; Fri, 11 Aug 2017 18:03:19 +0000 Received: from [85.158.143.35] by server-6.bemta-6.messagelabs.com id 08/25-03937-761FD895; Fri, 11 Aug 2017 18:03:19 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrELMWRWlGSWpSXmKPExsVysyfVTTftY2+ kwfy7qhZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa0brqtcsBYv5K761nmdvYFzI28XIxSEksJlR YsbrDYwQzmlGickTNzJ3MXJysAloStz5/IkJxBYRkJa49vkyI4jNLBAn8X5RIwuILSzgKvGnf woriM0ioCrx4vYlsHpeAUuJi+smgsUlBOQldrVdBLI5ODiB4nMuy4KEhQQsJLb/W8c2gZF7AS PDKkaN4tSistQiXWMDvaSizPSMktzEzBxdQwMzvdzU4uLE9NScxKRiveT83E2MQP8yAMEOxr9 rAw8xSnIwKYnyJvj0RgrxJeWnVGYkFmfEF5XmpBYfYpTh4FCS4I1/D5QTLEpNT61Iy8wBBhpM WoKDR0mEV+IDUJq3uCAxtzgzHSJ1ilGX49WE/9+YhFjy8vNSpcR5eUCKBECKMkrz4EbAgv4So 6yUMC8j0FFCPAWpRbmZJajyrxjFORiVhHlTQS7hycwrgdv0CugIJqAj+nzAjihJREhJNTC2zT c5u2c3pxz3zx3Nq9fc9ov44edd6ZDwXPhk2ZLaFO2iU/uP/PuUL//R+nPb7O5f52IXiQptuGr 8zW1h7b18EX+W20r7Uu5WHMvr+V3rp8A2+dy+cyci7Ksr/Mz4dq7vzlzAlXPWobfxcc/EFY7d +VPaPwfVRZQ/ORNqGabB533cMUdmTo4SS3FGoqEWc1FxIgDMpPZAdQIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-11.tower-21.messagelabs.com!1502474598!74420351!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 22997 invoked from network); 11 Aug 2017 18:03:18 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-11.tower-21.messagelabs.com with SMTP; 11 Aug 2017 18:03:18 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E2F1B164F; Fri, 11 Aug 2017 11:03:17 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F2DE83F577; Fri, 11 Aug 2017 11:03:16 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 11 Aug 2017 19:02:56 +0100 Message-Id: <20170811180257.5493-11-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170811180257.5493-1-julien.grall@arm.com> References: <20170811180257.5493-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 10/11] xen/arm: Move sysregs.h in arm64 sub-directory X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" sysregs.h contains only code protected by #ifdef CONFIG_ARM_64. Move it in arm64 sub-directory to reflect that and remove the #ifdef. At the same time, fixup the guards. Signed-off-by: Julien Grall --- xen/include/asm-arm/arm64/processor.h | 2 ++ xen/include/asm-arm/{ => arm64}/sysregs.h | 10 +++------- xen/include/asm-arm/processor.h | 1 - 3 files changed, 5 insertions(+), 8 deletions(-) rename xen/include/asm-arm/{ => arm64}/sysregs.h (98%) diff --git a/xen/include/asm-arm/arm64/processor.h b/xen/include/asm-arm/arm64/processor.h index 24f836b023..c18ab7203d 100644 --- a/xen/include/asm-arm/arm64/processor.h +++ b/xen/include/asm-arm/arm64/processor.h @@ -3,6 +3,8 @@ #include +#include + #ifndef __ASSEMBLY__ /* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */ diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/arm64/sysregs.h similarity index 98% rename from xen/include/asm-arm/sysregs.h rename to xen/include/asm-arm/arm64/sysregs.h index 887368e248..084d2a1e5d 100644 --- a/xen/include/asm-arm/sysregs.h +++ b/xen/include/asm-arm/arm64/sysregs.h @@ -1,7 +1,5 @@ -#ifndef __ASM_ARM_SYSREGS_H -#define __ASM_ARM_SYSREGS_H - -#ifdef CONFIG_ARM_64 +#ifndef __ASM_ARM_ARM64_SYSREGS_H +#define __ASM_ARM_ARM64_SYSREGS_H #include @@ -168,9 +166,7 @@ #define ICH_AP1R2_EL2 __AP1Rx_EL2(2) #define ICH_AP1R3_EL2 __AP1Rx_EL2(3) -#endif - -#endif +#endif /* _ASM_ARM_ARM64_SYSREGS_H */ /* * Local variables: diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 855ded1b07..9eacb1be29 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -2,7 +2,6 @@ #define __ASM_ARM_PROCESSOR_H #include -#include #ifndef __ASSEMBLY__ #include #endif From patchwork Fri Aug 11 18:02:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 109906 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1250066qge; Fri, 11 Aug 2017 11:05:22 -0700 (PDT) X-Received: by 10.36.113.2 with SMTP id n2mr16875347itc.38.1502474722426; Fri, 11 Aug 2017 11:05:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502474722; cv=none; d=google.com; s=arc-20160816; b=a3+s9MhORzZYw/+M7AL0k6EfPRj4hyYJNctPRQ9VPYUXUWT6RwsBEmgym5PC81ezOD cy2zBQpjYKn5BTf2NMYc55k9x+t4AQy1ox/851E+jiNbv+kVaJACZM6rJSz7ZtQZu2mQ tlbFU3h2bpzPmYtKfE6/Bf+Kp1bdiyEcA930pi2AhkD4Uer704tFNBTXvA0NGyKYhCcM YuVBkI2BLRY3gG4h4nFTkcgRFQxnjeoFTm1kQkP0kfmxF5iTxOGKUNpNfPw6hrQq1v7p 7sOd8P7T6LOGG9VhzyCHNKnCRVqGfQlX9teK5dufSTabnFIvniT7Y5a/jLkDLjYTk3SC 4SYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=7OxuVEQ/TDwnxfTTuTPhqtjqP2ZAKZLjotBQioUDUf0=; b=by8PlZK4HqzoU9bk39aTuxA0a73pJ6QZQakypPOB00BYjPjJoKAvEkC+8bIZgguNgZ +F9vegiudRRFhXzru8EKNxw2OVXl+HjXiFTQuSbpCJ0+R8msTVdQ9b4o2G2mOkjb6tgz Bi9f4U1+HJJRQDyiCjiaBv6ou8w6Fmz41XXXg7jNIe3jMIeDOpbbDgzivysjecRbk2CB d2j/1YsCPLdc4Jseqy5PcrVjSCcr92cxP89QmG9a8SFXWKzAlbOE7JjOs/JxxeVbRciI DAiSwt5pc+xF2It44VuPwxC6G7JDK+ALZSKDEsx3NbsNuD0eD97nTqImSFWf5fT67Jts RwQA== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id n8si1477149iod.0.2017.08.11.11.05.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Aug 2017 11:05:22 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dgEHK-0002dl-45; Fri, 11 Aug 2017 18:03:22 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dgEHJ-0002cI-4W for xen-devel@lists.xen.org; Fri, 11 Aug 2017 18:03:21 +0000 Received: from [85.158.137.68] by server-12.bemta-3.messagelabs.com id 0E/E3-01862-861FD895; Fri, 11 Aug 2017 18:03:20 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrILMWRWlGSWpSXmKPExsVysyfVTTf9Y2+ kwYxP5hZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8bpw0+YCpqlKpoXT2NpYNwk1sXIxSEksJlR 4siRtUwQzmlGicunZzB3MXJysAloStz5/IkJxBYRkJa49vkyI4jNLBAn8X5RIwuILSxgLfFtz 3l2EJtFQFViV3MfWD2vgKXEo7O/wOolBOQldrVdZO1i5ODgBIrPuSwLEhYSsJDY/m8d2wRG7g WMDKsY1YtTi8pSi3SN9ZKKMtMzSnITM3N0DQ2M9XJTi4sT01NzEpOK9ZLzczcxAr3LAAQ7GJu /OB1ilORgUhLlTfDpjRTiS8pPqcxILM6ILyrNSS0+xCjDwaEkwfvkPVBOsCg1PbUiLTMHGGYw aQkOHiUR3pAPQGne4oLE3OLMdIjUKUZdjlcT/n9jEmLJy89LlRLn5QEpEgApyijNgxsBC/lLj LJSwryMQEcJ8RSkFuVmlqDKv2IU52BUEuaNAZnCk5lXArfpFdARTEBH9PmAHVGSiJCSamC85t RgrO/OtuRCsU9KqfKZ8MdvHgntNK57F7nQ0Xfajy+xF9bYnjoU8jmLs4rzZ8Whl1yBsR6zWt4 ondSUivB+z+lu2nXTsOqs97HEYjXxNedPn/rFsutlw5rUTJesrVc4++rj1v2My37TH6hq37+e U2I9e9mEEnnm01V2pWIt0+0dmNzfNCixFGckGmoxFxUnAgD4LTaedAIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-15.tower-31.messagelabs.com!1502474599!105600285!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 20283 invoked from network); 11 Aug 2017 18:03:19 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-15.tower-31.messagelabs.com with SMTP; 11 Aug 2017 18:03:19 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1E93C1650; Fri, 11 Aug 2017 11:03:19 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2EB9B3F577; Fri, 11 Aug 2017 11:03:18 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 11 Aug 2017 19:02:57 +0100 Message-Id: <20170811180257.5493-12-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170811180257.5493-1-julien.grall@arm.com> References: <20170811180257.5493-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 11/11] xen/arm: Limit the scope of cpregs.h X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Currently, cpregs.h is included in pretty much every files even for arm64. However, the only use for arm64 is when emulating co-processors. For arm32, cpregs.h rely on the presence of processor.h (define *_SYSREG helpers). So move the inclusion in asm-arm/arm32/processor.h. cpregs.h will also be directly included in the co-processors emulation to accomodate arm64. Signed-off-by: Julien Grall --- xen/arch/arm/smp.c | 1 - xen/arch/arm/vcpreg.c | 1 + xen/arch/arm/vgic-v3.c | 1 + xen/arch/arm/vtimer.c | 2 ++ xen/include/asm-arm/arm32/processor.h | 2 ++ xen/include/asm-arm/percpu.h | 1 - xen/include/asm-arm/processor.h | 1 - 7 files changed, 6 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/smp.c b/xen/arch/arm/smp.c index e7df0874d6..554f4992e6 100644 --- a/xen/arch/arm/smp.c +++ b/xen/arch/arm/smp.c @@ -1,6 +1,5 @@ #include #include -#include #include #include #include diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index f3b08403fb..e363183ba8 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -18,6 +18,7 @@ #include +#include #include #include #include diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index cbeac28b28..a0cf993d13 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index 9c7e8f441c..0460962f08 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -29,6 +30,7 @@ #include #include #include +#include /* * Check if regs is allowed access, user_gate is tail end of a diff --git a/xen/include/asm-arm/arm32/processor.h b/xen/include/asm-arm/arm32/processor.h index 68cc82147e..fb330812af 100644 --- a/xen/include/asm-arm/arm32/processor.h +++ b/xen/include/asm-arm/arm32/processor.h @@ -1,6 +1,8 @@ #ifndef __ASM_ARM_ARM32_PROCESSOR_H #define __ASM_ARM_ARM32_PROCESSOR_H +#include + #define ACTLR_CAXX_SMP (1<<6) #ifndef __ASSEMBLY__ diff --git a/xen/include/asm-arm/percpu.h b/xen/include/asm-arm/percpu.h index 7968532462..cdf64e0f77 100644 --- a/xen/include/asm-arm/percpu.h +++ b/xen/include/asm-arm/percpu.h @@ -4,7 +4,6 @@ #ifndef __ASSEMBLY__ #include -#include #if defined(CONFIG_ARM_32) # include #elif defined(CONFIG_ARM_64) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 9eacb1be29..51ce802063 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -1,7 +1,6 @@ #ifndef __ASM_ARM_PROCESSOR_H #define __ASM_ARM_PROCESSOR_H -#include #ifndef __ASSEMBLY__ #include #endif