From patchwork Wed May 13 10:29:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 200668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D56BC2D0FA for ; Wed, 13 May 2020 10:30:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E46720753 for ; Wed, 13 May 2020 10:30:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732472AbgEMKac (ORCPT ); Wed, 13 May 2020 06:30:32 -0400 Received: from foss.arm.com ([217.140.110.172]:42576 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729731AbgEMKab (ORCPT ); Wed, 13 May 2020 06:30:31 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 433A1D6E; Wed, 13 May 2020 03:30:31 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0EFAC3F305; Wed, 13 May 2020 03:30:29 -0700 (PDT) From: Andre Przywara To: Rob Herring , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland , Marc Zyngier Subject: [PATCH v3 01/20] dt-bindings: arm: gic: Allow combining arm, gic-400 compatible strings Date: Wed, 13 May 2020 11:29:57 +0100 Message-Id: <20200513103016.130417-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200513103016.130417-1-andre.przywara@arm.com> References: <20200513103016.130417-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The arm,gic-400 compatible is probably the best matching string for the GIC in most modern SoCs, but was only introduced later into the kernel. For historic reasons and to keep compatibility, some SoC DTs were thus using a combination of this name and one of the older strings, which currently the binding denies. Add a stanza to the DT binding to allow "arm,gic-400", followed by either "arm,cortex-a15-gic" or "arm,cortex-a7-gic". This fixes binding compliance for quite some SoC .dtsi files in the kernel tree. Signed-off-by: Andre Przywara --- .../devicetree/bindings/interrupt-controller/arm,gic.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml index 9a47820ef346..3ab258c82930 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml @@ -39,6 +39,12 @@ properties: - qcom,msm-8660-qgic - qcom,msm-qgic2 + - items: + - const: arm,gic-400 + - enum: + - arm,cortex-a15-gic + - arm,cortex-a7-gic + - items: - const: arm,arm1176jzf-devchip-gic - const: arm,arm11mp-gic From patchwork Wed May 13 10:29:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 200667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51BA6C2D0FA for ; Wed, 13 May 2020 10:30:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 391C5206CC for ; Wed, 13 May 2020 10:30:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732542AbgEMKae (ORCPT ); Wed, 13 May 2020 06:30:34 -0400 Received: from foss.arm.com ([217.140.110.172]:42590 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729731AbgEMKae (ORCPT ); Wed, 13 May 2020 06:30:34 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DCC611FB; Wed, 13 May 2020 03:30:33 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C2FE93F305; Wed, 13 May 2020 03:30:32 -0700 (PDT) From: Andre Przywara To: Rob Herring , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland Subject: [PATCH v3 03/20] arm64: dts: arm: fvp: Move fixed devices out of bus node Date: Wed, 13 May 2020 11:29:59 +0100 Message-Id: <20200513103016.130417-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200513103016.130417-1-andre.przywara@arm.com> References: <20200513103016.130417-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The devicetree compiler complains when DT nodes without a reg property live inside a (simple) bus node: Warning (simple_bus_reg): Node /bus@8000000/motherboard-bus/v2m_refclk32khz missing or empty reg/ranges property Move the fixed clocks, the fixed regulator, and the config bus subtree to the root node, since they do not depend on any busses. Signed-off-by: Andre Przywara --- .../boot/dts/arm/rtsm_ve-motherboard.dtsi | 136 +++++++++--------- 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index d1bfa62ca073..f61e313ab1a4 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -8,6 +8,74 @@ * VEMotherBoard.lisa */ / { + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + v2m_fixed_3v3: v2m-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 63500000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + reset { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + bus@8000000 { motherboard { arm,v2m-memory-map = "rs1"; @@ -30,27 +98,6 @@ interrupts = <15>; }; - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - iofpga@300000000 { compatible = "simple-bus"; #address-cells = <1>; @@ -198,53 +245,6 @@ }; }; }; - - v2m_fixed_3v3: v2m-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 63500000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; }; }; }; From patchwork Wed May 13 10:30:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 200666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DD1CC2D0FC for ; Wed, 13 May 2020 10:30:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DE2F1206CC for ; Wed, 13 May 2020 10:30:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732579AbgEMKah (ORCPT ); Wed, 13 May 2020 06:30:37 -0400 Received: from foss.arm.com ([217.140.110.172]:42606 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729731AbgEMKah (ORCPT ); Wed, 13 May 2020 06:30:37 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9F3FB1FB; Wed, 13 May 2020 03:30:36 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 832E53F305; Wed, 13 May 2020 03:30:35 -0700 (PDT) From: Andre Przywara To: Rob Herring , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland Subject: [PATCH v3 05/20] arm64: dts: arm: foundation: Move fixed clocks out of bus node Date: Wed, 13 May 2020 11:30:01 +0100 Message-Id: <20200513103016.130417-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200513103016.130417-1-andre.przywara@arm.com> References: <20200513103016.130417-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The devicetree compiler complains when DT nodes without a reg property live inside a (simple) bus node: Warning (simple_bus_reg): Node /bus@8000000/v2m_refclk32khz missing or empty reg/ranges property Move the fixed clocks to the root node, since they do not depend on any busses. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/arm/foundation-v8.dtsi | 42 +++++++++++----------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index e26b492795c5..e5b8a9b5c410 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -92,6 +92,27 @@ timeout-sec = <30>; }; + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + bus@8000000 { compatible = "arm,vexpress,v2m-p1", "simple-bus"; arm,v2m-memory-map = "rs1"; @@ -157,27 +178,6 @@ interrupts = <15>; }; - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - iofpga@300000000 { compatible = "simple-bus"; #address-cells = <1>; From patchwork Wed May 13 10:30:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 200665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CCF5C2D0FA for ; Wed, 13 May 2020 10:30:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 80FEE206E5 for ; Wed, 13 May 2020 10:30:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732623AbgEMKak (ORCPT ); Wed, 13 May 2020 06:30:40 -0400 Received: from foss.arm.com ([217.140.110.172]:42620 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729731AbgEMKaj (ORCPT ); Wed, 13 May 2020 06:30:39 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6017D1FB; Wed, 13 May 2020 03:30:39 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2BD853F305; Wed, 13 May 2020 03:30:38 -0700 (PDT) From: Andre Przywara To: Rob Herring , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland , Marc Zyngier Subject: [PATCH v3 07/20] arm64: dts: juno: Fix mem-timer Date: Wed, 13 May 2020 11:30:03 +0100 Message-Id: <20200513103016.130417-8-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200513103016.130417-1-andre.przywara@arm.com> References: <20200513103016.130417-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Juno's mem-timer DT node was not fully compliant with the DT binding, which has certain expectation about child nodes and their size and address cells values. Use a cell size of 1, as the binding requests, and spell out the ranges property to be binding compliant. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/arm/juno-base.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index f5889281545f..3feefd61eb76 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -11,14 +11,14 @@ compatible = "arm,armv7-timer-mem"; reg = <0x0 0x2a810000 0x0 0x10000>; clock-frequency = <50000000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x2a820000 0x20000>; status = "disabled"; frame@2a830000 { frame-number = <1>; interrupts = ; - reg = <0x0 0x2a830000 0x0 0x10000>; + reg = <0x10000 0x10000>; }; }; From patchwork Wed May 13 10:30:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 200664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83CB6C2D0FA for ; Wed, 13 May 2020 10:30:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6D3F7206E5 for ; Wed, 13 May 2020 10:30:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732641AbgEMKan (ORCPT ); Wed, 13 May 2020 06:30:43 -0400 Received: from foss.arm.com ([217.140.110.172]:42636 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729731AbgEMKam (ORCPT ); Wed, 13 May 2020 06:30:42 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3AEC71FB; Wed, 13 May 2020 03:30:42 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 068FA3F305; Wed, 13 May 2020 03:30:40 -0700 (PDT) From: Andre Przywara To: Rob Herring , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland , Marc Zyngier Subject: [PATCH v3 09/20] arm64: dts: arm: juno: Fix GIC child nodes Date: Wed, 13 May 2020 11:30:05 +0100 Message-Id: <20200513103016.130417-10-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200513103016.130417-1-andre.przywara@arm.com> References: <20200513103016.130417-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The GIC DT nodes for the Juno boards were not fully compliant with the DT binding, which has certain expectations about child nodes and their size and address cells values. Use smaller #address-cells and #size-cells values, as the binding requests, and adjust the reg properties accordingly. This requires adjusting the interrupt nexus nodes as well, as one field of the interrupt-map property depends on the GIC's address-size. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/arm/juno-base.dtsi | 50 +++++++++++++------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 3feefd61eb76..dfb2fef37030 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -74,35 +74,35 @@ <0x0 0x2c02f000 0 0x2000>, <0x0 0x2c04f000 0 0x2000>, <0x0 0x2c06f000 0 0x2000>; - #address-cells = <2>; + #address-cells = <1>; #interrupt-cells = <3>; - #size-cells = <2>; + #size-cells = <1>; interrupt-controller; interrupts = ; - ranges = <0 0 0 0x2c1c0000 0 0x40000>; + ranges = <0 0 0x2c1c0000 0x40000>; v2m_0: v2m@0 { compatible = "arm,gic-v2m-frame"; msi-controller; - reg = <0 0 0 0x10000>; + reg = <0 0x10000>; }; v2m@10000 { compatible = "arm,gic-v2m-frame"; msi-controller; - reg = <0 0x10000 0 0x10000>; + reg = <0x10000 0x10000>; }; v2m@20000 { compatible = "arm,gic-v2m-frame"; msi-controller; - reg = <0 0x20000 0 0x10000>; + reg = <0x20000 0x10000>; }; v2m@30000 { compatible = "arm,gic-v2m-frame"; msi-controller; - reg = <0 0x30000 0 0x10000>; + reg = <0x30000 0x10000>; }; }; @@ -546,10 +546,10 @@ <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic 0 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; msi-parent = <&v2m_0>; status = "disabled"; iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */ @@ -813,19 +813,19 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 15>; - interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <0 0 1 &gic 0 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <0 0 2 &gic 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <0 0 3 &gic 0 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, - <0 0 4 &gic 0 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, - <0 0 5 &gic 0 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, - <0 0 6 &gic 0 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, - <0 0 7 &gic 0 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, - <0 0 8 &gic 0 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, - <0 0 9 &gic 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, - <0 0 10 &gic 0 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, - <0 0 11 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <0 0 12 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <0 0 1 &gic 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <0 0 2 &gic 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <0 0 3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <0 0 4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <0 0 5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <0 0 6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <0 0 7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <0 0 8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <0 0 9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; }; site2: tlx@60000000 { @@ -835,6 +835,6 @@ ranges = <0 0 0x60000000 0x10000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0>; - interrupt-map = <0 0 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; }; }; From patchwork Wed May 13 10:30:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 200663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70F0CC2D0FC for ; Wed, 13 May 2020 10:30:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 533AB206D6 for ; Wed, 13 May 2020 10:30:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732652AbgEMKap (ORCPT ); Wed, 13 May 2020 06:30:45 -0400 Received: from foss.arm.com ([217.140.110.172]:42650 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729731AbgEMKap (ORCPT ); Wed, 13 May 2020 06:30:45 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 165621FB; Wed, 13 May 2020 03:30:45 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D66463F305; Wed, 13 May 2020 03:30:43 -0700 (PDT) From: Andre Przywara To: Rob Herring , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland , Marc Zyngier Subject: [PATCH v3 11/20] arm64: dts: arm: Fix ITS node names and #msi-cells Date: Wed, 13 May 2020 11:30:07 +0100 Message-Id: <20200513103016.130417-12-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200513103016.130417-1-andre.przywara@arm.com> References: <20200513103016.130417-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The GIC ITS nodes in the fastmodel DTS files were not fully binding compliant. Use one of the allowed node names, also add the required #msi-cells property for the older model. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi | 3 ++- arch/arm64/boot/dts/arm/fvp-base-revc.dts | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi index 906f51935b36..e4a3c7dbcc20 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi @@ -19,9 +19,10 @@ <0x0 0x2c02f000 0x0 0x2000>; interrupts = ; - its: its@2f020000 { + its: msi-controller@2f020000 { compatible = "arm,gic-v3-its"; msi-controller; + #msi-cells = <1>; reg = <0x20000 0x20000>; }; }; diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts index 66381d89c1ce..0cf96ceff431 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts @@ -126,7 +126,7 @@ <0x0 0x2c02f000 0 0x2000>; // GICV interrupts = ; - its: its@2f020000 { + its: msi-controller@2f020000 { #msi-cells = <1>; compatible = "arm,gic-v3-its"; reg = <0x0 0x2f020000 0x0 0x20000>; // GITS From patchwork Wed May 13 10:30:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 200662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC847C2D0FC for ; Wed, 13 May 2020 10:30:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D63BF20769 for ; Wed, 13 May 2020 10:30:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732670AbgEMKas (ORCPT ); Wed, 13 May 2020 06:30:48 -0400 Received: from foss.arm.com ([217.140.110.172]:42666 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729731AbgEMKas (ORCPT ); Wed, 13 May 2020 06:30:48 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AF6C811B3; Wed, 13 May 2020 03:30:47 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 961103F305; Wed, 13 May 2020 03:30:46 -0700 (PDT) From: Andre Przywara To: Rob Herring , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland Subject: [PATCH v3 13/20] arm64: dts: arm: Fix serial node names Date: Wed, 13 May 2020 11:30:09 +0100 Message-Id: <20200513103016.130417-14-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200513103016.130417-1-andre.przywara@arm.com> References: <20200513103016.130417-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The UARTs for all Arm Ltd. boards were using "uart" as their node name stub. Replace that with the required "serial" string, to comply with the PL011 DT binding. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 8 ++++---- arch/arm64/boot/dts/arm/foundation-v8.dtsi | 8 ++++---- arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +- arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 8 ++++---- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index d4d88ce996a5..f4a65d693f15 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -316,7 +316,7 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; - v2m_serial0: uart@90000 { + v2m_serial0: serial@90000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; @@ -324,7 +324,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial1: uart@a0000 { + v2m_serial1: serial@a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; @@ -332,7 +332,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial2: uart@b0000 { + v2m_serial2: serial@b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; @@ -340,7 +340,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial3: uart@c0000 { + v2m_serial3: serial@c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index 63efb88595d4..e226c5e080c2 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -189,7 +189,7 @@ reg = <0x010000 0x1000>; }; - v2m_serial0: uart@90000 { + v2m_serial0: serial@90000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; @@ -197,7 +197,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial1: uart@a0000 { + v2m_serial1: serial@a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; @@ -205,7 +205,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial2: uart@b0000 { + v2m_serial2: serial@b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; @@ -213,7 +213,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial3: uart@c0000 { + v2m_serial3: serial@c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 2b34661d426c..ee860d539395 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -729,7 +729,7 @@ }; }; - soc_uart0: uart@7ff80000 { + soc_uart0: serial@7ff80000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0x7ff80000 0x0 0x1000>; interrupts = ; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index f61e313ab1a4..b81651b1890a 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -158,7 +158,7 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; - v2m_serial0: uart@90000 { + v2m_serial0: serial@90000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; @@ -166,7 +166,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial1: uart@a0000 { + v2m_serial1: serial@a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; @@ -174,7 +174,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial2: uart@b0000 { + v2m_serial2: serial@b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; @@ -182,7 +182,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial3: uart@c0000 { + v2m_serial3: serial@c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; From patchwork Wed May 13 10:30:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 200661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FC53C2D0FD for ; Wed, 13 May 2020 10:30:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ED1D024927 for ; Wed, 13 May 2020 10:30:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732694AbgEMKav (ORCPT ); Wed, 13 May 2020 06:30:51 -0400 Received: from foss.arm.com ([217.140.110.172]:42682 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732741AbgEMKau (ORCPT ); Wed, 13 May 2020 06:30:50 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 549651FB; Wed, 13 May 2020 03:30:50 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3B3133F305; Wed, 13 May 2020 03:30:49 -0700 (PDT) From: Andre Przywara To: Rob Herring , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland Subject: [PATCH v3 15/20] arm64: dts: arm: Fix bus node names Date: Wed, 13 May 2020 11:30:11 +0100 Message-Id: <20200513103016.130417-16-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200513103016.130417-1-andre.przywara@arm.com> References: <20200513103016.130417-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Most Arm Ltd. boards are employing a layered bus structure, to map the hardware design (SoC, motherboard, IOFPGA) and structure the DTs. The "simple-bus" nodes only allow a limited set of node names. Switch to use *-bus to be binding compliant. This relies on a pending dt-schema.git fix for now: https://github.com/devicetree-org/dt-schema/pull/38 Signed-off-by: Andre Przywara --- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 4 ++-- arch/arm64/boot/dts/arm/foundation-v8.dtsi | 2 +- arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +- arch/arm64/boot/dts/arm/juno-motherboard.dtsi | 4 ++-- arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi | 4 ++-- arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 4 ++-- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index f4a65d693f15..f5c8f07b4918 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -174,7 +174,7 @@ }; bus@8000000 { - motherboard { + motherboard-bus { model = "V2M-P1"; arm,hbi = <0x190>; arm,vexpress,site = <0>; @@ -220,7 +220,7 @@ port1-otg; }; - iofpga@300000000 { + iofpga-bus@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index e226c5e080c2..05ae893d1b2e 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -178,7 +178,7 @@ interrupts = <15>; }; - iofpga@300000000 { + iofpga-bus@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index ee860d539395..bd4e0b15f9c8 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -828,7 +828,7 @@ <0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; }; - site2: tlx@60000000 { + site2: tlx-bus@60000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi index f3279327a665..eeee51f1251b 100644 --- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi @@ -92,7 +92,7 @@ }; bus@8000000 { - motherboard { + motherboard-bus { compatible = "arm,vexpress,v2p-p1", "simple-bus"; #address-cells = <2>; /* SMB chipselect number and offset */ #size-cells = <1>; @@ -133,7 +133,7 @@ vddvario-supply = <&mb_fixed_3v3>; }; - iofpga@300000000 { + iofpga-bus@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi index 350cbf17e8b4..b917d9d3f1c4 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi @@ -6,10 +6,10 @@ */ / { bus@8000000 { - motherboard { + motherboard-bus { arm,v2m-memory-map = "rs2"; - iofpga@300000000 { + iofpga-bus@300000000 { virtio-p9@140000 { compatible = "virtio,mmio"; reg = <0x140000 0x200>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index b81651b1890a..001a0a3c7f66 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -77,7 +77,7 @@ }; bus@8000000 { - motherboard { + motherboard-bus { arm,v2m-memory-map = "rs1"; compatible = "arm,vexpress,v2m-p1", "simple-bus"; #address-cells = <2>; /* SMB chipselect number and offset */ @@ -98,7 +98,7 @@ interrupts = <15>; }; - iofpga@300000000 { + iofpga-bus@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From patchwork Wed May 13 10:30:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 200660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDE75C2D0FA for ; Wed, 13 May 2020 10:30:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9E43D206D6 for ; Wed, 13 May 2020 10:30:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732759AbgEMKay (ORCPT ); Wed, 13 May 2020 06:30:54 -0400 Received: from foss.arm.com ([217.140.110.172]:42700 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732741AbgEMKax (ORCPT ); Wed, 13 May 2020 06:30:53 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EDFED11B3; Wed, 13 May 2020 03:30:52 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D467B3F305; Wed, 13 May 2020 03:30:51 -0700 (PDT) From: Andre Przywara To: Rob Herring , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland Subject: [PATCH v3 17/20] arm64: dts: arm: Fix VExpress LED names Date: Wed, 13 May 2020 11:30:13 +0100 Message-Id: <20200513103016.130417-18-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200513103016.130417-1-andre.przywara@arm.com> References: <20200513103016.130417-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The common LED binding wants the LED node names to start with led- and then have just a single number. Changing the naming for the 8 user LEDs from using user to led-. Also there is no default-trigger named "mmc0" in the kernel, so use the more generic "disk-activity". Signed-off-by: Andre Przywara --- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index f5c8f07b4918..e6308fb76183 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -51,49 +51,49 @@ leds { compatible = "gpio-leds"; - user1 { + led-1 { label = "v2m:green:user1"; gpios = <&v2m_led_gpios 0 0>; linux,default-trigger = "heartbeat"; }; - user2 { + led-2 { label = "v2m:green:user2"; gpios = <&v2m_led_gpios 1 0>; linux,default-trigger = "disk-activity"; }; - user3 { + led-3 { label = "v2m:green:user3"; gpios = <&v2m_led_gpios 2 0>; linux,default-trigger = "cpu0"; }; - user4 { + led-4 { label = "v2m:green:user4"; gpios = <&v2m_led_gpios 3 0>; linux,default-trigger = "cpu1"; }; - user5 { + led-5 { label = "v2m:green:user5"; gpios = <&v2m_led_gpios 4 0>; linux,default-trigger = "cpu2"; }; - user6 { + led-6 { label = "v2m:green:user6"; gpios = <&v2m_led_gpios 5 0>; linux,default-trigger = "cpu3"; }; - user7 { + led-7 { label = "v2m:green:user7"; gpios = <&v2m_led_gpios 6 0>; linux,default-trigger = "cpu4"; }; - user8 { + led-8 { label = "v2m:green:user8"; gpios = <&v2m_led_gpios 7 0>; linux,default-trigger = "cpu5"; From patchwork Wed May 13 10:30:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 200659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BA15CA90AF for ; Wed, 13 May 2020 10:30:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3DF27206D6 for ; Wed, 13 May 2020 10:30:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732780AbgEMKa4 (ORCPT ); Wed, 13 May 2020 06:30:56 -0400 Received: from foss.arm.com ([217.140.110.172]:42710 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732741AbgEMKa4 (ORCPT ); Wed, 13 May 2020 06:30:56 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E39921FB; Wed, 13 May 2020 03:30:55 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7A1113F305; Wed, 13 May 2020 03:30:54 -0700 (PDT) From: Andre Przywara To: Rob Herring , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org Subject: [PATCH v3 19/20] dt-bindings: mali-midgard: Allow dma-coherent Date: Wed, 13 May 2020 11:30:15 +0100 Message-Id: <20200513103016.130417-20-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200513103016.130417-1-andre.przywara@arm.com> References: <20200513103016.130417-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the boolean dma-coherent property to the list of allowed properties, since some boards (Arm Juno) integrate the GPU this way. Signed-off-by: Andre Przywara --- Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml index 0407e45eb8c4..5d7165385e1f 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml @@ -87,6 +87,8 @@ properties: "#cooling-cells": const: 2 + dma-coherent: true + required: - compatible - reg