From patchwork Sun May 3 15:42:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 201187 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F155DC28CBC for ; Sun, 3 May 2020 15:42:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CF02821835 for ; Sun, 3 May 2020 15:42:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588520558; bh=cT0OetYZ/YUt8aV+lPE7R4oJyBHx66QFKj3UJB9PhuY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=EDhyKgFGwik6A64Y8FBPRU4R8L8wCkpl9i+gsBZkZWgjDgYjom6sRHHw6f2XLkZcd j99pG48z4hIeYCh1YUuk4YiL3c3+cUdBbvv8+69UJmV5McUXYsPyNpm3KIF3rTiS0f LqyZt7vw5f1silHWG2tV6i/aNYMLu1xjDpiHgDtQ= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728807AbgECPmi (ORCPT ); Sun, 3 May 2020 11:42:38 -0400 Received: from mail.kernel.org ([198.145.29.99]:57488 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728677AbgECPmh (ORCPT ); Sun, 3 May 2020 11:42:37 -0400 Received: from localhost.localdomain (unknown [157.51.190.160]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8614520757; Sun, 3 May 2020 15:42:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588520557; bh=cT0OetYZ/YUt8aV+lPE7R4oJyBHx66QFKj3UJB9PhuY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JRr5HCXvisbwPBU9GxOBgPMtkgZNsgRSGp3f289RS2bWJu9madzFQgiEpQfGQ43vJ Xms/j9mxHcLO8iftdnOWJTcwPfXKJgj0FsDStPFlt3gncly7PDXIY9AtclNXerygx/ ahNoXPrtK20zj855RKIvWcxgQtQOOHWSVgr3C5jM= From: mani@kernel.org To: robh+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com Cc: devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 2/6] ARM: dts: stm32: Add missing pinctrl entries for STM32MP15 Date: Sun, 3 May 2020 21:12:11 +0530 Message-Id: <20200503154215.23654-3-mani@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200503154215.23654-1-mani@kernel.org> References: <20200503154215.23654-1-mani@kernel.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Manivannan Sadhasivam These pinctrl definitions will be used by Stinger96/IoTBox boards from Shiratech. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 64 ++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index aeddcaadb829..858c83038e5a 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1519,6 +1519,30 @@ }; }; + usart2_pins_b: usart2-1 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_sleep_pins_b: usart2-sleep-1 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; + usart3_pins_a: usart3-0 { pins1 { pinmux = ; /* USART3_TX */ @@ -1558,6 +1582,19 @@ }; }; + uart4_pins_c: uart4-2 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + uart7_pins_a: uart7-0 { pins1 { pinmux = ; /* UART4_TX */ @@ -1573,6 +1610,19 @@ }; }; + uart7_pins_b: uart7-1 { + pins1 { + pinmux = ; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART7_RX */ + bias-disable; + }; + }; + uart8_pins_a: uart8-0 { pins1 { pinmux = ; /* UART8_TX */ @@ -1647,4 +1697,18 @@ bias-disable; }; }; + + spi4_pins_a: spi4-0 { + pins { + pinmux = , /* SPI4_SCK */ + ; /* SPI4_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SPI4_MISO */ + bias-disable; + }; + }; }; From patchwork Sun May 3 15:42:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 201186 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, LOTS_OF_MONEY, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D30B3C28CBC for ; Sun, 3 May 2020 15:42:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A16D8207DD for ; Sun, 3 May 2020 15:42:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588520569; bh=uWNiGByJKk3ntpqr+nIyoYe+iYdSnhAXy65p/6Bw8qU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=0x9AMwx90sbsUHtSpilEQAQNZONvLlowyyPRvtiok1wXTa1zxOSRSS46NWOvLB9SO YKGAlRDEYAwxnjh/ld/J60Xym3V2wil+uyYf4Ab+Xz5pTrfczJZ/n+uMI5U5STZmdx RT6sSU1r7eVAQlVsKkd0og5NuugJkc/YOJUhgtLo= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728837AbgECPmt (ORCPT ); Sun, 3 May 2020 11:42:49 -0400 Received: from mail.kernel.org ([198.145.29.99]:57812 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728677AbgECPms (ORCPT ); Sun, 3 May 2020 11:42:48 -0400 Received: from localhost.localdomain (unknown [157.51.190.160]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id DCCB620836; Sun, 3 May 2020 15:42:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588520567; bh=uWNiGByJKk3ntpqr+nIyoYe+iYdSnhAXy65p/6Bw8qU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=usG2SiTvv8OvQchQ94dUUgvmGqeJuBfpQPqNQA85a+lzWCQ7jRknPT+KbaVO8p6G0 Jq6PkK17DxnI9ZtAQOXBTc4737/7VxzQCukpqs3TlpCtzKLusQSAfvz/PL98AAKDJp VYJexh69r2DZEF8fl4rtqBlldtx5euLM2FTcBP+U= From: mani@kernel.org To: robh+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com Cc: devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 4/6] ARM: dts: stm32: Add Stinger96 board support Date: Sun, 3 May 2020 21:12:13 +0530 Message-Id: <20200503154215.23654-5-mani@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200503154215.23654-1-mani@kernel.org> References: <20200503154215.23654-1-mani@kernel.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Manivannan Sadhasivam Stinger96 is a 96Boards IoT Extended edition board designed and manufactured by Shiratech solutions based on STM32MP1 SoC. Following are the features of this board: * 256MB DDR * 125MB NAND Flash * Onboard BG96 modem * 1x uSD * 2x USB (1 available as external connector and another connected to BG96) * 1x SPI * 1x PCM * 2x UART (apart from serial console) * 2x I2C (apart from one connected to PMIC) Following peripherals are tested and known to work: * BG96 modem * 1x I2C (LS-I2C0) * 1x SPI * 1x UART (LS-UART0) * USB (Only Gadget mode) * uSD More information about this board can be found in Shiratech website: https://www.shiratech-solutions.com/products/stinger96/ Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/stm32mp157a-stinger96.dts | 12 + arch/arm/boot/dts/stm32mp157a-stinger96.dtsi | 342 +++++++++++++++++++ 3 files changed, 355 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-stinger96.dts create mode 100644 arch/arm/boot/dts/stm32mp157a-stinger96.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f43467b02bcd..966b81dfffd6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1030,6 +1030,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-disco.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157a-dk1.dtb \ + stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dts b/arch/arm/boot/dts/stm32mp157a-stinger96.dts new file mode 100644 index 000000000000..249a53877512 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Manivannan Sadhasivam + */ + +/dts-v1/; +#include "stm32mp157a-stinger96.dtsi" + +/ { + model = "Shiratech STM32MP157A Stinger96 board"; + compatible = "shiratech,stm32mp157a-stinger96", "st,stm32mp157"; +}; diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi new file mode 100644 index 000000000000..58275bcf9e26 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Manivannan Sadhasivam + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include +#include + +/ { + aliases { + mmc0 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + serial2 = &usart2; + spi0 = &spi4; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x10000000>; + }; + + led { + compatible = "gpio-leds"; + + led1 { + label = "green:user1"; + gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:user2"; + gpios = <&gpioh 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "green:user3"; + gpios = <&gpioh 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "green:user4"; + gpios = <&gpiof 12 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; +}; + +/* Only headless mode is supported */ +&gpu { + status = "disabled"; +}; + +/* LS-I2C0 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <1000>; + i2c-scl-falling-time-ns = <300>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + v2v9: ldo2 { + regulator-name = "v2v9"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + broken-cd; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +/* LS-SPI0 */ +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins_a>; + cs-gpios = <&gpioe 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* BG96 */ +&usart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_b>; + pinctrl-1 = <&usart2_sleep_pins_b>; + st,hw-flow-ctrl; + status = "okay"; +}; + +/* LS-UART0 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_c>; + st,hw-flow-ctrl; + status = "okay"; +}; + +/* Debug console */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_b>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; From patchwork Sun May 3 15:42:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 201185 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 227B2C28CBC for ; Sun, 3 May 2020 15:43:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0023A20757 for ; Sun, 3 May 2020 15:42:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588520580; bh=OXq9FMct3mDZL6PvVE4nWjIKjobcNyfHQcSwBAqBwVc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=kLv+onKPmHmloVfTo7JgZxIrorODxsTnxDvsr4WSHkE3Q0vTP7CKItqKydY9ecVoo 8cl6ctnKFXJXCCZFMc2Z44HtTrc0aku3x3FzkMKwHcp5ceWtgHhgmAR2I+YuF9n3DO zvXEh7DGd3z+EoZZ/HRqbf2Ef5YvEghCfGSr7c6E= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728865AbgECPm7 (ORCPT ); Sun, 3 May 2020 11:42:59 -0400 Received: from mail.kernel.org ([198.145.29.99]:58046 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728677AbgECPm7 (ORCPT ); Sun, 3 May 2020 11:42:59 -0400 Received: from localhost.localdomain (unknown [157.51.190.160]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id DFD1A20836; Sun, 3 May 2020 15:42:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588520578; bh=OXq9FMct3mDZL6PvVE4nWjIKjobcNyfHQcSwBAqBwVc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=g5WnNTF+PpnXSAALCoeR5nGgbygm1L8Fk1PZV4vXBXwWNTMEayAVswXAZZFhPx/wR MpaRoJy9H9TrM3zRapq/fgk2yLXbSp4O0/iJnkhcLfgGGyLbWDqEpHEebakySG/3Zb Zo72aUdzp27OtlT14UJMhR4qWJCKA6we/I03GIJw= From: mani@kernel.org To: robh+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com Cc: devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 6/6] ARM: dts: stm32: Add IoT Box board support Date: Sun, 3 May 2020 21:12:15 +0530 Message-Id: <20200503154215.23654-7-mani@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200503154215.23654-1-mani@kernel.org> References: <20200503154215.23654-1-mani@kernel.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Manivannan Sadhasivam IoT Box is an IoT gateway device based on Stinger96 board powered by STM32MP1 SoC, designed and manufactured by Shiratech Solutions. This device makes use of Stinger96 board by having it as a base board with one additional mezzanine on top. Following are the features exposed by this device in addition to the Stinger96 board: * WiFi/BT * CCS811 VOC sensor * 2x Digital microphones IM69D130 * 12x WS2812B LEDs Following peripherals are tested and known to work: * WiFi/BT * CCS811 More information about this device can be found in Shiratech website: https://www.shiratech-solutions.com/products/iot-box/ Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/stm32mp157a-iot-box.dts | 68 +++++++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-iot-box.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 966b81dfffd6..455ec6eb6303 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1030,6 +1030,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-disco.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157a-dk1.dtb \ + stm32mp157a-iot-box.dtb \ stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ stm32mp157c-dk2.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157a-iot-box.dts b/arch/arm/boot/dts/stm32mp157a-iot-box.dts new file mode 100644 index 000000000000..70f394b4d3c0 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-iot-box.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Manivannan Sadhasivam + */ + +/dts-v1/; +#include "stm32mp157a-stinger96.dtsi" + +/ { + model = "Shiratech STM32MP157A IoT Box"; + compatible = "shiratech,stm32mp157a-iot-box", "st,stm32mp157"; + + wlan_pwr: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&i2c2 { + ccs811@5b { + compatible = "ams,ccs811"; + reg = <0x5b>; + wakeup-gpios = <&gpioa 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; + }; +}; + +/* WiFi */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + broken-cd; + non-removable; + st,neg-edge; + bus-width = <1>; + vmmc-supply = <&wlan_pwr>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* Bluetooth */ +&uart4 { + /* Note: HW flow control is broken, hence using custom CTS/RTS gpios */ + /delete-property/st,hw-flow-ctrl; + cts-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpiob 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + bluetooth { + shutdown-gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; + compatible = "brcm,bcm43438-bt"; + max-speed = <115200>; + }; +};