From patchwork Sat Feb 4 01:34:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baoyou Xie X-Patchwork-Id: 93332 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp848980qgi; Fri, 3 Feb 2017 17:34:49 -0800 (PST) X-Received: by 10.84.233.193 with SMTP id m1mr25649055pln.126.1486172089031; Fri, 03 Feb 2017 17:34:49 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i80si26999033pfa.223.2017.02.03.17.34.48 for ; Fri, 03 Feb 2017 17:34:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-watchdog-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-watchdog-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-watchdog-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753428AbdBDBer (ORCPT ); Fri, 3 Feb 2017 20:34:47 -0500 Received: from mail-pf0-f176.google.com ([209.85.192.176]:33883 "EHLO mail-pf0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753329AbdBDBeq (ORCPT ); Fri, 3 Feb 2017 20:34:46 -0500 Received: by mail-pf0-f176.google.com with SMTP id e4so9607456pfg.1 for ; Fri, 03 Feb 2017 17:34:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Bp3j5DodJQ5kA+onWaBYsyhHHbKAkehXcC9DybKAhV4=; b=iEDlX1bGxd/pAyEj1/+ryvRyw6sMmpPLFRpJhu1ZUt6//wvKPUTrbu5Nn3Gn48aTB0 3MHx6E2DaVwQ8/PNKvINZZwQ57inttskzJZWzSxorbJ3Pf8YBzYQWX2p0VfyITltx97O BShcOJ5uWup9AXCVdmPkguwvQ+5WtlUxv8S/I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Bp3j5DodJQ5kA+onWaBYsyhHHbKAkehXcC9DybKAhV4=; b=ata6/jqLmt6x6AIAPDGLCHrnqeSpDQC9iBGmir2wZyl3hxSyeJR/pV26VLL3irKlbO ox8nvDzIWmY+N5BOgmW0l6heTd6RpnqpXD37Tj/K71sEIzGas2motlmrcG8ENNSIG4/j EYvULvEjygyiQL1Sf8sj1dSevmTsWEYCTeq0Y8rkf3i53/4RIolCUMuDfKsqYZIz4uuy sUFOWFIF8B/XzH8xnmcakHt4ZJWQOEDzReg7ZZD2RMdFpyfHlTF8h2af3Nu24zR90RP7 4wo2kqpmYQHTZ3RvDxrkz8scElXwMetMhsZYWzKxrIiwiKQNvWCFwM0HrPyJOHLqPA4v 1AIA== X-Gm-Message-State: AIkVDXIqdp12L87UT4gHs+WiOOCGL8yC7L8xzL8MbbhASINuoMC1K/G8+YAib5SBlle/SePc X-Received: by 10.99.67.1 with SMTP id q1mr21837096pga.210.1486172085496; Fri, 03 Feb 2017 17:34:45 -0800 (PST) Received: from localhost.localdomain ([104.237.91.145]) by smtp.gmail.com with ESMTPSA id u24sm70045499pfi.25.2017.02.03.17.34.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 03 Feb 2017 17:34:45 -0800 (PST) From: Baoyou Xie To: jun.nie@linaro.org, wim@iguana.be, linux@roeck-us.net, robh+dt@kernel.org, mark.rutland@arm.com, mathieu.poirier@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, baoyou.xie@linaro.org, xie.baoyou@zte.com.cn, chen.chaokai@zte.com.cn, wang.qiang01@zte.com.cn Subject: [PATCH v9 2/3] MAINTAINERS: add zx2967 watchdog controller driver to ARM ZTE architecture Date: Sat, 4 Feb 2017 09:34:14 +0800 Message-Id: <1486172055-13162-2-git-send-email-baoyou.xie@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1486172055-13162-1-git-send-email-baoyou.xie@linaro.org> References: <1486172055-13162-1-git-send-email-baoyou.xie@linaro.org> Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Add the zx2967 watchdog controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Guenter Roeck diff --git a/MAINTAINERS b/MAINTAINERS index edfdea3..275c434 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1990,11 +1990,13 @@ F: drivers/clk/zte/ F: drivers/reset/reset-zx2967.c F: drivers/soc/zte/ F: drivers/thermal/zx* +F: drivers/watchdog/zx2967_wdt.c F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt F: Documentation/devicetree/bindings/soc/zte/ F: Documentation/devicetree/bindings/thermal/zx* +F: Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt F: include/dt-bindings/soc/zx*.h ARM/ZYNQ ARCHITECTURE From patchwork Sat Feb 4 01:34:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baoyou Xie X-Patchwork-Id: 93333 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp849021qgi; Fri, 3 Feb 2017 17:35:03 -0800 (PST) X-Received: by 10.99.94.71 with SMTP id s68mr21262800pgb.181.1486172103284; Fri, 03 Feb 2017 17:35:03 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t6si26998025pfi.59.2017.02.03.17.35.03 for ; Fri, 03 Feb 2017 17:35:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-watchdog-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-watchdog-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-watchdog-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753457AbdBDBez (ORCPT ); Fri, 3 Feb 2017 20:34:55 -0500 Received: from mail-pf0-f169.google.com ([209.85.192.169]:33893 "EHLO mail-pf0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753329AbdBDBey (ORCPT ); Fri, 3 Feb 2017 20:34:54 -0500 Received: by mail-pf0-f169.google.com with SMTP id e4so9608044pfg.1 for ; Fri, 03 Feb 2017 17:34:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mpFsFzL5l7cXkouK5NzJ9H1sr5iLuxUuSjeJwSJKUDE=; b=HHZIHhG3LfIONdD5nB1A/OtDwt3Ox9upHNFqKMUhOaZIupI5Emxzk5eIpm0f6k9OHt 69y561l4Is+bQmVAcyAV4Uq+wt1zfVZxVzYu5oAak9/OdeDx0QG16CT7Ifq7Zo0eAzWT WW91UL+S+LAchSA5vkYysWvI2KfAOT35xcAnE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mpFsFzL5l7cXkouK5NzJ9H1sr5iLuxUuSjeJwSJKUDE=; b=ONorrH2TWfDAB1rATGHSE8PR97+VmyZ4+v9/4GVscFk37j1IQbTUmua5E1mDwVhLcW fnNwAGlPb1LiYoay/HEb1DyErjAtTmd4zqZbOKtz/h73aQitMlQ9nlGeMoCw4jSD8eFL 5Rjo2I8drNXm/kclcvdPDx6kMODi3AAxYQDoaSFhH3hiOcQdO//BLCDKlUI6xiYNOMuG 9t58OZKq60SIpNUPoxrdACH3cfdu/vmef87M+nf5Ty/HjqNOyNJbmiroqo6jV2F+x4TF FkYNjf4QhMJg0B1lzv0VZKwM0TevZvni3H6d3ZPaoSo/X3mcd6s+sFlqZTO3mSqDMa9Y xOhA== X-Gm-Message-State: AIkVDXJRhYe46z6xRRZNFoKU4kPx1L5/RgfsyrHYNmYBYo2x9+FL2HiDxDfFyT5FT9GDoj9I X-Received: by 10.98.75.16 with SMTP id y16mr21788865pfa.23.1486172093226; Fri, 03 Feb 2017 17:34:53 -0800 (PST) Received: from localhost.localdomain ([104.237.91.145]) by smtp.gmail.com with ESMTPSA id u24sm70045499pfi.25.2017.02.03.17.34.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 03 Feb 2017 17:34:52 -0800 (PST) From: Baoyou Xie To: jun.nie@linaro.org, wim@iguana.be, linux@roeck-us.net, robh+dt@kernel.org, mark.rutland@arm.com, mathieu.poirier@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, baoyou.xie@linaro.org, xie.baoyou@zte.com.cn, chen.chaokai@zte.com.cn, wang.qiang01@zte.com.cn Subject: [PATCH v9 3/3] watchdog: zx2967: add watchdog controller driver for ZTE's zx2967 family Date: Sat, 4 Feb 2017 09:34:15 +0800 Message-Id: <1486172055-13162-3-git-send-email-baoyou.xie@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1486172055-13162-1-git-send-email-baoyou.xie@linaro.org> References: <1486172055-13162-1-git-send-email-baoyou.xie@linaro.org> Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org This patch adds watchdog controller driver for ZTE's zx2967 family. Signed-off-by: Baoyou Xie --- drivers/watchdog/Kconfig | 10 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/zx2967_wdt.c | 291 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 302 insertions(+) create mode 100644 drivers/watchdog/zx2967_wdt.c -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Guenter Roeck Reviewed-by: Mathieu Poirier diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index acb00b5..05093a2 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -714,6 +714,16 @@ config ASPEED_WATCHDOG To compile this driver as a module, choose M here: the module will be called aspeed_wdt. +config ZX2967_WATCHDOG + tristate "ZTE zx2967 SoCs watchdog support" + depends on ARCH_ZX + select WATCHDOG_CORE + help + Say Y here to include support for the watchdog timer + in ZTE zx2967 SoCs. + To compile this driver as a module, choose M here: the + module will be called zx2967_wdt. + # AVR32 Architecture config AT32AP700X_WDT diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 0c3d35e..bf2d296 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -82,6 +82,7 @@ obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o obj-$(CONFIG_ATLAS7_WATCHDOG) += atlas7_wdt.o obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o +obj-$(CONFIG_ZX2967_WATCHDOG) += zx2967_wdt.o # AVR32 Architecture obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o diff --git a/drivers/watchdog/zx2967_wdt.c b/drivers/watchdog/zx2967_wdt.c new file mode 100644 index 0000000..e290d5a --- /dev/null +++ b/drivers/watchdog/zx2967_wdt.c @@ -0,0 +1,291 @@ +/* + * watchdog driver for ZTE's zx2967 family + * + * Copyright (C) 2017 ZTE Ltd. + * + * Author: Baoyou Xie + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ZX2967_WDT_CFG_REG 0x4 +#define ZX2967_WDT_LOAD_REG 0x8 +#define ZX2967_WDT_REFRESH_REG 0x18 +#define ZX2967_WDT_START_REG 0x1c + +#define ZX2967_WDT_REFRESH_MASK GENMASK(5, 0) + +#define ZX2967_WDT_CFG_DIV(n) ((((n) & 0xff) - 1) << 8) +#define ZX2967_WDT_START_EN 0x1 + +/* + * Hardware magic number. + * When watchdog reg is written, the lowest 16 bits are valid, but + * the highest 16 bits should be always this number. + */ +#define ZX2967_WDT_WRITEKEY (0x1234 << 16) +#define ZX2967_WDT_VAL_MASK GENMASK(15, 0) + +#define ZX2967_WDT_DIV_DEFAULT 16 +#define ZX2967_WDT_DEFAULT_TIMEOUT 32 +#define ZX2967_WDT_MIN_TIMEOUT 1 +#define ZX2967_WDT_MAX_TIMEOUT 524 +#define ZX2967_WDT_MAX_COUNT 0xffff + +#define ZX2967_WDT_CLK_FREQ 0x8000 + +#define ZX2967_WDT_FLAG_REBOOT_MON BIT(0) + +struct zx2967_wdt { + struct watchdog_device wdt_device; + void __iomem *reg_base; + struct clk *clock; +}; + +static inline u32 zx2967_wdt_readl(struct zx2967_wdt *wdt, u16 reg) +{ + return readl_relaxed(wdt->reg_base + reg); +} + +static inline void zx2967_wdt_writel(struct zx2967_wdt *wdt, u16 reg, u32 val) +{ + writel_relaxed(val | ZX2967_WDT_WRITEKEY, wdt->reg_base + reg); +} + +static void zx2967_wdt_refresh(struct zx2967_wdt *wdt) +{ + u32 val; + + val = zx2967_wdt_readl(wdt, ZX2967_WDT_REFRESH_REG); + /* + * Bit 4-5, 1 and 2: refresh config info + * Bit 2-3, 1 and 2: refresh counter + * Bit 0-1, 1 and 2: refresh int-value + * we shift each group value between 1 and 2 to refresh all data. + */ + val ^= ZX2967_WDT_REFRESH_MASK; + zx2967_wdt_writel(wdt, ZX2967_WDT_REFRESH_REG, + val & ZX2967_WDT_VAL_MASK); +} + +static int +zx2967_wdt_set_timeout(struct watchdog_device *wdd, unsigned int timeout) +{ + struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd); + unsigned int divisor = ZX2967_WDT_DIV_DEFAULT; + u32 count; + + count = timeout * ZX2967_WDT_CLK_FREQ; + if (count > divisor * ZX2967_WDT_MAX_COUNT) + divisor = DIV_ROUND_UP(count, ZX2967_WDT_MAX_COUNT); + count = DIV_ROUND_UP(count, divisor); + zx2967_wdt_writel(wdt, ZX2967_WDT_CFG_REG, + ZX2967_WDT_CFG_DIV(divisor) & ZX2967_WDT_VAL_MASK); + zx2967_wdt_writel(wdt, ZX2967_WDT_LOAD_REG, + count & ZX2967_WDT_VAL_MASK); + zx2967_wdt_refresh(wdt); + wdd->timeout = (count * divisor) / ZX2967_WDT_CLK_FREQ; + + return 0; +} + +static void __zx2967_wdt_start(struct zx2967_wdt *wdt) +{ + u32 val; + + val = zx2967_wdt_readl(wdt, ZX2967_WDT_START_REG); + val |= ZX2967_WDT_START_EN; + zx2967_wdt_writel(wdt, ZX2967_WDT_START_REG, + val & ZX2967_WDT_VAL_MASK); +} + +static void __zx2967_wdt_stop(struct zx2967_wdt *wdt) +{ + u32 val; + + val = zx2967_wdt_readl(wdt, ZX2967_WDT_START_REG); + val &= ~ZX2967_WDT_START_EN; + zx2967_wdt_writel(wdt, ZX2967_WDT_START_REG, + val & ZX2967_WDT_VAL_MASK); +} + +static int zx2967_wdt_start(struct watchdog_device *wdd) +{ + struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd); + + zx2967_wdt_set_timeout(wdd, wdd->timeout); + __zx2967_wdt_start(wdt); + + return 0; +} + +static int zx2967_wdt_stop(struct watchdog_device *wdd) +{ + struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd); + + __zx2967_wdt_stop(wdt); + + return 0; +} + +static int zx2967_wdt_keepalive(struct watchdog_device *wdd) +{ + struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd); + + zx2967_wdt_refresh(wdt); + + return 0; +} + +#define ZX2967_WDT_OPTIONS \ + (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) +static const struct watchdog_info zx2967_wdt_ident = { + .options = ZX2967_WDT_OPTIONS, + .identity = "zx2967 watchdog", +}; + +static struct watchdog_ops zx2967_wdt_ops = { + .owner = THIS_MODULE, + .start = zx2967_wdt_start, + .stop = zx2967_wdt_stop, + .ping = zx2967_wdt_keepalive, + .set_timeout = zx2967_wdt_set_timeout, +}; + +static void zx2967_wdt_reset_sysctrl(struct device *dev) +{ + int ret; + void __iomem *regmap; + unsigned int offset, mask, config; + struct of_phandle_args out_args; + + ret = of_parse_phandle_with_fixed_args(dev->of_node, + "zte,wdt-reset-sysctrl", 3, 0, &out_args); + if (ret) + return; + + offset = out_args.args[0]; + config = out_args.args[1]; + mask = out_args.args[2]; + + regmap = syscon_node_to_regmap(out_args.np); + if (IS_ERR(regmap)) { + of_node_put(out_args.np); + return; + } + + regmap_update_bits(regmap, offset, mask, config); + of_node_put(out_args.np); +} + +static int zx2967_wdt_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct zx2967_wdt *wdt; + struct resource *base; + int ret; + struct reset_control *rstc; + + wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); + if (!wdt) + return -ENOMEM; + + platform_set_drvdata(pdev, wdt); + + wdt->wdt_device.info = &zx2967_wdt_ident; + wdt->wdt_device.ops = &zx2967_wdt_ops; + wdt->wdt_device.timeout = ZX2967_WDT_DEFAULT_TIMEOUT; + wdt->wdt_device.max_timeout = ZX2967_WDT_MAX_TIMEOUT; + wdt->wdt_device.min_timeout = ZX2967_WDT_MIN_TIMEOUT; + wdt->wdt_device.parent = &pdev->dev; + + base = platform_get_resource(pdev, IORESOURCE_MEM, 0); + wdt->reg_base = devm_ioremap_resource(dev, base); + if (IS_ERR(wdt->reg_base)) { + dev_err(dev, "ioremap failed\n"); + return PTR_ERR(wdt->reg_base); + } + + zx2967_wdt_reset_sysctrl(dev); + + wdt->clock = devm_clk_get(dev, NULL); + if (IS_ERR(wdt->clock)) { + dev_err(dev, "failed to find watchdog clock source\n"); + return PTR_ERR(wdt->clock); + } + + ret = clk_prepare_enable(wdt->clock); + if (ret < 0) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + clk_set_rate(wdt->clock, ZX2967_WDT_CLK_FREQ); + + rstc = devm_reset_control_get(dev, NULL); + if (IS_ERR(rstc)) { + dev_err(dev, "failed to get rstc"); + ret = PTR_ERR(rstc); + goto err; + } + + reset_control_assert(rstc); + reset_control_deassert(rstc); + + watchdog_set_drvdata(&wdt->wdt_device, wdt); + watchdog_init_timeout(&wdt->wdt_device, + ZX2967_WDT_DEFAULT_TIMEOUT, dev); + watchdog_set_nowayout(&wdt->wdt_device, WATCHDOG_NOWAYOUT); + + ret = watchdog_register_device(&wdt->wdt_device); + if (ret) + goto err; + + dev_info(dev, "watchdog enabled (timeout=%d sec, nowayout=%d)", + wdt->wdt_device.timeout, WATCHDOG_NOWAYOUT); + + return 0; + +err: + clk_disable_unprepare(wdt->clock); + return ret; +} + +static int zx2967_wdt_remove(struct platform_device *pdev) +{ + struct zx2967_wdt *wdt = platform_get_drvdata(pdev); + + watchdog_unregister_device(&wdt->wdt_device); + clk_disable_unprepare(wdt->clock); + + return 0; +} + +static const struct of_device_id zx2967_wdt_match[] = { + { .compatible = "zte,zx296718-wdt", }, + {} +}; +MODULE_DEVICE_TABLE(of, zx2967_wdt_match); + +static struct platform_driver zx2967_wdt_driver = { + .probe = zx2967_wdt_probe, + .remove = zx2967_wdt_remove, + .driver = { + .name = "zx2967-wdt", + .of_match_table = of_match_ptr(zx2967_wdt_match), + }, +}; +module_platform_driver(zx2967_wdt_driver); + +MODULE_AUTHOR("Baoyou Xie "); +MODULE_DESCRIPTION("ZTE zx2967 Watchdog Device Driver"); +MODULE_LICENSE("GPL v2");